FEATURES
FUNCTIONAL BLOCK DIAGRAM
1.3 pF off capacitance
3.5 pF on capacitance
1 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at +12 V, ±15 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 12-lead LFCSP packages
Typical power consumption: <0.03 µW
ADG1236
S1A
D1
S1B
IN1
IN2
S2A
D2
S2B
APPLICATIONS
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio/video signal routing
Communication systems
04776-001
Data Sheet
Low Capacitance, Low Charge Injection,
±15 V/12 V iCMOS, Dual SPDT Switch
ADG1236
Figure 1.
GENERAL DESCRIPTION
The ADG1236 is a monolithic CMOS device containing two
independently selectable SPDT switches. It is designed on an
iCMOS® process. iCMOS (industrial CMOS) is a modular
manufacturing process combining high voltage complementary
metal-oxide semiconductor (CMOS) and bipolar technologies.
It enables the development of a wide range of high performance
analog ICs capable of 33 V operation in a footprint that no
previous generation of high voltage devices has been able to
achieve. Unlike analog ICs using conventional CMOS processes,
iCMOS components can tolerate high supply voltages while
providing increased performance, dramatically lower power
consumption, and reduced package size.
The ultralow capacitance and charge injection of the device
make it an ideal solution for data acquisition and sample-andhold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth makes
the device suitable for video signal switching. iCMOS construction
ensures ultralow power dissipation, making the device ideally
suited for portable and battery-powered instruments.
Rev. A
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. In the
off condition, signal levels up to the supplies are blocked. Both
switches exhibit break-before-make switching action for use in
multiplexer applications.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
1.3 pF off capacitance (±15 V supply).
1 pC charge injection.
3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V.
No VL logic power supply required.
Ultralow power dissipation: <0.03 µW.
16-lead TSSOP and 12-lead 3 mm × 3 mm LFCSP packages.
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Technical Support
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ADG1236
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................6 Applications ....................................................................................... 1 ESD Caution...................................................................................6 Functional Block Diagram .............................................................. 1 Truth Table for Switches ...............................................................6 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ............................7 Product Highlights ........................................................................... 1 Terminology .......................................................................................8 Revision History ............................................................................... 2 Typical Performance Characteristics ..............................................9 Specifications..................................................................................... 3 Test Circuits ..................................................................................... 12 Dual Supply ................................................................................... 3 Outline Dimensions ....................................................................... 14 Single Supply ................................................................................. 5 Ordering Guide .......................................................................... 14 REVISION HISTORY
3/16—Rev. 0 to Rev. A
Changes to Figure 2 and Figure 3 ................................................... 7
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
9/05—Revision 0: Initial Version
Rev. A | Page 2 of 16
Data Sheet
ADG1236
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameters
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
25°C
Y Version1
−40°C to +85°C −40°C to +125°C
VDD to VSS
120
190
3.5
6
20
57
230
260
10
12
72
79
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
±0.02
±0.6
Drain Off Leakage, ID (Off )
±0.1
±0.02
±0.1
±0.02
±0.2
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Test Conditions/Comments1
V
Ω typ
Ω max
Ω typ
VS = ±10 V, IS = −1 mA; Figure 20
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −1 mA
Ω max
Ω typ
Ω max
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VS = ∓10 V; Figure 21
±1
nA max
nA typ
VS = ±10 V, VS = ∓10 V; Figure 21
±0.6
±1
VS = VD = ±10 V; Figure 22
±0.6
±1
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
VIN = VINL or VINH
2.0
0.8
0.005
2
Break-Before-Make Time Delay, tD
125
150
70
90
25
Charge Injection
Off Isolation
−1
80
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
Channel-to-Channel Crosstalk
85
dB typ
Total Harmonic Distortion + Noise
0.15
% typ
−3 dB Bandwidth
CS (Off )
1000
1.3
1.6
3.5
4.3
MHz typ
pF typ
pF max
pF typ
pF max
Transition Time, tTRANS BOFF AON
200
115
10
CD, CS (On)
VS = −5 V, 0 V, +5 V; IS = −1 mA
nA typ
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANS AOFF BON
Unit
Rev. A | Page 3 of 16
RL = 300 Ω, CL = 35 pF
VS = 10 V; Figure 23
RL = 300 Ω, CL = 35 pF
VS = 10 V; Figure 23
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; Figure 24
VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Figure 27
RL = 10 kΩ, 5 V rms, f = 20 Hz to
20 kHz
RL = 50 Ω, CL = 5 pF; Figure 28
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
ADG1236
Parameters
POWER REQUIREMENTS
IDD
Data Sheet
25°C
Y Version 1
−40°C to +85°C −40°C to +125°C
0.001
1.0
IDD
170
230
ISS
0.001
1.0
ISS
0.001
1.0
1
2
Temperature range for Y version is −40°C to +125°C.
Guaranteed by design; not subject to production test.
Rev. A | Page 4 of 16
Unit
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA max
Test Conditions/Comments 1
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Data Sheet
ADG1236
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameters
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
Y Version 1
−40°C to +85°C −40°C to +125°C
0 V to VDD
300
475
4.5
16
60
±0.02
±0.1
±0.02
±0.1
±0.02
±0.2
567
625
26
27
±0.6
±1
±0.6
±1
±0.6
±1
2.0
0.8
0.001
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
Transition Time, tTRANS BOFF AON
Transition Time, tTRANS AOFF BON
Break-Before-Make Time Delay, tD
3
105
140
155
190
50
175
255
10
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
−0.8
75
85
800
1.6
1.9
4
4.9
0.001
1.0
IDD
170
230
1
2
Temperature range for Y version is −40°C to +125°C.
Guaranteed by design; not subject to production test.
Rev. A | Page 5 of 16
Unit
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
VS = 0 V to 10 V, IS = −1 mA; Figure 20
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
Ω max
Ω typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF max
pF typ
pF max
µA typ
µA max
µA typ
µA max
VS = 3 V, 6 V, 9 V, IS = −1 mA
VDD = 13.2 V
VS = 1 V/10 V, VD = 10 V/1 V; Figure 21
VS = 1 V/10 V, VD = 10 V/1 V; Figure 21
VS = VD = 1 V or 10 V, Figure 22
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 23
RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 23
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; Figure 24
VS = 6 V, RS = 0 Ω, CL = 1 nF; Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 26;
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
RL = 50 Ω, CL = 5 pF; Figure 28
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
ADG1236
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs 1
Digital Inputs1
Peak Current, S or D
Continuous Current per
Channel, S or D
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
16-Lead TSSOP, θJA Thermal
Impedance
12-Lead LFCSP, θJA Thermal
Impedance
Reflow Soldering Peak
Temperature, Pb Free
1
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
100 mA (pulsed at 1 ms,
10% duty cycle max)
25 mA
−40°C to +125°C
−65°C to +150°C
150°C
112°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
TRUTH TABLE FOR SWITCHES
Table 4.
IN
0
1
80°C/W
260°C
Over voltages at IN, S, or D are clamped by internal diodes. Current must be
limited to the maximum ratings given.
Rev. A | Page 6 of 16
Switch A
Off
On
Switch B
On
Off
Data Sheet
ADG1236
NC
D1 1
D1
3
14
NC
S1B 2
S1B
4
ADG1236
13
VDD
VSS
5
TOP VIEW
(Not to Scale)
VSS 3
12
S2B
GND
6
11
D2
NC
7
10
S2A
NC
8
9
IN2
Table 5. Pin Function Descriptions
Mnemonic
IN1
S1A
D1
S1B
VSS
GND
NC
IN2
S2A
D2
S2B
VDD
8 S2B
7 D2
11 IN1
Figure 3. LFCSP Pin Configuration
Figure 2. TSSOP Pin Configuration
Pin No.
TSSOP
LFCSP
1
11
2
12
3
1
4
2
5
3
6
4
7, 8, 14 to 16 10
9
5
10
6
11
7
12
8
13
9
TOP VIEW
(Not to Scale)
9 VDD
NOTES
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
2. THE EXPOSED PAD MUST BE TIED
TO SUBSTRATE, VSS.
04776-002
NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
ADG1236
Description
Logic Control Input.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
No Connect.
Logic Control Input.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Positive Power Supply Potential.
Rev. A | Page 7 of 16
04776-003
NC
S1A
S2A 6
16
15
IN2 5
1
2
GND 4
IN1
10 NC
12 S1A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADG1236
Data Sheet
TERMINOLOGY
CD (Off)
The off switch drain capacitance, measured with reference to
ground.
IDD
The positive supply current.
ISS
The negative supply current.
CD, CS (On)
VD (VS)
The analog voltage on Terminals D and S.
The on switch capacitance, measured with reference to ground.
CIN
The digital input capacitance.
RON
The ohmic resistance between D and S.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
tTRANS
The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one
address state to another.
IS (Off)
The source leakage current with the switch off.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
ID (Off)
The drain leakage current with the switch off.
Off Isolation
A measure of unwanted signal coupling through an off switch.
ID, IS (On)
The channel leakage current with the switch on.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
VINL
The maximum input voltage for Logic 0.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
VINH
The minimum input voltage for Logic 1.
On Response
The frequency response of the on switch.
IINL (IINH)
The input current of the digital input.
CS (Off)
The off switch source capacitance, measured with reference to
ground.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
Rev. A | Page 8 of 16
Data Sheet
ADG1236
TYPICAL PERFORMANCE CHARACTERISTICS
250
200
TA = 25°C
180
VDD = 13.5V
VSS = –13.5V
200
TA = +125°C
ON RESISTANCE (Ω)
160
140
120
VDD = 16.5V
VSS = –16.5V
100
80
60
100
TA = –40°C
0
–18 –15 –12
3
0
6
9
–9 –6 –3
SOURCE OR DRAIN VOLTAGE (V)
12
15
0
–15
18
Figure 4. On Resistance as a Function of VD (VS) for Dual Supply
04776-014
04776-011
20
–10
–5
0
5
TEMPERATURE (°C)
10
15
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
600
600
TA = 25°C
VDD = 4.5V
VSS = –4.5V
TA = +125°C
ON RESISTANCE (Ω)
VDD = 5V
VSS = –5V
400
VDD = 5.5V
VSS = –5.5V
300
VDD = 12V
VSS = 0V
500
500
200
TA = +85°C
400
TA = +25°C
300
TA = –40°C
200
100
0
–6
04776-012
100
–4
0
2
–2
SOURCE OR DRAIN VOLTAGE (V)
4
04776-015
ON RESISTANCE (Ω)
TA = +25°C
50
40
0
0
6
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
2
4
6
8
TEMPERATURE (°C)
10
12
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
0.20
450
TA = 25°C
400
VDD = 10.8V
VSS = 0V
350
VDD = 12V
VSS = 0V
0.10
LEAKAGE (nA)
300
250
VDD = 13.2V
VSS = 0V
200
VDD = 15V
VSS = –15V
VBIAS = +10V/–10V
0.15
IS (OFF)
0.05
0
–0.05
ID, IS (ON)
150
–0.10
100
–0.15
04776-013
ON RESISTANCE (Ω)
TA = +85°C
150
50
0
0
2
4
6
8
10
SOURCE OR DRAIN VOLTAGE (V)
12
–0.20
0
14
Figure 6. On Resistance as a Function of VD (VS) for Single Supply
04776-016
ON RESISTANCE (Ω)
VDD = 15V
VSS = –15V
VDD = 15V
VSS = –15V
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 9. Leakage Currents as a Function of Temperature, Dual Supply
Rev. A | Page 9 of 16
ADG1236
Data Sheet
0.35
220
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
0.30
200
180
0.25
AOFF BON 12V SS
AOFF BON 15V DS
140
TIME (ns)
LEAKAGE (nA)
160
0.20
0.15
ID, IS (ON)
0.10
120
BOFF AON 12V SS
100
80
0.05
60
IS (OFF)
0
BOFF AON 15V DS
–0.05
–0.10
0
20
40
100
60
80
TEMPERATURE (°C)
04776-004
04776-017
40
20
0
–40
120
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 13. tTRANSITION Times vs. Temperature
Figure 10. Leakage Currents as a Function of Temperature, Single Supply
60
0
IDD PER CHANNEL
TA = 25°C
–10
50
VDD = 15V
VSS = –15V
TA = 25°C
–20
30
20
VDD = 12V
VSS = 0V
2
4
6
8
LOGIC, INX (V)
–50
–60
–70
10
12
–90
–100
10k
14
100k
1M
10M
FREQUENCY (Hz)
100M
1G
Figure 14. Off Isolation vs. Frequency
Figure 11. IDD vs. Logic Level
6
0
TA = 25°C
–10
4
VDD = 15V
VSS = –15V
TA = 25°C
–20
VDD = 15V
VSS = –15V
0
CROSSTALK (dB)
2
VDD = 12V
VSS = 0V
–2
–30
–40
–50
BETWEEN
SA AND SB
–60
–70
–80
–4
–6
–15
04776-005
CHARGE INJECTIOIN (pC)
04776-010
0
0
–40
–80
04776-018
10
–30
–10
–5
0
VBIAS (V)
5
10
BETWEEN
S1 AND S2
–90
–100
10k
15
100k
1M
10M
FREQUENCY (Hz)
Figure 15. Crosstalk vs. Frequency
Figure 12. Charge Injection vs. Source Voltage
Rev. A | Page 10 of 16
100M
04776-008
IDD (µA)
OFF ISOLATION (dB)
VDD = 15V
VSS = –15V
40
1G
Data Sheet
ADG1236
5
0
4
CAPACITANCE (pF)
ON RESPONSE (dB)
–5
VDD = 15V
VSS = –15V
TA = 25°C
VDD = 15V
VSS = –15V
TA = 25°C
–10
–15
–20
SOURCE/DRAIN ON
3
2
SOURCE OFF
1
100k
1M
10M
100M
FREQUENCY (Hz)
1G
0
–15
10G
Figure 16. On Response vs. Frequency
04776-007
–30
10k
04776-009
–25
–10
–5
5
10
15
Figure 18. Capacitance vs. Source Voltage for Dual Supply
5
10.00
LOAD = 10kΩ
TA = 25°C
SOURCE/DRAIN ON
CAPACITANCE (pF)
4
1.00
THD + N (%)
0
VBIAS (V)
VDD = 5V, VSS = –5V, VS = 3.5Vrms
VDD = 15V, VSS = –15V, VS = 5Vrms
0.10
VDD = 12V
VSS = 0V
TA = 25°C
3
2
SOURCE OFF
0.01
10
100
1k
FREQUENCY (Hz)
10k
04776-006
04776-019
1
0
0
100k
2
4
6
VBIAS (V)
8
10
Figure 19. Capacitance vs. Source Voltage for Single Supply
Figure 17. THD + N vs. Frequency
Rev. A | Page 11 of 16
12
ADG1236
Data Sheet
TEST CIRCUITS
V
S
D
04776-020
IDS
VS
Figure 20. Test Circuit 1—On Resistance
ID (OFF)
S
A
D
A
VS
04776-021
IS (OFF)
VD
Figure 21. Test Circuit 2—Off Resistance
ID (ON)
S
D
NC = NO CONNECT
A
04776-022
NC
VD
Figure 22. Test Circuit 3—On Leakage
VDD
VDD
D
SA
VOUT
RL
300
IN
VIN
VIN
50%
50%
VIN
50%
50%
VSS
SB
VS
0.1F
CL
35pF
90%
VOUT
GND
tON
90%
tOFF
04776-023
0.1F
VSS
Figure 23. Test Circuit 4—Switching Times
0.1F
VDD
VSS
VDD
VSS
SB
VS
0.1F
VIN
D
SA
VOUT
RL
300
IN
VOUT
CL
35pF
80%
tBBM
VIN
tBBM
04776-024
GND
Figure 24. Test Circuit 5—Break-Before-Make Time Delay
VDD
VSS
VDD
VSS
0.1F
VIN (NORMALLY
CLOSED SWITCH)
ON
SB
VS
D
VOUT
SA
CL
1nF
IN
VIN
GND
OFF
NC
VIN (NORMALLY
OPEN SWITCH)
VOUT
VOUT
QINJ = CL  VOUT
Figure 25. Test Circuit 6—Charge Injection
Rev. A | Page 12 of 16
04776-025
0.1F
Data Sheet
VSS
VDD
0.1F
0.1F
VDD
NETWORK
ANALYZER
VSS
NC
SA
IN
SB
VSS
0.1F
0.1F
NETWORK
ANALYZER
50
VDD
VSS
SA
VOUT
RL
50
50
VS
SB
D
D
VIN
RL
50
VOUT
IN
VS
GND
VOUT
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
Figure 26. Test Circuit 7—Off Isolation
0.1F
VDD
NC
IN
SA
SB
VDD
0.1F
VSS
VDD
VSS
0.1F
AUDIO PRECISION
NETWORK
ANALYZER
VSS
VOUT
VS
Figure 28. Test Circuit 9—Bandwidth
VSS
0.1F
04776-028
04776-026
GND
OFF ISOLATION = 20 log
VDD
R
50
RS
50
S
50
IN
VS
V p-p
VS
D
D
VIN
RL
50
VOUT
VIN
04776-027
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
VOUT
GND
GND
INSERTION LOSS = 20 log
RL
10k
Figure 29. Test Circuit 10—THD + Noise
Figure 27. Test Circuit 8—Channel-to-Channel Crosstalk
Rev. A | Page 13 of 16
04776-029
VDD
ADG1236
ADG1236
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
PIN 1
INDICATOR
0.30
0.23
0.18
0.50
BSC
10
PIN 1
INDICATOR
12
1
9
EXPOSED
PAD
1.45
1.30 SQ
1.15
3
7
TOP VIEW
0.80
0.75
0.70
0.70
0.60
0.50
6
0.25 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
4
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WEED.
111808-A
3.10
3.00 SQ
2.90
Figure 31. 12-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-12-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADG1236YRUZ
ADG1236YRUZ-REEL
ADG1236YRUZ-REEL7
ADG1236YCPZ-500RL7
ADG1236YCPZ-REEL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
12-Lead Lead Frame Chip Scale Package [LFCSP]
12-Lead Lead Frame Chip Scale Package [LFCSP]
Z = RoHS Compliant Part.
Rev. A | Page 14 of 16
Package Option
RU-16
RU-16
RU-16
CP-12-4
CP-12-4
Data Sheet
ADG1236
NOTES
Rev. A | Page 15 of 16
ADG1236
Data Sheet
NOTES
©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04776-0-3/16(A)
Rev. A | Page 16 of 16