Engineer To Engineer Note
EE-44
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How to design a DRAM
Controller to interface a DRAM
with the SHARC DSP
Introduction:
This document provides a reference design for
customers on how to interface a DRAM with the
SHARC DSP using a DRAM Controller. The
controller is implemented as a state-machine on a
Xilinx PLD. This design has been simulated, built
in hardware, and tested to operate successfully.
The design, however, has not been optimized for
best performance. Recommendations for further
modifications as well as alternative designs will be
given in Section IV.
1.
SHARC:
A SHARC EZ-KIT Lite evaluation board is used in
this design. All the signals shown in this block are
available from the external connectors on this
board.
2.
DRAM:
A 4Meg x 32 bit DRAM (MT8D432M-6x, 60ns access
time) manufactured by Micron is used for this
project. Data sheets showing specific timings are
available from Micron.
3.
Mux, Refresh Timer, DRAM Controller:
These are three separate modules that are
programmed onto one 69 I/O pin Xilinx PLD
(XC95108-10PC84).
I.
Design Overview:
Different applications require specific ways of
DRAM interfacing. This design implements a
DRAM controller to interface a 4 Meg DRAM by
Micron with the SHARC.
1
3
Dat31-0
Addr10-0
Addr21-
1
1
1
C
Mux
2
Addr10-0
/RAS/CA
/WR_Dra
/RAS/CA
MuxSe
/WR_Dra
R
Shar
c
/MS0
/MS0
/RD
/RD
/WR
/WR
Page
Brd_Rst
Page
DRAM
Controlle
r
/Rese
CLKIN
CLKIN
RFQ
Ack
DRAM
Dat31-0
Refres
h
Timer RFC
3
RFQ
RFC
Ack
Figure 1: DRAM Interfacing Block Diagram
a
DRAM is an ideal solution for mass data storage
with high speed. However, DRAM requires page
swapping if an access crosses a page boundary. In
addition, DRAM requires refreshing so that data is
retained properly. This means an external
controller is needed to handle the interface between
the Sharc processor and the DRAM.
The refresh timer works as follows: during reset,
the counter is forced to zero from any state. When
reset is released, the counter will start counting up
to 620. At this point, the counter resets to zero and
starts counting again. At the same time, a refresh
request (RFQ) is asserted, signaling the controller
to refresh one row of the DRAM. There are
different ways of refreshing the DRAM. For this
design, CBR or CAS Before RAS method is used as
illustrated in the diagram below. First, the
controller returns CAS and RAS to high, if
necessary. Next, the controller brings CAS low, and
then RAS low in the next cycle. It is important that
RAS and CAS should remain high or low long
enough to meet the time specifications in the data
sheets. At the end of the refresh cycles, the
controller asserts RFC (refresh complete) to signal
the refresh timer to bring RFQ low.
The controller receives input signals from the Sharc
on each memory access and asserts the right control
signals to the DRAM to read or write. Eleven 2:1
mux’s are used to select between column address
and row address depending on whether the
controller is doing a page swap or a normal
read/write. The refresh timer is responsible for
telling the controller when to refresh the DRAM.
II.
Descriptions of the Refresh Timer and the
Controller
Using the CBR refresh method, the user does not
have to worry about which row to refresh. The
DRAM itself has an internal counter that keeps
track of which row to refresh. Each time a CBR is
performed, this internal counter will increment by
one so that the next adjacent page is refreshed on
the next CBR.
1.
Refresh Timer:
Data sheets for this 4 Meg DRAM specify that all
2048 rows or pages need to be refreshed every
32ms. Spreading this task into equal intervals
shows that a new row needs to be refreshed every
15.625µs (32ms/2048). In this design, a refresh
request is generated by the timer every 15.525µs or
621 cycles if using a 40 Mhz clock.
By refreshing one row every 15.5µs, the entire 4
Meg DRAM will effectively be refreshed within
every 32ms.
Clkin
Counte
r
0
0
1
2
619
620
0
1
2
3
4
5
6
7
8
/Reset
RFQ
/RAS
/CAS
RFC
Figure 2: Dram Refreshing for One Row or Page
EE-44
CBR or
CAS Before RAS
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b.
2.
DRAM Controller:
a.
Normal Page Swap, Read, Write
Figure 3 below illustrates the operations of an outof-page read followed immediately by a within-page
write. Note that the timing diagram given here
does not reflect precisely the number of cycles used
in the Abel file. Refer to discussion about
optimization toward the end of this document.
Upon the detection of /MS and Page, the controller
will assert MuxSel to select the row address. Then
/RAS is asserted low to latch in the new row
address. Note that MuxSel is clocked at the
negative clock edge so that row address is valid by
the falling edge of /RAS. Then, if this is a read,
/WR_DRAM is kept high while /CAS is asserted low.
During the same cycle, Ack is asserted high to
indicate the completion of one memory access. Note
that /RAS is held low so that the same page is
retained. It will remain low until a page swap is
required or a DRAM refresh is serviced.
Refresh Request during a Read/Write:
If the DRAM controller is servicing a memory
access when a refresh request occurs, the controller
will keep going to complete that memory read or
write before entering the refresh cycles. RFQ will
stay high until one row refresh has been done and
RFC is asserted. This is illustrated in Figure 4.
c.
Memory Access Request during a Refresh
Service:
If the Sharc asserts /MS while the controller is
refreshing the DRAM, the controller will continue
to finish the refresh before servicing the memory
access. Without having Ack high during this time,
the Sharc will keep driving /MS, /RD or /WR, Data
and Address lines. Note that in this design, the
Sharc is configured to use Ack-only as waitstates.
Figure 5 illustrates this scenario.
In this example, a write follows immediately. Since
it is a same-page operation, only /CAS needs to go
low. /WR_DRAM is asserted this time for a write
cycle.
Clkin
/MS0
Page
Out-of-page READ
/RD
Within-page WRITE
/WR
MuxSel
AddrOu
t
/RAS
Col Addr
Row
Col
Col
/CAS
/WR_
DRA
Ack
Figure 3: Page Swap, Read, Write
EE-44
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It’s time to
refresh !
Read/Write
Completes
RFQ
/MS, /RD,
/WR
Reading/Writing
/RAS, /CAS
Refreshing
RFC
Figure 4: Refresh Request during a Read/Write
It’s time to
refresh !
RFQ
/RAS, /CAS
Refreshing
RFC
/MS, /RD,
/WR
Ack
Read/Write
pending
Read/Write begins
..
.end
Figure 5: Memory Access Request during a Refresh Service
EE-44
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d.
During the Idle/Reset cycle, the controller keeps
/RAS and /CAS high which will put the DRAM into
a low power mode. From here, the controller can
go to refresh cycles if RFQ is asserted or go to start
a memory access. Note that coming out of the idle
state, the controller needs to update the page in the
DRAM regardless of whether this is a out-of-page
access or not. The reason is that /RAS is no longer
held low during idle period.
Controller State Machine:
This DRAM controller is implemented as a Mealy
state machine and is programmed onto a Xilinx
PLD with 69 I/O pins. The state diagram on the
following page shows the flow of the design with
transitions from one state to another. Please refer
to the Abel source code for the output signals.
In the state of Read/Write within Page, the
controller can remain here to wait for the next
memory access or go to refresh the DRAM if
necessary.
Several states in the state machine are used merely
to hold /CAS or /RAS low or high in order to meet
the time specifications. Further optimization could
be done to speed up the design as discussed in a
later section.
Reset
Idle/Reset
(S0)
/MS0
RFQ
end of S7
/MS0,
(regardless of Page)
Page Swap
(S8..S10)
Refresh
(S1..S7)
/MS0, Page
RFQ
Read/Write
within Page
(S12)
end of S10
Read/Write
/MS0
after a Page Swap
(without Page)
(S11)
end of S11
else
remain
in S12
end of S15
Extending
Cas/Ras
(S13..S15)
Figure 6: DRAM Controller State Diagram
EE-44
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III.
Hardware Description
A prototype of this design has been built with the
layout shown in Figure 7 below.
On the left is the DRAM board with 2 major
components:
1. DRAM: This is placed along the long edge
close to the Sharc EZ-Kit Lite board so that
the lengths of the wires connected to the
Sharc EZ-Kit Lite board are minimized for
noise reduction purposes.
2. Xilinx PLD: This is the DRAM Controller.
The refresh timer and the mux’s are all
programmed onto this same PLD. The Abel
file attached with this document includes all
code and equations necessary to program
this PLD.
Other components include the following:
On the right is the Sharc EZ-KIT Lite board with
four external connectors shown in the figures. All
the signals shown in Figure 1: DRAM Interfacing
Block Diagram are available from these connectors.
This board runs on its own power supply. However,
common ground is needed between the two boards.
At least one thick wire should be used to make this
connection between the ground plane of the DRAM
board and the ground pin of the power connector to
the Sharc EZ-KIT Lite board.
Twisted pairs of wires are used for all data lines,
address lines, and control signals with the looping
wire grounded to reduce signal interference. Same
method is used for the clock signal but with thicker
wire.
1. A JTAG connector that allows the users to
easily program the PLD using a parallel
EZJTAG download cable from Xilinx.
2. An optional socket to hold the Xtal if an
external clock is used.
3. Power connector. An external power source
that can provide at least 1.5A must be used
to satisfy the demand of the DRAM.
Figure 8: Twisted Pair of
Wires
DRAM
(MT8D432M-6x)
External
power
source
J1
Optional
Xtal Clock
J6
SHAR
J3
EZ-ICE
Connector
Sharc EZ-Kit
Lite External
Connectors
Xilinx
Xilinx
JTAG
Connector
J21
Xilinx PLD
(XC9510810PC84)
Common
Ground
Power to
Sharc EZKIT
Figure 7: Components and Board Layout
EE-44
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Each VDD pin on the DRAM and the PLD has two
decoupling capacitors of .02uF and 1.0uF in
parallel. On the pin where the power supply is
brought into the board, two capacitors of .1uF and
22uF are used.
Note that on the Sharc EZ-KIT Lite board, there is
an EZ-ICE connector which allows the users to
attach an EZ-ICE and use this emulator to debug
the DRAM Controller.
IV.
Possible Design Modifications and
Improvement
*** Important Notes about This Design ***
However, the DRAM Controller has only been
tested with a 40Mhz clock taken from the Sharc EZKIT Lite board. This means there are two possible
improvements for speed.
1.
60 Mhz clock is used:
In this Design we use an external EPSON
Americana 60 Mhz Oscilator(SG-615PCV) in
addition to the other hardware to make the
controller function faster. In the Appendix of this
EE Note we provide
App. 1.
App. 2.
App. 3.
App. 4.
2.
Abel Source Code: consists of
equations to implement the refresh
timer, mux’ , and the state machine for
the controller. The Abel code has been
synthesized and fitted using the
Foundations Series Tool Suite
Schematics: is drawn using OrCAD.
J1, J3, and J6 are the actual
connectors on the Sharc EZ-Kit Lite
board.
Layout
Overall Layout
It is also recommended to optimize the logic of the
state-machine for better performance, especially
those states that extend the /CAS and /RAS control
signals.
Of course, another solution to this design problem
would be changing the entire approach to a more
effective method. If the controller is run at a fast
clock speed, it is possible just to program waitstates
on the SHARC and not use the ACK signal at all. If
a refresh request occurs during a burst of write or
read cycles, the controller may assert the Suspend
Bus Tri-State (/SBTS) signal to halt the dsp, and
then service the refresh. This way the SHARC will
not occupy the address bus and data bus while the
controller is refreshing the DRAM. If there are
other external devices to the system, these devices
may make use of the bus while the dsp is halting.
/SBTS may also be used during a page swapping
cycle. The controller latches in the new row address
before asserting /SBTS. When the address lines of
the dsp become tri-stated, the controller puts back
the row address onto the bus and asserts /RAS to
update the page in the DRAM. Then, it releases
/SBTS to continue the memory access normally.
V.
Conclusion
This design has been tested to work quite
successfully. However, this is not the optimal
design as far as speed is concerned. Once in a
while, it is still subjective to noise, especially when
all or most of the data lines switch to high at the
same time causing a few glitches on some control
signals. If someone tries to duplicate this process, it
is recommended that further measures be taken to
clean out such noises. For example, putting a
capacitor and a resistor (with calculated values) in
series near input pins to the Sharc might help
reduce reflection on these transmission lines.
66Mhz or higher clock is used:
If a faster external clock is used as originally
intended for this design, then other considerations
have to be taken into account. The immediate
benefit would be speed. However, there will be
timing issues such as making Ack meet the setup
and hold time so that the Sharc can sample
correctly. Another potential problem is that
running a 66Mhz will introduce more noise to the
system, especially for a wire-wrapping board.
EE-44
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Dramctrl
MODULE DramCtrl
title 'Dram Controller';
"Input signals"
Reset_
DramClkin
pin 81
pin 9
istype 'reg';
istype 'reg'; "Ext 60MHz Cloc
MS0_
RD_
WR_
Page
A00,A01,A02,A03,A04
A05,A06,A07,A08,A09,A10
A11,A12,A13,A14,A15
A16,A17,A18,A19,A20,A21
pin
pin
pin
pin
pin
pin
pin
pin
istype
istype
istype
istype
istype
istype
istype
istype
k
"Input/Output"
RFQ
ut to Controller's Input"
RFC
Output to Timer's Input"
"Output signals"
RAS_
CAS_
WR_DRAM_
Ack
be in sync with SHARC Clk
MuxSel
: ColAddr
Y00,Y01,Y02,Y03,Y04
Y05,Y06,Y07,Y08,Y09,Y10
q0, q1, q2, q3
State Machine
t0, t1, t2, t3, t4
t5, t6, t7, t8, t9
53
36
35
33
80,79,77,76,75
74,72,71,70,69,68
67,66,65,63,62
61,58,57,56,55,54
'reg';
'reg';
'reg';
'reg';
'com';
'com';
'com';
'com';
pin 50
istype 'reg';
"Timer's Outp
pin 51
istype 'reg';
"Controller's
pin
pin
pin
pin
istype
istype
istype
istype
24
25
26
34
'reg';
'reg';
'reg';
'reg';
"Ack needs to
pin 52
istype 'reg';
"H: RowAddr; L
pin 11,12,13,14,15
pin 17,18,20,21,23,19
pin 43,44,45,46
istype 'com';
istype 'com';
istype 'reg';
"Variables for
pin 82,83,84,1,2
pin 3,4,5,6,7
istype 'reg';
istype 'reg';
xepld property 'FAST ON'; "Special Setting for Xilinx CPLD
declarations
S0 =
S4 =
S8 =
S12 =
[0,0,0,0];
[0,1,0,0];
[1,0,0,0];
[1,1,0,0];
S1
S5
S9
S13
=
=
=
=
[0,0,0,1];
[0,1,0,1];
[1,0,0,1];
[1,1,0,1];
S2
S6
S10
S14
=
=
=
=
[0,0,1,0];
[0,1,1,0];
[1,0,1,0];
[1,1,1,0];
S3
S7
S11
S15
=
=
=
=
[0,0,1,1];
[0,1,1,1];
[1,0,1,1];
[1,1,1,1];
"Intermediate variables
"use the following line for actual code : cnt_ref = 930;
CNT_REF = t9 & t8 & t7 & !t6 & t5 & !t4 & !t3 & !t2 & t1 & !t0;
"use the following line for simulation : cnt_ref = 31;
"CNT_REF = !t9 & !t8 & !t7 & !t6 & !t5 & t4 & t3 & t2 & t1 & t0;
count = [t9,t8,t7,t6,t5,t4,t3,t2,t1,t0];
lowerAddr = [A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00];
upperAddr = [A21,A20,A19,A18,A17,A16,A15,A14,A13,A12,A11];
fsmState = [q3,q2,q1,q0];
SCLR = !Reset_ # CNT_REF;
C,H,L,Z = .C.,1,0,.Z.;
equations
App. 1-1
Dramctrl
[q3,q2,q1,q0].clk = DramClkin;
[RAS_,CAS_,WR_DRAM_,Ack].clk = DramClkin;
[RFQ,RFC].clk = DramClkin;
[MuxSel].clk = !DramClkin;
[t0,t1,t2,t3,t4,t5,t6,t7,t8,t9].clk = DramClkin;
Ack.oe=Reset_; " This is used to disable Ack when EZ-Kit Lite is booting.
"This reset is separate from Sharc Reset. This is a temporary
"work around. So that the UART and the DRAM don't conflict.
"Below
t0 :=
t1 :=
t2 :=
t3 :=
t4 :=
t5 :=
t6 :=
t7 :=
t8 :=
t9 :=
is the refresh timer:
(!t0) & !SCLR;
(t1 $ t0) & !SCLR;
(t2 $ (t1 & t0)) & !SCLR;
(t3 $ (t2 & t1 & t0)) & !SCLR;
(t4 $ (t3 & t2 & t1 & t0)) & !SCLR;
(t5 $ (t4 & t3 & t2 & t1 & t0)) & !SCLR;
(t6 $ (t5 & t4 & t3 & t2 & t1 & t0)) & !SCLR;
(t7 $ (t6 & t5 & t4 & t3 & t2 & t1 & t0)) & !SCLR;
(t8 $ (t7 & t6 & t5 & t4 & t3 & t2 & t1 & t0)) & !SCLR;
(t9 $ (t8 & t7 & t6 & t5 & t4 & t3 & t2 & t1 & t0)) & !SCLR;
RFQ := !RFC & ((CNT_REF # RFQ.FB) & Reset_);
"Shown here is the Multiplexer for Row and Column Addresses.
Y00 = (A00 & !MuxSel ) # (A11 & MuxSel);
Y01 = (A01 & !MuxSel ) # (A12 & MuxSel);
Y02 = (A02 & !MuxSel ) # (A13 & MuxSel);
Y03 = (A03 & !MuxSel ) # (A14 & MuxSel);
Y04 = (A04 & !MuxSel ) # (A15 & MuxSel);
Y05 = (A05 & !MuxSel ) # (A16 & MuxSel);
Y06 = (A06 & !MuxSel ) # (A17 & MuxSel);
Y07 = (A07 & !MuxSel ) # (A18 & MuxSel);
Y08 = (A08 & !MuxSel ) # (A19 & MuxSel);
Y09 = (A09 & !MuxSel ) # (A20 & MuxSel);
Y10 = (A10 & !MuxSel ) # (A21 & MuxSel);
state_diagram [q3,q2,q1,q0];
"******************Idle/Reset State*********************
State S0:
IF (!Reset_)
THEN S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE IF (RFQ)
THEN S1 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE IF (!MS0_)
THEN S8 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE
Goto S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
"******************Refreshing states********************
State S1:
IF (!Reset_)
THEN S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE
Goto S2 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
State S2:
IF (!Reset_)
THEN S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
App. 1-2
Dramctrl
ELSE
Goto S3 WITH {RAS_ := 1; CAS_ := 0; WR_DRAM_ := 1;}
State S3:
IF (!Reset_)
THEN S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE
Goto S4 WITH {RAS_ := 0; CAS_ := 0; WR_DRAM_ := 1;}
State S4:
IF (!Reset_)
THEN S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE
Goto S5 WITH {RAS_ := 0; CAS_ := 1; WR_DRAM_ := 1;}
State S5:
IF (!Reset_)
THEN S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE
Goto S6 WITH {RAS_ := 0; CAS_ := 1; WR_DRAM_ := 1;}
State S6:
IF (!Reset_)
THEN S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE
Goto S7 WITH {RAS_ := 0; CAS_ := 1; WR_DRAM_ := 1; RFC := 1;}
State S7:
IF (!Reset_)
THEN S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE IF (!MS0_)
THEN S8 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE
Goto S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
"*****************PageSwap State*****************************
State S8:
IF (!Reset_)
THEN S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE
Goto S9 WITH {MuxSel := 1; RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
State S9:
IF (!Reset_)
THEN S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE
Goto S10 WITH {MuxSel := 1; RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
State S10:
IF (!Reset_)
THEN S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE
Goto S11 WITH {MuxSel := 1; RAS_ := 0; CAS_ := 1; WR_DRAM_ := 1;}
State S11:
IF (!Reset_)
THEN S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE
Goto S12 WITH {MuxSel := 1; RAS_ := 0; CAS_ := 1; WR_DRAM_ := 1;}
"*****************Waiting for RD/WR State after PageSwap************
State S12:
App. 1-3
Dramctrl
IF (!Reset_)
THEN S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE IF (!RD_)
THEN S14 WITH {RAS_ := 0; CAS_ := 0; WR_DRAM_ := 1; Ack := 0;}
ELSE IF (!WR_)
THEN S14 WITH {RAS_ := 0; CAS_ := 0; WR_DRAM_ := 0; Ack := 0;}
ELSE
Goto S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
"*****************Waiting for RFQ or next mem access****************
State S13:
IF (!Reset_)
THEN S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE IF (RFQ)
THEN S1 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE IF (!MS0_ & Page)
THEN S8 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE IF (!MS0_ & !Page & !RD_)
THEN S14 WITH {RAS_ := 0; CAS_ :=0; WR_DRAM_ := 1; Ack := 0;}
ELSE IF (!MS0_ & !Page & !WR_)
THEN S14 WITH {RAS_ := 0; CAS_ :=0; WR_DRAM_ := 0; Ack := 0;}
ELSE
Goto S13 WITH {RAS_ := 0; CAS_ := 1; WR_DRAM_ := 1;}
"*****************Extending CAS/RAS State****************************
State S14:
IF (!Reset_)
THEN S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE IF (!RD_)
THEN S15 WITH {RAS_ := 0; CAS_ :=1; WR_DRAM_ := 1; Ack := 1;}
ELSE IF (!WR_)
THEN S15 WITH {RAS_ := 0; CAS_ :=1; WR_DRAM_ := 1; Ack := 1;}
ELSE
GOTO S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
State S15:
IF (!Reset_)
THEN S0 WITH {RAS_ := 1; CAS_ := 1; WR_DRAM_ := 1;}
ELSE
GOTO S13 WITH {RAS_ := 0; CAS_ := 1; WR_DRAM_ := 1; Ack := 0;}
END DramCtrl
App. 1-4
4
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
1
JP1
2
B
B
VDD
11
12
13
14
15
17
18
20
21
23
19
82
83
84
1
2
3
4
5
6
7
24
25
26
1
3
60
Mhz
OUT
OE
4
VDD
GND
Created:
Modified:
C
C
Y1
Clock
CAS0*
CAS1*
CAS2*
CAS3*
RAS0*
RAS2*
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PRD2
PRD3
PRD4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
U1
VDD
12
13
14
15
16
17
18
28
31
32
19
11
29
33
35
36
37
38
45
46
48
66
71
68
69
70
44
34
40
43
41
42
47
D
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
2
4
6
8
20
22
24
26
49
51
53
55
57
61
63
65
3
5
7
9
21
23
25
27
50
52
54
56
58
60
62
64
CAS DWG NO
Dwg. Scale is:
E
DATA16
DATA17
DATA18
DATA19
DATA20
DATA21
DATA22
DATA23
DATA24
DATA25
DATA26
DATA27
DATA28
DATA29
DATA30
DATA31
DATA32
DATA33
DATA34
DATA35
DATA36
DATA37
DATA38
DATA39
DATA40
DATA41
DATA42
DATA43
DATA44
DATA45
DATA46
DATA47
Sheet:
E
1
1.0
of
2
Revision
NOTE: The Jumper is placed so that the Controller can be set
in reset state while the SHARC EZKIT LITE uses the ACK
signal. In other words the ACK of UART will not conflict
with ACK of Controller. If jumper isn't used the SHARC
EZ-ICE program will still work; simply connect Reset of
controller with reset of EZKIT LITE.
DRAM
MT8D432M-6X
DRAM Controller
DRAM
WE*
C.K.P.
Controller
CAGE Code
Internal
D
ControllerSchematic.dsn
Schematic File Name:
A
Size
C.K.P.
Monday, December 08, 1997
Tuesday, June 30, 1998
Approved By:
Checked By:
Drafted By:
Designed By:
2
JUMPER
VDD
ACK
Y00
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
RAS*
CAS*
WR_DRAM*
43
44
45
46
HW DEVELOPMENT TOOLS ENG.
Q0
Q1
Q2
Q3
Controller
34
A
U2
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
RFQ
RFC
MUXSEL
TDI
TDO
TMS
TCK
ACK
P A G E W R * R D *MS0*
80
79
77
76
75
74
72
71
70
69
68
67
66
65
63
62
61
58
57
56
55
54
50
51
52
28
59
29
30
22
38
64
73
78
GND
GND
GND
GND
GND
GND
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR20
ADDR21
TDI
TDO
TMS
TCK
Controller
VCC
VCC
VCC
VCC
VCC
Analog Devices
Computer Products Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
PRD1
81
8
16
27
42
49
60
3
2
1
A
67
RESET*
10
30
59
VSS
VSS
VSS
9
DRAMCLKIN
TIE
TIE
TIE
TIE
TIE
TIE
TIE
TIE
TIE
VCC
VCC
VCC
1
72
39
33
35
36
53
PAGE
WR*
RD*
MS0*
10
31
32
37
39
40
41
47
48
4
3
2
1
4
3
2
1
MS0*
ADDR20
ADDR18
ADDR16
ADDR13
ADDR11
ADDR10
ADDR8
ADDR5
ADDR3
ADDR1
GND
TMS
TDI
TDO
TCK
A
A
J3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
GND
VDD
TCK
TDI
TDO
TMS
J5
HEADER 25X2
VDD
17
13
11
7
3
1
VDD
B
ADDR21
ADDR19
ADDR17
ADDR15
ADDR14
ADDR12
ADDR9
ADDR7
ADDR6
ADDR4
ADDR2
ADDR0
Xilinx Jtag Header
DATA43
DATA45
DATA47
PAGE
RD*
HW DEVELOPMENT TOOLS ENG.
B
Analog Devices
Computer Products Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
J1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
C
VDD
DATA42
DATA44
DATA46
ACK
WR*
D
DATA18
DATA20
DATA21
DATA23
DATA26
DATA28
DATA30
DATA32
DATA35
DATA37
DATA39
GND
C.K.P.
CAGE Code
DRAM Controller
Internal
Connectors
Size
D
ControllerSchematic.dsn
Schematic File Name:
A
C.K.P.
HEADER 20X2
Designed By:
Drafted By:
Checked By:
Tuesday, December 09, 1997
Tuesday, June 30, 1998
Approved By:
Created:
Modified:
C
J6
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
HEADER 25X2
CAS DWG NO
Dwg. Scale is:
VDD
E
DATA16
DATA17
DATA19
2
DATA22
DATA24
DATA25
DATA27
DATA29
DATA31
DATA33
DATA34
DATA36
DATA38
DATA40
DATA41
Sheet:
E
1.0
2
Revision
of
4
3
2
1
J3
L I T E
SHARC
E Z - K I T
E P R O M
U 7
S H A R C
J1
a
J6
J6
L O O K
A T
A d d r [ 0 : 1 0 ]
F O R
P i n 3
6 0 M H Z
C L K
J T A G
H e a d e r
S i d e
S i g n a l s
B o t t o m o f
S o l d e r
X i l i n x
C P L D
B o t t o m o f
C h i p
A H 1 & A H 2
S i m m
J3
t o
C P L D
B F 1 & B F 2
C o n n e c t e d
t o
C O N N E C T I O N S .
C o n n e c t e d
P I N O U T
P L A N E
E X A C T
R A S * , C A S * , W E *
J1
T A B L E
D R A M S i m m M o d u l e
B o t t o m V i e w
G R O U N D
A C 1 9 & A D 1 9
Y [ 0 : 1 0 ]
A G 4 2 & A G 4 3
B E 4 2 & B E 4 3
P L E A S E
A C 3 8 & A D 3 8
A H 1 & A H 2
B F 1 & B F 2
J3
P L E A S E
T o p
o f
L O O K
J T A G
H e a d e r
J1
o f
E X A C T
B o t t o m
F O R
1 1
6 0 M H Z
C L K
T A B L E
1
T o p o f
C h i p
X i l i n x
C P L D
A T
A C 1 9 & A D 1 9
V O L T A G E
H e a d e r
E n d
A C 3 8 & A D 3 8
J6
A G 4 2 & A G 4 3
B E 4 2 & B E 4 3
C O N N E C T I O N S .
S o l d e r
P I N O U T
P L A N E
E n d
S o l d e r
H e a d e r
o f
B o t t o m
V i e w
T o p
M o d u l e
S i m m
D R A M
E n d
S o l d e r
H e a d e r
o f
B o t t o m
S H A R C
T o p
E Z - K i t
B o a r d
i s
L i t e
t h e
i s
P r o t o
u p s i d e
B o a r d
d o w n
o n
f a c i n g
b o t t o m
u p .