-156. Explain why the following CMOS layout design rules are needed?
(15 pts)
Ans. The CMOS process layout design rules are derived from considerations of process
tolerances, mask alignment tolerances, yield expectation, and reliability requirements.
a. Minimum poly width R3:
R3 is needed to prevent open poly lines as well as to control the minimum Leff of
transistors. The minimum poly line width becomes the Lmask dimension for a minimum
L transistor. Leff is given by Lmask – L, where L = 2x the lateral diffusion of the
source and drain junctions plus any additional etching bias of the poly line.
b. Minimum poly spacing R4:
R4 is needed in order to prevent adjacent poly lines from shorting together. If the poly
spacing is too small, the space will not etch out completely and will leave polysilicon
material behind which will cause the adjacent lines to short together.
c. Minimum gate extension of poly over active R5:
R5 is required in order to prevent a shorted path connecting between source and drain in
the event of mask misalignment and other process tolerances (poly overetch, for
example). Such a shorted path between source and drain turns the expected FET device
into simply a thin gate oxide capacitor.
d. Minimum contact size R10 or R15:
R10 and R15 are required in order to make sure the contact openings completely etch out
and completely fill with metal. If R10 or R15 are too small, the contact openings will not
fully open, and the metal wire on top will not connect to the diffusion or poly underneath,
or may cause a high resistance contact.
e. Minimum metal width R8:
A minimum metal line width rule R8 is required in order to prevent open circuits due to
necking down of the lines. Process tolerances such as etching and mask image tolerances
may cause the wire to neck down, as well as small particles (dirt) in the photoresist
process. Such necking of the wire width can easily cause an open circuit in the wire.
f. Minimum metal space R9:
R9 is needed to prevent shorts occurring between adjacent parallel lines built on Metal 1
(or any metal level). Due to normal process tolerances, the metal etching process may
fail to remove all the metal between two adjacent wires if the space is too small.
g. Minimum N-well to N active spacing:
This is needed to keep N+ sources and drains spaced sufficiently far enough away from
any N-well region (normally biased at Vdd). This will aid in preventing punch-through
between an N+ region and the N-well, as well as reducing the susceptibility to latchup.