1100 MHz Variable Gain Amplifiers and
Baseband Programmable Filters
ADRF6518
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Matched pair of programmable filters and triple VGAs
Continuous gain control range: 72 dB
Digital gain control: 30 dB
Filter bypass mode bandwidth (BW)
±1 dB gain flatness: 300 MHz
−3 dB small signal bandwidth: 650 MHz/1100 MHz, VGA2
and VGA3 21 dB/12 dB, respectively
6-pole Butterworth filter: 1 MHz to 63 MHz
in 1 MHz steps, 0.5 dB corner frequency
Peak detector
IMD3: >65 dBc for 1.5 V p-p composite output
HD2, HD3: >65 dBc for 1.5 V p-p output
Differential input and output
Flexible output and input common-mode ranges
Optional dc output offset correction
SPI programmable filter corners and gain steps
Single 3.3 V supply operation with power-down feature
ENBL INP1
APPLICATIONS
INM1
VPS RAVG VGN1 OFS1 VPS
ADRF6518
VPSD
OPP1
COMD
OPM1
LE
COM
VGN3
CLK
SPI
VOCM
DATA
SDO/RST
COM
VICM/AC
OPM2
VPI
OPP2
COM
INP2
INM2
VPS
VPK VGN2 OFS2 VPS
Figure 1
Point-to-point and point-to-multipoint radios
Baseband IQ receivers
Diversity receivers
ADC drivers
Instrumentation
Medical
GENERAL DESCRIPTION
The ADRF6518 is a matched pair of fully differential low noise and
low distortion programmable filters and variable gain amplifiers
(VGAs). Each channel is capable of rejecting large out-of-band
interferers while reliably boosting the wanted signal, thus reducing
the bandwidth and resolution requirements on the analog-todigital converters (ADCs). The excellent matching between
channels and their high spurious-free dynamic range over all
gain and bandwidth settings make the ADRF6518 ideal for
quadrature-based (IQ) communication systems with dense
constellations, multiple carriers, and nearby interferers. The
various amplifier gains, filter corners and other features are all
programmable via a serial port interface (SPI) port.
The first VGA that precedes the filters offers 24 dB of continuous
gain control with fixed gain options of 9 dB, 12 dB, and 15 dB, and
sets a differential input impedance of 400 Ω. The filters provide
a six-pole Butterworth response with 0.5 dB corner frequencies
from 1 MHz to 63 MHz in 1 MHz steps. For operation beyond
63 MHz, the filter can be disabled and completely bypassed,
thereby extending the −3 dB BW up to 1100 MHz. A wideband
Rev. 0
peak detector is available to monitor the peak signal at the filter
inputs. The pair of VGAs that follow the filters each provides
24 dB of continuous gain control with fixed gain options of
12 dB, 15 dB, 18 dB, and 21 dB. The output buffers offer an
additional option of 3 dB or 9 dB gain and provide a differential
output impedance of less than 10 Ω. They are capable of driving
1.5 V p-p into 400 Ω loads at better than 65 dBc HD3. The output
common-mode voltage defaults to VPS/2 and can be adjusted
down to 900 mV via the VOCM pin. Independent, built-in dc
offset correction loops for each channel can be disabled via the
SPI if fully dc-coupled operation is desired. The high-pass
corner frequency is determined by external capacitors on the
OFS1 and OFS2 pins and the postfilter VGA gain.
The ADRF6518 operates from a 3.15 V to 3.45 V supply and
consumes a maximum supply current of 400 mA. When fully
disabled, it consumes <1 mA. The ADRF6518 is fabricated in an
advanced silicon-germanium BiCMOS process and is available in a
32-lead, exposed pad LFCSP. Performance is specified over the
−40°C to +85°C temperature range.
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Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
11449-001
Data Sheet
ADRF6518
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Maximizing the Dynamic Range ............................................. 25
Applications ....................................................................................... 1
Key Parameters for Quadrature-Based Receivers .................. 25
Functional Block Diagram .............................................................. 1
Applications Information .............................................................. 26
General Description ......................................................................... 1
Basic Connections ...................................................................... 26
Revision History ............................................................................... 2
Supply Decoupling ..................................................................... 26
Specifications..................................................................................... 3
Input Signal Path ........................................................................ 26
Timing Diagrams.......................................................................... 5
Output Signal Path ..................................................................... 26
Absolute Maximum Ratings............................................................ 6
DC Offset Compensation Loop Enabled ................................ 26
ESD Caution .................................................................................. 6
Common-Mode Bypassing ....................................................... 27
Pin Configuration and Function Descriptions ............................. 7
Serial Port Connections............................................................. 27
Typical Performance Characteristics ............................................. 8
Enable/Disable Function ........................................................... 27
Filter Mode .................................................................................... 8
Gain Pin Decoupling ................................................................. 27
Bypass Mode ............................................................................... 16
Peak Detector Connections ...................................................... 27
Mixed Power and Filter Modes................................................. 18
Error Vector Magnitude (EVM) Performance ........................... 27
Characterization ............................................................................. 19
EVM Test Setup .......................................................................... 27
Noise Figure Calculation ........................................................... 19
EVM Measurement .................................................................... 27
Register Map and Codes ................................................................ 20
EVM System Measurement....................................................... 29
Theory of Operation ...................................................................... 21
Effect of Filter BW on EVM...................................................... 31
Input VGAs ................................................................................. 21
Pull-Down Resistors for Disable Function ............................. 31
Peak Detector .............................................................................. 22
Instability at High Gain in Filter Bypass Mode ...................... 31
Programmable Filters................................................................. 22
Linear Operation of the ADRF6518......................................... 32
Variable Gain Amplifiers (VGAs) ............................................ 23
Evaluation Board ............................................................................ 33
Output Buffers/ADC Drivers ................................................... 23
Evaluation Board Control Software ......................................... 33
DC Offset Compensation Loop................................................ 23
Schematics and Artwork ........................................................... 34
Programming the ADRF6518 ................................................... 23
Outline Dimensions ....................................................................... 39
Noise Characteristics ................................................................. 24
Ordering Guide .......................................................................... 39
Distortion Characteristics ......................................................... 24
REVISION HISTORY
6/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 40
Data Sheet
ADRF6518
SPECIFICATIONS
VPS, VPI, VPSD = 3.3 V, TA = 25°C, ZLOAD = 400 Ω, power mode bit (B9) = 0 (low power mode), digital gain code bits (B8 to B2) =
0000001, and dc offset disable bit (B1) = 0 (enabled), unless otherwise noted.
Table 1.
Parameter
FREQUENCY RESPONSE, FILTER BYPASS MODE
±1 dB Gain Flatness Bandwidth
−3 dB Small Signal Bandwidth
FREQUENCY RESPONSE
Low-Pass Corner Frequency, fC
Step Size
Corner Frequency Absolute Accuracy
Corner Frequency Matching
Pass-Band Ripple
Gain Matching
Group Delay Variation
Corner Frequency = 1 MHz
Corner Frequency = 30 MHz
Group Delay Matching
Corner Frequency = 1 MHz
Corner Frequency = 30 MHz
Stop-Band Rejection
Relative to Pass Band
INPUT STAGE
Maximum Input Swing
Differential Input Impedance
Input Common-Mode Range, DC-Coupled
Mode
Input Common-Mode, AC-Coupled Mode
VICM/AC Input Impedance
PEAK DETECTOR
Output Scaling
Reset Threshold
GAIN CONTROL
Gain Range
Voltage Attenuation Range
Gain Slope
Gain Error
OUTPUT STAGE
Maximum Output Swing
Differential Output Impedance
Output DC Offset
Output Common-Mode Range
Test Conditions/Comments
Min
Max
300
650
1100
VGA2 and VGA3 21 dB digital gain setting
VGA2 and VGA3 12 dB digital gain setting
Six-pole Butterworth filter, 0.5 dB bandwidth
Typ
1
Over operating temperature range
Channel A and Channel B at same gain and
bandwidth settings
Channel A and Channel B at same gain and
bandwidth settings
From midband to peak
Unit
MHz
MHz
MHz
1
±8
±0.5
63
MHz
MHz
% fC
% fC
0.5
±0.1
dB p-p
dB
135
11
ns
ns
5
0.2
ns
ns
30
75
dB
dB
5.0
400
Channel A and Channel B at same gain
2 × fC
5 × fC
INP1, INM1, INP2, INM2, VICM/AC
At minimum gain, VGN1 = 0 V
1.5 V p-p input voltage, HD3 > 65 dBc (VPI = 3.3 V),
VICM/AC floating or logic high
1.5 V p-p input voltage, HD3 > 65 dBc (VPI = 5.0 V),
VICM/AC floating or logic high
VPI = 3.3 V to 5.0 V, VICM/AC = 0 V
VPK, RAVG, SDO/RST
Relative to peak voltage at filter input
Logic high duration > 25 ns
VGN1, VGN2, VGN3
Maximum digital gains
Minimum digital gains
Each attenuator; VGAIN from 0 V to 1 V
1.35
1.95
V p-p
Ω
V
1.35
3.1
V
VOCM Input Impedance
Rev. 0 | Page 3 of 40
V
kΩ
1
>2.0
V/V peak
V
−6
−36
−24
+66
+36
0
30
0.2
VGAIN from 300 mV to 800 mV
OPP1, OPM1, OPP2, OPM2, VOCM
At maximum gain, RLOAD = 400 Ω
HD2 > 65 dBc, HD3 > 65 dBc, RLOAD = 400 Ω
Inputs shorted, offset loop enabled
1.5 V p-p output voltage
VOCM left floating
VPS/2
7.75
3
1.5
<10
<20
0.9
VPS − 1.2
VPS/2
23
dB
dB
dB
mV/dB
dB
V p-p
V p-p
Ω
mV
V
V
kΩ
ADRF6518
Parameter
NOISE/DISTORTION
Corner Frequency = 63 MHz
Output Noise Density
Second Harmonic, HD2
Third Harmonic, HD3
IMD3
DIGITAL LOGIC
Input High Voltage, VHIGH
Input Low Voltage, VLOW
Input Current, IHIGH/ILOW
Input Capacitance, CIN
SPI TIMING
fCLK
tDH
tDS
tLH
tLS
tPW
tD
POWER AND ENABLE
Supply Voltage Range
Total Supply Current
Disable Current
Disable Threshold
Enable Response Time
Disable Response Time
Data Sheet
Test Conditions/Comments
Min
Minimum gain at fC/2
Maximum gain at fC/2
16 MHz fundamental, 1.5 V p-p Output Level
Gain = 6 dB
Gain = 54 dB
16 MHz fundamental, 1.5 V p-p Output Level
Gain = 6 dB
Gain = 54 dB
30 MHz and 31 MHz tones, 1.5 V p-p output level
Gain = 0 dB
Gain = 30 dB
Gain = 60 dB
LE, CLK, DATA, SDO
LE, CLK, DATA, SDO
1/tCLK
DATA hold time
DATA setup time
LE hold time
LE setup time
CLK high pulse width
CLK to SDO delay
VPS, VPSD, COM, COMD, ENBL
3.15
ENBL = 3.3 V
Maximum BW setting, high power filter
Minimum BW setting, low power filter
Filter bypassed, high power mode
Filter bypassed, low power mode
ENBL = 0 V, with pull-down resistors on output
Delay following ENBL low-to-high transition
Delay following ENBL high-to-low transition
Rev. 0 | Page 4 of 40
Typ
Max
Unit
−104.6
−104.3
dBV/Hz
dBV/Hz
65
65
dBc
dBc
82
81
dBc
dBc
60
80
80
dBc
dBc
dBc
>2
<0.8
<1
2
V
V
µA
pF
20
5
5
5
5
5
5
MHz
ns
ns
ns
ns
ns
ns
3.3
400
360
260
230
1
1.6
20
300
3.45
V
mA
mA
mA
mA
mA
V
µs
ns
Data Sheet
ADRF6518
TIMING DIAGRAMS
tCLK
tPW
CLK
tLH
tLS
LE
DATA
tDH
WRITE BIT
LSB
LSB + 1
LSB + 2
LSB + 3
MSB – 3
MSB – 2
MSB – 1
MSB- 2
MSB
NOTES
1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 16-BIT REGISTER. FOR A WRITE OPERATION,
THE FIRST BIT SHOULD BE A LOGIC 1. THE 16-BIT WORD IS THEN REGISTERED INTO THE DATA PIN ON CONSECUTIVE RISING EDGES OF THE CLOCK.
11449-002
tDS
Figure 2. Write Mode Timing Diagram
tPW
tCLK
tD
CLK
tLH
tLS
LE
DATA
SDO
tDH
READ BIT
DC
LSB
DC
LSB + 1
DC
LSB + 2
DC
DC
LSB + 3
MSB – 3
DC
MSB – 2
DC
MSB – 1
DC
MSB
NOTES
1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 16-BIT REGISTER. FOR A WRITE OPERATION, THE
FIRST BIT SHOULD BE A LOGIC 1. THE 16-BIT WORD IS THEN REGISTERED INTO THE DATA PIN ON CONSECUTIVE RISING EDGES OF THE CLOCK.
Figure 3. Read Mode Timing Diagram
Rev. 0 | Page 5 of 40
11449-003
tDS
ADRF6518
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltages, VPS, VPSD
VPI
ENBL, LE, CLK, DATA, SDO
INP1, INM1, INP2, INM2, VICM
OPP1, OPM1, OPP2, OPM2, VOCM
OFS1, OFS2, VPK, RAVG
VGN1, VGN2, VGN3
Internal Power Dissipation
θJA (Exposed Pad Soldered to Board)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
Rating
3.45 V
5.25 V
VPSD + 0.5 V
VPS + 0.5 V
VPS + 0.5 V
VPS + 0.5 V
VPS + 0.5 V
1.25 W
37.4°C/W
150°C
−40°C to +85°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 40
Data Sheet
ADRF6518
32
31
30
29
28
27
26
25
ENBL
INP1
INM1
VPS
RAVG
VGN1
OFS1
VPS
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADRF6518
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
OPP1
OPM1
COM
VGN3
VOCM
COM
OPM2
OPP2
NOTES
1. CONNECT THE EXPOSED PADDLE TO
A LOW IMPEDANCE GROUND PAD.
11449-004
COM
INP2
INM2
VPS
VPK
VGN2
OFS2
VPS
9
10
11
12
13
14
15
16
VPSD
COMD
LE
CLK
DATA
SDO/RST
VICM/AC
VPI
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
Mnemonic
VPSD
COMD
3
4
5
6
LE
CLK
DATA
SDO/RST
7
VICM/AC
8
VPI
9, 19, 22
COM
10, 11, 30, 31
INP2, INM2,
INM1, INP1
VPS
VPK
12, 16, 25, 29
13
14, 21, 27
15, 26
17, 18, 23, 24
20
28
32
VGN2, VGN3,
VGN1
OFS2, OFS1
OPP2, OPM2,
OPM1, OPP1
VOCM
RAVG
ENBL
EP
Description
Digital Positive Supply Voltage: 3.15 V to 3.45 V.
Digital Common. Connect this pin to an external circuit common using the lowest possible
impedance.
Latch Enable. SPI programming pin. TTL levels: VLOW < 0.8 V, VHIGH > 2 V.
SPI Port Clock. TTL levels: VLOW < 0.8 V, VHIGH > 2 V.
SPI Data Input. TTL levels: VLOW < 0.8 V, VHIGH > 2 V.
SPI Data Output (SDO). TTL levels: VLOW < 0.8 V, VHIGH > 2 V.
Peak Detector Reset (RST). A >25 ns high pulse is required on this pin to reset the detector.
Input Common-Mode Reference (VICM). VPI/2 reference output for optimal common-mode level
to drive the differential inputs. If this pin is used as a common-mode reference for the commonmode output of the previous stage, only connect high impedance nodes to this pin.
AC Coupling/Internal Bias Activation (AC). Pull this pin low for ac coupling of the inputs.
Input Stage Supply Voltage: 3.15 V to 5.25 V. Connect VPI to VPS if the input common-mode range
is narrow (1.35 V to 1.95 V). Connect VPI to 5 V if a common-mode input up to 3.1 V is desired.
Analog Common. Connect COM to an external circuit common using the lowest possible
impedance.
Differential Inputs, 400 Ω Differential Input Impedance.
Analog Positive Supply Voltage: 3.15 V to 3.45 V.
Peak Detector Output. Scaling of 1 V/V peak differential at filter inputs is performed, and the
bigger peak of two channels is reported.
VGA1, VGA2, and VGA3 Analog Gain Control. 0 V to 1 V, 30 mV/dB gain scaling.
Offset Correction Loop Compensation Capacitors. Connect capacitors to a circuit common.
Differential Outputs. These outputs have a <10 Ω output impedance. Common-mode range is 0.9
V to VPS − 1.2 V; default is VPS/2.
Output Common-Mode Setpoint. VOCM defaults to VPS/2 if left open.
Peak Detector Time-Constant Resistor. Connect this pin to VPS. Leave this pin open for the longest
hold time. The RAVG range is ∞ to 1 kΩ.
Chip Enable. Pull this pin high to enable the chip.
Exposed Ground Pad. Connect the exposed pad to a low impedance ground pad.
Rev. 0 | Page 7 of 40
ADRF6518
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
FILTER MODE
VPS, VPI, VPSD = 3.3 V, TA = 25°C, ZLOAD = 400 Ω, power mode bit (B9) = 0 (low power mode), digital gain code bits (B8 to B2) = 1111110,
dc offset disable bit (B1) = 0 (enabled), filter corner = 63 MHz, ac coupling mode, fundamental at 31 MHz, unless otherwise noted. For
HD2/HD3 vs. gain plots: 1.5 V p-p output target level, and reference Figure 67 for analog gain distribution.
4
0
3
–5
+25°C, VPS = 3.15V, 3.3V, 3.45V
2
–10
GAIN ERROR (dB)
–40°C, VPS = 3.15V, 3.3V, 3.45V
GAIN (dB)
–15
–20
–25
–40°C, VPS = 3.15V, 3.3V, 3.45V
1
0
–1
+25°C, VPS = 3.15V, 3.3V, 3.45V
–30
–2
–35
–3
+85°C, VPS = 3.15V, 3.3V, 3.45V
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VGN1 (V)
11449-005
–4
0
0
100
200
300
400
500
600
700
800
900
1000
VGN1 (mV)
Figure 5. In-Band Gain vs. VGN1 over Supply and Temperature
11449-008
+85°C, VPS = 3.15V, 3.3V, 3.45V
–40
Figure 8. Gain Error vs. VGN1 over Supply and Temperature
0
4
–5
3
+25°C, VPS = 3.15V, 3.3V, 3.45V
–10
2
GAIN ERROR (dB)
–40°C, VPS = 3.15V, 3.3V, 3.45V
GAIN (dB)
–15
–20
–25
–40°C, VPS = 3.15V, 3.3V, 3.45V
1
0
–1
+25°C, VPS = 3.15V, 3.3V, 3.45V
–30
–2
–35
–3
+85°C, VPS = 3.15V, 3.3V, 3.45V
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VGN2 (V)
–4
11449-006
0
0
100
200
300
400
500
600
700
800
900
1000
VGN2 (mV)
Figure 6. In-Band Gain vs. VGN2 over Supply and Temperature
11449-009
+85°C, VPS = 3.15V, 3.3V, 3.45V
–40
Figure 9. Gain Error vs. VGN2 over Supply and Temperature
4
0
3
–5
+25°C, VPS = 3.15V, 3.3V, 3.45V
2
–10
–40°C, VPS = 3.15V, 3.3V, 3.45V
GAIN ERROR (dB)
–40°C, VPS = 3.15V, 3.3V, 3.45V
–20
–25
1
0
–1
+25°C, VPS = 3.15V, 3.3V, 3.45V
–30
–2
–35
–3
+85°C, VPS = 3.15V, 3.3V, 3.45V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VGN3 (V)
–4
0
100
200
300
400
500
600
700
800
900
1000
VGN3 (mV)
Figure 10. Gain Error vs. VGN3 over Supply and Temperature
Figure 7. In-Band Gain vs. VGN3 over Supply and Temperature
Rev. 0 | Page 8 of 40
11449-010
+85°C, VPS = 3.15V, 3.3V, 3.45V
–40
11449-007
GAIN (dB)
–15
Data Sheet
ADRF6518
60
15
50
10
DIGITAL GAIN = 0000001
40
5
30
DIGITAL GAIN = 111110
0
OP1dB (dBV)
GAIN (dB)
20
10
0
–10
–5
–10
–15
–20
–20
–30
5
15
25
35
45
55
65
–30
–10
11449-011
–50
75
FREQUENCY (MHz)
0
10
20
30
40
50
GAIN (dB)
11449-014
–25
–40
Figure 14. OP1dB vs. Gain at a Fundamental of 16 MHz
Figure 11. Gain vs. Frequency over VGN1/VGN2/VGN3
–30
0
+85°C, VPS = 3.15V, 3.3V, 3.45V
+25°C, VPS = 3.15V, 3.3V, 3.45V
–40°C, VPS = 3.15V, 3.3V, 3.45V
BANDWIDTH = 63 MHz
–5
DIGITAL GAIN = 0000001
–10
–35
DIGITAL GAIN = 0000000
DIGITAL GAIN = 0000010
GAIN (dB)
GAIN (dB)
–15
DIGITAL GAIN = 0000100
–20
DIGITAL GAIN = 0000110
–25
DIGITAL GAIN = 0001110
–30
DIGITAL GAIN = 0011110
DIGITAL GAIN = 0010110
DIGITAL GAIN = 0111110
–35
–40
–45
DIGITAL GAIN = 1111110
5
10
15
20
25
30
35
40
45
50
55
60
FREQUENCY (MHz)
–50
11449-012
–45
3
13
23
33
43
53
63
73
83
93
103
FREQUENCY (MHz)
11449-015
–40
Figure 15. Frequency Response over Supply and Temperature;
VGN1/VGN2/VGN3 = 0 V, Filter Corners = 15 MHz, 30 MHz, and 60 MHz
Figure 12. Digital Gain vs. Frequency; VGN1/VGN2/VGN3 = 0 V
40
0.3
35
30
25
0.1
GAIN (dB)
GAIN MISMATCH (dB)
0.2
0
–0.1
20
15
10
5
0
–0.2
Figure 13. Gain Mismatch Between Channels vs. VGN1/VGN2/VGN3 Voltage
Rev. 0 | Page 9 of 40
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
FREQUENCY (MHz)
Figure 16. Gain vs. Frequency over BW Setting (Linear);
VGN1/VGN2/VGN3 = 0 V
11449-016
1/1/1
–10
11449-013
1/1/0.8
1/1/0.6
1/1/0.4
1/1/0
VGN1/VGN2/VGN3 (V)
1/1/0.2
1/0.8/0
1/0.6/0
1/0.4/0
1/0/0
1/0.2/0
0.8/0/0
0.6/0/0
0.4/0/0
0/0/0
–0.3
0.2/0/0
–5
ADRF6518
Data Sheet
31
10
8
6
GROUP DELAY (ns)
GAIN (dB)
30
29
4
2
0
–2
BANDWIDTH = 15MHz
BANDWIDTH = 7MHz
–4
28
–6
11
21
31
41
51
11449-017
1
–10
61
FREQUENCY (MHz)
2
Figure 17. Gain vs. Frequency over BW Setting (Linear); Scaled to Show
Peaking
35
4
30
3
GROUP DELAY MISMATCH (ns)
5
15
10
5
0
–5
10 12
14 16
18
FREQUENCY (MHz)
20
22
24
2
1
0
–1
BANDWIDTH = 30MHz
BANDWIDTH = 60MHz
–2
–3
10
100
FREQUENCY (MHz)
–5
11449-117
1
5
Figure 18. Gain vs. Frequency over BW Setting (Log);
VGN1 = 1 V, VGN2 = 0.7 V, VGN3 = 0.75 V
15
25
35
45
FREQUENCY (MHz)
55
65
11449-120
–4
–10
Figure 21. IQ Group Delay Mismatch vs. Frequency
(BW = 30 MHz and BW = 60 MHz)
0
0.2
0.4
FREQUENCY (MHz)
0.6
0.8
1.0
1.2
50
60
0.50
100
BANDWIDTH = 7MHz
0.40
80
0.30
70
0.20
MISMATCH (dB)
90
60
50
BANDWIDTH = 15MHz
40
0.10
0.00
BANDWIDTH = 63MHz
BANDWIDTH = 1MHz
–0.10
–0.20
30
BANDWIDTH = 30MHz
–0.30
20
BANDWIDTH = 60MHz
–0.40
10
0
2
20
FREQUENCY (MHz)
Figure 19. Group Delay vs. Frequency; VGN1/VGN2/VGN3 = 0 V
–0.50
11449-118
GROUP DELAY (ns)
8
0
10
20
30
40
FREQUENCY (MHz)
11449-121
GAIN (dB)
20
6
Figure 20. IQ Group Delay Mismatch vs. Frequency
(BW = 7 MHz and BW = 15 MHz)
40
25
4
11449-119
–8
27
Figure 22. IQ Amplitude Mismatch vs. Frequency; VGN1/VGN2/VGN3 = 0 V
Rev. 0 | Page 10 of 40
Data Sheet
ADRF6518
50
–95
15dB
12dB
9dB
–96
35
30
25
20
–98
–99
–100
–101
–102
–103
–104
–105
–106
63MHz
32MHz
16MHz
8MHz
4MHz
2MHz
–107
–108
15
–109
0
100
200
300
400
500
600
700
800
900
1000
VGN1 (mV)
Figure 23. Noise Figure vs. VGN1 over VGA1 Digital Gain; Noise Density
Measured at Half of Filter Corner
55
200
300
400
500
600
700
800
900
1000
Figure 26. Output Noise Density vs. VGN1 over Bandwidth Setting;
Digital Gain = 0000001, Noise Density Measured at Half of Filter Corner
–105
40
35
30
25
20
15
GAIN = 60dB
–110
–115
–120
–125
GAIN = 40dB
–130
–135
–140
GAIN = 20dB
100
200
300
400
500
600
700
800
900
1000
VGN1 (mV)
Figure 24. Noise Figure vs. VGN1 over Filter Corner;
Digital Gain = 0000001, Noise Density Measured at Half of Filter Corner
–100
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
FREQUENCY (MHz)
Figure 27. Output Noise Density vs. Frequency; Filter Corner = 7 MHz,
Digital Gain = 0000001, Noise Density Measured at Half of Filter Corner
–100
15dB
12dB
9dB
–105
OUTPUT NOISE DENSITY (dBV/Hz)
–101
–150
11449-023
0
11449-026
–145
10
–102
–103
–104
–105
–106
–107
–108
GAIN = 60dB
–110
–115
–120
GAIN = 40dB
–125
–130
–135
GAIN = 20dB
–140
–109
–110
0
100
200
300
400
500
600
700
800
900
1000
VGN1 (mV)
Figure 25. Output Noise Density vs. VGN1 over VGA1 Digital Gain;
Noise Density Measured at Half of Filter Corner
–145
11449-024
OUTPUT NOISE DENSITY (dBV/Hz)
100
VGN1 (mV)
OUTPUT NOISE DENSITY (dBV/Hz)
NOISE FIGURE (dB)
45
0
–100
63MHz
32MHz
16MHz
8MHz
4MHz
2MHz
50
–110
11449-022
0
0
20
40
60
80
100
120
FREQUENCY (MHz)
140
160
180
200
11449-027
NOISE FIGURE (dB)
40
–97
11449-025
OUTPUT NOISE DENSITY (dBV/Hz)
45
Figure 28. Output Noise Density vs. Frequency; Filter Corner = 60 MHz,
Digital Gain = 0000001
Rev. 0 | Page 11 of 40
ADRF6518
Data Sheet
90
100
80
90
80
50
40
+25°C, VPS = 3.30V
+25°C, VPS = 3.15V
+25°C, VPS = 3.45V
+85°C, VPS = 3.30V
+85°C, VPS = 3.15V
+85°C, VPS = 3.45V
–40°C, VPS = 3.30V
–40°C, VPS = 3.15V
–40°C, VPS = 3.45V
30
20
10
–6
0
6
12
18
24
30
36
42
48
54
30
60
0
–6
6
12
18
24
30
36
42
48
54
60
66
Figure 32. HD3 vs. Gain over Supply and Temperature; 16 MHz Fundamental
Tone, Digital Gain = 0000001
90
90
80
80
70
HD2 AT 32MHz (dBc)
70
60
50
+25°C, VPS = 3.30V
+25°C, VPS = 3.15V
+25°C, VPS = 3.45V
+85°C, VPS = 3.30V
+85°C, VPS = 3.15V
+85°C, VPS = 3.45V
–40°C, VPS = 3.30V
–40°C, VPS = 3.15V
–40°C, VPS = 3.45V
20
10
–6
0
6
12
18
24
30
36
42
48
54
60
50
40
30
20
VOCM = 0.90V
VOCM = 1.25V
VOCM = 1.65V
VOCM = 1.95V
10
60
GAIN (dB)
0
–6
0
6
12
18
24
30
36
42
48
54
60
66
GAIN (dB)
Figure 30. HD3 vs. Gain over Supply and Temperature; 16 MHz Fundamental
Tone, Digital Gain = 0000000
11449-031
30
11449-129
40
Figure 33. HD2 vs. Gain over VOCM; 16 MHz Fundamental Tone,
Digital Gain = 0000001
90
100
80
90
80
HD3 AT 48MHz (dBc)
70
60
50
40
+25°C, VPS = 3.30V
+25°C, VPS = 3.15V
+25°C, VPS = 3.45V
+85°C, VPS = 3.30V
+85°C, VPS = 3.15V
+85°C, VPS = 3.45V
–40°C, VPS = 3.30V
–40°C, VPS = 3.15V
–40°C, VPS = 3.45V
20
10
0
6
12
18
24
30
36
GAIN (dB)
42
48
54
60
70
60
50
40
30
VOCM = 0.90V
VOCM = 1.25V
VOCM = 1.65V
VOCM = 1.95V
20
10
66
11449-030
30
0
–6
0
GAIN (dB)
100
0
–12
+25°C, VPS = 3.30V
+25°C, VPS = 3.15V
+25°C, VPS = 3.45V
+85°C, VPS = 3.30V
+85°C, VPS = 3.15V
+85°C, VPS = 3.45V
–40°C, VPS = 3.30V
–40°C, VPS = 3.15V
–40°C, VPS = 3.45V
40
10
Figure 29. HD2 vs. Gain over Supply and Temperature; 16 MHz Fundamental
Tone, Digital Gain = 0000000
HD3 AT 48MHz (dBc)
50
20
GAIN (dB)
HD2 AT 32MHz (dBc)
60
Figure 31. HD2 vs. Gain over Supply and Temperature; 16 MHz Fundamental
Tone, Digital Gain = 0000001
Rev. 0 | Page 12 of 40
0
–6
0
6
12
18
24
30
36
42
48
54
60
66
GAIN (dB)
Figure 34. HD3 vs. Gain over VOCM; 16 MHz Fundamental Tone,
Digital Gain = 0000001
11449-131
0
–12
70
11449-130
HD3 AT 48MHz (dBc)
60
11449-029
HD2 AT 32MHz (dBc)
70
Data Sheet
ADRF6518
90
50
80
45
40
70
35
60
30
OIP3 (dBV)
50
40
25
20
30
15
0
0.02
10
VGA1 = 9dB, VGN1 = 0V
VGA1 = 9dB, VGN1 = 1V
VGA1 = 15dB, VGN1 = 0V
VGA1 = 15dB, VGN1 = 1V
10
0.04
0.06
0.09
0.14
0.23
0.36
0.57
0.90
+25°C
+85°C
–40°C
5
1.14
VGA1 OUTPUT SIGNAL LEVEL (V p-p)
0
–6
0
6
12
18
24
30
36
42
48
54
60
66
GAIN (dB)
Figure 35. HD2 vs. VGA1 Output Signal Level (Inferred);
16 MHz Fundamental Tone, VGN2/VGN3 = 0 V
11449-135
20
11449-032
HD2 AT 32MHz (dBc)
DIGITAL GAIN = 0000001
Figure 38. In-Band OIP3 vs. Gain over Temperature;
30 MHz and 31 MHz Tones, Digital Gain = 0000001
100
120
90
100
70
80
IMD3 (dBc)
60
50
40
60
40
20
VGA1 = 9dB, VGN1 = 0V
VGA1 = 9dB, VGN1 = 1V
VGA1 = 15dB, VGN1 = 0V
VGA1 = 15dB, VGN1 = 1V
10
0
0.02
0.04
0.06
0.09
0.14
0.23
0.36
0.57
0.90
GAIN = 40
GAIN = 30
GAIN = 20
GAIN = 10
GAIN = 0
20
1.14
VGA1 OUTPUT SIGNAL LEVEL (V p-p)
0
0.5
0.6
0.9
1.3
1.8
2.5
3.6
11449-036
30
11449-132
HD3 AT 48MHz (dBc)
80
4.5
COMPOSITE OUTPUT VOLTAGE (V p-p)
Figure 36. HD3 vs. VGA1 Output Signal Level (Inferred);
16 MHz Fundamental Tone, VGN2/VGN3 = 0 V
Figure 39. In-Band IMD3 vs. Composite Output Voltage over Gain;
30 MHz and 31 MHz Tones , Digital Gain = 1111110
50
110
100
DIGITAL GAIN = 0000001
40
90
80
30
DIGITAL GAIN = 111110
10
60
50
GAIN = 66
GAIN = 60
GAIN = 50
GAIN = 40
GAIN = 30
GAIN = 30
GAIN = 20
GAIN = 10
GAIN = 0
GAIN = –5
40
0
30
20
–10
–20
–20
–10
0
10
20
GAIN (dB)
30
40
50
60
11449-035
10
Figure 37. In-Band OIP3 vs. Gain over Digital Gain; 1.5 V p-p Composite
Output Target, 30 MHz and 31 MHz Tones
Rev. 0 | Page 13 of 40
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
COMPOSITE OUTPUT VOLTAGE (V p-p)
Figure 40. In-Band IMD3 vs. Composite Output Voltage over Gain;
30 MHz and 31 MHz Tones , Digital Gain = 0000001
11449-037
IMD3 (dBc)
OIP3 (dBV)
70
20
Data Sheet
0.45
0.40
ISUPPLY (mA)
5
15
25
35
45
55
65
GAIN = 1111110,
GAIN = 1111110,
GAIN = 0000001,
GAIN = 0000001,
LOW POWER
HIGH POWER
LOW POWER
HIGH POWER
0.20
0
5
10
15
20
25
30
35
40
45
50
55
60
65
FILTER BANDWIDTH (MHz)
Figure 44. Supply Current vs. Filter Bandwidth over Digital Gain and Power
Modes
0.45
VGA1 = 15dB
VGA1 = 12dB
VGA1 = 9dB
–15
DIGITAL
DIGITAL
DIGITAL
DIGITAL
0.25
Figure 41. Out-of-Band IIP2, IMD2 vs. PIN over Digital Gain;
115 MHz and 145 MHz Tones
0
0.30
OUT-OF-BAND IP2
INPUT LEVEL AT 115MHz AND 145MHz (dBV)
15
0.35
11449-140
60
VGA1 = 15dB
50
40
VGA1 = 12dB
30
VGA1 = 9dB
20
10
0
–10
–20
–30
–40
2:1 SLOPE
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–65 –55 –45 –35 –25 –15 –5
11449-141
IMD2 AT 30MHz (dBV)
ADRF6518
0.40
–45
ISUPPLY (mA)
–60
3:1 SLOPE
–75
–90
0.35
0.30
–105
OUT-OF-BAND IIP3
–120
0.25
–135
+25°C, DIGITAL GAIN = 1111110, LOW POWER
+85°C, DIGITAL GAIN = 1111110, LOW POWER
–40°C, DIGITAL GAIN = 1111110, LOW POWER
–150
0
5
10
15
INPUT LEVEL AT 115MHz AND 145MHz (dBV)
0.20
11449-142
–165
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
Figure 42. Out-of-Band IIP3, IMD3 vs. PIN over Digital Gain;
115 MHz and 145 MHz Tones
0
5
10
15
20
25
30
35
40
45
50
55
60
65
FILTER BANDWIDTH (MHz)
11449-041
IMD3 AT 30MHz (dBV)
–30
Figure 45. Supply Current vs. Filter Bandwidth over Temperature, Digital
Gain, and Power Modes
80
0.45
75
GAIN = 20dB
0.40
70
CMRR (dB)
0.30
GAIN = 1111110,
GAIN = 1111110,
GAIN = 0000001,
GAIN = 0000001,
5
10
15
20
25
30
35
40
45
FILTER BANDWIDTH (MHz)
60
55
50
LOW POWER
HIGH POWER
LOW POWER
HIGH POWER
45
0.20
0
65
50
55
60
65
Figure 43. Supply Current vs. Filter Bandwidth over Digital Gain and Power
Modes
Rev. 0 | Page 14 of 40
40
0
10
20
30
40
50
FREQUENCY (MHz)
Figure 46. Common-Mode Rejection Ratio vs. Frequency
60
11449-046
DIGITAL
DIGITAL
DIGITAL
DIGITAL
0.25
11449-040
ISUPPLY (mA)
GAIN = 60dB
0.35
Data Sheet
ADRF6518
VPK
(200mV/DIV)
BASEBAND OUTPUT
(500mV/DIV)
0.1
0.01
–24
11449-047
Figure 47. Peak Detector Time Domain Response
+25°C
+85°C
–40°C
–19
–14
–9
–4
VIN (dBV)
1
6
11
Figure 50. Peak Detector Output vs. VIN over Temperature;
VGN1 = 0.5 V, VGN2 = VGN3 = 0 V
PEAK DETECTOR OUTPUT (V peak)
0.6
20dB GAIN STEP
VGN1 = 200mV to 860mV
(200mV/DIV)
500ns/DIV
OPEN
1MΩ
100kΩ
0.5
0.4
0.3
0.2
0.1
0
11449-048
25mV p-p TO 250mV p-p
(50mV/DIV)
16
0
2
4
6
8
10
12
14
16
18
20
TIME (ms)
Figure 48. VGA1 Gain Step Response; VGN2/VGN3 = 0.5 V, −24 dBV RMS
Input Signal Level, C27 = 100 pF
Figure 51. Peak Detector Hold Time over RAVG
VPK
(200mV/DIV)
20dB GAIN STEP
VGN2/VGN3 = 200mV to 530mV
(100mV/DIV)
500ns/DIV
10ns/DIV
Figure 49. VGA2/VGA3 Gain Step Response; VGN1 = 0.5 V, −4 dBV RMS Input
Signal Level, C17 and C32 = 100 pF
Rev. 0 | Page 15 of 40
Figure 52. Peak Detector Reset Time Domain Response
11449-055
75mV p-p TO 750mV p-p
(50mV/DIV)
11449-148
SDO/RST
(1V/DIV)
11449-050
20ns/DIV
1
11449-044
PEAK DETECTOR OUTPUT (V peak)
10
ADRF6518
Data Sheet
BYPASS MODE
VPS = 3.3 V, TA = 25°C, ZLOAD = 400 Ω, power mode bit (B9) = 1 (high power mode), digital gain code bits (B8 to B2) = 1111110, dc offset
disable bit (B1) = 0 (enabled), unless otherwise noted.
GAIN (dB)
30
DIGITAL GAIN = 0000001
20
10
DIGITAL GAIN = 1111110
–10
1M
10M
100M
1G
FREQUENCY (Hz)
40
35
30
25
20
15
11449-202
0
15dB
12dB
9dB
0
100
200
300
400
500
600
700
800
Figure 53. Frequency Response over Supply and Temperature
1000
Figure 56. Noise Figure vs. VGN1 over Digital Gain
30
–110
15dB
12dB
9dB
–111
OUTPUT NOISE DENSITY (dBV/Hz)
25
GROUP DELAY (ns)
900
VGN1 (mV)
11449-158
40
45
VPS = 3.15V, 3.3V, 3.45V
+85°C
+25°C
–40°C
NOISE FIGURE (dB) RE TO 50Ω LOAD
50
20
15
10
5
–112
–113
–114
–115
–116
–117
–118
10M
100M
FREQUENCY (Hz)
1G
–120
11449-154
0
1M
0
200
300
400
500
600
700
800
900
1000
VGN1 (mV)
Figure 54. Group Delay vs. Frequency
Figure 57. Output Noise Density vs. VGN1 over Digital Gain
–100
70
–110
60
VGN1, VGN2, VGN3:
1V ,1V ,1V
HD2 AT 160MHz (dBc)
–120
–130
VGN1, VGN2, VGN3:
1V ,1V ,0V
–140
–150
VGN1, VGN2, VGN3:
0V ,0V ,0V AND 1V ,0V ,0V
–160
50
40
30
+85°C
+25°C
–40°C
20
–180
50
100
150
200
250
300
350
400
FREQUENCY (MHz)
Figure 55. Output Noise Density vs. Frequency over Analog Gains;
Digital Gain = 0000001
0
0
6
12
18
24
30
36
GAIN (dB)
42
48
54
60
11449-051
10
–170
11449-156
OUTPUT NOISE DENSITY (dBV/Hz)
100
11449-159
–119
Figure 58. HD2 vs. Gain over Temperature; Fundamental at 80 MHz, Digital
Gain = 0000001
Rev. 0 | Page 16 of 40
Data Sheet
ADRF6518
90
80
70
80
VGN1, VGN2, VGN3 = 1V
DIGITAL GAIN = 0000001
VGN1, VGN2, VGN3 = 1V
DIGITAL GAIN = 1111110
VGN1, VGN2, VGN3 = 0V
DIGITAL GAIN = 0000001
VGN1, VGN2, VGN3 = 0V
DIGITAL GAIN = 1111110
60
50
40
60
GAIN (dB)
50
40
+85°C
+25°C
–40°C
30
30
20
10
0
–10
–20
20
–30
10
6
12
18
24
30
36
42
48
54
60
GAIN (dB)
–50
1M
10M
Figure 59. HD3 vs. Gain over Temperature; Fundamental at 80 MHz, Digital
Gain = 0000001
10
PEAK DETECTOR OUTPUT (V peak)
100
IMD3 (dBc)
80
60
40
0
0.5
0.6
0.9
1.3
1.8
2.5
3.6
4.5
COMPOSITE OUTPUT VOLTAGE (V p-p)
40
30
20
10
36
42
48
54
60
66
GAIN (dB)
11449-056
+25°C
+85°C
–40°C
30
+25°C
+85°C
–40°C
–19
–14
–9
–4
VIN (dBV)
50
24
0.1
1
6
11
16
Figure 63. Peak Detector Output vs. VIN over Temperature; VGN1 = 0.5 V,
VGN2/VGN3 = 0 V; 125 MHz Tone
Figure 60. IMD3 vs. Composite Output Voltage over VOCM;
VGN1/VGN2/VGN3 = 1 V, 125 MHz and 126 MHz Tones
18
1
0.01
–24
11449-061
GAIN = 40
GAIN = 30
GAIN = 20
GAIN = 10
GAIN = 0
20
OIP3 BYPASS (dBV)
1G
Figure 62. Gain vs. Frequency
120
0
12
100M
FREQUENCY (Hz)
11449-203
0
11449-052
0
–40
11449-065
HD3 AT 240MHz (dBc)
70
Figure 61. In-Band OIP3 Bypass vs. Gain over Temperature;
Digital Gain = 0000001, 125 MHz and 126 MHz Tones
Rev. 0 | Page 17 of 40
ADRF6518
Data Sheet
MIXED POWER AND FILTER MODES
VPS = 3.3 V, TA = 25°C, ZLOAD = 400 Ω, digital gain code bits (B8 to B2) = 1111110, dc offset disable bit (B1) = 0 (enabled), unless
otherwise noted.
100
80
BANDWIDTH = 63MHz
90
70
GAIN = 60dB
80
60
GAIN = 40dB
ISOLATION (dB)
70
CMRR (dB)
50
GAIN = 20dB
40
30
GAIN = 20dB
60
50
40
GAIN = 60dB
30
20
20
10
100
200
300
400
500
600
700
800
900
1000
FREQUENCY (MHz)
0
100
11449-057
0
Figure 64. Common-Mode Rejection Ratio (CMRR) vs. Frequency
GAIN = 20dB
ISOLATION (dB)
80
GAIN = 60dB
70
60
50
10
20
30
40
FREQUENCY (MHz)
50
60
11449-171
40
0
400
500
600
700
800
900
1000
Figure 66. Channel Isolation (OPM1_SE to OPM2_SE) vs. Frequency, Bypass Mode
90
30
300
FREQUENCY (MHz)
100
BANDWIDTH = 63MHz
200
11449-172
10
0
Figure 65. Channel Isolation (OPM1_SE to OPM2_SE) vs. Frequency, Filter Mode
Rev. 0 | Page 18 of 40
Data Sheet
ADRF6518
CHARACTERIZATION
1.2
VGN1
VGN2
VGN3
VGN1
VGN2
VGN3
VGN1/VGN2/VGN3 (V)
1.0
0.8
NOISE FIGURE CALCULATION
SOLID LINES, DIGITAL GAIN CODE = 0000001
DASHED LINES, DIGITAL GAIN CODE = 0000000
All of the noise figure plots (see Figure 23, Figure 24, and
Figure 56) were completed by input referring the output noise
density and then dividing it by the theoretical noise density of a
50 Ω resister. The input SMA on the evaluation board was
terminated with a 50 Ω resistor to ground, which provided the
ADRF6518 input with a 400 Ω differential impedance via the 8:1
balun. In signal chain calculations, it is often convenient to
reference the noise figure to 50 Ω, even though the ADRF6518
input is terminated in 400 Ω.
0.6
0.4
0.2
The noise factor is calculated as follows:
0
6
12
18
24
30
36
42
48
54
60
GAIN (dB)
66
N OUT
11449-066
0
–12 –6
Noise Factor =
Figure 67. Gain Distribution for HD2/HD3 vs. Gain
Figure 67 shows the ADRF6518 analog gain distribution for the
HD2 vs. gain and HD3 vs. gain plots while the gain and input
voltage levels were swept and while keeping the output voltage
level at 1.5 V p-p.
GAIN
N 50Ω
where the noise densities are in nV/√Hz and GAIN is in linear
terms. The noise figure is then
Rev. 0 | Page 19 of 40
Noise Figure = 10 log10(Noise Factor)
ADRF6518
Data Sheet
REGISTER MAP AND CODES
The filter frequency, amplifier gains, filter bypass mode, and
offset correction loops can be programmed using the SPI
interface. Table 5 provides the bit map for the internal 15-bit
register of the ADRF6518.
Table 4. Filter Mode and Power Mode Options
B9
0
Filter Bypass
VGA low power; filter off
1
VGA high power; filter
off
Filter
VGA low power; filter low
power
VGA low power; filter high
power
Table 5. Register Map
MSB
B15
B14
B13
B12
B11
B10
Filter frequency code and filter bypass mode
Code = 1 dB corner in MHz
For example, 31 MHz = 011111 (MSB first)
Use 000000 for filter bypass mode
B9
B8
Power mode
0: low power
1: high power
Use 1 for filter BW > 31 MHz, in
filter mode
Use 1 for channel BW > 60 MHz,
in filter bypass mode
B7
VGA1 gain
00: 15 dB
01: 12 dB
10: 9 dB
11: 9 dB
Rev. 0 | Page 20 of 40
B6
B5
B4
B3
Digital gain code
VGA2 gain
VGA3 gain
00: 21 dB
00: 21 dB
01: 18 dB
01: 18 dB
10: 15 dB
10: 15 dB
11: 12 dB
11: 12 dB
B2
Postamp
0: 3 dB
1: 9 dB
LSB
B1
DC offset disable
0: enable
1: disable
Data Sheet
ADRF6518
THEORY OF OPERATION
1MHz TO 63MHz
24dB PROGRAMMABLE 24dB
VGA
FILTERS
VGA
24dB
VGA
3dB/9dB
ADC
DRIVER
BASEBAND
INPUTS
BASEBAND
OUTPUTS
3dB/9dB
12dB/15dB/
18dB/21dB
12dB/15dB/
18dB/21dB
INPUT
COMMON-MODE
CONTROL
9dB/12dB/15dB
ANALOG
GAIN CONTROL
30mV/dB
GAIN AND FILTER
PROGRAMMING
SPI BUS
OUTPUT
COMMON-MODE
CONTROL
11449-067
SPI
INTERFACE
Figure 68. Signal Path Block Diagram for a Single Channel of the ADRF6518
The ADRF6518 consists of a matched pair of input VGAs
followed by programmable filters, and then by a cascade of two
variable gain amplifiers and output ADC drivers. The filters can
be bypassed and powered down through the SPI interface for
operation beyond the maximum filter bandwidth. The block
diagram of a single channel is shown in Figure 68.
The programmability of the filter bandwidth and of the prefiltering and postfiltering fixed gains through the SPI interface offers
great flexibility when coping with signals of varying levels in the
presence of noise and large, undesired signals near the desired
band. The entire differential signal chain is dc-coupled with
flexible interfaces at the input and output. The bandwidth and
gain setting controls for the two channels are shared, ensuring
close matching of their magnitude and phase responses. The
ADRF6518 can be fully disabled through the ENBL pin.
Filtering and amplification are fundamental operations in any
signal processing system. Filtering is necessary to select the
intended signal while rejecting out-of-band noise and interferers. Amplification increases the level of the desired signal to
overcome noise added by the system. When used together,
filtering and amplification can extract a low level signal of
interest in the presence of noise and out-of-band interferers.
Such analog signal processing alleviates the requirements on the
analog, mixed signal, and digital components that follow.
INPUT VGAs
The input VGAs provide a convenient interface to the sensitive
filter sections that follow. They are designed to have a low noise
figure and high linearity. The combination of analog gain control
and digital gain settings allow a wide range of input signal levels
to be conditioned to drive the filters at up to 1.5 V p-p amplitude.
The VGAs set a differential input impedance of 400 Ω.
The baseband input signal can be ac-coupled or dc-coupled via
Pin 7 selection. When the signal is dc-coupled, the wide input
common-mode voltage is supported by having an optional 5 V
supply on Pin 8, VPI. The default common-mode voltage is
VPI/2, which is available on the dual function Pin 7, VICM/AC,
to set the output common-mode voltage of the driving circuit.
However, this is optional and input common-mode can be
independently set within the supported range. For a 3.3 V
supply on VPI, the input common mode can range from 1.35 V
to 1.95 V, while maintaining a 5 V p-p input level at >60 dBc
HD2 and HD3. For a 5 V supply on VPI, the input common-mode
range extends to 1.35 V to 3.1 V. Extra current is drawn from the
VPI supply to support an input common mode greater than the
midvalue of the main 3.3 V supply, that is, VPS/2.
The VICM/AC voltage is not buffered and must be sensed at a
high impedance point to prevent it from being loaded down.
When the baseband input signal is ac-coupled, pull the VICM/AC
pin low to activate the internal bias for the input stage.
The input VGAs have analog gain control of 24 dB, followed
by a digital gain settings of 9 dB, 12 dB, or 15 dB, selectable
through the SPI (see the Register Map and Codes section). The
VGAs are based on the Analog Devices, Inc., patented X-AMP®
architecture, consisting of tapped 24 dB attenuators, followed by
programmable gain amplifiers. The X-AMP architecture generates a continuous linear-in-dB monotonic gain response with
low ripple. The analog gain of the VGA sections are controlled
through the high impedance VGN1 pin with an accurate slope
of 30 mV/dB. Adjust the VGA analog gain through an AGC
mechanism, such that 1.5 V p-p at the output of the first VGA is
not exceeded. If, however, the input signal is small enough, the
first VGA can be set at full gain for best noise figure (NF) performance and gain control achieved in the second or third VGA.
Driving ADRF6518 Single-Ended
The input structure of the ADRF6518 is designed for differential drive. However, with some performance degradation, it can
be driven single-ended, especially at low bandwidth signals. See
the Applications Information section for guidance on singleended drive.
Rev. 0 | Page 21 of 40
ADRF6518
Data Sheet
PEAK DETECTOR
0
PROGRAMMABLE FILTERS
The integrated programmable filter is the key signal processing
function in the ADRF6518. The filters follow a six-pole Butterworth prototype response that provides a compromise between
band rejection, ripple, and group delay. The 0.5 dB bandwidth is
programmed from 1 MHz to 63 MHz in 1 MHz steps via the serial
programming interface (SPI) as described in the Programming
the ADRF6518 section.
The filters are designed so that the Butterworth prototype filter
shape and group delay responses vs. frequency are retained for
any bandwidth setting. Figure 69 and Figure 70 illustrate the
ideal six-pole Butterworth response. The group delay, τg, is
defined as
τg = −∂φ/∂ω
where:
φ is the phase in radians.
ω = 2πf is the frequency in radians per second.
Note that for a frequency scaled filter prototype, the absolute
magnitude of the group delay scales inversely with the bandwidth; however, the shape is retained. For example, the peak
group delay for a 28 MHz bandwidth setting is 14× less than
for a 2 MHz setting.
RELATIVE MAGNITUDE (Hz)
–60
–80
–100
–120
–140
10M
100M
1G
FREQUENCY (Hz)
11449-068
–180
1M
Figure 69. Sixth-Order Butterworth Magnitude Response for 0.5 dB
Bandwidths Programmed from 2 MHz to 29 MHz in 1 MHz Steps
500
400
BW = 2MHz
BW = 28MHz
300
200
14×
100
0
–100
100k
1M
10M
100M
FREQUENCY (Hz)
11449-069
The peak detector can be used in an AGC loop to set the appropriate signal level at the filter input. For such an implementation,
filter VPK appropriately, considering that it is a peak hold
output. A high pulse of 25 ns or longer duration applied to the
SDO/RST dual function pin resets the VPK voltage to 0 V by
discharging the internal holding capacitor.
–40
–160
GROUP DELAY (ns)
To measure the signal level at the critical interface of the VGA1
output and the programmable filter input, a peak detector has
been implemented. The peak detector simultaneously measures
both channels at the VGA1 output and reports the bigger of the
two at the VPK pin. The on-chip holding capacitor and negligible leakage at the internal node ensure a large droop time of the
order of a millisecond, which is a function of the peak voltage as
well. Bigger peak voltage results in longer droop time. The droop
time can be adjusted down by placing a resistor between the
RAVG and VPS pins. Typical values of RAVG can range from
1 MΩ to 1 kΩ. As the RAVG resistor value is reduced, the peak
voltage, VPK, appears as an envelope output. The peak detector
has the attack bandwidth of 100 MHz.
–20
Figure 70. Sixth-Order Butterworth Group Delay Response for
0.5 dB Bandwidths Programmed to 2 MHz and 28 MHz
The corner frequency of the filters is defined by RC products,
which can vary by ±30% in a typical process. Therefore, all the
parts are factory calibrated for corner frequency, resulting in
a residual ±8% corner frequency variation over the −40°C to
+85°C temperature range. Although absolute accuracy requires
calibration, the matching of RC products between the pair of
channels is better than 1% by observing careful design and
layout practices. Calibration and excellent matching ensure
that the magnitude and group delay responses of both channels
track together, a critical requirement for digital IQ-based
communication systems.
Bypassing the Filters
For higher bandwidth applications, filters of the ADRF6518 can
be bypassed via the SPI. In the filter bypass mode, filters are
disabled and power consumption is significantly reduced. The
bandwidth of cascaded VGAs, which is significantly larger than
63 MHz maximum of the filters, is fully realized in the filter
bypass mode.
Rev. 0 | Page 22 of 40
Data Sheet
ADRF6518
VARIABLE GAIN AMPLIFIERS (VGAs)
The fixed gain following both of the variable gain sections can
also be programmed to 12 dB, 15 dB, 18 dB, or 21 dB to maximize the dynamic range.
OUTPUT BUFFERS/ADC DRIVERS
The low impedance (<10 Ω) output buffers of the ADRF6518
are designed to drive either ADC inputs or subsequent amplifier
stages. They are capable of delivering up to 4 V p-p composite
two-tone signals into 400 Ω differential loads with >60 dBc
IMD3. The output common-mode voltage defaults to VPS/2,
but it can be adjusted from 900 mV to VPS − 1.2 V without loss
of drive capability by presenting the VOCM pin with the
desired common-mode voltage. The high input impedance of
VOCM allows the ADC reference output to be connected
directly. Even though the output common-mode voltage is
adjustable, and the offset compensation loop can null the
accumulated dc offsets (see the DC Offset Compensation Loop
section), it may still be desirable to ac-couple the outputs by
selecting the coupling capacitors according to the load impedance and desired bandwidth.
DC OFFSET COMPENSATION LOOP
In many signal processing applications, no information is
carried in the dc level. In fact, dc voltages and other low
frequency disturbances can often dominate the intended signal
and consume precious dynamic range in the analog path and
bits in the data converters. These dc voltages can be present
with the desired input signal or can be generated inside the
signal path by inherent dc offsets or other unintended signaldependent processes such as self-mixing or rectification.
Because the ADRF6518 is fully dc-coupled, it may be necessary
to remove these offsets to realize the maximum signal-to-noise
ratio (SNR). The external offsets can be eliminated with accoupling capacitors at the input pins; however, that requires
large value capacitors because the impedances can be fairly low,
and high-pass corners may need to be <10 Hz in some cases. To
address the issue of dc offsets, the ADRF6518 provides an offset
correction loop that nulls the output differential dc level, as
shown in Figure 71. If the correction loop is not required, it can
be disabled through the SPI port.
COFS
OFDS
OFSx
BASEBAND
OUTPUTS
FROM
FILTERS
50dB
VGA
OUTPUT ADC
DRIVER
GAIN
11449-070
The cascaded VGA2 and VGA3 are also based on the X-AMP
architecture, and each has 24 dB gain range with separate high
impedance gain control inputs, VGN2 and VGN3. The VGA
structures of the second and third VGAs are identical to that of
the first VGA. However, these have slightly higher noise figure
and less drive level capability. Their output is rated at 1 V p-p
for >60 dBc HD2 and HD3. Depending on the input signal
range, the second or third VGA or both can be used for AGC
purposes. The critical level to consider while making this choice
is the signal level at the output of the VGAs, which must not
exceeded 1 V p-p to maintain low distortion.
Figure 71. Offset Compensation Loop Operates Around the VGA
and Output Buffer
The offset control loop creates a high-pass corner, fHP, that
is superimposed on the normal Butterworth filter response
when filters are enabled. Typically, fHP is many orders of
magnitude lower than the lower programmed filter bandwidth
so that there is no interaction between them. Setting fHP is
accomplished with capacitors, COFS, from the OFS1 and OFS2
pins to ground. Because the correction loop works around the
VGA sections, fHP is also dependent on the total gain of the
cascaded VGAs. In general, the expression for fHP is given by
fHP (Hz) = 6.7 × Post Filter Linear Gain/COFS (µF)
where Post Filter Linear Gain is expressed in linear terms, not
in decibels (dB), and is the gain following the filters, which
excludes the VGA1 gain.
Note that fHP increases in proportion to the gain. For this
reason, choose COFS at the highest operating gain to guarantee
that fHP is always below the maximum limit required by the
system.
PROGRAMMING THE ADRF6518
The 0.5 dB corner frequencies for both filters, the digital gains of all
the VGAs, and the output buffers are programmed simultaneously through the SPI port. In addition to these, enabling the dc
offset compensation loop and power mode selection are also
controlled through SPI port. A 16-bit register stores 15 data bits,
including the 6-bit code for corner frequencies of 1 MHz through
63 MHz and filter bypass, as well as the codes for VGA gains,
and the postamplifier gain (see Table 5). The SPI protocol not
only allows these selections to be written to the DATA pin, but
also allows the stored code to be read back via the SDO/RST pin.
The latch enable (LE) pin must first go to a Logic 0 for a read or
write cycle to begin. On the next rising edge of the clock (CLK),
a Logic 1 on the DATA pin initiates a write cycle, whereas a
Logic 0 on the DATA pin initiates a read cycle. In a write cycle,
the next 15 CLK rising edges latch the desired 15-bit code, LSB
first. This results in 16-bit code, including the first Logic 1 to
initiate a write cycle. When LE goes high, the write cycle is
completed and different codes are presented various blocks that
need programming. In a read cycle, the next 15 CLK falling
edges present the stored 15-bit code, LSB first. When LE goes
high, the read cycle is completed. Detailed timing diagrams are
shown in Figure 2 and Figure 3.
Rev. 0 | Page 23 of 40
ADRF6518
Data Sheet
NOISE CHARACTERISTICS
The output noise behavior of the ADRF6518 depends on the gain
and bandwidth settings. VGA1 noise dominates in the filter
bypass mode and at high filter corner settings. While at low
corner settings, filter noise tends to dominate.
The filter contributes a noise spectral density profile that is flat
at low frequencies, peaks near the corner frequency, and then
rolls off as the filter poles roll off the gain and noise. The
magnitude of the noise spectral density contributed by the filter,
expressed in nV/√Hz, varies inversely with the square root of
the bandwidth setting, resulting in filter noise in nV that is
nearly constant with the bandwidth setting. However, with
VGA1 NF being lower than the filter, VGA1 tends to dominate
the overall NF. At higher frequencies, after the filter noise rolls
off, the noise floor is set by the VGAs.
Each of the X-AMP VGA sections used in the ADRF6518
contributes a fixed noise spectral density to its respective output,
independent of the analog gain setting. With the digital gain
change, however, VGA output noise changes, because the gain
setting resistors values change. As an example, the VGA1 NF
corresponding to a 15 dB gain setting is 17.3 dB, whereas for a
9 dB gain, the NF is 19 dB. When cascaded, the total noise
contributed by the VGAs at the output of the ADRF6518
increases gradually with higher gain. This is apparent in the
noise floor variation at high frequencies at different VGA gain
settings. The exact relationship depends on the programmed
fixed gain of the amplifiers. At lower frequencies within the filter
bandwidth setting, the VGAs translate the filter noise directly to
the output by a factor equal to the gain following the filter.
At low values of VGA gain, the noise at the output is the flat
spectral density contributed by the last VGA. As the gain
increases, more of the filter and first VGA noise appears at
the output. Because the intrinsic filter noise density increases
at lower bandwidth settings, it is more pronounced than it is
at higher bandwidth settings. In either case, the noise density
asymptotically approaches the limit set by the VGAs at the
highest frequencies. For other values of VGA gain and bandwidth
setting, the detailed shape of the noise spectral density changes
according to the relative contributions of the filters and VGAs.
Because the noise spectral density outside the filter bandwidth
is limited by the VGA output noise, it may be necessary to use
an external, fixed frequency, passive filter prior to analog-todigital conversion to prevent noise aliasing from degrading the
signal-to-noise ratio. A higher sampling rate, relative to the maximum required ADRF6518 corner frequency setting, reduces the
order and complexity of this external filter.
DISTORTION CHARACTERISTICS
To maintain low distortion through the cascaded VGAs and
filter of the ADRF6518, consider the distortion limits of each
stage. The first VGA has higher signal handling capability and
bandwidth than VGA2 and VGA3, because it must cope with
out-of-band signals that can be larger than the in-band signals.
In the filter mode, these out-of-band signals are filtered before
reaching VGA2 and VGA3. It is important to understand the
signals presented to the ADRF6518 and to match these signals
with the input and output characteristics of the part. It is useful
to partition the ADRF6518 into the front end, composed of
VGA1 and the filter, and the back end, composed of VGA2 and
VGA3 and the output buffers.
VGA1 can handle a 5 V p-p signal at a maximum analog attenuation setting, without experiencing appreciable distortion at the
input. In most applications, VGA1 gain should be adjusted such
that the maximum signal presented at the filter inputs (or
VGA2 input in filter bypass mode) is <1.5 V p-p. At this level,
the front end does not limit the distortion performance. The
peak detector output, VPK, can be used as an indicator of the
signal level present at this critical interface. Choose the second
and third VGA gains such that their output levels do not exceed
1 V p-p. If the output signal level is expected to exceed 1.5 V p-p,
it is recommended to set the postamplifier gain to 9 dB.
For these signal level considerations, it is recommended that the
out-of-band signal, if larger than the desired in-band signal, be
addressed. In filter mode, such an out-of-band signal only
affects the VGA1 operation, because it is filtered out by the
filter and does not affect the following stages. In this case, a
high VGA2 and VGA3 gain may be needed to raise the small
desired signal to a higher level at the output. In the filter bypass
mode, such out-of-band signals may need to be filtered prior to
the ADRF6518.
The overall distortion introduced by the part depends on the
input drive level, including the out-of-band signals, and the
desired output signal level. To achieve best distortion
performance and the desired overall gain, keep in mind the
maximum signal levels indicated previously when selecting
different VGA gains.
To distinguish and quantify the distortion performance of the
input section, two different IP3 specifications are presented.
The first is called in-band IP3 and refers to a two-tone test
where the signals are inside the filter bandwidth. This is exactly
the same figure of merit familiar to communications engineers
in which the third-order intermodulation level, IMD3, is
measured.
To quantify the effect of out-of-band signals, a new out-of-band
(OOB) IIP3 figure of merit is introduced. This test also involves
a two-tone stimulus; however, the two tones are placed out-ofband so that the lower IMD3 product lands in the middle of the
filter pass band. At the output, only the IMD3 product is visible
because the original two tones are filtered out. To calculate the
OOB IIP3 at the input, the IMD3 level is referred to the input
by the overall gain. The OOB IIP3 allows the user to predict the
impact of out-of-band blockers or interferers at an arbitrary
signal level on the in-band performance. The ratio of the desired
input signal level to the input-referred IMD3 at a given blocker
level represents a signal-to-distortion limit imposed by the outof-band signals.
Rev. 0 | Page 24 of 40
Data Sheet
ADRF6518
MAXIMIZING THE DYNAMIC RANGE
When used in the filter mode, the role of the ADRF6518 is to
increase the level of a variable in-band signal while minimizing
out-of-band signals. Ideally, this is achieved without degrading
the SNR of the incoming signal or introducing distortion to the
incoming signal.
The first goal is to maximize the output signal swing, which can
be defined by the ADC input range or the input signal capacity
of the next analog stage. For the complex waveforms often encountered in communication systems, the peak-to-average ratio, or
crest factor, must be considered when choosing the peak-to-peak
output. From the chosen output signal and the maximum gain
of the ADRF6518, the minimum input level can be defined.
As the input signal level increases, the VGA3 gain is reduced
from its maximum gain point to maintain the desired fixed
output level. VGA2 and VGA1 can then be adjusted as the input
signal level keeps increasing. This maintains the best NF for the
cascaded chain. The output noise, initially dominated by the
filter and VGA1 combination, follows the gain reduction,
yielding a progressively better SNR. At some point, the VGA3
and VGA2 gains drop sufficiently so that their noise becomes
dominant, resulting in a slower reduction in SNR from that
point. From the perspective of SNR alone, the maximum input
level is reached when the VGA1 reaches its minimum gain.
Distortion must also be considered when maximizing the dynamic
range. At low and moderate signal levels, the output distortion
is constant and assumed to be adequate for the selected output
level. At some point, the input signal becomes large enough that
distortion at the input limits the system. This can be kept in check
by monitoring peak detector voltage, VPK.
The most challenging scenario in terms of dynamic range is the
presence of a large out-of-band blocker accompanying a weaker
in-band wanted signal. In this case, the maximum input level is
dictated by the blocker and its inclination to cause distortion.
After filtering, the weak wanted signal must be amplified to the
desired output level, possibly requiring the maximum gain on
VGA2 and VGA3. In such a case, both the distortion limits
associated with the blocker at the input and the SNR limits
created by the weaker signal and higher gains are present
simultaneously. Furthermore, not only does the blocker
scenario degrade the dynamic range, it also reduces the range of
input signals that can be handled because a larger part of the
gain range is simply used to extract the weak desired signal from
the stronger blocker.
KEY PARAMETERS FOR QUADRATURE-BASED
RECEIVERS
The majority of digital communication receivers make use of
quadrature signaling, in which bits of information are encoded
onto pairs of baseband signals that then modulate in-phase (I)
and quadrature (Q) sinusoidal carriers. Both the baseband and
modulated signals appear quite complex in the time domain with
dramatic peaks and valleys. In a typical receiver, the goal is to
recover the pair of quadrature baseband signals in the presence
of noise and interfering signals after quadrature demodulation.
In the process of filtering out-of-band noise and unwanted interferers and restoring the levels of the wanted I and Q baseband
signals, it is critical to retain their gain and phase integrity over
the bandwidth.
In filter mode, the ADRF6518 delivers flat in-band gain and
group delay, consistent with a six-pole Butterworth prototype
filter, as described in the Programmable Filters section.
Furthermore, careful design ensures excellent matching of these
parameters between the I and Q channels. Although absolute
gain flatness and group delay can be corrected with digital
equalization, mismatch introduces quadrature errors and
intersymbol interference that degrade bit error rates in digital
communication systems.
For wideband signals, filters can be bypassed and the
ADRF6518 then becomes a dual cascaded chain of three VGAs,
offering large gain range options, while maintaining gain and
group delay match between the two channels.
Rev. 0 | Page 25 of 40
ADRF6518
Data Sheet
APPLICATIONS INFORMATION
BASIC CONNECTIONS
1.35 V to 1.95 V while VPI = 3.3 V. The user has the option of tying
VPI to a voltage up to 5 V. This provides a common-mode range of
1.35 V to 3.1 V. In general, the minimum input common-mode
voltage is always 1.35 V, but the maximum common-mode voltage
is VCM_MAX = 0.64 × VPI − 0.135 V. The VICM pin can be used as a
reference common-mode voltage for driving a high impedance
sensing node of the preceding cascaded part (VICM has a
7.75 kΩ impedance).
Figure 72 shows the basic connections for a typical ADRF6518
application.
SUPPLY DECOUPLING
Apply a nominal supply voltage of 3.3 V to the supply pins,
VPS, VPI, and VPSD. The supply voltage must not exceed
3.45 V or drop below 3.15 V for VPS and VPSD. The supply
voltage on VPI must not exceed 5.25 V. Decouple each supply
pin to ground with at least one low inductance, surface-mount
ceramic capacitor of 0.1 µF placed as close as possible to the
ADRF6518 device.
OUTPUT SIGNAL PATH
The low impedance (10 Ω) output buffers are designed to drive
a high impedance load, such as an ADC input or another amplifier
stage. The output pins—OPP1, OPM1, OPP2, and OPM2—sit
at a nominal output common-mode voltage of VPS/2, but can
be driven to a voltage of 0.9 V to VPS − 1.2 V by applying the
desired common-mode voltage to the high impedance VOCM
pin.
The ADRF6518 has three separate supplies: two analog supplies
and a digital supply. Take care to separate the analog and digital
supplies with a large surface-mount inductor of 33 µH. Then
decouple each supply separately to its respective ground through
a 10 μF capacitor.
DC OFFSET COMPENSATION LOOP ENABLED
INPUT SIGNAL PATH
When the dc offset compensation loop is enabled via B1 of the
SPI register, the ADRF6518 can null the output differential dc
level. The loop is enabled by setting B1 = 0. The offset
compensation loop creates a high-pass corner frequency, which
is proportional to the value of the capacitors that are connected
from the OFS1 and OFS2 pins to ground. For more information
about setting the high-pass corner frequency, see the DC Offset
Compensation Loop section.
Each signal path has an input VGA, accessed through the INP1,
INM1, INP2, and INM2 pins, that sets a differential input
impedance of 400 Ω.
The inputs can be dc-coupled or ac-coupled. To ac couple the
inputs, the user must pull the VICM/AC pin to ground. This
provides an input common-mode voltage of VPI/2. To dc
couple the inputs, let the VICM pin float. If using direct dc
coupling, the common-mode voltage, VCM, can range from
INPUT1(–)
0.1µF
VPS
0.1µF
INPUT1(+)
SERIAL CONTROL INTERFACE
VPS
VPS
0.1µF
OUTPUT1(+)
ENBL INM1
RAVG OFS1
INP1
VGN1
VPS
VPS
OPP1
VPSD
0.1µF
VPSD
OPM1
COMD
COM
LE
ADRF6518
CLK
SDO/RST
COM
VICM/AC
OPM2
VPI
0.1µF
VOCM
DATA
0.1µF
OUTPUT1(–)
VGN3
0.1µF
OUTPUT2(–)
OPP2
VPS
VGN2
VPS
INP2
OFS2
COM INM2
VPK
0.1µF
VPS
0.1µF
INPUT2(+)
VPI
OUTPUT2(+)
0.1µF
VPS
0.1µF
11449-071
INPUT2(–)
Figure 72. Basic Connections
Rev. 0 | Page 26 of 40
Data Sheet
ADRF6518
COMMON-MODE BYPASSING
Decouple the ADRF6518 common-mode pins, VICM/AC and
VOCM, to ground. Use at least one low inductance, surfacemount ceramic capacitor with a value of 0.1 μF to decouple the
common-mode pins.
•
SERIAL PORT CONNECTIONS
The ADRF6518 has a SPI port to control the gain and filter bandwidth settings. Data can be written to the internal 15-bit register
and read from the register. It is recommended that low-pass RC
filtering be placed on the SPI lines to filter out any high frequency
glitches. See Figure 88, the evaluation board schematic, for an
example of a low-pass RC filter.
ENABLE/DISABLE FUNCTION
To enable the ADRF6518, pull the ENBL pin high. Driving the
ENBL pin low disables the device, reducing current consumption to approximately 1 mA at room temperature. For the
disable function to work properly, connect 10 kΩ pull-down
resistors from the signal output pins (OPP1, OPM1, OPP2,
OPM2) to ground to allow a dc path to ground for proper
discharge (see Figure 67). If the disable function is not used,
pull-down resistors are not necessary.
GAIN PIN DECOUPLING
The ADRF6518 has three analog gain control pins: VGN1,
VGN2, and VGN3. Use at least one low inductance, surfacemount ceramic capacitor with a value of 0.1 μF to decouple
each gain control pin to ground.
PEAK DETECTOR CONNECTIONS
The ADRF6518 has a peak detector output on the VPK pin,
with a scaling of 1 V/V peak differential at filter inputs. The
bigger peak of the two channels is reported. The peak detector
time-constant can be changed with a resistor from the RAVG
pin to VPS. Leave the RAVG pin open for the longest timeconstant (hold time). The RAVG resistor range is ∞ to 1 kΩ.
To reset the peak detector, pull the SDO/RST pin high for 25 ns
or longer. Logic levels are VLOW < 0.8 V, VHIGH > 2 V.
ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE
Error vector magnitude (EVM) is a measure used to quantify
the performance of a digital radio transmitter or receiver by
measuring the fidelity of the digital signal transmitted or
received. Various imperfections in the link, such as magnitude
and phase imbalance, noise, and distortion, cause the
constellation points to deviate from their ideal locations.
In general, a receiver exhibits three distinct EVM limitations
vs. received input signal power. As signal power increases, the
distortion components increase.
•
•
At large enough signal levels, where the distortion components due to the harmonic nonlinearities in the device are
falling in-band, EVM degrades as signal levels increase.
At medium signal levels, where the signal chain behaves
in a linear manner and the signal is well above any notable
noise contributions, EVM has a tendency to reach an optimal level determined dominantly by either the quadrature
accuracy and IQ gain match of the signal chain or the
precision of the test equipment.
As signal levels decrease, such that noise is a major contributor, EVM performance vs. the signal level exhibits
a decibel-for-decibel degradation with decreasing signal
level. At these lower signal levels, where noise is the
dominant limitation, decibel EVM is directly proportional
to the SNR.
EVM TEST SETUP
The basic setup to test the EVM for the ADRF6518 consisted of
an Agilent MXG N5182B vector signal generator used as a
signal source and an Agilent DSO7104B oscilloscope used to
sample the signal while connected to a computer running Agilent
89600 vector signal analysis (VSA) software to calculate the EVM
of the signal. The I and Q outputs of the ADRF6518 were
loaded with 400 Ω differential impedances and connected
differentially to two AD8130 amplifiers to convert the signals
into single-ended signals. The single-ended signals were
connected to the input channels of the vector signal analyzer.
EVM MEASUREMENT
EVM was measured for the ADRF6518 only (the AD8130
amplifiers were used, but their EVM contribution is minimal
and do not dominate the measurement). The N5182B IQ baseband
differential outputs drove the ADRF6518 inputs through 1 µF
coupling capacitors. Large coupling capacitors are necessary to
keep the high-pass corner created by the capacitors as low as
possible and to prevent the low-pass corner from corrupting the
signal. The VICM/AC pin was grounded to enable ac coupling.
The VPI pin was connected to 3.3 V by shorting it to VPS. The
alpha of the pulse response filter was set to 0.35. The baseband
input power to the ADRF6518 was swept, and the analog gains
were adjusted to maintain a target 1.5 V p-p differential signal
level on both the I and Q outputs. The VGA1 analog gain was
adjusted to limit its output to 1.5 V p-p (0.75 V peak on the
peak detector output). The filter corner was set to 63 MHz, and
the digital gains for VGA1, VGA2, VGA3, and the postamplifier
were set to 15 dB, 21 dB, 21 dB, and 3 dB, respectively. Several
signal bandwidths, signal types, gains, and output levels were
tested, in filter mode and in filter bypass mode.
It is important to keep the high-pass corner of the output offset
compensation loop low compared to the signal bandwidth. The
lower the signal bandwidth is, the lower the user must set the
high-pass corner to ensure that the minimal amount of the
signal is not corrupted. See the Applications Information
section of the ADRF6510 and the ADRF6516 data sheets for
additional information on the effects of setting the high-pass
corner too high in frequency.
It is also important to set the filter corner appropriately for the
given signal bandwidth. The user must be careful not to set the
filter corner too low in an attempt to achieve more rejection of
Rev. 0 | Page 27 of 40
ADRF6518
Data Sheet
the out-of-band blockers, because this can corrupt the data in
the signal and degrade the EVM. For examples of this, see the
applications information section in the ADRF6510 and the
ADRF6516 data sheets. Figure 83 also shows this trade-off
between filter corner and signal bandwidth.
0
–10
–15
EVM (dB)
In Figure 73 through Figure 77, the x-axis is appropriately
labeled in units of a voltage ratio, which is defined as
20 × log10(x/1 V p-p)
–20
–25
–30
–35
where x is any number in units of V p-p.
–40
Figure 73 and Figure 74 show EVM vs. input voltage over
different symbol rates in filter mode (filter corner = 63 MHz)
and in filter bypass mode, respectively. EVM is generally better
for higher symbol rates while in filter bypass mode. This is
mainly due to the absence of noise and distortion components
that the filter introduces. For the same 80 MSPS signal, EVM
improves 11 dB when switching from a 63 MHz filter corner to
filter bypass mode. For the lower symbol rates, the difference in
EVM between a 63 MHz filter corner and filter bypass mode is
negligible.
–45
–50
–40
–10
–10
0
10
20
Figure 74. EVM vs. Input Voltage over Symbol Rates; Filter Bypass Mode,
QPSK, Gain Code = 0000000, 1.5 V p-p Differential Output Level Maintained
Figure 75 and Figure 76 show EVM vs. input voltage over
different modulation types at 50 MSPS in filter mode and in
filter bypass mode, respectively. EVM improves for the highorder modulation types when the filter is in bypass mode.
0
QPSK
16QAM
256QAM
–5
–10
–15
EVM (dB)
5MSPS
10MSPS
50MSPS
80MSPS
–20
VIN (dBV p-p)
0
–5
–30
–15
–20
–25
–30
–35
–20
–40
–25
–50
–40
–35
–30
–20
–10
0
10
20
VIN (dBV p-p)
–40
11449-081
–45
–30
Figure 75. EVM vs. Input Voltage over Modulation Type; Filter Corner =
63 MHz, QPSK, 50 MSPS, Gain Code = 0000000, 1.5 V p-p Differential Output
Level Maintained
–20
–10
VIN (dBV p-p)
0
10
20
0
QPSK
16QAM
256QAM
–5
Figure 73. EVM vs. Input Voltage over Symbol Rates; Filter Corner = 63 MHz,
QPSK, Gain Code = 0000000, 1.5 V p-p Differential Output Level Maintained
–10
EVM (dB)
–15
–20
–25
–30
–35
–40
–45
–50
–40
–30
–20
–10
VIN (dBV p-p)
0
10
20
11449-082
–30
11449-079
–45
–50
–40
11449-080
This is done because the 100 Ω differential baseband source
(Agilent MXG N5182B) drives the 400 Ω differential input
impedance of the ADRF6518. The standard unit of power ratio,
dBm, is only applicable in a 50 Ω system.
EVM (dB)
5MSPS
10MSPS
50MSPS
80MSPS
100MSPS
–5
Figure 76. EVM vs. Input Voltage over Modulation Type; Filter Bypass Mode,
QPSK, 50 MSPS, Gain Code = 0000000, 1.5 V p-p Differential Output Level
Maintained
Rev. 0 | Page 28 of 40
Data Sheet
ADRF6518
Figure 77 shows EVM vs. input voltage over various digital gain
settings. There is about a 1 dB spread of EVM over the gain
settings.
EVM (dB)
–15
–20
–25
–30
–20
–35
–25
–40
–30
–45
–35
–50
–80
–40
–60
–50
–40
–30
–20
–10
0
10
20
PIN (dBm)
–20
–10
VIN (dBV p-p)
0
10
20
Figure 77. EVM vs. Input Voltage over Digital Gain Settings, Filter Corner =
63 MHz, QPSK, 50 MSPS, 1.5 V p-p Differential Output Level Maintained
EVM SYSTEM MEASUREMENT
An overall EVM measurement was completed with the ADL5380
IQ demodulator driving the ADRF6518. The interface between
the two parts was dc-coupled. To achieve this, the VICM/AC
pin was floated to enable dc coupling mode and the VPI pin on
the ADRF6518 was connected to 5 V to accommodate the 3.1 V
output common-mode voltage of the ADL5380. The RF carrier
frequency applied to the RF input of the ADL5380 and the LO
frequency were set to 900 MHz, creating a zero intermediate
frequency (I/F). The alpha of the pulse response filter was set to
0.35. The RF input power to the ADL5380 was swept, and the
analog gains on the ADRF6518 were adjusted to maintain a
target 1.5 V p-p differential signal level on both the I and Q
outputs. The VGA1 analog gain was adjusted to limit its output
to 1.5 V p-p (0.75 V peak on the peak detector output). The
filter corner was set to 63 MHz, and digital gains for VGA1,
VGA2, VGA3, and the postamplifier were set to 15 dB, 21 dB,
21 dB, and 3 dB, respectively. Several signal bandwidths, signal
types, gains, and output levels were tested, in filter mode and in
filter bypass mode.
Figure 78 shows three different symbol rates: 10 MSPS, 50 MSPS,
and 80 MSPS, with the filter enabled. There is a degradation of
EVM with increasing symbol rate, but at 10 MSPS, the system
achieves better than −40 dB of EVM for about 50 dB of the
input power range. The degradation of EVM at the high input
power for Figure 78 to Figure 83 is caused by the ADL5380
compressing. By placing an RF attenuator in front of the
ADL5380, the user can extend the dynamic range of the system.
Figure 78. EVM vs. Input Power Over Symbol Rate; QPSK, Filter Corner =
63 MHz, Gain Code = 0000000, 1.5 V p-p Differential Output Level
Maintained
Figure 79 shows four different symbol rates, with the filter in
bypass mode. EVM generally improves while in filter bypass
mode, especially at the higher symbol rates, due to the absence
of noise, IQ gain mismatch, IQ phase mismatch, raw group
delay, and group delay mismatch, which are some dominant
sources of error that the filter adds when enabled.
0
10MSPS
50MSPS
80MSPS
100MSPS
–5
–10
–15
EVM (dB)
–30
11449-083
–45
–50
–40
–70
11449-084
–10
–15
9dB, 12dB, 12dB, 3dB
12dB, 12dB, 12dB, 3dB
15dB, 12dB, 12dB, 3dB
15dB, 15dB, 15dB, 3dB
15dB, 18dB, 18dB, 3dB
15dB, 21dB, 21dB, 3dB
15dB, 21dB, 21dB, 9dB
–20
–25
–30
–35
–40
–45
–50
–80
–70
–60
–50
–40
–30
–20
PIN (dBm)
–10
0
10
20
11449-085
–5
10MSPS
50MSPS
80MSPS
–10
EVM (dB)
0
0
–5
Figure 79. EVM vs. Input Power over Symbol Rate; Filter Bypass Mode,
Gain Code = 0000000, 1.5 V p-p Differential Output Level Maintained
Figure 80 shows the EVM for a 50 MSPS signal over several
different digital modulation types while the filter is in bypass
mode. Up to 256 QAM, there is an improvement to EVM, but
this is due to how EVM is calculated, rather than absolute
symbol error being reduced. (EVM is calculated as the ratio of
the rms power of the symbol error vector to the rms average
power of the constellation. A similar and perhaps better metric
is modulation error ratio, or MER, which is defined as the ratio
of the rms power of the ideal symbol to the rms power of the
symbol error vector.) The 1024 QAM signal starts to degrade
due to the noise and distortion components impacting the
closely packed symbols in the constellation.
Rev. 0 | Page 29 of 40
ADRF6518
Data Sheet
–5
–10
–15
–20
–20
EVM (dB)
–15
–25
–30
–30
–35
–35
–40
–40
–45
–45
–70
–60
–50
–40
–30
–20
–10
0
10
20
PIN (dBm)
Figure 80. EVM vs. Input Power over Digital Modulation Type; Filter Bypass
Mode, Gain Code = 0000000, 1.5 V p-p Differential Output Level Maintained
Figure 81 shows the same four modulation types as in Figure 80,
but with the filter enabled. EVM is generally degraded due to
filter noise, as described in the Noise Characteristics section.
0
QPSK
16QAM
256QAM
1024QAM
–5
–10
–50
–80
11449-086
–50
–80
–15
–20
–35
–10
–40
–15
–45
–20
–50
–40
–30
–20
PIN (dBm)
–10
0
10
20
EVM (dB)
–5
–60
–60
–50
–40
–30
–20
–10
0
10
20
Figure 83 shows the EVM for several different digital gain settings.
There is an approximate 2 dB to 3 dB of EVM degradation at
the following gain settings: VGA1 = 9 dB, VGA2 = 12 dB,
VGA3 = 12 dB, and postamplifier = 3 dB. This is due to the
noise figure of the ADRF6518 increasing with the lower gain
setting of VGA1 (VGA1 sets the noise figure for the part). This
correlation is shown in Figure 23, which shows about a 2 dB
increase in noise figure when the VGA1 digital gain is changed
from 15 dB to 9 dB.
0
–70
–70
Figure 82. EVM vs. Input Power over Output Level; Filter Corner = 63 MHz,
QPSK, 50 MSPS, Gain Code = 0000000
–30
–50
–80
1.5V p-p
2.0V p-p
2.5V p-p
3.0V p-p
3.5V p-p
4.0V p-p
4.5V p-p
5.0V p-p
PIN (dBm)
–25
11449-087
EVM (dB)
–25
11449-088
–10
EVM (dB)
0
QPSK
16QAM
256QAM
1024QAM
GAINS:
GAINS:
GAINS:
GAINS:
GAINS:
GAINS:
GAINS:
15dB/21dB/21dB/3dB
15dB/21dB/21dB/9dB
9dB/12dB/12dB/3dB
12dB/12dB/12dB/3dB
15dB/12dB/12dB/3dB
15dB/15dB/15dB/3dB
15dB/18dB/18dB/3dB
–25
–30
Figure 81. EVM vs. Input Power over Digital Modulation Type;
Filter Corner = 63 MHz, Gain Code = 0000000, 1.5 V p-p Differential Output
Level Maintained
–35
Figure 82 shows a sweep over several output setpoints, from
1.5 V p-p to 5.0 V p-p. EVM only changes by a couple of
decibels for the full output range tested, which gives the user
flexibility in determining the level at which the output signal is
maintained. Although not shown in Figure 82, signals slightly
bigger than 5 V p-p have drastically degraded EVM, and loss of
lock can occur easily.
–45
–40
–50
–80
–70
–60
–50
–40
–30
–20
PIN (dBm)
–10
0
10
20
11449-089
0
–5
Figure 83. EVM vs. Input Power over Gain Code; Filter Mode = 63 MHz, QPSK,
50 MSPS, 1.5 V p-p Differential Output Level Maintained
Rev. 0 | Page 30 of 40
Data Sheet
ADRF6518
EFFECT OF FILTER BW ON EVM
PULL-DOWN RESISTORS FOR DISABLE FUNCTION
Figure 84 shows how changing the filter BW affects the EVM
for signals at several different symbol rates. The x-axis is
normalized such that it displays the baseband bandwidth of
each respective signal to the set filter corner. For example, a
filter corner of 10 MHz and a signal with a baseband bandwidth
of 5 MHz yields 2 Hz/Hz. Similarly, a filter corner of 50 MHz
and a signal with a baseband bandwidth of 25 MHz also yields
2 Hz/Hz. Baseband bandwidth is defined by the following:
The ADRF6518 offers a disable function, by pulling ENBL low,
that brings the supply current to approximately 1 mA. For the
function to work correctly, a dc path to ground must be
established on the output pins (OPP1, OPM1, OPP2, OPM2) to
allow proper discharge of the postamplifier. Figure 85 shows
how to properly place the pull-down resistors. The resistor
value must be big enough so that it does not interfere with the
output impedance that the postamplifer sees (for example, 400 Ω),
but not so big that it prevents proper discharge, effectively
becoming an open circuit. For most applications, a value of
RPULLDOWN = 10 kΩ sufficiently satisfies these conditions.
BWBB 
( Symbol Rate)  1   
2
The general behavior shows that the higher the ratio of the filter
corner to baseband bandwidth is, the better the EVM. This
behavior starts to plateau at around a 2× ratio. This behavior
affects the higher bandwidth signal more so than the smaller
bandwidth signals. The primary reason for this behavior is that
the noise is not flat across frequency (there is some interaction
between the filters and all the gain stages). The noise shaping
degrades EVM as the filter corner starts to encroach well
outside of the signal bandwidth.
INSTABILITY AT HIGH GAIN IN FILTER BYPASS
MODE
The user must be cautious while operating the ADRF6518 at the
highest of gains in filter bypass mode. Due to the high gain (up
to 66 dB) and wide bandwidth (up to 350 MHz with maximum
digital gains), the ADRF6518 is susceptible to oscillations when
it is in filter bypass mode and its gain is set above 60 dB. The
oscillation manifests itself with a broadband rise in the noise
floor and significantly degrades the SNR and EVM. Orthogonal
input to output signal paths on the printed circuit board (PCB)
helps reduce this oscillation. This can be seen in the top layer
silkscreen, shown in Figure 90. It is recommended that any
posts or headers not be placed for measurement purposes on
the signal paths, especially the output signal paths. Doing so
causes the output signal to radiate back to the input and induce
the oscillation at even lower gains than 60 dB.
0
5MSPS
10MSPS
20MSPS
50MSPS
–5
–10
EVM (dB)
–15
–20
–25
–30
–35
–40
–50
0
1
2
3
4
5
6
7
8
9
10
FILTER CORNER/BASEBAND BANDWIDTH (Hz/Hz)
11449-090
–45
32 ENBL
31 INP1
30 INM1
29 VPS
28 RAVG
27 VGN1
26 OFS1
25 VPS
Figure 84. EVM vs. Filter Corner/Baseband BW Ratio over Symbol Rate,
Filter Corner = 63 MHz, QPSK, 1.5 V p-p Output Level, −20 dBm Input Power
1
2
24 OPP1
23 OPM1
3
4
5
6
7
8
22 COM
21 VGN3
20 VOCM
19 COM
18 OPM2
17 OPP2
ADRF6518
RPULLDOWN
I
TO NEXT STAGE
RPULLDOWN
RPULLDOWN
Q
TO NEXT STAGE
Figure 85. Pull-Down Resistors
Rev. 0 | Page 31 of 40
11449-201
11
12
13
14
15
16
9
10
RPULLDOWN
COM
INP2
INM2
VPS
VPK
VGN2
OFS2
VPS
VPSD
COMD
LE
CLK
DATA
SDO/RST
VICM/AC
VPI
ADRF6518
Data Sheet
(OPP1/OPM2, OPP2/OPM2); therefore, the user must infer the
signal level at the input and output of each stage from the device
under test (DUT) input signal level and the gain settings, both
analog and digital. The maximum recommended signal levels
are shown in Figure 88. All signal levels are in V p-p differential.
The ADRF6518 has multiple stages per channel. Each stage can
independently be driven into compression depending on the
gain settings and input signal level. There is only access to the
input stages (INP1/INM1, INP2/INM2) and the output stages
5.0V p-p
2.2V p-p
2.2V p-p
2.6V p-p
3.1V p-p
5.0V p-p
INP1/INP2
OPP1/OPP2
INM1/INM2
OPM1/OPM2
VGN1
VGN3
VGN2
Figure 86. Maximum Signal Levels; Single Channel Shown
Rev. 0 | Page 32 of 40
11449-200
LINEAR OPERATION OF THE ADRF6518
Data Sheet
ADRF6518
EVALUATION BOARD
An evaluation board is available for testing the ADRF6518.
EVALUATION BOARD CONTROL SOFTWARE
The ADRF6518 evaluation board is controlled through the USB
port on a PC. This software enables/disables the dc offset
compensation loop and controls the filter corner frequency, the
high and low power modes, and the minimum and maximum
gains for each amplifier in the ADRF6518. For information
about the register map, see Table 5. For information about SPI
port timing and control, see Figure 2 and Figure 3.
To program the filter mode, offset correction, and power mode,
move the respective slider switch in the upper right corner of
the window.
To program the maximum gains of VGA1, VGA2, VGA3, and
the postamplifier, click the VGA1 Gain dB, VGA2 Gain dB,
VGA3 Gain dB, and Post Amp Gain dB drop-down boxes and
select the desired gain.
•
The VGA1 maximum gain can be set to 9 dB, 12 dB, or
15 dB.
The VGA2 and VGA3 maximum gain can be set to 12 dB,
15 dB, 18 dB, or 21 dB.
The postamplifier maximum gain can be set to 3 dB or 9 dB.
After the software is downloaded and installed, start the basic
user interface to program the filter corner and gain values (see
Figure 87).
•
To program the filter corner, perform one of the following:
When the user clicks the Write Selected Cutoff Frequency to
Device button, a write operation is executed, immediately
followed by a read operation. The updated information is
displayed in the VGA1 Gain dB, Filter Corner MHz, VGA2
Gain dB, VGA3 Gain dB, and Post Amp Gain dB fields.
•
Click the arrow in the Frequency Corner MHz section of
the window, select the desired corner frequency from the
menu, and click Write Selected Cutoff Frequency to
Device.
Click Frequency +1 MHz or Frequency −1 MHz to
increment or decrement the frequency corner in 1 MHz
steps from the current frequency corner.
11449-072
•
•
Figure 87. Analog Devices ADRF6518 Evaluation Software
Rev. 0 | Page 33 of 40
ADRF6518
Data Sheet
SCHEMATICS AND ARTWORK
VPOS
VPOSD
VPS
L2
33µH
VPSD
VPS
R3
0Ω
VPI
R45
open
C1
10µF
INM1
T1
6
R15
open
C33
open
C12
0.1µF
R47
0Ω
L1
33µH
COMD
C2
10µF
COM
COM_1
COM_2
C6
0.1µF
1
2
4
3
R37
open
R31
0Ω
VGN1
R48
0Ω
OPP1
C27
0.1µF
R19
0Ω
INP1_SE
R43
open
C23
0.1µF
C14
0.1µF
C10
VPS
R5
open
C9
0.1µF
0.1µF
TST1
1
C16
0.1µF
VPSD
R18
0Ω
C4
0.1µF
CLK
C53
DNI
R68
DNI
C19
0.1µF
25
1
VPSD
OPP1
2
COMD
OPM1 23
3
LE
4
CLK
5
DATA
R41
0Ω
OPM1_SE
C20
0.1µF
R39
open
VPS
26
27
OFS1
VPS
INP1
28
VGN1
29
INM1
R66
DNI
30
31
ENBL
C56
DNI
RAVG
32
LE
4
6
R20
0Ω
P2
R63
0Ω
T3
3
2
VPS
24
COM 22
C17
0.1µF
6
OPM2 18
VPI
OPP2
C31
0.1µF
9
10
11
VPS
C30
10µF
R21
10kΩ
VICM/AC
8
OFS2
C25
DNI
7
VGN2
C5
0.1µF
VPI
COM 19
VPS
VICM
R1
0Ω
SDO
SDO/RST
VPK
R67
DNI
VGN3
VOCM 20
INM2
C55
DNI
VGN3 21
ADRF6518
COM
DATA
INP2
R17
0Ω
12
13
14
15
16
VOCM
C18
0.1µF
17
C22
0.1µF
R38
open
C21
0.1µF
OPM2_SE
VPI
C13
0.1µF
R2
0Ω
R46
open
R35
0Ω
C8
INP2_SE
C7
R32
0Ω
R49
0Ω
T2
6
1
4
3
C15
0.1µF
VPS
C24
0.1µF
0.1µF
R6
open
0.1µF
C3
0.1µF
C32
0.1µF
R42
0Ω
3
T4
4
2
TST2
1
6
VGN2
R36
0Ω
2
R4
VPK
C34
open
0Ω
R50
0Ω
OPP2
R40
open
VPS
C11
0.1µF
INM2
R44
open
LEGEND
VGN1
VGN2
VGN3
VOCM
1
2
3
4
VPK
5
P4
1
6
7
8
9
10
P1
2
NET NAME
TEST POINT
SMA INPUT/OUTPUT
DIGITAL GROUND
ANALOG GROUND
Figure 88. Evaluation Board Schematic
Rev. 0 | Page 34 of 40
11449-073
VICM
Data Sheet
ADRF6518
Y1
24 MHz
3V3_USB
3
1
C51
22pF
C54
22pF
4
3V3_USB
2
R62
100kΩ
R64
100kΩ
C45
0.1mF
52
51
50
49
48
47
46
45
44
43
PD6_FD14
PD5_FD13
PD4_FD12
PD3_FD11
PD2_FD10
PD1_FD9
PD0_FD8
WAKEUP
VCC
1 RDY0_SLRD
53
GND
GND
54
PD7_FD15
55
CLKOUT
56
VCC
C37
0.1mF
GND
3 AVCC
C49
0.1mF
5V_USB
PA6_PKTEND39
PA5_FIFOARD138
XTALIN
6 AGND
1
2
3V3_USB
3
PA4_FIFOARD037
CY7C68013A-56LTXC
U4
7 AVCC
4
41
40
PA7_FLAGD_SCLS_N
4 XTALOUT
5
8 DPLUS
PA3_WU2 36
LE
PA2_SLOE 35
CLK
9 DMINUS
PA1_INT1_N34
DATA
10 AGND
PA0_INT0_N33
5
G1
G2
G3
G4
3V3_USB
11 VCC
VCC 32
12 GND
CTL2_FLAGC 31
13 IFCLK
SDO
3V3_USB
VCC
PB0_FD0
PB1_FD1
PB2_FD2
PB3_FD3
PB4_FD4
PB5_FD5
PB6_FD6
PB7_FD7
GND
VCC
GND
CTL1_FLAGB 30
17
18
19
20
21
22
23
24
25
26
27
28
SDA
14 RESERVED
SCL
15
16
R61
2kΩ
CTL0_FLAGA29
CR2
3V3_USB
3V3_USB
24LC64-I_SN
U2
3V3_USB
1
A0
SDA
5
2
A1
SCL
6
3
A2
WC_N
7
R59
2kΩ
C38
10pF
C39
0.1µF
ADP3334
U3
R60
2kΩ
3V3_USB
C52
1.0µF
4 GND
VCC
8
R70
140kΩ
C50
1000pF
3V3_USB
R69
78.7kΩ
1
OUT1
IN2 8
2
OUT2
IN1 7
3
FB
SD 6
4
NC
GND 5
5V_USB
C47
1.0µF
R65
2kΩ
CR1
DGND
3V3_USB
C40
0.1µF
C41
0.1µF
C42
0.1µF
C35
0.1µF
C36
0.1µF
C44
0.1µF
C46
0.1µF
11449-074
P5
RESET_N 42
2 RDY1_SLWR
C48
10pF
Figure 89. USB Evaluation Board Schematic
Rev. 0 | Page 35 of 40
Data Sheet
11449-075
ADRF6518
11449-076
Figure 90. Top Layer Silkscreen
Figure 91. Component Side Layout
Table 6. Evaluation Board Configuration Options
Components
C1, C2, C4, C11, C12, C15, C16,
C30, C31, L1, L2, R2, R3, P4
Function
Power supply and ground decoupling. Nominal supply decoupling
consists of a 0.1 µF capacitor to ground.
T1, T2, C3, C6, C7 to C10, R31,
R32, R43, R44, R45, R46, R47,
R48, R49, R50
Input interface. The INP1_SE, INM1, INP2_SE, and INM2 input SMAs
are used to drive the part differentially by bypassing the baluns.
Using only INP1_SE and INP2_SE in conjunction with the baluns
enables single-ended operation. The default configuration of the
evaluation board is for single-ended operation.
T1 and T2 are 8:1 impedance ratio baluns that transform a singleRev. 0 | Page 36 of 40
Default Conditions
C1, C2, C30 = 10 µF (Size 1210)
C4, C11, C12, C15, C16, C31 =
0.1 µF (Size 0402)
L1, L2 = 33 µH (Size 1812)
R2, R3 = 0 Ω (Size 0402)
P4 = installed
T1, T2 = Pulse Electronics
CX2049LNL
C3, C6 = 0.1 µF (Size 0402)
C7 to C10 = 0.1 µF (Size 0602)
R31, R32, R47 to R50 = 0 Ω (Size
0402)
Data Sheet
Components
ADRF6518
P1, R4, R15, C33, C34
Function
ended signal in a 50 Ω system into a balanced differential signal in a
400 Ω system.
R31, R32, R47, R48, R49, and R50 are populated for appropriate
balun interface
To bypass the T1 and T2 baluns for differential interfacing, remove
the balun interfacing resistors, R31, R32, R47, R48, R49, and R50, and
populate R43, R44, R45, and R46 with 0 Ω resistors.
Output interface. The OPP1, OPM1_SE, OPP2, and OPM2_SE output
SMAs are used to obtain differential signals from the part when the
output baluns are bypassed. Using OPM1_SE, OPM2_SE, and the
baluns, the user can obtain single-ended output signals. The default
configuration of the evaluation board is for single-ended operation.
T3 and T4 are 8:1 impedance ratio baluns that transform a
differential signal in a 400 Ω system into a single-ended signal in a
50 Ω system.
To bypass the T3 and T4 baluns for differential interfacing, remove
the balun interfacing resistors, R19, R20, R35, R36, R41, and R42, and
populate R37, R38, R39, and R40 with 0 Ω resistors.
R5 and R6 can be populated with an impedance of at least 400 Ω to
terminate the output in differential applications.
Enable interface. The ADRF6518 is powered up by applying a logic
high voltage to the ENBL pin (Jumper P2 is connected to VPS).
Serial control interface. The digital interface sets the corner
frequency, VGA1/VGA2/VGA3 maximum gains, and the
postamplifier maximum gain using the serial interface via the LE,
CLK, DATA, and SDO pins.
RC filter networks can be populated on the CLK, LE, and DATA lines
to filter the SPI signals. CLK, DATA, and LE signals can be observed
via P3 for debug purposes. Setting C25, C53, and C56 = 330 pF is
recommending for filtering.
DC offset compensation loop. The dc offset compensation loop is
enabled via the SPI port. When enabled, the C13 and C14 capacitors
are connected to circuit common. The high-pass corner frequency is
expressed as follows:
fHP (Hz) = 6.7 × (Post Filter Linear Gain/COFS (µF))
Input common-mode reference. The input common-mode voltage
can be monitored at the VICM pin. If the VICM pin is left open, an
input common-mode voltage must be supplied externally ( DC
coupling mode). If VICM pin is connected to ground, the input
common-mode defaults to VPI/2 (ac coupling mode).
Output common-mode setpoint. The output common-mode
voltage can be set externally when applied to the VOCM pin. If the
VOCM pin is left open, the output common-mode voltage defaults
to VPS/2.
Analog gain control. The range of the analog gain pins, VGN1, VGN2,
and VGN3, is from 0 V to 1 V, creating a gain scaling of 30 mV/dB.
Peak detector.
U2, U3, U4, P5
Cypress microcontroller, EEPROM, and LDO.
C35, C36, C40, C41, C42, C44,
C46
3.3 V supply decoupling. Several capacitors are used for decoupling
on the 3.3 V supply.
T3, T4, C19 to C24,
R5, R6,
R19, R20,
R35 to R42
P2
P3, R1, R17, R18, R21, R63, C25,
C53, C55, C56
C13, C14
C5
C18
C17, C27, C32
Rev. 0 | Page 37 of 40
Default Conditions
R43 to R46 = open (Size 0402)
T3, T4 = Pulse Electronics
CX2049LNL
C19 to C24 = 0.1 µF (Size 0402)
R5, R6 = open (size 0402)
R19, R20, R35, R36, R41, R42 = 0 Ω
(Size 0402)
R37 to R40 = open
(Size 0402)
P2 = installed for enable
P3 = installed
R1 = 0 Ω (Size 0402)
R21 = 10 kΩ (Size 0402)
C25, C53, C55, C56 = open (Size
0402)
R17, R18, R63 = 1 kΩ (Size 0402)
C13, C14 = 0.1 µF (Size 0402)
C5 = 0.1 µF (Size 0402)
C18 = 0.1 µF (Size 0402)
C17, C27, C32 = 0.1 µF (Size 0402)
P1 = installed
R4 = 0 Ω (Size 0402)
R15, C33, C34 = open (Size 0402)
U2 = Microchip MICRO24LC64
U3 = Analog Devices
ADP3334ACPZ
U4 = Cypress Semiconductor
CY7C68013A-56LTXC
P5 = Mini USB connector
C35, C36, C40, C41, C42, C44, C46
= 0.1 µF (0402)
ADRF6518
Data Sheet
Components
C37, C38, C39, C45, C48, C49,
R59, R60, R61, R62, R64, CR2
Function
Cypress and EEPROM components.
C47, C50, C52, R65, R69, R70,
CR1
LDO components.
Y1, C51, C54
Crystal oscillator and components. 24 MHz crystal oscillator.
Rev. 0 | Page 38 of 40
Default Conditions
C38, C48 = 10 pF (0402)
C37, C39, C45, C49 = 0.1 µF (0402)
R59, R60, R61 = 2 kΩ (0402)
R62, R64 = 100 kΩ (0402)
CR2 = ROHM SML-21OMTT86
C47, C52 = 1 µF (0402)
C50 = 1000 pF (0402)
R65 = 2 kΩ (0402)
R69 = 78.7 kΩ (0402)
R70 = 140 kΩ (0402)
CR1 = ROHM SML-21OMTT86
Y1 = NDK NX3225SA-24MHz
C51, C54 = 22 pF (0402)
Data Sheet
ADRF6518
OUTLINE DIMENSIONS
0.30
0.25
0.18
32
25
1
24
0.50
BSC
3.45
3.30 SQ
3.15
EXPOSED
PAD
17
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
8
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PIN 1
INDICATOR
9
BOTTOM VIEW
0.25 MIN
3.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
05-24-2012-A
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 92. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADRF6518ACPZ-R7
ADRF6518ACPZ-WP
ADRF6518-EVALZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead LFCSP_WQ, 7” Tape and Reel
32-Lead LFCSP_WQ, Waffle Pack
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 39 of 40
Package Option
CP-32-13
CP-32-13
ADRF6518
Data Sheet
NOTES
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11449-0-6/13(0)
Rev. 0 | Page 40 of 40