AN-1234
APPLICATION NOTE
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Interfacing the ADL5534 Dual IF Gain Block to the AD9640 High Speed ADC
Figure 1 shows an application circuit where the ADL5534 drives
the AD9640, a 150 MSPS, 14-bit ADC. The two 49.9 Ω resistors
connected to the AD9640 CML output establish the 0.9 V dc
bias for the AD9640 inputs and set the AD9640 differential
input impedance to 100 Ω.
CIRCUIT FUNCTION AND BENEFITS
This circuit uses the ADL5534 IF amplifier to provide a dual
IF gain block for the AD9640 14-bit, 150 MSPS dual ADC. The
ADL5534 is a high linearity, dual fixed, 20 dB gain amplifier
that can be adapted for use as a driver for a high performance
IF sampling ADC. The ADL5534 provides a simple approach
to interfacing the RFIN signal level of 200 mV p-p to the 2 V p-p
full scale of the high speed ADC. The low noise (2.5 dB NF at
70 MHz) and low distortion (IP3 of 40 dBm at 70 MHz) of the
ADL5534 ensure that the ADC performance is not compromised.
When operated as a quasi-differential amplifier, the ADL5534’s
two amplifiers present 100 Ω differential input and output
impedances. The input signal from a 50 Ω RF source is
converted to a differential signal with a 1:2 impedance ratio
flux-coupled transformer. This matches the 50 Ω source to the
100 Ω differential load of the ADL5534. Between the ADL5534
output and the AD9640 input, a third-order low-pass filter
presenting a 100 Ω differential impedance to the source and
load is implemented.
CIRCUIT DESCRIPTION
Table 1. Devices Connected/Referenced
Product
ADL5534
AD9640
Description
20 MHz to 500 MHz dual IF amplifier
14-bit, 80/105/125/150 MSPS, dual ADC
Due to the different common mode voltage levels required by
the ADL5534 and the AD9640, the ADL5534 must be ac-coupled
to the AD9640. Capacitors of 100 pF were chosen to reduce any
low frequency noise coming from the ADL5534 and to provide
dc blocking.
5V
10nF
13
Z1
ADL5534
1nF
CLIN1
NC
15
14
NC
RFOUT1
NC
CLIN2
NC
GND
CML = 0.9V
NC
RFOUT2
NC
5
1:2
Z
4
1µF
NC
12
1nF
120nH
11
100pF
10
120nH
33Ω
1.8V
VIN+
49.9Ω
16pF
100pF
AVDD CML DVDD
AD9640
4.7pF
49.9Ω
9
120nH
1.8V
120nH
33Ω
VIN–
AGND
DRGND
8
3
10nF
NC
NC
RFIN
7
2
NC
6
1
RFIN2
MINI-CIRCUITS
ADT2-1T-1P+
TRANSFORMER
RFIN1
16
470nH
470nH
1µF
GND
Figure 1. Interface Between the ADL5534 and AD9640 with 49.9 Ω Resistors to CML to Establish the 0.9 V DC Bias for the AD9640 Inputs and
Set the AD9640 Differential Impedance to 100 Ω (Simplified Schematic: Decoupling and All Connections Not Shown)
Rev. B | Page 1 of 3
08537-001
5V
10nF
AN-1234
Application Note
The measured results for this filter show 0.5 dB insertion loss
for a 20 MHz bandwidth centered around 92 MHz. Figure 2
shows the measured wideband response for the filter.
0 SFDR = 78.267dBc
NOISE FLOOR = –110.131dB
–15 FUND 1 = –7.181dBFs
FUND 2 = –7.191dBFs
–30 IMD (2F1 – F2) = –80.538dBc
IMD (2F2 – F1) = –82.086dBc
–45
5
(dBFS)
0
–10
–60
–75
–90
–15
–105
–20
–120
–25
–135
–30
0
6
–35
18
24
30
36
42
48
54
60
FREQUENCY (MHz)
Figure 4. Measured Two-Tone Performance for Input Tones at 93 MHz and
92 MHz, Sample Rate of 122.8 MSPS
–45
50
100
150
200
250
300
350
400
FREQUENCY (MHz)
08537-002
–40
COMMON VARIATIONS
Figure 2. Measured Frequency Response of the LC Filter
The single-tone FFT results shown in Figure 3 for an input signal of
approximately 93 MHz show an SNR of 69.3 dB and an SFDR of
82 dBc. Note that because of aliasing, the fundamental frequency
in the FFT is at 122.8 MHz – 93 MHz = 31.8 MHz.
0 SNR = 69.334dBc
SFDR = 82.267dBc
–15 NOISE FLOOR = –109.519dB
FUND = –1.05dBFs
–30 SECOND = –82.262dBc
THIRD = –88.688dBc
–45
(dBFS)
12
08537-004
NORMALIZED LOSS (dB)
–5
This application circuit can be modified for any IF frequency
within the operating range of the ADL5534 and AD9640. As an
alternative to the ADL5534, the AD8375, a digitally programmable
differential variable gain amplifier, can be used.
Alternatively, the AD8352, a resistor programmable differential
amplifier, can be used to convert from single ended to differential
without the requirement of an external balun. The AD8352,
AD8375, and AD8376 (dual version of the AD8375) are all true
differential amplifiers that provide rejection of common-mode
signals at their input.
The circuit must be constructed on a multilayer PC board with
a large area ground plane. Proper layout, grounding, and decoupling techniques must be used to achieve optimum performance
(see MT-031 Tutorial, MT-101 Tutorial, the ADL5534 evaluation
board layout, and the AD9640 evaluation board layout). Both the
ADL5534 and the AD9640 have exposed thermal pads that should
be soldered directly to the low impedance ground plane.
–60
–75
–90
–105
–120
0
6
12
18
24
30
36
42
48
54
60
FREQUENCY (MHz)
08537-003
–135
Figure 3. Measured Single-Tone Performance for An Input Frequency of
93 MHz, Sample Rate of 122.8 MSPS
The two-tone results for tones at 91 MHz and 93 MHz are
shown in Figure 4 and yield an IMD3 of −80.5 dBc and
SFDR of 78 dBc. The AD9640 was clocked at a sample rate
of 122.8 MSPS for both single and two-tone tests.
LEARN MORE
AN-742 Application Note, Frequency Domain Response of
Switched Capacitor ADCs. Analog Devices.
AN-827 Application Note, A Resonant Approach to Interfacing
Amplifiers to Switched-Capacitor ADCs. Analog Devices.
Kester, Walt. 2006. High Speed System Applications. Analog
Devices. Chapter 2, “Optimizing Data Converter Interfaces.”
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of “AGND” and “DGND.” Analog Devices.
MT-073 Tutorial, High Speed Variable Gain Amplifiers. Analog
Devices.
MT-101 Tutorial, Decoupling Techniques. Analog Devices.
Rev. B | Page 2 of 3
Application Note
AN-1234
Data Sheets and Evaluation Boards
REVISION HISTORY
ADL5534 Data Sheet
4/13—Rev. A to Rev. B
Changed Document Title from CN-0049 to
AN-1234 .............................................................................. Universal
ADL5534 Evaluation Board
AD9640 Data Sheet
AD9640 Evaluation Board
AD8352 Data Sheet
AD8375 Data Sheet
2/10—Rev. 0 to Rev. A
Updated Format ................................................................. Universal
Changes to Circuit Function and Benefits..................................... 1
Changes to Circuit Description....................................................... 1
Changes to Common Variations ..................................................... 2
8/08—Revision 0: Initial Version
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AN08537-0-4/13(B)
Rev. B | Page 3 of 3