YOUR SEMICONDUCTOR SOLUTIONS RESOURCE
Volume 10, Issue 2
ANALOG-TO-DIGITAL
CONVERTER AND DRIVER ICS
ADC with Configurable Filtering
Adds Flexibility . . . . . . . . . . . . . . . . . . . 1
High Speed ADC Portfolio Responds
to Market Demands . . . . . . . . . . . . . . . 2
High Performance ADC Dissipates Only
15 mW to Solve Heat Dissipation . . . . 3
Smallest SAR ADC Targets SpaceConstrained Applications . . . . . . . . . . . 3
ADC Selection Guide . . . . . . . . . . . . . . 4
ADC with Integrated Quadrature
Error Correction Minimizes Errors . . . . 6
Why Use an ADC Driver Amplifier? . . . . 6
Circuits from the Lab—Tested
Design Resource . . . . . . . . . . . . . . . . . 7
Buffer Enhances Clock Integrity to
Enable Rated Performance . . . . . . . . . 7
Diff Amp Calculator Design Tool . . . . . . 8
Precision ∑-∆ ADC with Configurable Filtering Adds Flexibility
to Industrial Measurement System Designs
Engineers designing industrial measurement systems must take into account the need to reject
50 Hz and 60 Hz power line frequencies in sensitive signal chains. Some system modules need a
high level of power line rejection and must sacrifice conversion speed to meet these requirements,
while other system modules must provide faster conversion speeds but still maintain some reduced
level of power line rejection. Until now, the design engineer had to select and qualify two separate
∑-∆ ADCs to meet requirements in these two types of data measurement systems.
Solution The AD7194 8-/16-channel, 4.8 kHz, ultralow noise, 24-bit ∑-∆ ADC with integrated PGA and
fast settling filter is the first ADC to offer design engineers a flexible approach to solving the
power line rejection problem. The AD7194 contains a regular sinc filter, which gives excellent
rejection of 50 Hz and 60 Hz
AD7194: DEEP 50 Hz AND 60 Hz REJECTION, FDATA = 50 Hz, T
= 80 ms
line frequencies. However,
0
the device also offers a
fast settling filter option,
–20
which allows customers to
–40
achieve nearly four times
–60
the conversion speed, while
maintaining around 40 dB
–80
of line frequency rejection.
–100
With this flexibility in application,
–120
system designers can utilize
0
50
100
150
200
250
300
one ∑-∆ ADC IC for multiple
FREQUENCY (Hz)
industrial measurement system
AD7194: SINGLE CYCLE FAST SETTLING, FDATA = 42.1 Hz, T
= 23.8 ms
requirements, saving time to
0
market and R&D costs.
SETTLE
H(f) (dB)
Contents
SETTLE
–20
•Fast settling filter option
•Ultralow noise
–40
H(f) (dB)
AD7194 Features
–60
–80
•On-chip PGA
–100
•16 channels in 32-lead,
5 mm × 5 mm LFCSP
–120
0
50
100
150
200
FREQUENCY (Hz)
250
Applications
Visit our new website for
data sheets, samples,
and additional
resources.
www.analog.com/V10ADCs
• PLC/DCS analog input modules
• Temperature measurement
• Test and measurement systems
• Scientific instruments
ADI engineers offer multiple tested circuit solutions for designing a precision weigh
scale system. For access to these circuit notes, visit www.analog.com/circuits and
view the News section.
300
New High Speed ADC Portfolio Responds to Today’s Market Demands for Lower
Power and Smaller Package Footprint
Industries such as test instrumentation, communications, and healthcare have traditionally provided a large market for state-of-the-art,
high speed, high performance ADCs. These markets were early adopters of the latest breakthrough technology, which they in turn
used to enable the next generation of their products and systems. The converter requirements of these markets were typically driven
by signal chain performance specifications rather than power dissipation and package size. However, today’s market environment
emphasizes reducing overall system power (“going green”) to enable lower total cost of ownership for operators and to address the
global mandate for energy conservation. In addition, there is a trend to make
systems portable and battery-operated, which puts further constraints on board
space and cooling capacities. These market pressures are, of course, to be met
with no reduction in system performance. A new breed of high speed converter is
needed.
Solution In response to these market demands for low power consumption and smaller
package sizes in high speed, high performance ADCs with no corresponding
trade-offs in performance, ADI has developed a family of 26 new 10-bit to 16-bit
ADCs that move the power curve decidedly downward. In fact, in the case of the
16-bit, 125 MSPS ADCs, power is reduced by 87% over competing devices. This
lower power and its accompanying reduced heat dissipation requirement have
enabled the use of smaller, pin-compatible package sizes to reduce board space
and offer flexibility in system upgrade options.
Industry’s Smallest 16-Bit, Low Power, Single Channel ADC Spans 20 MSPS to 80 MSPS
The AD9266 single channel, 16-bit, low power ADC is available in a small 5 mm × 5 mm package, and the pinout supports
resolutions from 10 bits to 16 bits. The low power multistage ADC core is based on a proprietary, high performance, sample-and-hold
circuit and on-chip voltage reference. The product uses a differential pipeline architecture with output error correction logic to provide
16-bit accuracy at 80 MSPS data rates and guarantees no missing codes over the full operating temperature range. The ADC contains
several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and
programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom
patterns, along with custom user-defined test patterns entered via the SPI.
Industry’s First Low Power, Single Channel, 16-Bit ADC Clocks at 125 MSPS
The AD9265 single channel, 16-bit, low power ADC was designed to support communications applications requiring low bill of
material costs, small size, and flexibility. Consuming only 370 mW, this breakthrough in power consumption represents a 51% savings
compared to competitive low power solutions. The ADC core features a multistage, differential pipelined architecture with integrated
output error correction logic. The AD9265 features a wide bandwidth differential sample-and-hold analog input amplifier supporting a
variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer provides
means to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The ADC
output data are either parallel 1.8 V CMOS or 1.8 V LVDS (DDR). Flexible power-down options allow significant power savings when
desired. Programming for setup and control are accomplished using a 3-bit SPI-compatible serial interface. Production quantities are
available now.
Industry First: Sub 100 mW/Channel, Low Power, Dual Channel ADC Spans 20 MSPS to 80 MSPS
The AD9269 dual channel, 16-bit, low power ADC consumes 93 mW per channel, which is 6.5 times lower than competing devices.
The AD9269 is a monolithic, dual channel, 16-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS ADC featuring a high performance sampleand-hold circuit and on-chip voltage reference. It’s also the industry’s first 16-bit ADC family to include a QEC and dc offset digital
processing block. This converter uses multistage differential pipeline architecture with output error correction logic to provide 16-bit
accuracy at 80 MSPS data rates, and guarantees no missing codes over the full operating temperature range. The ADC operates from
a 1.8 V supply and contains several features designed to maximize flexibility and minimize system cost, such as programmable clock
and data alignment and programmable digital test pattern generation.
The entire high speed, low power ADC portfolio is included in the selection table on Page 4 and Page 5 of this solutions bulletin.
2
For data sheets, samples, and additional resources, visit www.analog.com/V10ADCs
18-Bit, 2 MSPS, High Performance ADC Dissipates Only 15 mW to Solve Heat
Dissipation in Dense Data Acquisition System Designs
Data acquisition system designers are frequently being asked to implement dense multichannel signal capture systems without the
benefit of heat management circuitry because of the added noise, potential data corruption, cost, and space that this circuitry would
introduce. These designers require data conversion components that do not sacrifice speed or performance to achieve the low power
dissipation specifications needed.
Solution The AD7986 18-bit, 2 MSPS ADC IC offers an industry-leading combination of 97 dB SNR performance, 15 mW power consumption,
and small footprint. This combination of features allows designers to accommodate more high resolution data acquisition channels in
smaller spaces and obviates the need for complex heat dissipation and cooling subsystems that consume resources and real estate.
The performance and low power achieved by the AD7986 ADC also enable new generations of portable and battery-powered high
resolution data acquisition systems.
AD7986 Features
Applications
•18-bit resolution with no missing codes
•Throughput: 2 MSPS (TURBO = high),
1.5 MSPS (TURBO = low)
•Low power dissipation: 15 mW with
external VREF, 26 mW with internal VREF
•Data acquisition systems
•SNR: 97 dB with external VREF
•Laboratory equipment
•Medical instruments
•20-lead, 4 mm × 4mm LFCSP
Smallest 12-Bit SAR ADC with Integrated Temperature Sensor Features
4 mm × 4 mm Package Size to Target Space-Constrained Applications
To meet today’s industrial market environment, many data acquisition design engineers require multichannel data acquisition with
added temperature sensing in space-constrained applications.
Solution The AD7298 12-bit, 1 MSPS SAR ADC is the world’s smallest
8-channel SPI interface ADC with internal temperature sensor
and voltage reference. The device is housed in a very small
4 mm × 4 mm, 20-lead LFCSP.
The AD7298 is ideally suited for monitoring variables in a variety
of systems, including telecommunications, as well as process and
industrial control. This device offers more functionality per mm2 of
package area than any similar converter device on the market. A
2.5 V 6 ppm/°C internal reference offers both accurate conversion
and additional space-saving advantages. An on-board band gap
temperature sensor digitizes temperature with a resolution of
0.25°C. On-board sequencer functionality allows multichannel
preprogrammability, allowing conversion on a sequence of
selected channels. A digital interface voltage range of 1.8 V to
3.6 V allows flexibility in its microprocessor interface.
AD7298 Features
AD7298 ADC Block Diagram
AVDD
AGND
REFIN
REF
BUF
VIN0
T/H
INPUT
MUX
VIN7
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
SEQUENCER
SCLK
DOUT
CONTROL LOGIC
DIN
CS
TEMP
SENSOR
VDRIVE
PD
•12-bit, 1 MSPS throughput, 8-channel SAR ADC
Applications
•Channel sequencer functionality
• Multichannel data acquisition systems
• ±2°C internal temperature-to-digital sensor
• Base station monitoring applications
• Instrumentation and control
•Internal 2.5 V reference
•20-lead LFCSP
For data sheets, samples, and additional resources, visit www.analog.com/V10ADCs
3
New 𝚺-𝚫 ADCs
Part
Resolution
Number
(Bits)
AD7190
AD7191
Number of Channels
Differential/Pseudo Differential
Noise
(rms)
PGA
On-Chip
Clock
2/4
8.5 nV
Yes
24
24
2/4
15 nV
Yes
Package
Price
($U.S.)
Yes
24-lead TSSOP
5.90
Yes
Pin-programmable
24-lead TSSOP
3.80
AD7192
24
2/4
11 nV
Yes
Yes
24-lead TSSOP
4.90
AD7193
24
4/8
11 nV
Yes
Yes
28-lead TSSOP
5.40
AD7194
24
8/16
11 nV
Yes
Yes
32-lead LFCSP
6.40
AD7171
16
1/0
11.5 μV
No
Yes
10-lead LFCSP
1.15
AD7170
12
1/0
11.5 μV
No
Yes
10-lead LFCSP
0.95
New PulSAR® ADCs
Part
Resolution
Number
(Bits)
Speed
(MSPS)
Power
(mW)
SNR
(dB)
INL
(LSB)
Package
Price
($U.S.)
AD7986
18
2
15
97
±2
20-lead LFCSP
33.13
AD7984
18
1.33
10.5
99.7
±2.25
10-lead LFCSP, 10-lead MSOP
28.29
AD7982
18
1
7
99
±2.5
10-lead LFCSP, 10-lead MSOP
23.28
AD7985
16
2.5
15.5
90
±1.5
20-lead LFCSP
30.99
AD7983
16
1.33
10.5
91.6
±1.25
10-lead LFCSP, 10-lead MSOP
20.19
AD7980
16
1
7
91.5
±2
10-lead LFCSP, 10-lead MSOP
13.38
AD7944
14
2.5
9
84.5
±1
20-lead LFCSP
9.99
Price
($U.S.)
New Multichannel SAR ADCs
Part
Resolution
Channels
Number
(Bits)
Throughput
Rate
AIN Range
(V)
Power
Supply (V)
Interface
AD7291
8
12
22 kSPS
0 to ref
2.7 to 3.6
I2C®
20-lead TSSOP
3.90
AD7298
8
12
1 MSPS
0 to ref
2.7 to 3.6
SPI
20-lead TSSOP
3.90
New High Speed, Low Power ADCs
Resolution
Part Number
(Bits)
Number of
Channels
Sample Rate
(MSPS)
Power Consumption
(mW/Channel)
Price ($U.S.)
1
65
70
4.17
1
80
78
4.50
1
65
76
12.08
1
80
85
16.70
1
65
77
23.35
1
80
87
25.00
1
80
241
33.00
AD9255BCPZ-105
1
105
322
45.00
AD9609BCPZ-65
AD9609BCPZ-80
AD9629BCPZ-65
AD9629BCPZ-80
10
12
AD9649BCPZ-65
AD9649BCPZ-80
AD9255BCPZ-80
14
AD9255BCPZ-125
1
125
370
59.93
AD9265BCPZ-80
1
80
241
48.33
AD9265BCPZ-105
1
105
322
56.67
AD9265BCPZ-125
1
125
370
65.00
AD9266BCPZ-65
1
65
97
43.33
AD9266BCPZ-80
1
80
110
48.33
AD9269BCPZ-65
2
65
80
73.66
2
80
93
84.09
AD9269BCPZ-80
16
16
All prices shown are in 1000 quantity.
4
Package
For data sheets, samples, and additional resources, visit www.analog.com/V10ADCs
ADC Driver Amplifier ICs
Part
Number
–3 dB BW
(MHz)
Minimum
Gain ACL
(dB)
Voltage
Supply
(V)
Supply
Current
(mA)
Slew
Rate
(V/𝛍s)
Distortion
(2nd)
(dBc)
Distortion
(3rd)
(dBc)
Package
Price
($U.S.)
AD8132
350
1
±5
10.7
1200
–97
–100
8-lead MSOP,
8-lead SOIC
1.67
AD8139
410
1
5 to 12
24.5
800
–90
–105
8-lead LFCSP,
8-lead SOIC
3.75
AD8275
15
0.2 (fixed)
3.3 to 15
1.9
25
–106
(THD + N)
–106
(THD + N)
8-lead MSOP
1.60
AD8351
2200
1
3 to 5.5
28
13,000
–79
–81
10-lead MSOP
2.68
AD8352
2200
—
3 to 5.5
37
11,000
–83
–83
16-lead LFCSP
3.53
ADA4922-1
38
1
±12
9.4
730
–116
–109
—
3.63
ADA4927-1
2300
1
4.5 to 11
22.1
5000
–87
–89
16-lead LFCSP
3.79
ADA4932-1
560
1
3 to 11
9.6
410
–72
–80
16-lead LFCSP
2.95
ADA4937-1
1900
1
3 to 5.25
39.5
6000
–70
–84
16-lead LFCSP
3.79
ADA4938-1
1000
1
4.5 to 11
40
4700
–82
–82
16-lead LFCSP,
24-lead LFCSP
3.79
ADA4939-1
1400
2
3 to 5
37.7
6800
–77
–95
16-lead LFCSP
3.79
ADA4941-1
30
2
2.7 to 12
2.3
22
–75
–71
8-lead LFCSP,
8-lead SOIC
2.42
ADA4950-1
750
1
3 to 11
9.5
2900
–80
–84
16-lead LFCSP,
24-lead LFCSP
2.99
ADL5561
2900
6
3.3
40
9800
–95
–87
16-lead LFCSP
3.68
ADC Clock Buffers
Part Number Number of References
Number of Outputs
Max Output (MHz)
Jitter (ps)
Price ($U.S.)
ADCLK905
1
1 ECL
6000
0.06
5.60
ADCLK907
2
2 ECL
6000
0.06
6.75
ADCLK925
1
2 ECL
6000
0.06
5.95
ADCLK914
1
1 HVDS
6000
0.11
6.95
ADCLK946
1
6 LVPECL
4800
0.075
6.25
ADCLK954
2
12 LVPECL
4800
0.075
6.95
Power Management ICs
Part
Number
Description
VIN Range
(V)
VOUT Preset
Summary
(V)
IOUT
Max
(A)
ISW
Peak
(A)
Supply
Current
(𝛍A)
Switching
Frequency
(MHz)
Price
($U.S.)
ADP2108
600 mA, 3 MHz, fast transient,
synchronous step-down converter
2.3 to 5.5
11 options:
1.0 to 3.3
0.6
1.3
19
3
0.60
ADP2109
Compact 600 mA, 3 MHz, step-down
converter with output discharge
2.3 to 5.5
4 options:
1.0 to 1.8
0.6
1.3
18
3
0.70
ADP2121
600 mA, 6 MHz, synchronous,
step-down dc-to-dc converter
2.3 to 5.5
4 options:
1.8 to 1.875
0.5
1
36
6
0.80
ADP2503
600 mA, 2.5 MHz, buck-boost
dc-to-dc converter
2.3 to 5.5
6 options:
2.8 to 5
0.6
1
38
2.5
1.30
ADP2504
1 A, 2.5 MHz, buck-boost
dc-to-dc converter
2.3 to 5.5
6 options:
2.8 to 5
1
1.3
38
2.5
1.40
All prices shown are in 1000 quantity.
For data sheets, samples, and additional resources, visit www.analog.com/V10ADCs
5
ADC with Integrated Quadrature Error Correction and DC Offset Digital Processing
Blocks Dynamically, Minimizes Errors Produced by I/Q Complex Signal Receivers
In today’s multichannel, high data rate communications systems, quadrature and gain errors can be produced by mismatching and
leakage in the individual components in the I/Q receiver signal chain stages ahead of the ADC function. These errors can affect
quality of service, network reliability, and overall system functionality.
Solution The AD9269 is the industry’s first dual 16-bit, 80 MSPS ADC, and it includes a QEC and a dc offset digital processing block
specifically designed to address this problem. This functional block dynamically minimizes the errors produced in an in-phase/
quadrature (I/Q) complex signal receiver system. By utilizing the QEC functional block, system designers can relax component
testing requirements by enabling this function to minimize gain and phase errors due to component mismatches. The net result can
be a more robust receiver design. Depending on operating conditions, enabling the QEC function of the AD9269 dual ADC can result
in as much as 60 dB of image suppression.
The AD9269 operates from a 1.8 V supply and contains several additional features designed to maximize flexibility and minimize
system cost, such as programmable clock and data alignment and programmable digital test pattern generation.
Integrated Quadrature Error Correction (QEC Minimizes I/Q Complex Rx Errors)
WITHOUT QEC
WITH QEC
–60 dBc OF IMAGE
SUPPRESSION
Why Use an ADC Driver Amplifier Instead of a Transformer in Front of an ADC?
In order to properly condition a signal for an analog-to-digital converter (ADC), four considerations must be made. First, if the
signal is single-ended, it needs to be converted to a differential signal. Sending a single-ended (ground-referenced) signal into a
differential input ADC results in the immediate loss of 6 dB of dynamic range, which means a bit is lost before the conversion even
begins. Second, most ADCs have large sampling capacitors on the input to hold the sampled value during the conversion cycle.
When the ADC switches back from hold mode to track mode, the capacitor is reconnected to the input and a large charge injection
can occur, injecting noise back into the signal path. Reverse isolation is required to prevent the charge injection. Third, unless the
dc level of the incoming signal already exactly matches the required common-mode input level, dc level translation must occur.
Finally, ADC inputs can load signal sources, especially sources with high source impedances, and an impedance transformation
stage may be required.
Of these four functions, a transformer can only perform one: the single-ended-to-differential conversion. There is no reverse
isolation on a transformer. As a passive device, there is no ability to provide power gain or impedance transformation. A voltage
gain results in a corresponding current reduction. While some circuit tricks involving ac coupling and rebiasing a signal can be
employed to interface dc levels through a transformer, this approach means that low frequency content (below the ac coupling
high-pass response) will be lost.
A differential amplifier acting as an ADC driver, however, can provide all four functions. Analog Devices offers a wide assortment
of differential amplifiers for ADC driver functions in a variety of applications. There are the ADL5561 and ADL5562 for high IF
signals and the ADA4937 and ADA4939 for dc to low-/mid-IF signals. The ADA4927 also serves this space and offers the additional
benefit of high performance at high gains. There are the ADA4932 and ADA4950 for low power applications and many more. There
is even the ADA4941 for the precision converter space. Whatever the application, Analog Devices has a differential amplifier that
will enhance circuit performance and simplify design efforts.
6
For data sheets, samples, and additional resources, visit www.analog.com/V10ADCs
Circuits from the Lab—Tested Design Resource Provides Faster Time
to Market and Lowers Risks
As design engineers look to build systems from the ground up, they often rely on various calculators, simulation
models, software, and other design tools to aid in the selection, evaluation, and implementation of components.
Circuits from the Lab™ by Analog Devices is a new design assistance resource that provides design engineers with tested circuit
solutions for many common applications. Circuits from the Lab pairs at least two complementary components, such as an ADC and
amplifier, to present a circuit optimized for a targeted application. Each circuit has been built and tested in the lab and can be easily
integrated into designs, resulting in reduced design risk and faster time to market.
Featured Circuits from the Lab
CN-0041 Circuit Note, Single-Ended-to-Differential
Conversion Using the AD8138 Low Distortion Differential
ADC Driver and AD7356 5 MSPS, 12-Bit SAR ADC
This circuit provides single-ended-to-differential conversion of an
input signal to the AD7356, 5 MSPS, 12-bit SAR ADC. This circuit
has been designed to ensure maximum performance of the
AD7356 by providing adequate settling time and low impedance.
An ideal method of applying differential drive to the AD7356 is
to use a differential amplifier, such as the AD8138. This part
can be used as a single-ended-to-differential amplifier or as a
differential-to-differential amplifier. The AD8138 also provides
common-mode level shifting. For access to this circuit note, visit
www.analog.com/CN-0041.
CF1
2.048V
1.024V
0V
RF1
RS
RG1
+2.048V
GND
–2.048V
51𝛀
VOCM
RG2
AD8138
VIN+
AD7356
RS
VIN–
REFA /REFB
2.048V
1.024V
0V
RF2
CF2
10k𝛀
10𝛍F
10k𝛀
Buffer Enhances Clock Integrity to Enable Rated Performance from High Performance,
High Speed ADCs
Designers using high performance, high speed analog-to-digital converters (ADC) in their systems do so to bring speed, accuracy,
and high resolution to their system. One of the primary selection criteria for the ADC is its signal-to-noise (SNR) ratio. Ancillary design
elements impact the converter’s performance—and a key consideration is clock integrity. Jitter on the input clock of the ADC will
degrade its SNR performance, and it can be a significant challenge to maintain a good low noise/low jitter clock signal throughout the
entirety of the system’s clock tree.
Solution Analog Devices has developed a broad portfolio of clock buffers designed to help designers solve this clock integrity challenge. With a
clock buffer inserted between the converter and the system clock tree, jitter figures on the order of 75 fs for LVPECL fanout buffers and
extremely low skew on the order of 9 ps (picoseconds) can readily be achieved. These buffer ICs also provide up to 12 channels of low
jitter clock fanout and sharpen the edge of a clock signal that may have been slowed by long trace routing across the PCB.
The ideal clock signal for a data converter features not only low phase noise/jitter but also very sharp rise and fall edges. When a very
sharp edge for just one or two converters is needed, the ADCLK905, ADCLK907, ADCLK914, and ADCLK925 clock buffers can provide
very fast edges with extremely little impact on the noise of the clock signal when located in close proximity to the converter. In addition to
sharpening edges, parts such as the ADCLK914 also provide high differential voltage swing, which can serve to limit ADC coupling noise.
ADI has a portfolio of low jitter clock buffer products ranging from one to 12 outputs and various logic families to meet the requirements
of clocking high performance, high speed ADCs.
For data sheets, samples, and additional resources, visit www.analog.com/V10ADCs
7
Analog Devices, Inc.
600 North Bedford Street
East Bridgewater, MA 02333-1122
ADI Diff Amp Calculator Design Tool Simulates Diff Amp Performance
The advantages of driving a high performance ADC input differentially are compelling—improved common-mode
noise and interference rejection, increased dynamic range, and common-mode offset adjustment capability are
among the benefits. However, selecting and interfacing the correct differential amplifier driver for a given ADC can
be a challenging and time-consuming engineering task.
Solution ADI’s new ADI Diff Amp Calculator™ is an updated and
downloadable version of ADI’s popular online ADIsimDiffAmp™
design tool. This free graphical calculation tool reduces
differential amplifier design time from hours to minutes.
The new tool performs all the required differential amplifier
calculations, which reduces design risks and further speeds
time to market. This tool calculates gain and component
values of a differential amplifier circuit for terminated or
unterminated inputs or output loads, as well as determines
the input/output and VOCM voltage range. In addition, it
calculates noise and power dissipation to ensure that the
device meets the required operating conditions. There is
also a graphical plot of the total noise of the amplifier and
surrounding circuitry conveniently displayed in an intuitive and easy to understand format.
Download your free copy today at www.analog.com/diffampcalculator.
AN-1026 Application Note, High Speed Differential ADC Driver Design Considerations, provides in-depth
technical details on designing with differential amplifiers in high speed applications. To access this note,
visit www.analog.com/AN1026.
All prices in this bulletin are in USD in quantities
greater than 1000 (unless otherwise noted),
recommended lowest grade resale, FOB U.S.A.
I2C refers to a communications protocol
originally developed by Philips Semiconductors
(now NXP Semiconductors).
©2009 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the
property of their respective owners.
Inventory Code: ADC-V10-IS2-09
Printed in the U.S.A.
SB08796-2-12/09
www.analog.com
Analog Devices, Inc.
Worldwide Headquarters
Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
U.S.A.
Tel: 781.329.4700
(800.262.5643,
U.S.A. only)
Fax: 781.461.3113
Analog Devices, Inc.
Europe Headquarters
Analog Devices, Inc.
Wilhelm-Wagenfeld-Str. 6
80807 Munich
Germany
Tel: 49.89.76903.0
Fax: 49.89.76903.157
Analog Devices, Inc.
Japan Headquarters
Analog Devices, KK
New Pier Takeshiba
South Tower Building
1-16-1 Kaigan, Minato-ku,
Tokyo, 105-6891
Japan
Tel: 813.5402.8200
Fax: 813.5402.1064
Analog Devices, Inc.
Southeast Asia
Headquarters
Analog Devices
22/F One Corporate Avenue
222 Hu Bin Road
Shanghai, 200021
China
Tel: 86.21.2320.8000
Fax: 86.21.2320.8222