A Robust Battery Monitoring Solution Using
the Latch-Up Proof ADG5408 8:1 Multiplexer
By Sean Brown
Integrated circuits that are used in environments such as automotive,
military, process, or industrial applications can be exposed to conditions
that are beyond the specified operating limits. In battery monitoring
systems, fault conditions can develop, and overvoltages can be applied
to these ICs. Even transient overvoltage conditions may cause traditional
CMOS switches to experience a condition known as latch-up. Latch-up is
an undesirable, high current state that can lead to device failure and can
persist even after the fault condition has been removed.
+18V
In junction isolation technology, the N- and P-wells of the PMOS and NMOS
transistors form a parasitic silicon-controlled rectifier (SCR) circuit. An overvoltage condition can trigger this SCR, causing a significant amplification of
current that, in turn, leads to latch-up.
Latch-up can occur if either the input or the output pin voltage exceeds the
supply rail by more than a diode drop or by improper power supply sequencing. If a fault occurs on the channel, and the signal exceeds the maximum
rating, the fault can trigger the latch-up state in a typical CMOS part.
–18V
VDD GND VSS
ADG5408
S1
BAT 1
BAT 2
BAT 3
BAT 4
BAT 5
BAT 6
BAT 7
S2
S3
S4
D
S5
S6
S7
S8
BAT 8
1-OF-8
DECODER
A0 A1
A2 EN
+18V
–18V
+VS
RG
–VS
+IN
VOUT
–18V
+18V
AD8226
–IN
VDD GND VSS
ADG5408
RG
S1
REF
S2
S3
S4
D
S5
S6
S7
S8
1-OF-8
DECODER
A0 A1
A2 EN
Figure 1. Battery monitoring circuit.
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TO SDP BOARD
VOUT
During circuit power-up, it is also possible for voltages to occur on inputs
before power is applied to the CMOS switch, especially if multiple supplies
are used to power the circuit. This condition may exceed the maximum
rating of the device and trigger a latch-up state.
POST-TRIGGER SOURCE CURRENT (mA)
10
The ADG5408 is a high voltage 8:1 multiplexer that is latch-up proof.
The trench isolation technology used in the fabrication of the ADG5408
prevents the latch-up state and reduces the need for external protection
circuitry. Latch-up proof does not guarantee overvoltage protection and
only means the switch does enter the high current SCR mode. The ADG5408
also has an electrostatic discharge (ESD) rating of 8 kV human body model
(ANSI/ESDA/JEDEC JS-001-2010).
The circuit in Figure 1 shows the ADG5408 used in a battery monitoring
application. One multiplexer is used for the positive terminal and another
for the negative terminal. This differential multiplexing allows the use of
a single instrumentation amplifier for up to eight channels. The amplifier
then removes the common-mode voltage from each of the batteries.
When an IC is being designed and evaluated, it is subjected to a test to
assess its vulnerability to latch-up. During a latch-up test, a stress current
is applied to the pin for 1 ms, called the trigger, and the current at the
pin is measured before and after the trigger. The maximum stress test is
conducted with the switch set to open, the drain (D) set to VDD, and the
source (S) set to VSS, as depicted in Figure 2.
VSS
GND
0
–10
–20
–30
–40
TYPICAL CMOS
ADG5408
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
–220
–240
–260
–280
–310
–350
–390
–430
–470
–510
–550
–50
TRIGGER CURRENT (mA)
Figure 3. Post latch-up trigger current comparison.
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VDD
VSS
VDD
S
D
Figure 2. Latch-up test configuration (pretrigger) common variations.
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The voltage of the source is then driven beyond VSS until the required
trigger current is achieved. If latch-up has not occurred, then the current
at the pin returns to its pretrigger value. After latch-up has occurred, the
pin continues to draw current without being driven by the trigger voltage.
This can only be stopped by powering down the part.
Figure 3 shows the comparison of results between a typical CMOS switch,
with epitaxial layer, and the ADG5408 when subjected to a latch-up test.
It can be seen that this typical CMOS switch reaches a latch-up current at
−290 mA, while the ADG5408 did not latch up until the test ended at −510 mA.
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