Integrated Power Management Solutions Analog Devices Announces a New ADP5054
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Integrated Power Management Solutions Analog Devices Announces a New Family of Multichannel Regulators 5V/12V ADP5054 6A BUCK 6A BUCK 2.5A BUCK 2.5A BUCK 1.0V 1.8V 1.5V XILINX®/ALTERA® FPGA 3.3V +15V BOOST REGULATOR ADC ADP5070 INVERTING REGULATOR AMP/ FILTER ANALOG INPUT SWITCH/MUX –15V analog.com/power ADP5050/ADP5051/ADP5052/ADP5053 Quad Buck Switching Regulator with LDO or POR/WDI in LFCSP ADP5050/ ADP5052 12V/5V INPUT OPTIONAL I 2C ADP5051/ ADP5053 4A BUCK REG1 1.2V 4A BUCK REG1 2.5V 1.2A BUCK REG 1.8V 1.2A BUCK REG 3.3V 200mA LDO 12V/5V INPUT OPTIONAL I 2C 1.5V MR WDI PWRGD 4A BUCK REG1 1.0V 4A BUCK REG1 2.5V 1.2A BUCK REG 1.8V 1.2A BUCK REG 3.3V POWER-ON, RESET, AND WATCHDOG VTHR RESET PWRGD 1Resistor programmable current limit (4 A, 2.5 A, or 1.2 A). Key Features • Wide input voltage range: 4.5 V to 15 V • ±1.5% output accuracy over full temperature range • 250 kHz to 1.4 MHz adjustable switching frequency • Adjustable/fixed output options via factory • Pseudo DVS (dynamic voltage scaling) • I2C interface with interrupt supportive on fault condition • CH1/CH2: programmable 1.2 A/2.5 A/4 A sync buck regulator with low-side FET driver • CH3/CH4: 1.2 A sync buck regulator • CH5: 200 mA low dropout LDO or watchdog timer and power-on reset • Precision enable on 0.8 V accurate threshold • • • • • • • • Active output discharge switch FPWM/PSM mode selection Frequency synchronization input or output Power-good flag on selective channels Startup with the precharged output 7 mm × 7 mm, 48-lead LFCSP package −40°C to +125°C junction temperature I2C functionality I2C Functionality ADP505x IC VIN = 4.5V TO 15V VOUT1 PVIN1 TO PVIN4 VOUT2 VCORE VOUT2 VAUX PVIN5 PROCESSOR/ SDA FPGA SDA ALWAYS ON 5V LDO SCL SCL nINT EN1 INT ADP5050 EN2 VOUT3 EN3 VOUT4 VDDIO EN4 EN5 VOUT5 MEM ANALOG PWRGD 28.3mm × 21.2mm ADP5050 application diagram featuring the I 2C interface. ADP505x solution size only 28.3 mm × 21.2 mm. Option 1: Resistor-programmable output voltage from 0.8 V to VIN ā 0.85 Option 2: Fixed output voltage with I2C programmability with these ranges for each channel 12V INPUT 12V INPUT VOLTAGE VOLTAGE 10.2V 10.2V (ADJUSTABLE) (ADJUSTABLE) 115Ė 115Ė (ADJUSTABLE) (ADJUSTABLE) JUNCTION JUNCTION TEMPERATURE TEMPERATURE [CH1: 0.85 V TO 1.60 V, 25 mV STEP] [CH2: 3.3 V TO 5.0 V, ~300 mV STEP] [CH3: 1.2 V TO 1.80 V, 100 mV STEP] INTERRUPT INTERRUPT [CH4: 2.5 V TO 5.5 V, 100 mV STEP] ADP505x output voltage options. | Integrated Power Management Solutions 2 INTERRUPT INTERRUPT TIMETIME Low input voltage detection on PVIN1. TIMETIME Overheat function on junction temperature. ADP5054 Quad Buck Switching Regulator in LFCSP Key Features • CH1/CH2: programmable 2 A/4 A/6 A sync buck regulator with low-side FET driver ADP5054 VIN 4.5V TO 15.5V 6A BUCK REG* 0.8V TO 0.85 × VIN @ 6A • Parallel CH1/CH2 to deliver up to 12 A output • CH3/CH4: 2.5 A buck regulator 6A BUCK REG* 2.5A BUCK REG 2.5A BUCK REG 0.8V TO 0.85 × VIN @ 6A • Parallel CH3/CH4 to deliver up to 5 A output • Wide input range: 4.5 V to 15.5 V 0.8V TO 0.85 × VIN @ 2.5A • Resistor adjustable or fixed output voltage • 250 kHz ā 2 MHz adjustable switching frequency 0.8V TO 0.85 × VIN @ 2.5A • 1/2 × fSW selective for each channel • Precision enable on accurate 0.8 V threshold PWGRD • Programmable current limit in CH1/CH2 • Soft start timer programmable *Resistor-programmable current limit (6 A, 4 A, 2 A). • FPWM/PSM mode selection • Active output discharge switch • PWRGD flag on selective channels • Frequency synchronization input or output • Hiccup or latch-off for output short protection • UVLO, OCP, TSD • 7 mm × 7 mm, 48-lead LFCSP package Power for FPGA Applications Example ADP5054 6A BUCK REGULATOR 1.2V/6A VCCINT 2.5V/4A VCCAUX CORE VOLTAGE FETs 4.5V TO 15.5V INPUT VOLTAGE 6A BUCK REGULATOR VCCO_0, 1, 2 1.5V/2A 2.5A BUCK REGULATOR DDR TERM. LDO 0.75V 2.5A BUCK REGULATOR VCC0_3 FPGA AUXILIARY VOLTAGE BANK 0 I/Os BANK 1 BANK 2 I/Os BANK 3 DDR3 MEMORY FLASH MEMORY 3.3V/1.2A PWRGD Part Number Number of Outputs ADP5050 2 × 1.2 A bucks 2 × 4 A1 bucks ADP5051 ADP5052 ADP5053 ADP5054 1 × 200 mA LDO 2 × 4 A1 bucks 2 × 1.2 A bucks 2 × 4 A1 bucks 2 × 1.2 A bucks 1 × 200 mA LDO 2 × 4 A1 bucks 2 × 1.2 A bucks 2 × 6 A2 bucks 2 × 2.5 A bucks VIN (V) 4.5 to 15 1.7 to 5.5 4.5 to 15 4.5 to 15 1.7 to 5.5 4.5 to 15 4.5 to 15.5 VOUT (V) Max Output Current (A) 0.8 to 0.85 × VIN 1.2/2.5/41 0.8 to 0.85 × VIN 0.5 to 4.75 1.2 0.8 to 0.85 × VIN 0.8 to 0.85 × VIN 0.8 to 0.85 × VIN 0.8 to 0.85 × VIN 0.5 to 4.75 200 mA 1.2/2.5/41 1.2 1.2/2.5/41 1.2 200 mA 0.8 to 0.85 × VIN 1.2/2.5/41 0.8 to 0.85 × VIN 1.2 0.8 to 0.85 × VIN 6/4/22 0.8 to 0.85 × VIN 2.5 I2C Reset Trip Threshold (V) Min Reset Timeout (ms) Typ Watchdog Timeout (ms) Package Price 1k List ($U.S.) Yes — — — 48-lead LFCSP 4.39 Yes 0.5 (adj) 1, 20, 140, 1120 6.3, 102, 1600, 25,600 48-lead LFCSP 4.59 — — — — 48-lead LFCSP 3.59 250 kHz to 1.4 MHz — 0.5 (adj) 1, 20, 140, 1120 6.3, 102, 1600, 25,600 48-lead LFCSP 3.79 250 kHz to 2 MHz — — — — 48-lead LFCSP 4.29 Switching Frequency Range 250 kHz to 1.4 MHz — 250 kHz to 1.4 MHz 250 kHz to 1.4 MHz — Resistor-programmable current limit (4 A, 2.5 A, or 1.2 A). 2Resistor-programmable current limit (6 A, 4 A, or 2 A). 1 analog.com/power | 3 ADP5070/ADP5071 Dual Switching Regulator for Generating VPOS and VNEG in LFCSP and TSSOP Key Features: ADP5070/ADP5071 INBK CC1 RC1 COMP1 ON L1 VPOS D1 (+12V, +15V,+18V) SW1 BOOST REGULATOR EN1 OFF CVREG RFT1 FB1 VREG COUT1 RFB1 PVIN1 VIN PVIN2 PGND CIN1 PVINSYS ON EN2 OFF CC2 RC2 CVREF VREF INVERTING INVERTING REGULATOR REGULATOR COUT2 RFB2 RFT2 FB2 COMP2 SW2 SS D2 SYNC/FREQ L2 SLEW SEQ • 4 mm × 4 mm, 20-lead LFCSP or TSSOP-EP package • Wide input voltage range: 2.85 V to 15 V VNEG (−12V, −15V,−18V) AGND • RESISTOR-PROGRAMMABLE (SYMMETRIC AND ASYMMETRIC) • EXAMPLE OUTPUTS SUPPORTED: ±3V, ±5V, ±12V, ±10V, +15V, AND −10V • APPLICATIONS: BIPOLAR AMPLIFIERS, ANALOG-TO-DIGITAL CONVERTERS AND DIGITAL-TO-ANALOG CONVERTERS, MULTIPLEXERS, AMPLIFIERS, CCDS AND OLEDS, RF PA BIAS SUPPLY, GaN FET BIAS, AND OPTICAL MODULES • Generates well regulated, independently resistor-programmable VPOS and VNEG outputs (for example, +15 V and −10 V) • True shutdown for both positive and negative outputs • 1.2 MHz/2.4 MHz switching frequency with optional external frequency synchronization from 1.0 MHz to 2.6 MHz • Resistor-programmable soft start timer • Individual precision enable and flexible start-up sequence control for symmetric start, VPOS first, or VNEG first • Boost and inverter, out of phase operation (180°) • UVLO, OCP, OVP, and TSD protection • −40°C to +125°C junction temperature • Supported by ADIsimPower tool set Boost Regulator—Positive Rail • Adjustable positive output: up to +39 V • Integrated 1.0 A/39 V main switch (ADP5070) • Integrated 2.0 A/39 V main switch (ADP5071) • Optional SEPIC configuration for automatic step-up/down Inverter Regulator—Negative Rail • Adjustable negative output: up to −39 V below VIN • Integrated 0.6 A/39 V main switch (ADP5070) • Integrated 1.2 A/39 V main switch (ADP5071) • Slew rate control for lower system noise http://download.analog.com/PMP/ADP507x_designer.zip SEPIC Configuration to Support Automatic Step-Up/Down Capability STANDALONE OR COUPLED INDUCTOR ADP5070 SEPIC BUCK AND RECEIVER CC1 RC1 ON INBK COMP1 L1 +5V SW1 EN1 OFF ADP5070/ADP5071 Demo Board C8 D1 L2 CVREG BOOST REGULATOR VREG COUT1 FB1 PVIN1 RFB1 RFT1 PGND VIN =12V CVREF PVIN2 VREF CIN1 PVINSYS ON OFF CC2 RC2 COUT2 RFB2 RFT2 FB2 INVERTING REGULATOR EN2 SW2 COMP2 D2 −5V L3 SS SYNC/FREQ SLEW SEQ AGND VIN: 12V VOUT_1: +5V VOUT_2: −5V • RESISTOR-PROGRAMMABLE (SYMMETRIC AND ASYMMETRIC) • EXAMPLE OUTPUTS SUPPORTED: ±5V, ±3.5V, +3.3V, AND −2.5V Part Number VIN (V) VOUT (V) Number of Outputs Output Current (mA) Key Features Package Price ($U.S.) ADP5070 New Boost/inverter: 2.85 to 15 Individual enable pin, adjustable outputs, soft start, and slew rate 20-lead LFCSP, 20-lead TSSOP 2.19 ADP5071 New 1 × boost 1 × inverter 1 × boost 1 × inverter Input current limit: boost: 1 A, inverter: 0.6 A Boost/inverter: 2.85 to 15 Boost: VIN to 39 Inverter: –0.5 to –39 below VIN Boost: VIN to 39 Inverter: –0.5 to –39 below VIN Input current limit: boost: 2 A, inverter: 1.2 A Individual enable pin, adjustable outputs, soft start, and slew rate 20-lead LFCSP, 20-lead TSSOP 2.39 | Integrated Power Management Solutions 4 ADP5135 and ADP5133 ADP5135: Triple, 1.8 A, 3 MHz Buck Regulator in LFCSP Key Features ADP5135 FPGA • Main input voltage range 3.0 V to 5.5 V 3.0V TO 5.5V • Three 1800 mA buck regulators AVIN C7 0.1šF • 4 mm × 4 mm, 24-lead LFCSP package AGND HOUSEKEEPING • Regulator accuracy of ±1.8% C1 10šF • Individual, dedicated buck power good pins ON SW1 L1 1šH EN1 1.8A BUCK 1 • 3 MHz buck operation with forced PWM and automatic PWM/PSM modes VIN2 Applications ON EN2 1.8A BUCK 2 R2 MODE FPWM AUTO GPOx VEN3 FB2 R3 PGND2 R4 VCORE C4 22šF VOUT3 VIN3 C5 10šF ON PGND1 SW2 L2 1šH OFF • Power for processors, application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and radio frequency (RF) chipsets C2 22šF VOUT2 C3 10šF • Buck output voltage range from 0.8 V to 3.8 V VIO R1 FB1 OFF • Precision enables pins for easier power sequencing VDDIO/ TO VEN2 VOUT1 VIN1 SW3 L3 1šH 1.8A BUCK 3 EN3 VMEM C6 22šF R5 FB3 R6 PGND3 OFF VDDIO R7 PG1 PG2 POWER GOOD R8 R9 GPIx PG3 AGND ADP5133: Dual 800 mA Buck Regulator in WLCSP 0.5 VOUT1 VIN1 2.3V TO 5.5V C1 4.7šF ON PROCESSOR/FPGA 800mA BUCK 1 EN1 VCORE SW1 L1 1šH FB1 R1 OFF C3 10šF R2 PGND1 ON 800mA BUCK 2 EN2 FB2 PGND2 VIO R4 2.0 GPL GPL C4 10šF OFF 3.5 4.0 4.5 3.5 4.0 4.5 5.0 5.5 mm 4.7šF 0402 2.5V GPL 10šF 0402 3.0 VIO 3.0 10šF 0402 1.0 2.5 2.5 PPL GPL L2 1šH R3 1.5 1.5 GPIO VOUT2 SW2 C2 4.7šF 0.5 2.0 MODE VIN2 VCORE 1.0 L1 L2 - 1šH 0603 ADP5133 GPL GPL D1 PGND1 C1 VIN1 B1 AGND A1 FB1 D2 SW1 C2 VOUT1 B2 MODE A2 AGND D3 SW2 C3 VOUT2 B3 EN1 A3 AGND D4 PGND2 C4 VIN2 B4 EN2 A4 FB2 GPL 4.7šF 0402 PPL 5.0 mm AGND 4.5mm × 5.5mm = 24.8mm2 Key Features • Input voltage range: 2.3 V to 5.5 V • Soft start and undervoltage lockout • −40°C to +125°C junction temperature • Two 800 mA buck regulators • Buck 1 and Buck 2 key specifications • Tiny, 2 mm × 2 mm, 16-ball WLCSP package • Adjustable and factory-programmable output voltages • Adjustable output voltage range: 0.8 V to 3.8 V • Fixed output voltage range: 0.9 V to 3.3 V • Regulator accuracy: ±1.8% • Overcurrent and thermal protection • Current mode architecture for excellent transient response and 100% duty operation • 3 MHz operating frequency • Forced PWM and auto PWM/PSM modes • Out of phase operation for reduced input filtering analog.com/power | 5 ADP5134 Dual, 3 MHz, 1.2 A Buck Regulator with Two 300 mA LDOs with Precision Enable and a Power Good in LFCSP Key Features ADP5134 • Main input voltage range 2.5 V to 5.5 V PROCESSOR/FPGA • Two 1200 mA buck regulators and two 300 mA LDO regulators VIN 2.5V TO 5.5V VOUT1 VIN1 ON L1 1šH SW1 C1 4.7šF • 4 mm × 4 mm, 24-lead LFCSP package VDDIO EN1 1.2A BUCK 1 VIO R1 FB1 C2 10šF PGND1 R2 • Factory-programmable or external adjustable VOUTx MODE FPWM AUTO • Precision enables pins for easier power sequencing VOUT2 • Regulator accuracy of ±1.8% OFF VIN2 • Factory selectable power-good pin C3 4.7šF • 3 MHz buck operation with forced PWM and automatic PWM/PSM modes ON GPOx SW2 L2 1šH 1.2A BUCK 2 EN2 FB2 R3 PGND2 R4 VCORE C4 10šF OFF AVIN • Buck 1/Buck 2: output voltage range from 0.8 V to 3.8 V C5 0.1šF • LDO1/LDO2: output voltage range of 0.8 V to 5.2 V VINLDO1 1.7V TO 5.5V • LDO1/LDO2: input voltage range from 1.7 V to 5.5 V VIN3 C6 1šF • LDO1/LDO2: high PSRR and low output noise ON VINLDO2 1.7V TO 5.5V Applications • Power for processors, application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and radio frequency (RF) chipsets HOUSEKEEPING OFF EN3 VOUT3 VMEM R5 FB3 LDO1 300mA C7 1šF R6 VIN4 C8 1šF ON EN4 VOUT4 LDO2 300mA VAUX R7 FB4 C9 1šF R8 OFF POWER GOOD VDDIO R1 100kš PG GPIx AGND Sequencing and Power Good with ADP5134 VIN VOUT1 VOUT4 UVLOR UVLOF VPO RF VP1 ADP5134 VP1 +VIN VP2 VP2 VIN1 ON/OFF EN1 BUCK 1 VIN2 VOUT2 VP3 VP3 EN2 BUCK 2 VIN3 VOUT3 VPO RR PG EN3 VDD VOUT5 VOUT2 VOUT3 LDO1 VIN4 EN4 VOUT1 FPGA SPARTAN 3× CYCLONE III CYCLONE IV VOUT4 LDO2 PG VP1 VP3 GPIN VP2 VDD Assumptions • Power good factory programmed to sense all regulators Benefits • • • • Precise and reliable Few external components needed Minimal cost adder (resistors) Flexible sequencing | Integrated Power Management Solutions 6 VIN EN REG5 (EXT) VOUT5 MEMORY ADP5040 and ADP5041 ADP5040: 1.2 A Buck and Dual 300 mA LDO with Individual Enables in LFCSP ADP5041: 1.2 A Buck and Dual 300 mA LDO, Supervisory, Watchdog, and Manual Reset in LFCSP ADP5041 ADP5040 AVIN AVIN SW L1 1šH SW L1 1šH VIN1 VIN1: 2.3V TO 5.5V FB1 1.2A BUCK C5 10šF ON VOUT1 @ 1.2A R1 C6 10šF R2 VIN1: 2.3V TO 5.5V VIN1 R2 EN1 OFF PGND R1 FB1 1.2A BUCK C5 10šF ON EN1 OFF VOUT1 VOUT1 PGND FPWM PSM/PWM MODE VIN2 VIN2: 1.7V TO 5.5V ON VOUT2 300mA LDO1 C1 1šF FB2 R3 VIN2 VIN2: 1.7V TO 5.5V VOUT2 @ 300mA C2 2.2šF R4 EN2 OFF FPWM PSM/PWM ON EN3 OFF ON VIIN3 VIN3: 1.7V TO 5.5V 300mA LDO2 C3 1šF FB4 AGND VOUT3 @ 300mA R5 C4 2.2šF R6 EN3 OFF VIN3: 1.7V TO 5.5V R3 FB2 R4 EN2 OFF MR ON VOUT2 300mA LDO1 EN_LD01 C1 1šF SUPERVISOR MODE VOUT1 @ 1.2A C6 10šF VIN3 C2 2.2šF nRSTO MICROPROCESSOR WDI R5 VTHR R6 VOUT3 300mA LDO2 C3 1šF VOUT2 @ 300mA R7 FB4 R8 VOUT3 @ 300mA C4 2.2šF AGND ADP5040 functional block diagram. ADP5041 functional block diagram. Key Features • Input voltage range: 2.3 V to 5.5 V • One 1.2 A buck regulator, fixed and adjustable output voltages, up to 96% efficiency • Two 300 mA LDOs, fixed and adjustable outputs • 4 mm × 4 mm, 20-lead LFCSP package • Initial regulator accuracy: ±1% • Overcurrent and thermal protection • Soft start • Undervoltage lockout • Open-drain processor reset with external adjustable threshold monitoring • ±1.5% threshold accuracy over the full temperature range • • • • Guaranteed reset output valid to VCC = 1 V Manual reset input Watchdog refresh input Two reset timeout options: 20 ms and 140 ms (minimum) • Two watchdog timeout options: 102 ms and 1600 ms (typical) ADP2311 Dual, 1 A Buck Regulators with Fail-Safe Monitoring 4.5V to 18V VIN1 ADP2311 BUCK 1 VIN2 BUCK 2 SW1 SW2 WDI WATCHDOG PFI VOLTAGE MONITOR nRSTO POR PFO ASIC/ PROCESSOR 3.3V V IO 1.2V V CORE GPIO INT RST GPIO Key Features • Precision enable inputs • Input voltage: 4.5 V to 18 V • Power feedback during power-off • Continuous output current: 1 A/1 A • Output accuracy: ±1.0% • UVLO, OCP, OVP, and thermal shutdown protection • Power fail comparator generates warning • 4 mm × 4 mm, 24-lead LFCSP package • Power-on reset with programmable delay timer Applications • Adjustable voltage monitor for power-down (Channel 2) • Watchdog refresh input • Industrial and instrumentation • Healthcare and medical • DC-to-DC point of load applications • Fixed switching frequency: 300 kHz • Internal compensation and soft start FPGA analog.com/power | 7 I 2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. BR09543-0-2/15(B) analog.com/power ADP5034 ADP5133 New Dual, 3 MHz buck regulator Dual, 3 MHz buck regulator ADP5134 New with dual LDO Inverter: 2.85 to 15 Inverter: 2.85 to 15 Inverter: 2.85 to 15 Inverting switching regulator for generating VNEG ADP5073 New Inverting switching regulator ADP5074 New for generating VNEG Inverting switching regulator ADP5075 New for generating VNEG Buck: 4.5 to 15 Buck: 4.5 to 15.5 4.5 to 18 Quad buck regulator, POR, and WDI with I2C Quad buck regulator with LDO Quad buck regulator with POR and WDI Quad buck regulator Dual 1 A buck ADP5051 New ADP5052 New ADP5053 New ADP5054 New ADP2311 New 1Resistor-programmable current limit (4 A, 2.5 A, or 1.2 A). 2Resistor-programmable current limit (6 A, 4 A, or 2 A). LDO: 1.7 to 5.5 Buck: 4.5 to 15 Buck: 4.5 to 15 LDO: 1.7 to 5.5 Quad buck regulator with LDO with I2C ADP5050 New Buck: 4.5 to 15 Boost/inverter: 2.85 to 15 Dual dc-to-dc with boost and inverter outputs for generating VPOS and VNEG Boost/inverter: 2.85 to 15 LDO: 1.7 to 5.5 Buck: 2.3 to 5.5 LDO: 1.7 to 5.5 Buck: 2.3 to 5.5 LDO: 1.7 to 5.5 Buck: 2.3 to 5.5 ADP5071 New Dual, 3 MHz, 800 mA buck ADP5037 regulator with dual 300 mA LDO 3 MHz buck regulator ADP5040 with dual LDO 3 MHz buck regulator with ADP5041 dual LDO, supervisor, and watchdog timer Dual dc-to-dc with boost ADP5070 New and inverter outputs for generating VPOS and VNEG ADP5135 New Triple, 3 MHz buck regulator Buck: 3.0 to 5.5 Buck: 2.3 to 5.5 Buck: 2.5 to 5.5 LDO: 1.7 to 5.5 Dual, 3 MHz buck regulator with dual LDO ADP5024 ADP5033 Dual, 1.2 A buck with 300 mA LDO Dual, 3 MHz buck regulator with dual LDO Dual, 800 mA buck with 300 mA LDO ADP5023 LDO: 1.7 to 5.5 Buck: 2.3 to 5.5 VIN (V) Buck: 2.3 to 5.5 LDO: 1.7 to 5.5 Buck: 2.3 to 5.5 LDO: 1.7 to 5.5 Buck: 2.3 to 5.5 LDO: 1.7 to 5.5 Buck: 2.3 to 5.5 LDO: 1.7 to 5.5 Dual, 3 MHz buck with 150 mA LDO Product Description ADP5022 Part Number VOUT (V) 800 300 1200 300 1200 300 2 × buck 2 × LDO 1 × buck 2 × LDO 1 × buck 2 × LDO 1000 — 0.95 × VFB Adj — PFO, PFI, WDI 24-lead LFCSP 48-lead LFCSP — 50, 100,150, 200 — — 48-lead LFCSP 6.3, 102, 1600, 25,600 1, 20, 140, 1120 0.5 (adj) — 48-lead LFCSP Individual enable pins with power good Individual enable pins with power good — — — — 48-lead LFCSP 12-ball WLCSP Enable pin, adjustable output, soft start, and slew rate I2C interface with individual enable pins and power good 16-lead LFCSP Enable pin, adjustable output, soft start, and slew rate 48-lead LFCSP 16-lead LFCSP Enable pin, adjustable output, soft start, and slew rate I2C interface with individual enable pins and power good 20-lead LFCSP, 20-lead TSSOP 20-lead LFCSP, 20-lead TSSOP 20-lead LFCSP 20-lead LFCSP Individual enable pin, adjustable outputs, soft start, and slew rate Individual enable pins, mode pin Individual enable pins and supervisor, WDI, mode pin, and MR pin Individual enable pin, adjustable outputs, soft start, and slew rate 24-lead LFCSP 24-lead LFCSP Precision enable pins and power-good pins Mode pin, individual enable pins 24-lead LFCSP Precision enable pins and power-good pin 16-ball WLCSP 2.38 4.29 3.79 3.59 4.59 4.39 0.99 1.75 1.49 2.39 2.19 1.79 1.39 1.69 1.69 2.09 1.29 1.99 Adjustable and fixed outputs 1.90 16-ball WLCSP 24-lead LFCSP, 28-lead TSSOP 1.79 Mode pin, individual enable pins 24-lead LFCSP 1.59 1.80 Price ($U.S.) Mode pin, two enable pins 24-lead LFCSP Mode pin, individual enable pins 16-ball WLCSP Package Mode pin, individual enable pins Mode pin, individual enable pins Key Features Individual enable pins with power good 6.3, 102, 1600, 25,600 — 1, 20, 140, 1120 — 0.5 (adj) 2 × buck Adj, (0.6 to 0.85 × VIN) 0.8 to 0.85 × VIN 0.8 to 0.85 × VIN 0.5 to 4.75 0.8 to 0.85 × VIN 0.8 to 0.85 × VIN 0.5 to 4.75 0.8 to 0.85 × VIN — — Yes 40001 1200 200 40001 1200 40001 1200 200 40001 1200 60002 2500 2 × buck 2 × buck 1 × LDO 2 × buck 2 × buck 2 × buck 2 × buck 1 × LDO 2 × buck 2 × buck 2 × buck 2 × buck — — — — Inverter: 0.6 A 1 × inverter Inverter: –0.5 to –39 below VIN — — — — — — Inverter: 2.4 A 1 × inverter Inverter: –0.5 to –39 below VIN — — — — — Inverter: 1.2 A 1 × inverter Inverter: –0.5 to –39 below VIN — — 102, 1600 — — — — — — — — — — Yes — Input current limit: boost: 2 A inverter: 1.2 A 1 × boost 1 × inverter Boost: VIN to 39 Inverter: –0.5 to –39 below VIN Boost: VIN to 39 — 20, 140 0.5 (adj) — Inverter: –0.5 to –39 below VIN — — — — — — — — — — — — — — — — 1800 3 × buck — — — — — — — — 800 — — 1200 300 — — Typ Watchdog Min Reset Reset Trip Threshold (V) Timeout (ms) Timeout (ms) — 2 × buck 800 300 1200 300 800 300 1200 300 2 × buck 1 × LDO 2 × buck 1 × LDO 2 × buck 2 × LDO 2 × buck 2 × LDO — I2C 2 × buck 2 × LDO 600 150 1 × LDO Output Current (mA) 2 × buck Number of Outputs Input current 1 × boost limit: boost: 1 A inverter: 0.6 A 1 × inverter Adj (0.8 to 5.2) Adj (0.8 to 3.8) Adj (0.8 to 5.2) Adj (0.8 to 3.8) Adj (0.8 to 5.2) Adj (0.8 to 3.8) Adj (0.8 to 3.8) Buck: 3.3, 3.0, 2.8, 2.5, 2.3, 2.0, 1.82, 1.8, 1.6, 1.5, 1.3, 1.2, 1.1, 1.0, 0.9, 0.8 LDO: 3.3, 3.0, 2.9, 2.8, 2.775, 2.5, 2.0, 1.875, 1.8, 1.75, 1.7, 1.65, 1.6, 1.55, 1.5, 1.2 Adj (0.8 to 3.8) Adj (0.8 to 5.2) Adj (0.8 to 3.8) Adj (0.8 to 5.2) Buck: 3.3, 3.0, 2.8, 2.5, 2.3, 2.0, 1.8, 1.6, 1.5, 1.4, 1.3, 1.2, 1.1, 1.0, 0.9 LDO: 3.3, 3.0, 2.8, 2.5, 2.25, 2.0, 1.8, 1.7, 1.6, 1.5, 1.2, 1.1, 1.0, 0.9, 0.8 Adj (0.8 to 3.8) Adj (0.8 to 5.2) Adj (0.8 to 3.8) or 3.3, 3.0, 2.8, 2.5, 2.3, 2.0, 1.8, 1.6, 1.5, 1.4, 1.3, 1.2, 1.1, 1.0, 0.9 Adj (0.8 to 3.8) Adj (0.8 to 5.2) Integrated Power Management Solutions (Micro-PMUs) Analog Devices, Inc. Worldwide Headquarters Analog Devices, Inc. Three Technology Way P.O. Box 9106 Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 (800.262.5643, U.S.A. only) Fax: 781.461.3113 Analog Devices, Inc. Europe Headquarters Analog Devices, Inc. Wilhelm-Wagenfeld-Str. 6 80807 Munich Germany Tel: 49.89.76903.0 Fax: 49.89.76903.157 Analog Devices, Inc. Japan Headquarters Analog Devices, KK New Pier Takeshiba South Tower Building 1-16-1 Kaigan, Minato-ku, Tokyo, 105-6891 Japan Tel: 813.5402.8200 Fax: 813.5402.1064 Analog Devices, Inc. Southeast Asia Headquarters Analog Devices 5F, Sandhill Plaza 2290 Zuchongzhi Road Zhangjiang Hi-Tech Park Pudong New District Shanghai, China 201203 Tel: 86.21.2320.8000 Fax: 86.21.2320.8222
