Integrated Power Solutions for Altera FPGAs
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Integrated Power Solutions for Altera FPGAs Modern high performance FPGA-based systems require an increasing number of dedicated rails supplying core, I/O, memory, PLL, and precision analog voltages. Typical FPGA-based systems today make use of standalone switching regulators and LDOs; but, as board area continues to shrink as end product form factors shrink, this complicates the task of designing more efficient power management solutions for powering FPGAs. Combining multiple switching regulators and LDOs into a single package enables very small, flexible, highly efficient power management solutions for powering FPGAs and precision analog components with the highest system reliability. ADP505x Solution Size Only 28.3 mm ∙ 21.2 mm Ultrasmall 12 V/5 V Quad Buck + LDO in LFCSP ADP5050 12V/5V INPUT 1.2V @ 4A 4A BUCK REG VCORE 2.5V @ 4A VAUX 4A BUCK REG 3.3V @ 1.2A 1.2A BUCK REG VIO M1 MGT 1.5V @ 1.2A OPTIONAL I 2C DDR MEMORY 1.2A BUCK REG 200mA LDO 1.2V @ 200mA PWRGD Fixed and Adjustable Output Voltages Wide Range of Switching Frequency Operation (250 kHz to 1.4 MHz) Resistor Programmable Current Limit on Buck 1 and Buck 2 (4 A, 2.5 A, 1.2 A ) Simple Power Supply Sequencing Frequency Synchronization Input or Output LDO or POR/WDI Options www.analog.com/multioutput-regulators ADP5050 Supply for Altera Cyclone V (GX/SX) • Max board size: 588 mm2 • Assumes 4 A, 4 A, 1 A, 1 A • Min board size: 310 mm2 • Assumes 3 A, 2 A, 1 A, 1 A • Estimated BOM: $4.95 (1 kpcs) ADP5050 BST1 PVIN1B C1 10𝛍F SW1A BUCK 1 4A COMP1 C2 SW1B OFF EN1 DL1 VREG Q1 G1 S2 VCCIO_1P8_1P5 G2 DL2 VDDR Q2 PVIN2B VREG BUCK 2 4A COMP2 OFF VCCBRAM C21 47𝛍F S1 R8 ON VCCINT C4 47𝛍F R4 PVIN2A C7 R7 1.1V PGND SS12 C5 10𝛍F ALTERA CYCLONE V R2 L1 = 2.2𝛍H D1 VREG C3 R3 ON R1 FB1 PVIN1A INPUT SUPPLY 4.5V TO 15V SW2A C6 BST2 EN2 L2 = 4.7𝛍H D2 SW2B R6 R5 FB2 VTT DRV EXTERNAL DDR2/DDR3 VTT C8 47𝛍F VCCIO_2P5 BST3 PVIN3 C9 10𝛍F BUCK 3 1.2A COMP3 C11 R11 ON C10 SW3 OFF VAUX L3 = 4.7𝛍H R9 FB3 EN3 R10 PGND3 VREG VCCPD 2.5V C12 22𝛍F VCCPGM VCCH_GXBL VCCA_FPLL VCCBAT SS34 BST4 PVIN4 C13 10𝛍F BUCK 4 1.2A COMP4 EN4 C19 AGND INT REG 100mA I 2C OSC PG R21 RT SYNC SDA SCL nINT FSYNC ADP5052—NON I2C VERSION | Integrated Power Solutions for Altera FPGAs 2 PWRGD VCC_RSTCLK_HPS VCC_AUX R16 C18 1𝛍F VCCL_GXBL VCCE_GXBL R20 VDDIO R19 VREG C20 R15 VIO VDD C15 22𝛍F VCCIO_HPS VCCPLL_HPS FB5 EN5 VCCPD_HPS 2.5V 1.1V TO 1.2V VOUT5 LDO 200mA OFF R13 PGND4 PVIN5 VIO C17 1𝛍F ON FB4 R18 OFF L4 = 4.7𝛍H R12 R17 C16 R14 ON C14 SW4 GPO1 GPO2 GPO3 GPO4 PowerPlay Power Estimation—Use Case for Altera Cyclone V Altera FPGA Selection Logic Family Elements Cyclone <115 k IV/E Cyclone <150 k IV/GX Cyclone ~300 k V/E Cyclone ~300 k V/GX Cyclone ~110 k V/SX Power Estimation1 Clock Low Speed Low Speed Toggle Logic Used Rate Clock High Speed High Speed Toggle DSP/ RAM Logic Used Rate Instances Blocks 100 MHz 33% 12.50% 400 MHz 17.00% 200 MHz 50% 12.50% 600 MHz 20.00% 100 MHz 33% 12.50% 500 MHz 17.00% 200 MHz 50% 12.50% 600 MHz 20.00% 100 MHz 44% 12.50% 600 MHz 12.00% 100 MHz 50% 12.50% 600 MHz 20.00% 100 MHz 50% 12.50% 600 MHz 20.00% 18.00% 36 × 36 mult/100 36 × 36 12.50% mult/200 12.50% 36 × 36 mult/100 36 × 36 12.50% mult/300 27 × 27 12.50% mult/300 27 × 27 12.50% mult/300 27 × 27 12.50% mult/50 RAM Clock Toggle Outputs I/ORate Out Load XCVR Freq XCVR Channels HSDI Freq HSDI Channels 100 50 MHz 100 40 MHz 30 pF N/A N/A N/A N/A 300 50 MHz 200 40 MHz 30 pF N/A N/A N/A N/A 350 200 MHz 200 50 MHz 30 pF 3.125 GHz 2 Tx/2 Rx N/A N/A 500 200 MHz 300 50 MHz 30 pF 3.125 GHz 2 Tx/2 Rx 500 200 MHz 100 50 MHz 30 pF 500 200 MHz 150 50 MHz 30 pF 3.125 GHz 6 Tx/6 Rx 1.25 GHz 300 200 MHz 150 50 MHz 30 pF 3.125 GHz 6 Tx/6 Rx 1.25 GHz N/A N/A N/A N/A 1.25 GHz 8 Tx + 8 Rx 8 Tx + 8 Rx 8 Tx + 8 Rx FPGA Power Consumption Derived from Spreadsheet 2 ICCINT + ICC 1.36 A (@ 1.2 V) 2.154 A (@ 1.2 V) 2.27 A (@ 1.2 V) 3.92 A (@ 1.2 V) 2.87 A (@ 1.1 V) 3.67 A (@ 1.1 V) 1.49 A (@ 1.1 V) ICCIO 0.033 A (@ 2.5 V) 0.055 A (@ 2.5 V) 0.04 A (@ 2.5 V) 0.04 A (@ 2.5 V) 0.032 A (@ 2.5 V) 0.045 A (@ 2.5 A) 0.042 A (@ 2.5 V) ICCA 0.039 A (@ 2.5 V) 0.039 A (@ 2.5 V) 0.042 A (@ 2.5 V) 0.039 A (@ 2.5 V) 0.04 A (@ 2.5 V) 0.058 A (@ 2.5 V) 0.128 A (@ 2.5 V) ICCPD 0.018 A (@ 1.1 V) 0.048 A (@ 1.1 V) 0.031 A (@ 1.2 V) 0.032 A (@ 1.2 V) 0.014 A (@ 2.5 V) 0.015 A (@ 2.5 V) 0.007 A (@ 2.5 V) ICCXCVR N/A N/A 0.231 A (@ 1.2 V) 0.231 A (@ 1.2 V) N/A 0.225 A (@ 1.1 V) 0.225 A (@ 1.1 V) 1Power requirement derived from Altera PowerPlay 12.1—the spreadsheet assumes at least 50% of resources occupation with 12.5% toggle rate. The core current is kept below the maximum driving capability of the suggested μPMU. 2The proposed μPMU supplies three to four FPGA rails: VCC, VCCA, VCCIO, and VCCPD from buck regulators while the transceiver (where applicable) is supplied from the LDO. One buck is dedicated to external DDR memories and the bus level. Only one I/O supply voltage is considered, and multiple I/O banks with different voltage levels can be supported. Bill of Materials for the ADP5050 Powering Altera Cyclone V Reference U1 C17, C18, C19, C20 C2, C6, C10, C14 C1, C5, C9, C13 C4, C8, C21 C12, C15 C3, C7, C11, C16 Footprint (mm) L1 1 L2, L3, L4 3 R21 R4, R8 R1, R2, R5, R6, R9, R10, R12, R13, R15, R16, R3, R7, R11, R14 R17, R18, R19, R20 1 2 Value 5-channel micro PMU 1 µF, X5R, 6.3 V 0.1 µF, X5R, 16 V 10 µF, X5R, 25 V 47 µF, X5R, 6.3 V 22 µF, X5R, 6.3 V 2.2 nF, X5R, 25 V Dual N-FETs, 20 V, 25 A, 16 mΩ Dual N-FETs, 30 V, 23 A, 25 mΩ Dual N-FETs, 30 V, 10 A, 20 mΩ 2.2 µH, 15.9 A, 12.7 mΩ 2.3 µH, 6.4 A, 22 mΩ 4.7 µH, 2.7 A, 57 mΩ 4.7 µH, 2.0 A, 70 mΩ 38.4 kΩ, resistor, 1% 22 kΩ, resistor, 5% 14 Resistor, 1% Various 0402 4 4 10 kΩ, resistor, 5% 10 kΩ, resistor, 5% Various Various 0402 0402 Q1 (Q2) Quantity 1 4 4 4 3 2 4 1 Part Number ADP5050ACPZ GRM155R60J105KE19D GRM155R61C104KA88D GRM219R61E106KA12 GRM21BR60J476ME15 GRM188R60J226MEA0 GRM155R61E222KA01D Vendor ADI Murata Murata Murata Murata Murata Murata 7.0 × 7.0 × 0.75 QFN 0402 0402 0805 0805 0603 0402 Si7232DN Vishay 3.3 × 3.3 × 1.0 QFN Si7228DN Vishay 3.3 × 3.3 × 1.0 QFN IRFHM8364 IR 3.3 × 3.3 × 0.9 QFN XAL6030-222ME NRS6045-2R3NMGK XFL4020-472ME NRS4018T-4R7MDGJ Coilcraft Taiyo Yuden Coilcraft Taiyo Yuden Various Various 6.0 × 6.0 × 3.0 6.0 × 6.0 × 4.5 4.0 × 4.0 × 2.0 4.0 × 4.0 × 1.8 0402 0402 Notes Value depends on output voltage setting Optional for I2C interface www.analog.com/multioutput-regulators | 3 ADP5050 Supply for Altera Stratix IV • Max board size: 588 mm2 • Assumes 4 A, 4 A, 1 A, 1 A • Min board size: 310 mm2 • Assumes 3 A, 2 A, 1 A, 1 A • Estimated BOM: $4.95 (1 kpcs) ADP5050 BST1 PVIN1B C1 10𝛍F SW1A BUCK 1 4A COMP1 C2 SW1B OFF EN1 DL1 VREG Q1 G1 VCCHIP S2 VCCIO_1P8_1P5 G2 DL2 1.5V, 1.8V VDDR Q2 PVIN2B VREG BUCK 2 4A COMP2 OFF VCCD_PLL PGND PVIN2A ON VCC C21 47𝛍F S1 R8 C7 R7 0.9V C4 47𝛍F R4 SS12 C5 10𝛍F ALTERA STRATIX IV R2 L1 = 2.2𝛍H D1 VREG C3 R3 ON R1 FB1 PVIN1A INPUT SUPPLY 4.5V TO 15V SW2A C6 BST2 EN2 L2 = 4.7𝛍H D2 SW2B R6 R5 VTT DRV EXTERNAL DDR2/DDR3 VTT C8 47𝛍F FB2 VCCIO_2P5 BST3 PVIN3 C9 10𝛍F BUCK 3 1.2A COMP3 C11 R11 ON C10 SW3 OFF VIO L3 = 4.7𝛍H R9 FB3 EN3 R10 PGND3 VREG VCCPD 2.5V C12 22𝛍F BST4 C13 10𝛍F BUCK 4 1.2A COMP4 EN4 AGND nINT FSYNC ADP5052—NON I C VERSION 2 | Integrated Power Solutions for Altera FPGAs 4 PWRGD C15 22𝛍F C18 1𝛍F VCCR VCCT VCCL_GXB VCCH_GXB VCCPT R20 PG SCL R19 OSC SDA R18 I 2C R16 R17 INT REG 100mA R21 RT SYNC/MODE R15 VIO VDDIO 1.1V 1.5V FB5 EN5 VREG C19 R13 VOUT5 VDD C20 R12 PGND4 LDO 200mA OFF L4 = 4.7𝛍H FB4 PVIN5 VAUX C17 1𝛍F ON C14 SW4 OFF VCC_AUX VCCA/VCCBAT PVIN4 ON VCCCLKIN VCC_PLL SS34 C16 R14 VCCPGM GPO1 GPO2 GPO3 GPO4 PowerPlay Power Estimation—Use Cases for Altera Stratix IV, V, and Arria V Altera FPGA Selection Logic Family Elements Stratix III Stratix IV/E Stratix IV/GX Power Estimation1 Clock Low Speed Low Speed Toggle Logic Used Rate Clock High Speed High Speed Toggle DSP/ RAM Logic Used Rate Instances Blocks <160 k 100 MHz 42% 12.50% 600 MHz 8.00% ~200 k 100 MHz 35% 12.50% 400 MHz 8.00% ~340 k 100 MHz 40% 12.50% 0.00% 0.00% N/A ~230 k 100 MHz 30% 12.50% <150 k 200 MHz 42% 12.50% 600 MHz N/A 0.00% 8.00% ~350 k 150 MHz 50% 12.50% Stratix V/GX ~340 k 100 MHz 45% 12.50% 800 MHz 5.00% 0.00% Arria V ~840 k 100 MHz 45% 12.50% 800 MHz 5.00% 18.00% 36 × 36 mult/20 36 × 36 12.50% mult/20 36 × 36 0.00% mult/20 36 × 36 12.50% mult/100 36 × 36 12.50% mult/100 36 × 36 0.00% mult/100 12.50% 36 × 36 mult/100 36 × 36 12.50% mult/100 RAM Clock Toggle Outputs I/ORate Out Load XCVR Freq XCVR Channels HSDI Freq HSDI Channels 120 50 MHz 200 40 MHz 30 pF N/A N/A 1.25 GHz 8Tx + 8Rx 120 50 MHz 200 40 MHz 30 pF N/A N/A 1.25 GHz 8Tx + 8Rx 120 50 MHz 300 50 MHz 30 pF N/A N/A 1.25 GHz 8Tx + 8Rx N/A 1.25 GHz 8Tx + 8Rx 100 50 MHz 150 50 MHz 30 pF N/A 210 50 MHz 300 50 MHz 30 pF 4.25 GHz 2Tx/2Rx 1.25 GHz 8Tx + 8Rx 210 50 MHz 300 50 MHz 30 pF 4.25 GHz 2Tx/2Rx 1.25 GHz 8Tx + 8Rx 400 100 MHz 500 50 MHz 30 pF 4.25 GHz 2Tx/2Rx 1.25 GHz 8Tx + 8Rx 1000 100 MHz 500 100 MHz 30 pF 4.25 GHz 4Tx/4Rx 1.25 GHz 8Tx + 8Rx FPGA Power Consumption Derived from Spreadsheet 2 ICCINT + ICC 3.45 A (@ 1.1 V) 3.20 A (@ 1.1 V) 2.26 A (@ 0.90 V) 3.90 A (@ 0.90 V) 1.95 A (@ 0.90 V) 2.80 A (@ 0.90 V) 3.30 A (@ 0.90 V)3 4.30 A (@ 0.85 V)3 6.52 A (@ 0.85 V)3 ICCIO ICCA ICCD 1.0 A (@ 2.5 V) 0.014 A (@ 2.5 V) 0.04 A (@ 1.1 V) ICCXCVR N/A 1.5 A (@ 2.5 V) 0.015 A (@ 2.5 V) 0.048 A (@ 1.1 V) N/A 1.6 A (@ 2.5 V) 0.23 A (@ 2.5 V) 0.23 A (@ 2.5 V) 0.25 A (@ 2.5 A) 0.37 A (@ 2.5 V) 0.45 A (@ 2.5 V) 0.015 A (@ 2.5 V) 0.001 A (@ 2.5 V) 0.018 A (@ 2.5 V) 0.02 A (@ 2.5 V) 0.014 A (@ 2.5 V) 0.019 A (@ 2.5 V) 0.048 A (@ 1.1 V) 0.028 A (@ 0.9 V) 0.035 A (@ 0.9 V) 0.045 A (@ 0.9 V) 0.15 A (@ 1.5 V) 0.15 A (@ 1.5 V) N/A N/A 0.725 A (@ 1.2 V) 0.725 A (@ 1.2 V) 0.725 A (@ 1.2 V) 0.82 A (@ 1 V) 1Power requirement derived from Altera PowerPlay 12.1—the spreadsheet assumes at least 50% of resources occupation. 2Assumes 1.5 V I/O domain and DDR3 control interface, current consumption for the external DDR is not considered. 34 A to 8 A core current requirement can be achieved by connecting the ADP505x Buck 1 and Buck 2 used in interleaved configuration (see Stratix V and Arria V application diagrams). Bill of Materials for the ADP5050 Powering Altera Stratix IV Reference U1 C17, C18, C19, C20 C2, C6, C10, C14 C1, C5, C9, C13 C4, C8, C21 C12, C15 C3, C7, C11, C16 Footprint (mm) L1 1 L2, L3, L4 3 R21 R4, R8 R1, R2, R5, R6, R9, R10, R12, R13, R15, R16, R3, R7, R11, R14 R17, R18, R19, R20 1 2 Value 5-channel micro PMU 1 µF, X5R, 6.3 V 0.1 µF, X5R, 16 V 10 µF, X5R, 25 V 47 µF, X5R, 6.3 V 22 µF, X5R, 6.3 V 2.2 nF, X5R, 25 V Dual N-FETs, 20 V, 25 A, 16 mΩ Dual N-FETs, 30 V, 23 A, 25 mΩ Dual N-FETs, 30 V, 10 A, 20 mΩ 2.2 µH, 15.9 A, 12.7 mΩ 2.3 µH, 6.4 A, 22 mΩ 4.7 µH, 2.7 A, 57 mΩ 4.7 µH, 2.0 A, 70 mΩ 38.4 kΩ, resistor, 1% 22 kΩ, resistor, 5% 14 Resistor, 1% Various 0402 4 4 10 kΩ, resistor, 5% 10 kΩ, resistor, 5% Various Various 0402 0402 Q1 (Q2) Quantity 1 4 4 4 3 2 4 1 Part Number ADP5050ACPZ GRM155R60J105KE19D GRM155R61C104KA88D GRM219R61E106KA12 GRM21BR60J476ME15 GRM188R60J226MEA0 GRM155R61E222KA01D Vendor ADI Murata Murata Murata Murata Murata Murata 7.0 × 7.0 × 0.75 QFN 0402 0402 0805 0805 0603 0402 Si7232DN Vishay 3.3 × 3.3 × 1.0 QFN Si7228DN Vishay 3.3 × 3.3 × 1.0 QFN IRFHM8364 IR 3.3 × 3.3 × 0.9 QFN XAL6030-222ME NRS6045-2R3NMGK XFL4020-472ME NRS4018T-4R7MDGJ Coilcraft Taiyo Yuden Coilcraft Taiyo Yuden Various Various 6.0 × 6.0 × 3.0 6.0 × 6.0 × 4.5 4.0 × 4.0 × 2.0 4.0 × 4.0 × 1.8 0402 0402 Notes Value depends on output voltage setting Optional for I2C interface www.analog.com/multioutput-regulators | 5 ADP5050 Supply for Altera Stratix V • Additional buck (ADP2384) for DDR • External DDR termination driver • Buck 1 and Buck 2 interleaved for 8 A VTT DRV BST1 PVIN1B C1 10𝛍F COMP1 SW1B EN1 R2 L1 = 1.2𝛍H S1 VCCD_PLL VCCHIP C21 100𝛍F PGND S2 R8 G2 DL2 EN2 VCC C4 100𝛍F Q1 G1 R4 SS12 0.9V D1 DL1 VREG R27 C2 VREG C3 R3 R2 SW1A BUCK 1 4A ALTERA STRATIX V (E, GS, GX) Q2 PVIN2A VREG BUCK 2 4A PVIN2B C5 10𝛍F SW2A C6 BST2 BST3 C9 10𝛍F BUCK 3 1.2A COMP3 ON C10 SW3 C11 R11 OFF VDDR BUCK 1/BUCK 2 INTERLEAVED CONNECTION UP TO 8A FB2 PVIN3 VCCIO_1P8_1P5 VCCIO_2P5 VIO L3 = 4.7𝛍H R9 FB3 EN3 R10 PGND3 VREG L2 = 1.2𝛍H D2 SW2B COMP2 DDR2/DDR3 VTT R1 FB1 PVIN1A INPUT SUPPLY 4.5V TO 15V VDDR ADP2384 4A BUCK ADP5050 VCCPD 2.5V C12 22𝛍F VCCPGM VCCCLKIN VCC_AUX VCC_PLL SS34 BST4 PVIN4 C13 10𝛍F BUCK 4 1.2A COMP4 EN4 R13 PGND4 R27 LDO 200mA PVIN5 R15 FB5 C17 1𝛍F VIO AGND OSC PG R21 RT SYNC/MODE SCL nINT FSYNC ADP5052—NON I2C VERSION | Integrated Power Solutions for Altera FPGAs 6 PWRGD R19 I 2C SDA R18 VDDIO INT REG 100mA R16 R17 VDD VREG 1V C15 22𝛍F 1.5V VOUT5 EN5 C19 R12 FB4 R26 C20 L4 = 4.7𝛍H R20 C16 R14 VIO C14 SW4 C18 1𝛍F VCCR VCCT VCCH_GXB VCCPT VCCPT VCCPT GPO1 GPO2 GPO3 GPO4 PowerPlay Power Estimation—Use Case for Altera Stratix V See Page 5. Bill of Materials for the ADP5050 Powering Altera Stratix V Reference U1 U2 C17, C18, C19, C20 C2, C6, C10, C14 C1, C5, C9, C13 C4, C21 C12, C15 C3, C11, C16 Q1 (Q2) Quantity 1 1 4 4 4 2 2 4 Value 5-channel micro PMU 20 V, 4 A buck regulator 1 µF, X5R, 6.3 V 0.1 µF, X5R, 16 V 10 µF, X5R, 25 V 100 µF, X5R, 6.3 V 22 µF, X5R, 6.3 V 2.2 nF, X5R, 25 V Dual N-FETs, 20 V, 25 A, 16 mΩ Dual N-FETs, 30 V, 23 A, 25 mΩ Dual N-FETs, 30 V, 10 A, 20 mΩ 1 L1, L2 2 Footprint (mm) Part Number ADP5050ACPZ ADP2384ACPZN GRM155R60J105KE19D GRM155R61C104KA88D GRM219R61E106KA12 GRM31CR60J107ME39 GRM188R60J226MEA0 GRM155R61E222KA01D Vendor ADI ADI Murata Murata Murata Murata Murata Murata 7.0 × 7.0 × 0.75 QFN 4.0 × 4.0 × 0.75 QFN 0402 0402 0805 1206 0603 0402 Si7232DN Vishay 3.3 × 3.3 × 1.0 QFN Si7228DN Vishay 3.3 × 3.3 × 1.0 QFN IRFHM8364 IR 3.3 × 3.3 × 0.9 QFN 1.2 µH, 22 A, 6.8 mΩ XAL6030-122ME Coilcraft 6.0 × 6.0 × 3.0 NRS6045-1R3NMGK XFL4020-472ME NRS4018T-4R7MDGJ Taiyo Yuden Coilcraft Taiyo Yuden Various Various 6.0 × 6.0 × 4.5 4.0 × 4.0 × 2.0 4.0 × 4.0 × 1.8 0402 0402 L3, L4 2 R21 R4, R8 R1, R2, R9, R10, R12, R13, R15, R16, R22, R23, R24, R25, R26, R27 R3, R11, R14 R17, R18, R19, R20 1 2 1.3 µH, 8.2 A, 16 mΩ 4.7 µH, 2.7 A, 57 mΩ 4.7 µH, 2.0 A, 70 mΩ 38.4 kΩ, resistor, 1% 22 kΩ, resistor, 5% 14 Resistor, 1% Various 0402 4 4 10 kΩ, resistor, 5% 10 kΩ, resistor, 5% Various Various 0402 0402 Notes Passive not included Value depends on output voltage setting and sequence threshold setting Optional for I2C interface Sequencing Requirements GROUP 4 GROUP 1 GROUP 2 GROUP 3 80% VCC GROUP 1 VCC VCCHIP VCCHSSI GROUP 2 VCCPD VCCPGM VCCA_FPLL VCC_AUX VCCA_GXB/GTB GROUP 3 VCCPT VCCH_GXB VCCD_FPLL VCCT_GXB/GTB VCCR_GXB/GTB VCCL_GTB GROUP 4 VCCO 80% OF LAST RAIL IN GROUP 2 www.analog.com/multioutput-regulators | 7 ADP5050 Supply for Altera Arria V ADP5050 VTT DRV BST1 PVIN1B C1 10𝛍F COMP1 SW1B EN1 R2 L1 = 1.2𝛍H 0.9V C4 100𝛍F Q1 G1 S1 R4 S2 R8 G2 DL2 EN2 VCCD_PLL C21 100𝛍F PGND SS12 VCC D1 DL1 VREG R23 C2 VREG C3 R3 R22 SW1A BUCK 1 4A DDR2/DDR3 VTT R1 FB1 PVIN1A INPUT SUPPLY 4.5V TO 15V VDDR ADP2384 4A BUCK ALTERA ARRIA V Q2 PVIN2A VREG BUCK 2 4A PVIN2B C5 10𝛍F SW2A C6 BST2 BST3 PVIN3 C9 10𝛍F BUCK 3 1.2A COMP3 R26 VCCIO_1P8_1P5 VCCIO_2P5 VIO L3 = 4.7𝛍H R9 FB3 EN3 R10 PGND3 VREG R27 C10 SW3 C11 R11 VDDR BUCK 1/BUCK 2 INTERLEAVED CONNECTION UP TO 8A FB2 COMP2 L2 = 1.2𝛍H D2 SW2B VCCPD 2.5V C12 22𝛍F VCCPGM VCCCLKIN VCC_AUX VCC_PLL SS34 BST4 PVIN4 C13 10𝛍F BUCK 4 1.2A COMP4 EN4 R13 PGND4 R27 LDO 200mA PVIN5 R15 FB5 C17 1𝛍F VIO AGND OSC PG R21 RT SYNC/MODE SDA SCL nINT FSYNC ADP5052—NON I2C VERSION | Integrated Power Solutions for Altera FPGAs 8 PWRGD R19 I 2C R18 VDDIO INT REG 100mA R16 R17 VDD VREG 1.15V C15 22𝛍F 1.5V VOUT5 EN5 C19 R12 FB4 R26 C20 L4 = 4.7𝛍H C18 1𝛍F VCCR VCCT VCCT VCCH_GXB VCCPT VCCPT R20 C16 R14 VIO C14 SW4 GPO1 GPO2 GPO3 GPO4 PowerPlay Power Estimation—Use Case for Altera Arria V See Page 5. Bill of Materials for the ADP5050 Powering Altera Arria V Reference U1 U2 C17, C18, C19, C20 C2, C6, C10, C14 C1, C5, C9, C13 C4, C21 C12, C15 C3, C11, C16 Quantity 1 1 4 4 4 2 2 4 Q1 (Q2) 1 L1, L2 2 L3, L4 2 R21 R4, R8 R1, R2, R9, R10, R12, R13, R15, R16, R22, R23, R24, R25, R26, R27 R3, R11, R14 R17, R18, R19, R20 1 2 Value 5-channel micro PMU 20 V, 4 A buck regulator 1 µF, X5R, 6.3 V 0.1 µF, X5R, 16 V 10 µF, X5R, 25 V 100 µF, X5R, 6.3 V 22 µF, X5R, 6.3 V 2.2 nF, X5R, 25 V Dual N-FETs, 20 V, 25 A, 16 mΩ Dual N-FETs, 30 V, 23 A, 25 mΩ Dual N-FETs, 30 V, 10 A, 20 mΩ 1.2 µH, 22 A, 6.8 mΩ 1.3 µH, 8.2 A, 16 mΩ 4.7 µH, 2.7 A, 57 mΩ 4.7 µH, 2.0 A, 70 mΩ 38.4 kΩ, resistor, 1% 22 kΩ, resistor, 5% 14 4 4 Part Number ADP5050ACPZ ADP2384ACPZN GRM155R60J105KE19D GRM155R61C104KA88D GRM219R61E106KA12 GRM31CR60J107ME39 GRM188R60J226MEA0 GRM155R61E222KA01D Si7232DN Si7228DN IRFHM8364 XAL6030-122ME NRS6045-1R3NMGK XFL4020-472ME NRS4018T-4R7MDGJ Footprint (mm) Vendor ADI ADI Murata Murata Murata Murata Murata Murata Vishay Vishay IR Coilcraft Taiyo Yuden Coilcraft Taiyo Yuden Various Various 7.0 × 7.0 × 0.75 QFN 4.0 × 4.0 × 0.75 QFN 0402 0402 0805 1206 0603 0402 3.3 × 3.3 × 1.0 QFN 3.3 × 3.3 × 1.0 QFN 3.3 × 3.3 × 0.9 QFN 6.0 × 6.0 × 3.0 6.0 × 6.0 × 4.5 4.0 × 4.0 × 2.0 4.0 × 4.0 × 1.8 0402 0402 Resistor, 1% Various 0402 10 kΩ, resistor, 5% 10 kΩ, resistor, 5% Various Various 0402 0402 Notes Passive not included Value depends on output voltage setting and sequence threshold setting Optional for I2C interface Sequencing Requirements GROUP 4 GROUP 1 GROUP 2 GROUP 3 80% VCC GROUP 1 VCC VCCHIP VCCHSSI GROUP 2 VCCPD VCCPGM VCCA_FPLL VCC_AUX VCCA_GXB/GTB GROUP 3 VCCPT VCCH_GXB VCCD_FPLL VCCT_GXB/GTB VCCR_GXB/GTB VCCL_GTB GROUP 4 VCCO 80% OF LAST RAIL IN GROUP 2 www.analog.com/multioutput-regulators | 9 ADP5050/ADP5051/ADP5052/ADP5053 Quad Buck Switching Regulator with LDO or POR/WDI in LFCSP ADP5050/ ADP5052 12V/5V INPUT OPTIONAL I 2C ADP5051/ ADP5053 4A BUCK REG1 1.2V 4A BUCK REG1 2.5V 1.2A BUCK REG 1.8V 1.2A BUCK REG 3.3V 200mA LDO 12V/5V INPUT OPTIONAL I 2C 1.5V MR WDI PWRGD 4A BUCK REG1 1.0V 4A BUCK REG1 2.5V 1.2A BUCK REG 1.8V 1.2A BUCK REG 3.3V POWER-ON RESET AND WATCHDOG VTHR RESET PWRGD 1Resistor programmable current limit (4 A, 2.5 A, or 1.2 A). Key Features • I2C interface with interrupt supportive on fault condition • CH1/CH2: programmable 1.2 A/2.5 A/4 A sync buck regulator with low-side FET driver • CH3/CH4: 1.2 A sync buck regulator • CH5: 200 mA low dropout LDO or watchdog timer and power-on reset • Precision enable on 0.8 V accurate threshold • Wide input voltage range: 4.5 V to 15 V • ±1.5% output accuracy over full temperature range • 250 kHz to 1.4 MHz adjustable switching frequency • Adjustable/fixed output options • Pseudo-DVS: dynamic voltage scaling • • • • • • • • Active output discharge switch FPWM/PSM mode selection Frequency synchronization input or output Power-good flag on selective channels Startup with the precharged output 48-lead, 7 mm × 7 mm LFCSP package −40°C to +125°C junction temperature I2C functionality I2C Functionality VIN = 4.5V TO 15V VOUT1 PVIN1 TO PVIN4 VOUT2 VCORE VOUT2 PVIN5 ALWAYS ON 5V LDO VAUX PROCESSOR/FPGA SDA SDA SCL EN1 EN2 ADP5050 SCL nINT INT VOUT3 EN3 VDDIO VOUT4 MEM EN4 VOUT5 EN5 ANALOG PWRGD ADP5050 application diagram featuring the I 2C interface. Option 1: Resistor programmable output voltage from 0.8 V to VIN ∙ 0.85 12V INPUT 12V INPUT VOLTAGE VOLTAGE 10.2V10.2V (ADJUSTABLE) (ADJUSTABLE) 115˚ 115˚ (ADJUSTABLE) (ADJUSTABLE) JUNCTION JUNCTION TEMPERATURE TEMPERATURE Option 2: Fixed output voltage with I2C programmability with these ranges for each channel [CH1: 0.85 V TO 1.60 V, 25 mV STEP] [CH2: 3.3 V TO 5.0 V, ~300 mV STEP] INTERRUPT INTERRUPT INTERRUPT INTERRUPT TIMETIME Low input voltage detection on PVIN1. 10 | Integrated Power Solutions for Altera FPGAs TIMETIME Overheat function on junction temperature. [CH3: 1.2 V TO 1.80 V, 100 mV STEP] [CH4: 2.5 V TO 5.5 V, 100 mV STEP] ADP505x output voltage options. www.analog.com/multioutput-regulators | 11 0.8 to 0.85 × VIN 0.5 to 4.75 Buck: 4.5 to 15 LDO: 1.7 to 5.5 1.8 to 5.5 Resistor programmable current limit (4 A, 2.5 A, or 1.2 A). 1 0.8 to 0.85 × VIN 0.8 to 0.85 × VIN 0.5 to 4.75 Buck: 4.5 to 15 Buck: 4.5 to 15 LDO: 1.7 to 5.5 Adj (0.8 to 3.8) Adj (0.8 to 5.2) ADP323 1.8 to 5.5 1.8 to 5.5 Buck: 2.5 to 5.5 LDO: 1.7 to 5.5 Triple, 200 mA LDO ADP322 Dual, 3 MHz buck regulator with dual LDO Triple, 200 mA LDO ADP320 LDO: 1.7 to 5.5 Buck: 2.3 to 5.5 3.3, 3.0, 2.8, 2.5, 2.3, 2.0, 1.82, 1.8, 1.6, 1.5, 1.4, 1.3, 1.2, 1.1, 1.0, 0.9 3.3, 3.0, 2.8, 2.5, 2.25, 2.0, 1.8, 1.7, 1.6, 1.5, 1.2, 1.1, 1, 0.9, 0.8 3.3, 3.0, 2.8, 2.5, 2.3, 2.0, 1.82, 1.8, 1.6, 1.5, 1.4, 1.3, 1.2, 1.1, 1.0, 0.9 3.3, 3.0, 2.8, 2.5, 2.25, 2.0, 1.8, 1.7, 1.6, 1.5, 1.2, 1.1, 1, 0.9, 0.8 LDO1: 3.3; LDO2: 1.8, 3.3; LDO3: 1.5 LDO1: 3.3, 2.8, 2.5; LDO2: 2.8, 2.5, 1.8; LDO3: 1.8. 1.5, 1.2 Adj (0.5 to 5) ADP5134 New Triple, 200 mA LDO ADP5043 LDO: 1.7 to 5.5 Buck: 2.3 to 5.5 0.8 to 0.85 × VIN 3 MHz buck regulator with LDO, supervisor, and dual watchdog timers ADP5042 2 × LDO Adj (0.8 to 5.2) LDO: 1.7 to 5.5 Buck: 4.5 to 15 3 MHz buck regulator with dual LDO, supervisor, and dual watchdog timers ADP5041 Quad buck regulator + POR and WDI 3 MHz buck regulator with dual LDO, supervisor, and watchdog timer ADP5040 ADP5053 New 3 MHz buck regulator with dual LDO ADP5037 2 × buck 2 × LDO 2 × buck 2 × LDO 1 × buck 2 × LDO 1 × buck 1 × LDO 2 × buck 2 × buck 2 × buck 2 × LDO 2 × buck 3 × LDO 2 × buck 2 × buck 1 × LDO 2 × buck 2 × buck 2 × buck 3 × LDO 3 × LDO 1 × LDO 1 × buck 2 × LDO 1 × buck 2 × LDO 2 × buck 2 × buck 1 × LDO 2 × buck 1 × LDO 1 × LDO 2 × buck Number of Outputs Buck: 2.3 to 5.5 LDO: 1.7 to 5.5 Buck: 2.3 to 5.5 LDO: 1.7 to 5.5 Buck: 2.3 to 5.5 LDO: 1.7 to 5.5 Buck: 2.3 to 5.5 Quad buck regulator + LDO Dual, 3 MHz, 800 mA buck regulator with dual 300 mA LDO ADP5034 LDO: 1.7 to 5.5 Buck: 2.3 to 5.5 ADP5052 New Dual, 3 MHz buck regulator with dual LDO ADP5033 Quad buck regulator + POR and WDI with I2C Dual, 3 MHz buck regulator with dual LDO ADP5024 ADP5051 New Dual, 1.2 A buck regulator with300 mA LDO Buck: 2.3 to 5.5 LDO: 1.7 to 5.5 Buck: 2.3 to 5.5 LDO: 1.7 to 5.5 LDO: 1.7 to 5.5 Buck: 2.3 to 5.5 Quad buck regulator + LDO with I2C Dual, 800 mA buck regulator with 300 mA LDO ADP5023 VOUT (V) 3.3, 3.0, 2.8, 2.5, 2.3, 2.0, 1.82, 1.8, 1.6, 1.5, 1.3, 1.2, 1.1, 1.0, 0.9, 0.8 3.3, 3.0, 2.9, 2.8, 2.775, 2.5, 2.0, 1.875, 1.8, 1.75, 1.7, 1.65, 1.6, 1.55, 1.5, 1.2 Adj (0.8 to 3.8) Adj (0.8 to 5.2) Adj (0.8 to 3.8) Adj (0.8 to 5.2) 3.3, 3.0, 2.8, 2.5, 2.3, 2.0, 1.8, 1.6, 1.5, 1.4, 1.3, 1.2, 1.1, 1.0, 0.9 3.3, 3.0, 2.8, 2.5, 2.25, 2.0, 1.8, 1.7, 1.6, 1.5, 1.2, 1.1, 1.0, 0.9, 0.8 Adj (0.8 to 3.8) Adj (0.8 to 5.2) Adj (0.8 to 3.8) Adj (0.8 to 5.2) Adj (0.8 to 3.8) Adj (0.8 to 5.2) Adj (0.8 to 3.8) VIN (V) ADP5050 New Dual, 3 MHz buck regulator with 150 mA LDO Product Description ADP5022 Part Number Integrated Power Management Solutions (Micro PMUs) 200 40001 1200 1200 300 1200 200 40001 1200 200 40001 1200 40001 200 200 300 800 300 800 300 1200 300 800 300 1200 300 1200 300 800 800 300 1200 300 150 600 Output Current (mA) — — — Yes Yes — — — — — — — — — — — — — I2C — 0.5 (adj) — 0.5 (adj) — — — 4.63, 3.08, 2.93, 2.63, 2.50, 2.35, 2.068, 1.692 4.63, 3.08, 2.93, 2.63, 2.50, 2.35, 2.068, 1.692 0.5 (adj) — — — — — — — Reset Trip Threshold (V) — 1, 20, 140, 1120 — 1, 20, 140, 1120 — — — 20, 140 20, 140 20, 140 — — — — — — — — 6.3, 102, 1600, 25,600 — 6.3, 102, 1600, 25,600 — — — 102, 1600 102, 1600 102, 1600 — — — — — — — Min Reset Typ Watchdog Timeout (ms) Timeout (ms) 16-lead LFCSP Fixed VOUT options Precision enables, power good pin Individual enable pins with power good Individual enable pins with power good I2C interface with individual enable pins and power good I2C interface with individual enable pins and power good 24-lead LFCSP 48-lead LFCSP 48-lead LFCSP 48-lead LFCSP 48-lead LFCSP 16-lead LFCSP 16-lead LFCSP Fixed VOUT options Adjustable VOUT options 20-lead LFCSP 20-lead LFCSP 20-lead LFCSP 20-lead LFCSP 24-lead LFCSP 24-lead LFCSP 28-lead TSSOP 16-ball WLCSP 24-lead LFCSP 24-lead LFCSP 16-ball WLCSP Package Individual enable pins and supervisor, WDI, WDI2, mode pin, and MR pin Individual enable pins and supervisor, WDI, WDI2, mode pin, and MR pin Individual enable pins, mode pin Individual enable pins and supervisor, WDI, mode pin, and MR pin Mode pin, individual enable pins Mode pin, individual enable pins Mode pin, two enable pins Mode pin, individual enable pins Mode pin, individual enable pins Mode pin, individual enable pins Key Features 2.09 3.79 3.59 4.59 4.39 0.54 0.54 0.54 1.79 1.99 1.79 1.39 1.69 1.99 1.90 1.79 1.59 1.80 Price ($U.S.) ADP505x Design Tool ADIsimPower™ now supports the ADP505x family of multichannel high voltage PMUs. This new family of parts supports 4/5 channels from inputs up to 15 V with load current up to 4 A per channel. Users can optimize the design by taking into account the thermal contributions of each channel by cascading channels, and even by placing the high current channels in parallel to create an 8 A rail. With the advanced features, users can specify independently each channel's performance, from ripple and transient, to switching frequency selection from the channels that support half the master frequency. As with all the other tools, evaluation boards are available by request directly from the tool. Download at download.analog.com/PMP/ADP505x_BuckDesigner.zip. Step 1: Step 2: Optimize for size, cost, or efficiency Specify each channel’s operating conditions, including “do not use” Analog Devices, Inc. Worldwide Headquarters Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 (800.262.5643, U.S.A. only) Fax: 781.461.3113 Analog Devices, Inc. Europe Headquarters Analog Devices, Inc. Wilhelm-Wagenfeld-Str. 6 80807 Munich Germany Tel: 49.89.76903.0 Fax: 49.89.76903.157 Analog Devices, Inc. Japan Headquarters Analog Devices, KK New Pier Takeshiba South Tower Building 1-16-1 Kaigan, Minato-ku, Tokyo, 105-6891 Japan Tel: 813.5402.8200 Fax: 813.5402.1064 Analog Devices, Inc. Asia Pacific Headquarters Analog Devices 5F, Sandhill Plaza 2290 Zuchongzhi Road Zhangjiang Hi-Tech Park Pudong New District Shanghai, China 201203 Tel: 86.21.2320.8000 Fax: 86.21.2320.8222 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Printed in the U.S.A. BR10509-0-11/13(B) www.analog.com/multioutput-regulators
