Development of National
System-on-Chip (NSoC)
Program in Taiwan
Dr. Chun-Yen Chang and Dr. Wei Hwang
National Chiao Tung University
Hsin-chu, Taiwan
http://nsoc.eic.nctu.edu.tw
Outline
„
„
„
„
Introduction
The Si-Soft Initiative
National SoC Program
Summary
NSoC
2
Nov. 18, 2004
Evolution of Silicon Technology
z Heterogeneous
z IP and Platform-based Design
z Low Power
z Scaleable, reuse methodology
SoC era
VLSI
1980
1990
GSI
2000
Computer Focus
2020
Comp./Comm./ Consumer/ Content/
Convergence
PC
μp + Memory
NSoC
2010
Wireless Multimedia Networking
DSP + Analog + RF
3
Nov. 18, 2004
Brilliant
Taiwan
IC
Design
&
Foundry
Unit: USD Billion
Taiwan
Fabless
Worldwide
Fabless
% of share
Taiwan
Foundry
Worldwide
Foundry
% of share
95
96
97
98
99
00
01
95 - 01
CAGR
0.7
0.8
1.3
1.3
2.2
3.3
3.6
31%
5.9
6.7
7.6
8.7
11.7
16.6
13.9
15%
12%
12%
17%
15%
19%
20%
26%
1.1
1.4
2.0
2.8
4.9
9.0
6.1
33%
5.1
5.0
5.1
5.3
7.5
12.9
8.3
8%
21%
27%
39%
52%
65%
70%
73%
Source: Dataquest, FSA, ITRI
Foundry: Ranked 1st Worldwide, shares 76%
IC Design: Ranked 2nd Worldwide, shares 30%
Our Vision: more than 50% by 2008
NSoC
4
Nov. 18, 2004
A few Top Academic Achievements in IT Research
1996-2002 Published Papers in 65 IEEE Journals & Magazines
2002
年
2001
年
2000
年
1999
年
1998
年
1997
年
1996
年
交通大學
（National Chiao-Tung University）
74
89
103
92
102
87
88
台灣大學
（National Taiwan University）
62
78
81
69
61
57
64
MIT
（Massachusetts Institute of Technology）
71
91
70
64
79
94
77
74
52
75
78
62
76
84
UCLA
（University of California at Los Angeles）
65
70
64
65
66
48
42
U.C. Berkely
（University of California at Berkeley）
52
60
46
64
49
54
83
University of Illinois at Urbana-Champaign
59
72
60
76
69
86
70
學
校
Stanford University
NSoC
5
Nov. 18, 2004
2001-2005 Published Papers in ISSCC
Country
2001
2002
2003
2004
2005
Total
USA
86
84
80
82
93
425
Japan
31
30
37
44
45
187
Korea
7
12
19
17
17
72
The
Netherlands
7
8
13
11
10
49
Germany
7
6
10
8
4
35
Taiwan
0
5
3
5
15
28
Belgium
8
4
3
7
4
26
Switzerland
4
0
4
5
10
23
Italy
0
3
5
4
8
20
Canada
4
2
4
2
7
19
France
2
0
4
3
6
15
Ireland
1
1
1
2
4
9
Finland
2
4
0
1
1
8
Total
159
159
183
191
224
916
NSoC
6
Nov. 18, 2004
2002-2004 Published Papers in IEDM
Country
2002
2003
2004
Total
USA
90
87
82
259
Japan
52
55
48
155
Korea
24
23
24
71
Taiwan
11
16
15
42
Germany
12
11
11
34
France
6
5
19
30
Belgium
6
8
10
24
Italy
7
8
8
23
Singapore
3
5
5
13
The
Netherlands
3
3
4
10
Total
214
221
226
661
NSoC
7
Nov. 18, 2004
Numbers of Patent Issued in USA
單位:篇
Country
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
U.S.A
3796
3
4115
3
42266
43838
46232
45939
50658
52194
68480
71841
73365
76927
76511
74616
Japan
1891
2
2048
5
21467
21872
22007
21379
22780
22891
30442
30973
31144
33258
34892
35541
Germany
6541
6465
6326
5995
5818
5831
6016
6107
7967
8101
9049
10111
10132
10394
Korea
163
337
470
689
874
1091
1415
1839
3167
3482
3182
3375
3583
3734
Taiwan
121
168
236
364
436
612
780
955
1534
2096
3073
3656
3681
3689
France
2373
2521
2611
2541
2380
2385
2387
2572
3182
3280
3417
3745
3669
3495
Canada
1005
1104
1038
1070
1107
1188
1294
1342
1825
2079
2276
2542
2536
2576
Holland
516
586
550
534
636
565
555
581
790
784
834
841
1662
2181
England
2046
2108
1808
1738
1586
1680
1750
1938
2362
2391
2364
2551
2286
2160
Swiss
1031
1065
1078
974
978
889
978
960
1211
1339
1418
1625
1632
1694
Sweden
565
556
472
472
566
643
743
760
1084
1301
1520
1669
1647
1513
Italy
983
937
1002
1007
953
839
922
962
1269
1184
1302
1289
1348
1276
Total
7407
7
7934
6
81115
82804
85339
85002
92390
95342
126297
13196
4
13632
3
14572
2
14816
9
16912
0
NSoC
8
Nov. 18, 2004
Global Competitiveness Report (2004-2005)
Country
Growth
Competitiveness
Technology
Public Policy
Macroeconomic
Environment
Finland
1
3
3
3
USA
2
1
21
15
Sweden
3
4
6
17
Taiwan
4
2
27
9
Denmark
5
6
1
4
Norway
6
10
5
2
Singapore
7
11
10
1
Swiss
8
7
8
5
Japan
9
5
16
29
Iceland
10
14
17
12
England
11
18
7
8
HK
21
34
9
13
Korea
29
9
41
35
Malaysia
31
27
38
20
Thailand
34
43
45
23
China
46
62
55
24
NSoC
9
Source: WEF (World Economy Forum)
Nov. 18, 2004
Si-Soft Initiative- Vision
„ Knowledge Economy
„The engine of all industries
Electro-Optical
Information
Appliances
Internet Intra-net
LCD, Optical Communication,
Storage Devices
Design
PDA’s , Games
Humanities/Art
IP Industry
Software, Routers
Protocols, Switches, Applications
Si-Soft
P-SOC
Energy
SOC, EDA,
Batteries, Cells
IP, Products, Services
S/W O/S
System Integration
Communications
Foundries
Packaging
Wireless, Satellite
MEMs
Bio-Informatics,
Bio-chips, BME
Si-Hard
Nano-Technology
Foundry, GaAs
ODM/OEM, Services
Material
Mechanical
Civil/Environmental
Chemical
Automotive, Aerospace
„ The food Chain of Si-Soft Family
NSoC
Bio-Medical
10
Nov. 18, 2004
Si-Soft Initiative / National SoC Program
Vision
Si-Soft Initiative
Execution
Mission
Design and
Service Park
NSoC Program
„ Design Service
„ IP Mall
„ EDA Vendors
„ Incubation Centers
„ Data Centers
NSoC
„ Strategy
„ Coordination and Promotion
„ Human Resources
„ Silicon Intellectual Property (SIP)
„ Innovative Platform and EDA
„ Innovative Product
„ Emerging Industry Development
11
Execution
Government Agencies:
NSC / MOE / MOEA
„ Projects Review and Funding
„ Human Resources Development
„ Technology Research Projects
„ IC Design Park Promotion
Nov. 18, 2004
National SoC Program- Vision
„ Promote Taiwan’s 2nd High -Tech Revolution (The Si-Soft Initiative)
„ Strengthen Taiwan’s industry to produce high value-added product
Manufacturing
Design
Industry Developing Key-point
Value Added
Value Chain
Supply Chain
Design
Sevice
NSoC
Innovative
Product
12
Nov. 18, 2004
National SoC Program- Goal
To provide
an outstanding
design environment for
the use of global systems
design firms.
Establish a rich
resource of Silicon IP
Integrate EDA Tool
and Services
These measures will enable
Taiwan to strengthen its
manufacturing niche
Provide Worldwide Customers
with Easy Design
and SoC Total Solutions
To establish a rich resource of Silicon Intellectual Property (SIP) in Taiwan
within the next 3-5 years, to integrate electronic design automation (EDA) software,
and to provide an outstanding design environment for the use of global systems
design firms. These measures will enable Taiwan to strengthen its manufacturing
niche, to continue its crucial role in the worldwide semiconductor business.
NSoC
13
Nov. 18, 2004
National SoC Research Program
Sub-plan 1
Sub-plan 2
Sub-plan 3
Sub-plan 4
Sub-plan 5
Human Resources
Innovative
Innovative
Innovative
Products
Platforms
IP
Emerging
Industry
Development
1. Human Resources
Pd Verification
2. Innovative
Products
Leading
Product
Vehicles
+
Foresight
Matching Plans
IP Verification
3. Innovative
Platforms
Service Verification
4. Innovative
IP
NSoC
Platform Verification
5. Emerging Industry
Development
14
Nov. 18, 2004
NSoC Human Resources Plan
„ Additional 85 faculty members per year specifically for SoC
design for four years (2002 -2005)
z The specialty areas include RF/AMS, digital, embedded software,
EDA tools and testing
„ Establishment of Six Consortiums from Universities (MOE)
z Advanced Technologies (ADV), Digital IP (DIP), Electronic Design
Automation (EDA), Mixed-Signal Design (MSD),Placement and
Layout (P&L) and System-on-Chip (SoC)
z New VLSI Circuits and Systems Curriculum Development for SoC
Era
„ Enhancement of SoC graduate research programs (NSC)
z Integrated Research Projects
z Mission Oriented Research Projects
NSoC
15
Nov. 18, 2004
SoC Education Development - (MOE)
„ VLSI Circuits and Systems Design Education Program
(six consortiums)
SoC : System on Chip
SoC
EDA : E. Design Automation
MSD : Mixed Signal Design
ESW
S&IP
P&L
EDA
P&L : Prototype & Layout
ESW : Embedded Software
S&IP : System IP Consortium
NSoC
16
MSD
Nov. 18, 2004
SoC Education Development – (MOE)
z Advanced Course
2002 2003
2004
SOC Experiment Platform
z SoC Innovation and Social Impact
z
z
z
z
z
z
z
Course Promotion
System Software & Verification
SoC as 2nd major
Under graduate EDA
Under graduate analog IC
Si-Soft Teacher Promotion
Course/HR
Data Base
• Embedded Software
• Nanometer Technology Circuit Design and EDA
NSoC
17
Nov. 18, 2004
NSoC Human Resources Plan
MOE：VLSI Circuits and Systems Design Education Program
„ Set up six Consortia : System on Chip Consortium (SoC)、 Design
Automation Consortium (EDA)、 Embedded Software Consortium (ESW)、
Mixed Signal Design Consortium (MSD)、 Prototype & Layout Consortium
(P&L) & System IP Consortium (S&IP)
„ Develop 16 inter-collegiate VLSI design courses（1 course per 5
Professors）& promote to 30 colleges。
„ Plan & promote the VLSI design program for university students not majoring
in electrical engineering or computer science.
„ Plan & promote the VLSI related inter-disciplinary courses such as high-tech
laws, science, technology and humanity, and so on.
„ Hold 4 times VLSI design related competitions and forums, over 3000
participants.
Class Participant
Year
Item
Long-term
15
390
IDB：Soc Human Resource Training
FY92
42
1156
Short-term
„ Long-term Class: 24 class,720 man/year.
20
497
„ Short-term Class: 30 class,110 man/year.
Long-term
FY93
„ Set up trainee Certification Examination System.
50
1363
Short-term
„ Total Trainee Amount in the right diagram :
127
3406
Amount
NSoC
18
Nov. 18, 2004
NSoC Innovative Product Plan
„ Three major SoC product lines
z Wireless, Processor, Optical Electronics
„ Design platform emphasis
z Build basic design, SIPs, integration, and design service
infrastructure.
„ Innovative Product Goals
z Utilize IP Malls and Design Platform to implement chip-set
and SoC.
z Extend to high end market and develop mainstream
products.
NSoC
19
Nov. 18, 2004
NSoC Innovative Product Plan
Execution
Unit
Major Projects
Gigabit NIC Single Chip Program
IC Plus Corp.
Development of SHDSL Transceiver chip set
Trendchip
Technologies, Corp.
ALI
C-Media Electronics
Inc.
WELTREND
Infineon
Technologies
AccFast Technology
Giga-Ethernet Controller with PCI Express
Genesys Logic
Solid State Camcorder SoC
Novatek
ADD
MICROTECHCORP.
Asymmetric Digital Subsciber Line II Plus Chipset Development
Multi-functional DVD Rewritable ICs Development Plan
High Defination and Deinterlacer-Integrated Video Processing System
Single Chip for Digital/Analog-Compatible TV
Digital TV SoC for TFT/PDP Based Display
Ipv4/v6 high-speed broadband network SoC
Road Runner
Interface architecture & specification between application processor
(MAP) and WCDMA wireless modem (WCDMA SoC), and validation
for this integration system
NSoC
Execution
Division
20
Department of
industrial
Technology
VIA Technologies,Inc.
Nov. 18, 2004
NSoC Innovative Product Plan
Execution
Division
Major Projects
„ IEEE802.11 a+b+g RF IC - Airoha Technology Corp.
„ 5GHz Wireless LAN RF (Radio Frequency) Transceiver
and PA (Power Amplifier) Module - MuChip、Gatax Technology
„ ZyFLEX Technologies, Inc. 、RoyalTek Company Ltd.、Service
& Quality Technology CO.、ELAN Microelectronics Corp. 、
Himax Technologies, Inc. 、iCreate Technologies Corp.、
Media Reality Technologies.inc.
Industrial
Development
Bureau
„ SoC for MPEG-4/21 Application and Next Generation Mobile
Communications Research -- NCTU
„ Embedded Bio-medical Diagnosis System-on-Chip Desig - CGU
„ Integrated SoC Design for Realizing MPEG-4 Multimedia
National
Science
Council
Information Appliances - NCKU
NSoC
21
Nov. 18, 2004
NSoC – Comprehensive IP Plan
„ Establish key SIPs for SoC realization
„ Verify the feasibility, usability and reusability of SIP
through Innovative Product Plan and Product Vehicles
„ Promote Taiwan as a global IP mall.
NSoC
22
Nov. 18, 2004
NSoC Comprehensive IP Plan
Major Projects
„ 10Gbps VCO by 0.18um 1P6M CMOS-NCU
„ 10Gbps Fiber IC by GaAs HBT-NCU
„ Advanced Network Security Processor –(NTHU)
„
„
„
„
„
„
„
„
„
„
„
„
„
DoIT
Academic Reseach
IEEE 802.11a&802.11g Advanced Ip (ADC/DAC) Development Project –INNOCHIP
32-bit Embedded Processor IP Development Project--SUNPLUS
The development of Multimedia Codec Accelerator Silicon IP --VIVOTEK
Multimedia SoC for Wireless Mobile Phone --quanta
Development key technologies of modualized audio IP --Formosa
development of 0.13um RFCMOS Design Platform and IP for RFIC Application - gigasolution
Advanced high performance Video DSP SoC –uleadtek/SAC/ITE
IP Verification throught Silicon Shuttle--UMC
Multimedia SoC for Wireless Mobile Phone– quanta
32-bit Low Power DSP Core-ITRI
Multimedia Platform Generator，develop C-Base flow-ITRI
WLANGPRS Dual-Mode RF Front End Receiver-ITRI
Accomplish MB-OFDM UWB PHY Simulation & Analysis- Chung-Shan Institute of
Science & Technology
NSoC
Execution
Division
23
Private Cooperation
Research Institutes
Nov. 18, 2004
NSoC Comprehensive IP Plan
Major Projects
Execution
Division
„ Innovative IP Design and SoC Implementation for Digital TV
„ Receivers Complied with DVB-T Standards-- NSYSU
„ A Unified, Low-Power RISC/DSP Processor with Configurable VLIW
„ For Multimedia SOC Applications--CCU
„ SoC Design of Low-Power Multi-Standard Multimedia Wireless
„ LAN – NCHU
„ SoC design for 10-G Ethernet--NTU
„ The Study of SoC Design Technologies for OFDM-based SDR
National
Science
Council
„ Baseband Processing-NCTU
„ Design and Implementation of High-Performance Analog Integrated
„ Circuits --NTU
„ Design Techniques for Ultra Low-power Programmable Processor
„ Based SoCs –CCU
NSoC
24
Nov. 18, 2004
Advanced SoC Research Project – (NSC)
„ Infrastructure Project
z Build infrastructure for design and verification labs: 5
„ Academic Integrated Project：
z Three categories: System, Platform, and IPs.
z 14 Groups and 88 Projects.
„ Object Oriented Research Project
z Promote extreme low power design, high frequency and
high performance analog circuits, processors and
embedded software, nanometer EDA and Test.
z 4 groups and 31 Projects.
„ Advanced SoC Research Project
z High level Integration technologys: 6 projects
NSoC
25
Nov. 18, 2004
NSoC Advanced Platform Plan
A turn-key solution for SoC Design - From software to SoC
Software
main() {
a0=a0+*r1++**r2;
a0=a0+*r1;
a0=a0+a1;
if(gt) goto over;
a0=a0-1;
over:
System
Spec
Behavior
Libraries
DSP
Analog
MCU
ASIC
Architecture (HW/SW
partitioning, co-design,
hierarchical)
Design
Generation
RTL, Synthesis,
Capture, Floor planning
Verification
Function, Performance, Power
Software
main() {
int i, j, k;
i=2;
j=0;
loop:
k=j*i+23;
j=4+j;
Std Cell & I/O
LPSC
Devices
Memories
Analog
Cores
Technology
Physical Design, Interconnect Modeling
(timing closure, signal integrity, …)
NSoC
26
Nov. 18, 2004
NSoC Emerging Industry Development
Customer’s Requirements
Foundry
Mask
Package
Testing
PCB
Assembly
Manufacturing
Service
NSoC
IP Collection
Platform
Service
EDA Service
Data Center
Design
SOC Design
Services
SoC Design Service
IP Mall and Design Platform
27
Nov. 18, 2004
NSoC Emerging Industry Development
Major Projects
„ IP Mall z FARADY Co.’s has accumulated 459 IPs, 12 deals
be done.
z Globalunichip Co.’s has accumulated 620 IPs, 30
deals be done.
„ EDA Service Planz SOTA 、Agilent、TSMC、SOCLE
„ Established the Nang-Kang SoC design district ,
providing research units & company EDA tools.
„ Set up Special Interest Groups (SIG): Digital Home SIG,
TWZigBee SIG, Home Networking SIG, DSC SIG.
NSoC
28
Execution
Division
Department of
industrial
Technology
Industrial
Development
Bureau
Nov. 18, 2004
SoC Design Service Park
„ Tau Yuan
„ Hua Ya
„ Long Tang
„ Nan Kong
„ Nai Hu
„ Hsin Teng
„ Hsin Chu
„ Tai Yan
„ Tai Chung
„ Tai Nan
„ Lu Chu
„ Sea Side
NSoC
INDUSTRIAL DEVELOPMENT
BUREAU
MINISTRY OF ECONOMIC AFFAIRS
29
Nov. 18, 2004
Achievement Statistics
Papers
Year
Execution ISSCC Int’l
Transfer
Other
Conferenc
Patent
IEEE JSSC Journal
Division
Technology Technology
Other
e
IC Design paper
Conference
Paper
FY92 ~FY93
NSC
11
24
50
191
62
30
5
19
FY92 ~FY93
DoIT
0
3
41
86
16
38
22
19
FY92 ~FY93
IDB
0
0
0
0
0
2
0
0
Amount
11
27
91
277
78
70
27
38
Forecast
FY93
NSC
7
14
48
151
33
52
16
22
FY93
DoIT
1
1
25
54
3
136
28
16
FY93
IDB
0
0
0
0
0
23
0
0
Amount
8
15
73
205
36
211
44
38
FY92 ~FY93 Obtained
FY93
Forecast
Amount
11
8
19
27
15
42
91
73
164
277
205
482
78
36
114
70
211
281
27
44
71
38
38
76
NSoC
30
Nov. 18, 2004
Total Execution Plan Status (1/2)
Goal
Current Status
(FY92,93 Jan~Sept)
FY93 Target
„Provide Worldwide
Customers with Easy
Design and SoC Total
Solutions
„IP MALL Project:2
„Platform Service Plan:4
„Establish IP MALL &
transaction
„Platform Service Plan:4
„Establish a Rich Store
of Silicon IPs
„Comprehensive IP Plan:9
„Comprehensive IP Plan:10
„Integrate EDA Tool and
Services
„Innovative Product Plan:11
„Advanced Platform Plan:3
„Research Centers:7
„IDB-Leading New
Product:10
„NSC-Environment
Plan:5,Integrated&TargetOriented Plan: 18set, 119
ea
„Innovative Product Plan:15
„Advanced Platform Plan:4
„Research Centers:10
„IDB-Leading New Product:20
„NSC-Integrated &TargetOriented Plan: 24set,153ea
NSoC
31
Nov. 18, 2004
Total Execution Plan Status (2/2)
Goal
Current Status
(FY92,93 Jan~Sept)
FY93 Target
„Incubate SIP、
EDA Tools、
SoC、SiP
human
resources
„Industry :
professional
training Course 497
participation，onjob training: 1363
participation
„Student : advanced
class 3359
participation
„Industry :
professional
training Course 720
participation，onjob training: 1600
participation
„Student : advanced
class 3800
participation 3800
NSoC
32
Nov. 18, 2004
Main Achievements in 2004
„ Technology Development
„ Economic Impact
„ SoC R&D Promotion
NSoC
33
Nov. 18, 2004
Technology Development (1/8)
„ 32-bit Embedded Processor IP Development Project
32-bit Embedded Processor IP
(A) Architecture Design
„ Instruction Set Architecture Design
„ Micro-Architecture Design
„ Module Design
(B) Implementation
„ Micro-Architecture Implementation
„ Module Implementation
„ Integrated Verification
„ Chip Realization for 0.18um Process
(C) SoC/IP Design and EDA Environment
„ EDA Environment Support
„ Soft IP Package for Processor
„ SoC Integration with Peripheral IPs
„ Integrated Verification in SoC Level
(Sunplus Technology)
NSoC
34
Nov. 18, 2004
32-bit Embedded Processor IP Development Project
Patents
Instruction Set
Architecture
MicroArchitecture
Software
Tool Chain
EDA
IP Issues
Module
Design
System
Integration
Implementation
Debug
Verification
(Sunplus Technology)
NSoC
35
Nov. 18, 2004
SoC R&D Platform
SoC Research
SoC Integration
Embedded Software Development
Operation System
Module Design
Integrated Develop Environment
Algorithm Implementation
Instruction Set Simulator
Circuit Design
Compiler
Embedded
Processor
Assembler
Test Bench
In-Circuit Emulator
Evaluation Board
Embedded Systems
Applications
Embedded System Development
Hardware/Software Co-design
Verification
Bus Functional Model
Reuse Methodology
IP Package
Microarchitecture
Instruction Set Architecture
Processor Research
(Sunplus Technology)
NSoC
36
Nov. 18, 2004
Technology Development (2/8)
„ Gigabit NIC Single Chip Program (IC Plus Corporation)
The 0.13~90nm CMOS Gigabit Ethernet NIC Single Chip
The Lowermost Power Consumption Compared With
Other 0.18u CMOS Gigabit NIC ICs
The Smallest Die Size Compared With Other 0.18u CMOS
Gigabit NIC ICs
IEEE 802.3 Compliant 1000BASE-T, 100BASE-TX,
10BASE-T
Complete Software Drivers And Utilities Support
Patents
„ SCA (Smart Cable Analyzing : Network Physical
Layer With Smart Cable Analyzing Function And
Application Device Thereof)
„ POA (Power Off Alert : Network Physical Layer
With Power Off Alerting Function And Alerting
Method Thereof)
NSoC
37
Nov. 18, 2004
Technology Development (3/8)
„ Advanced Network Security Processor-Layout View (NTHU)
HMAC01
RSA
C-DMA
&
RNG
AES02
AES01
NSoC
HMAC02
38
Nov. 18, 2004
Platform of Network Security Processor
Secret Key Crypto-Engine
AES
ARM922T
TIC
NIC
PMU
AHB
SMI
Packet
Processor
Cryptographic
DMA Controller
Cryptographic
Processor
Public Key Crypto-Engine
RSA/ECC
Hash Engine
HMAC MD5, HMAC SHA-1
Random Number
Generator
SMI : Static Memory Interface
TIC : Test Interface Controller
PLL
Internal
Memory System
PMU : Power Management Unit
NIC : Network Interface Controller
(NTHU)
NSoC
39
Nov. 18, 2004
Technology Development (4/8)
„ Advanced Unified DSP Core
z Brand new VLIW instruction set
architecture
‹ Combined compressed form,
various
condition, and rich bundle formats
‹ 8 pipelining stages
‹ Friendly for real-time embedded
systems
¾ Fast context switch
¾ Low interrupt latency
z Balancing four aspects
‹ High programmability
‹ High configurability
‹ High general purpose computation
‹ High DSP computation
ccu
NSoC
40
Nov. 18, 2004
System-Wide Power-Aware Design (5/8)
Application
Analyzer
O.S + Compiler + IPs
Hardware Tuning
C program
Main( ) {
}
Fun1();
Fun2();
…………
• IP Selection
• Core Library
• Architecture Models
•Microprocessor
•Memory Architecture
•Bus Structure
•Encoding
•Cache Organization
•Peripherals
Select Primitive：
•
•
•
•
•
Power analysis
Partitioning
Hierarchy
Power / Performance
……….
Architecture
IP1
RISC
…
Identify
Application
Characteristics
Target SoC
DSP
IPN
Software Tuning
•
•
•
•
•
•
•
•
Power-aware Library
Profiling
Code Optimization
OS scheduling policies
inst. Scheduling
Freq. Scaling
Registers Allocation
……
Peripherals
Memory
Cache
Energy Monitor
Component-based Energy
Instruction-based Energy
ccu
NSoC
41
Nov. 18, 2004
Technology Development (6/8)
„ Platform Service Development for RF SoC Design
(Agilent Technologies)
Program Structure Divided into six sub projects :
„ RF SOC Design Flow Service
z Establish reference design flow
z Identify service opportunities
„ System Modeling Services
z Assess ADS Behavioral model capability for IP reuse
z Develop ADS platform based behavioral modeling and verification
services
„ Package Modeling Service
z Demonstrate integration of package models into the ADS platform
z Develop services for package models in ADS
„ Test Preparation Service
„ Pilot Service Demonstration
„ RF Capability Development
Highlights
„ RF SoC Design Flow:
z Encapsulates RF IP
z Cross function integration
z Provides engineers mobility and high productivity
z Virtual vertical integration that allows concurrent design practices
z High frequency infrastructure maturity model
„ Service
z Behavioral modeling and verification service definition
NSoC
42
Nov. 18, 2004
Technology Development (7/8)
„ The Construction of SIP Mall and SIP Collection Project-Faraday
A. Project Goal
SIP Mall E-Commerce Platform
IT Infrastructure Research and Development
„ Adopt J2EE, Oracle, XML, and E-Commerce Security technologies
„ Design architecture of e-commerce platform to meet industry demand
Silicon IP Management
„ Build up an on-line SIP management system
„ Prepare a GUI interface for IP vendors to perform full-life-cycle IP
management, including registration, update and phase-out
SIP Transfer Protocol and Reuse Standard
„ Collaborate with international organization like VISA and ITRI to establish
IP reuse standard
„ Set up IP reuse and qualification standard for IP transfer on SIP Mall
website
SIP Trading and Servicing Mechanism
„ Create standard operating procedure for on-line SIP service
„ Enable real-time on-line service for SIP customers and vendors
SIP Mall Security Infrastructure
„ Implement network security infrastructure
„ Implement data encryption policy
„ Implement firewall to prevent possible intrusion
SIP Mall Operation and Maintenance
„ Integrate all related e-commerce services in one single website
„ Develop and promote on-line SIP business
NSoC
43
Nov. 18, 2004
Technology Development (8/8)
„ SoC Design Service Platform in 90nm and 130nm generation (TSMC)
„ 90 nm and130 nm Memory project
z Complete 90 nm and130 nm OTP complier circuit and chip design
z Complete SP and DP SRAM compiler circuit design
z Complete 1TRAM circuit and chip design
„ 90 nmand130 nm I/O project
z Complete90 nmand130 nm Standard I/O circuit and chip design
Complete130 nm 3.125 Gbps SerDes circuit and chip design
z Complete130 nm PCI Express programming and circuit
z simulationComplete130 nm USB 2.0 circuit and chip design 90
nmand130 nm Standard Cell project
z Complete90 nmand130 nm Standard Cell circuit and chip design 。
„ 90 nmand130 nm Analog IP project
z Complete1.6 GHzand800 MHz PLL circuit and chip design 。
z Complete400 MHz Single Power and Dual Power PLL circuit and
chip design Complete800 MHz de-skew and 1GHz Multi band PLL
circuit and chip design
z Complete250MHz, 10 bits, Video DAC circuit and chip design
NSoC
44
Nov. 18, 2004
Economic Impact
Industry
Impact
Private Circles
Investment
Year
Execution
Tech. Transfer
(thousand)
FY92、93
DoIT
10,484
199
30
FY92、93
IDB
-
51
4
amount
10,484
250
34
FY93 Forecast
DoIT
24,600
112
17
FY93 Forecast
IDB
-
38
1
amount
24,600
150
18
Total Amount
35,084
400
52
NSoC
45
(hundred
million)
(hundred
million)
Nov. 18, 2004
SoC R&D Promotion(1/3)
„ Define IP Qualification Guideline
z IP Qualification Alliance Established by 14 core members in
Taiwan to set complete & implementable IP Integration &
Qualification Std. (Apr. 8, 2003)
z IP Qualification Guidelines V 1.0 released (Nov. 30, 2003)
z IP Qualification Guidelines (VHDL Version)V 1.0 released
(Oct.22, 2004)
„ Promote Star IP Plan in academia
z Develop advanced IP for SoC Integration.
z Target advanced application domain.
z Through research institutes for seamless technology
transfer。
NSoC
46
Nov. 18, 2004
SoC R&D Promotion(2/3)
„ STC set up ”SoC Technology Center”
z System on Chip Key Technology Development 4 Year Project
z Domestic Communication and Optoelectronics Infrastructure
Construction Project
„ Chung-Shan Institute of Science & Technology develop SoC technology
z UWB System Platform and IP Development Project
z WCDMA WLL Development Project (under National Teccomm. Program)
„ Universities Establish SoC Centers
z Advanced Network Security Processor and the Related SOC Design and
Test Technologies (NTHU)
z Key Components for Fixed Wireless Communications (NCU)
z Experimental Project for SoC Collection,Verification and Interface
Integration (NCTU)
z Experimental Project for SoC Collection,Verification and Interface
Integration (NCTU、NCU、NCKU、NTU)
NSoC
47
Nov. 18, 2004
„ Universities Establish SoC Centers
z Advanced Network Security Processor and the Related
SOC Design and Test Technologies (NTHU)
z Key Components for Fixed Wireless Communications
(NCU)
z Experimental Project for SoC Collection,Verification and
Interface Integration (NCTU)
z Experimental Project for SoC Collection,Verification and
Interface Integration (NCTU、NCU、NCKU、NTU)
„ 4G and B3G Research and Development
z OFDM, MIMO and Intelligent BS Technologies
z System and Architecture Design: NTP
z FPGA, Key Component essential IPR: NSOC
z Participants: ITRI, CSIST, III, domestic industry
NSoC
48
Nov. 18, 2004
SoC R&D Promotion(3/3)
Introduce Domestic Research Centers
„Viatech
- VIA Advanced Technology Development Center
„Advantech - Embedded System R&D Center
„Quanta
- Quanta Research Institute
Introduce International Research Centers
„Intel
- Intel Innovation Center
„Broadcom - Network SoC R&D Center
„Pericom - Advanced Mixed-Signal IC R&D Center
„Synopsys - VDSM (Very-Deep Sub-Micron) EDA R&D
Center
NSoC
49
Nov. 18, 2004
Si-Soft Research Center
„ Transition From Manufacturing Industry to Value
z added Design Service
NSoC
50
Nov. 18, 2004
New Business Model
„ Facilitate the Exchanges of Valuable IPs
Silicon IPs
Government
Valuable Silicon IP Exchanges
System Houses
Fabless
Foundry
Function Enhancement / Cost Reduction
Enter into USA, Europe, Japan and China Markets
NSoC
51
Nov. 18, 2004
New SoC Business Frontiers
„ SoC Innovative Product Partnership (SIPP)
Data
Center
EDA
Service
Company
IP Mall
Service
SoC
VC
Service
SIPP
Foundry
Package, Test
Office
Put all the SoC support under one roof.
NSoC
52
Nov. 18, 2004
Global SoC Total Solution
IC Channel
EMS
System
Foundry
SoC Supply Chains
Data Center
IP Mall
Testing
Si-Soft
Promotion
Projects
Package
Design Service
SoC Platform
SoC Innovative
Product Partnership
(SIPP)
Fabless
NSoC
EDA Service
53
Nov. 18, 2004
Summaries
„ SoC technology and design have become a
dominant focus in today's global ICs industry
„ Taiwan Government ‘s Endorsement
z Si-Soft Initiative
z National SoC Program
„ Taiwan SoC Design Service Park
„ New SoC Business Model (SIPP)
NSoC
54
Nov. 18, 2004
Appendix
Market Analysis
IP /SOC Market Overview and Outlook
What is or should be D&R’s role in the IP business
Session 1A: IP Business model
Session 2A: Design Platform
Session 3A: Industrial Reuse Practice
Session 4A: ASIC Design Platform
Session 5A: Design Methodology
Session 6A: Design Methodology
Session 7A: Industrial IP Design practice
Open Forum 1A: Verification
Open Forum 1B: Reuse Practice
Open Forum 2B: Design Methodologies
Session 1B: Best IP Prize
Session 2B: IP SOC Verification
Session 3B: Best IP Prize
Session 4B : Verification
Session 5B: Multi-Processor and Multi-Thread SOC
NSoC
55
Nov. 18, 2004
Si-Soft Initiative
National SoC Program
Thank you for your attention
Your comments and suggestions
are very much appreciated
NSoC
56
Nov. 18, 2004