TECHNICAL ARTICLE
Snehal Prabhu
and Ian Beavers
Analog Devices, Inc.
| Share on Twitter
LESS THAN ONE IN A
QUADRILLION—A TEST
METHOD FOR MEASURING
ADC CONVERSION ERROR RATE
| Share on LinkedIn
|Email
Abstract
To err is human. But what claims can be made about your system’s
analog-to-digital converter (ADC)? We will review the extent of
our conversion error rate (CER) testing and analysis of high speed
ADCs. The ADC CER measurement process may take weeks or
months to complete depending upon the sample rate and the target
limit required. Often, testing beyond the first error rate occurrence
is needed for a high confidence level (CL) (Redd, 2000). For those
systems that require a low conversion error rate, it takes this kind
of detailed attention and effort to quantify. When we get done with
it all, the error rate can be established with high confidence—
better than <10–15.
Many real-world high speed sampling systems, such as electrical
test and measurement equipment, vital systems health monitoring,
radar, and electronic warfare countermeasures cannot tolerate a
high rate of ADC conversion errors. These systems are looking for
an extremely rare or small signal across a wide spectrum of noise.
False alert triggers in these systems can cause system failure.
Therefore, it is important to be able to quantify the frequency and
magnitude of a high speed ADC conversion error rate.
CER vs. BER
At the onset, let’s separate two distinct differences in error rate description. Conversion error rate (CER) is typically a result of the ADC making
an incorrect decision about an analog voltage sample and, therefore, its
respective digital code compared to the full-scale range of the converter
input. The bit error rate (BER) of an ADC could also describe a similar error.
But, for the purposes of our discussion here, we define BER as purely a
digitally received error of otherwise correctly converted code data. In such
a case, the correct ADC digital output fails to be properly received in a
downstream logic device such as an FPGA or ASIC. The degree to which
the code is in error and its frequency of occurrence is what we will discuss
in the remainder of this article.
The ADC conversion error may be difficult to glean by simply reading a
technical parameter off a data sheet. You can certainly get some kind of
estimation about the conversion error rate with a single number on a converter data sheet. But what exactly does the number quantify? You cannot
tell what size sample excursion is considered to qualify as an error and
are not able to identify the confidence level in either the test measurement or simulation. The definition of an “error” must be bounded in the
magnitude for which the frequency of occurrence is known.
Visit analog.com
Error Sources
There are several error sources, both internal and external to the ADC, that
can play a role in conversion errors. External sources include system power
supply glitches, ground bounce, abnormally large clock jitter, and potentially erroneous control commands. ADC data sheet recommendations and
applications notes will typically outline the best system layout practices to
circumvent these external issues. Internal sources to the ADC can mainly
be attributed to metastability (Beavers, 2014), or residual processing handoffs between stages in the analog domain, and output timing errors in the
digital and physical layer domain. These challenges must be analyzed by
the ADC design team during the development of the component.
Ideal ADC Transfer Function
Actual ADC Transfer Function
Digital Output
Code
Digital Output
Code
Analog Input
Analog Input
Figure 1. An ideal ADC sample has a single digital output for each bit of analog
resolution across the full scale (left). An example of real-world ADC output behavior
(right) shows some ambiguity related to internal and external noise.
A metastable condition in a bank of comparators can occur when the
comparator reference voltage is precisely equal to, or extremely close to,
the voltage to be compared (Kester, 2006). The closer in magnitude the
compared voltage is to its reference, the longer in time it takes for the
comparator to make a complete decision. In the case where the delta voltage between the two is very small or zero, the comparator may not have
enough time to resolve a final decision as to whether the voltage is above
or below the reference. As the conversion time expires for the sample,
the comparator outputs may be left in a metastable third state instead of
clearly deciding a valid logic output of 1 or 0 (Kester, 2006). This indecision will ripple through the ADC and can cause a conversion error.
A
Comparator
Output
(VIN > Reference)
Valid “1”
B Small +VIN
Output
C ~Zero +VIN
Undefinable State
(Metastable)
~Zero –VIN Valid “0”
Small –VIN
Output
Large –VIN
Large +VIN
Valid
Data A
Valid
Valid
Data B Data C
Time
Figure 2. An ideal ADC sample has a single digital output for each bit of analog
resolution across the full scale (left). An example of real-world ADC output behavior
(right) shows some ambiguity related to internal and external noise.
Less Than One in a Quadrillion—A Test Method For Measuring ADC Conversion Error Rate
In pipeline ADC architectures, additional potential sources of conversion
errors are those at the points of the interstage boundary handoff where
a residual voltage is passed from one stage to the next. For example, if
an uncorrected gain matching error occurs between two stages, then
the handoff of the residual voltage can have an error in the subsequent
stages. Additionally, a glitch in the residue DAC that sends a voltage to
the next ADC stage can also cause an unexpected disruption error in the
later processing (Kester, 2006). Inherent to all ADCs is a thermal noise
component present in any passive component that determines the
absolute noise floor of the ADC processing (Brannon, 2003). All these
potential sources of error must be vetted and quantified during a thorough
characterization of the ADC to ensure that there are not any gaps in the
execution of the converter.
The integral nonlinearity (INL) of the ADC is the transfer function across
the full-scale ADC input range of the actual samples code relative to the
ideal output (Kester, 2005). This information is also typically specified
and plotted in an ADC data sheet. The maximum deviation to the ideal
code is typically noted as some number of least significant bits (LSB). An
example INL plot can be seen below. Although it represents some amount
of absolute error, INL will typically only account for about 0 to 3 codes in
most high speed ADCs that are 16 bits or less in resolution. It will not be
a principal contributor to the actual converter error rate.
1.0
0.8
0.6
Input Referred Noise—
Ideal 14-Bit ADC
1
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
Codes
Figure 4. An example measured INL curve across all ADC codes shows about
±1 LSB or ±1 code of maximum error compared to an ideal sample, essentially
negligible to an ADC conversion error.
0.1
Test Method
0.01
0.001
0.0001
0.00001
N – 11
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
N + 11
0.000001
ADC Output Code
10
INL (LSB)
Input referred noise is one inherent component of ADC conversion imperfection that is inclusive of the thermal noise seen at the ADC input. It is often
quantified using a histogram of digital output codes, given an open or
floating ADC input. This is typically noted and shown within an ADC datasheet. The plots below show an example of the magnitude of this noise,
which in this case is [N] ± 11.
10
~±1
LSB
0.4
Noise Components
Histogram Count (Log—Millions)
Input Referred Noise—
Actual 14-Bit ADC
1
0.1
0.01
0.001
0.0001
0.00001
0.000001
N – 11
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
N + 11
2
Histogram Count (Log—Millions)
ADC Output Code
Figure 3. With an open or floating input, an ideal ADC will sample a single midscale
offset code as shown in the histogram on the left. An actual ADC will have input
referred noise that should exhibit a Gaussian shape curved histogram in log scale
on the right.
A test method for long-term CER detection can use a very low ADC input
frequency relative to the clock rate. The slope of the sine wave can be
approximated to be roughly a straight line between any adjacent two
sample points. Analogously, a frequency input that is slightly higher than
the sample rate will alias as a low frequency. For this case, there is a
predictable ideal solution whereby each adjacent sample can be within
±1 code from the previous sample. The input signal frequency and the
encode sample clock frequency need to be locked in a predictable phase
alignment. If this phase is not held constant, then the alignment will walk
out of phase and the measured data will not be useful. Thus, in order
to calculate the ideal conversion, sample(N + 1) – sample(N) should be a
code difference in magnitude of no more than 1.
Sources of small predictable conversion errors inherent in all ADCs include
integral nonlinearity, input noise, clock jitter, and quantization noise. All of
these noise contributors can be added cumulatively to obtain a worst-case
limit whereby, if exceeded, an error would be considered from two adjacent conversion samples. A 16-bit ADC will have 24 or 16× the number
of output codes as that of a 12-bit converter. Therefore, this expanded
resolution will have an impact on the number of codes used for a limit to
test the conversion error rate. All else being equal, a 16-bit ADC will have
a limit that is 16× wider than that of a 12-bit ADC.
An internal built-in-self-test (BIST) within the ADC can be used to establish
an error threshold based on thermal noise, clock jitter, and other system
nonlinearity. Particular samples can be flagged within the ADC core when
an error limit is exceeded with its corresponding sample count and error
magnitude. One of the main benefits of using an internal BIST is that it
isolates the error origin within the ADC core itself, which excludes those
errors due to received bit errors exclusively in the digital data transmission output. Once the error threshold is established, then a full system
measurement involving the ADC plus the link plus the FPGA or ASIC is
performed to determine the complete component CER.
10
10–1
10–2
10–3
10–4
10–5
10–6
10–7
10–8
10–9
10–10
10–11
10–12
10–13
10–14
10–15
10–16
10–17
ADC Error vs. “X” Sigma of Normal
Thermal Noise Distribution
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5
Sigma of Normal Thermal Phase
Figure 5. The conversion error rate of an ADC vs. its thermal noise is typically
only available through transistor level circuit simulations. An example plot for a
12-bit ADC is shown above where a thermal noise sigma of 8 must be tolerated to
achieve a CER of 10–15.
Let’s examine how we calculate the thermal noise contribution
(Brannon, 2003).
SNR = 20log(VSIGNAL/VNOISE)
VNOISE = VSIGNAL × 10^(–SNR/20)
To find the rms noise of an ADC, we must scale the VFULLSCALE:
VNOISE = (VFULLSCALE /(2 × √(2) × 10^(–SNR/20)
Calculating the thermal noise limit of the AD9625, a 12-bit, 2.6 GSPS ADC
designed for a full-scale range (FSR) of 1.1 V, with an SNR of 55 at 2.508 MHz
aliased input frequency using the following equations. Thermal noise
limit = 8 sigma × VINpp × 10 × (SNR/20)/2√(2) = 3.39 mV ~ ±12 codes.
In this case, an 8 sigma distribution of only the thermal noise alone can
contribute up to ±12 codes to a 10–15 error limit. This should be tested
against the total input referred noise measurement of the ADC. Keep in
mind that the input referred noise from a data sheet may not be based
on a large enough sample size for 10–15 testing. The input referred noise
will encompass all internal noise sources, including thermal noise.
In order to define the limit to possibly cover all the sources of the noise,
including the test equipment, we use the internal BIST to measure the
error magnitude distribution. Using an internal BIST within the AD9625
running at 2.5 GSPS and an aliased AIN frequency of 80 kHz close to the
full scale of an ADC under nominal supply and temperature conditions,
CER measurements were performed over a period of 20 days.
Let’s suppose that all of the ADC processing of an analog voltage to a
digital representation is ideal. The digital data still needs to be precisely
transmitted and received at the next stage of processing in an FPGA or
ASIC downstream in the signal chain. Digital snafus at this stage are
typically defined by the term bit errors or a bit error rate. However, comprehensive characterization of the data eye diagram output from an ADC at
the end of the PCB trace can be directly measured and compared against
the JESD204B receiver mask for a very good understanding of the output
quality (Farrelly, Loberg 2013).1
In order to establish a CER of 10–15, one quadrillion samples, within
1 sigma at 2.6 GSPS, we need to run this test continuously for 4.6 days.
In order to establish a higher confidence level with a larger sigma, this
test needs to be run even longer2. The testing requires a very stable test
environment with clean supply sources. Any nonsuppressed glitch on the
voltage supply to the converter under test will result in erroneous measurements and the testing will need to restart all over again.
An FPGA counter can be used to track the instances where the magnitude
difference between two adjacent samples in time exceeds the threshold
limit, counting that sample as a conversion error. The counter must keep a
cumulative total of errors throughout the duration of the testing. To ensure
that the system is working as expected, the magnitude of the error vs.
ideal should also be logged in a histogram plot. The time needed for the
test will be based upon the sample rate, the desired tested conversion
error rate, and the confidence level desired. A CER of <10–15 with a 95%
confidence level requires at least 14 days of continuous testing. An estimation of the CER can be done by extrapolating beyond measured values
with a lower confidence level (Redd, 2000).
Since measuring an ADC’s CER can be a time consuming exercise, you
may be wondering if it is possible to extrapolate beyond known measured
results. The good news is that yes, this can be done. However, there are
always trade-offs in this approach, so caveat lector may be in order. As
we continue to make an educated mathematical estimation of what the
error rate would be, had we tested for it with near certainty, we approach
ever diminishing confidence levels in our estimation.3 For example, it may
not be all that useful to know an error rate of 10–18, if we are less than 1%
confident in our answer.
The error threshold for conversion may sum cumulatively to 4 or 5 least
significant bits for any given sample. It may be slightly more or less depending upon the ADC resolution, system performance, and the application’s
error rate requirements. When this error band is used to compare against
the ideal value, a sample that exceeds this limit will be counted as a
conversion error. The error band for an ADC can be tested by adjusting
the threshold and monitoring typical performance data. The final test limit
used is the root mean squared sum of the imperfections, which is usually
dominated by the ADC thermal noise.
The tested data histogram of sampled values vs. the ideal resembles that
of a Poisson distribution, which is a discrete distribution. The major difference between a Poisson and a binomial distribution is that the Poisson
does not have a fixed number of trials. Instead, it uses the fixed interval
of time or space in which the number of successes is recorded, which is
analogous to the CER test method described. Any recorded sample that
is beyond the calculated error limit from ideal is identified as a bona fide
code error.
Code Histogram Count (Log)
Conversion Error Rate Due to Thermal Noise
Visit analog.com Calculated
Error Limit
Absolute Value of ADC Sampled Code vs. Ideal
Figure 6. By taking a long-term histogram of ADC samples compared to the
ideal output code, we can detect any excursion beyond the calculated limit.
The histogram resembles that of a Poisson distribution.
Systems
Now that we understand the CER for a single converter, we can compute
the error rate for an advanced synchronous system of many converters.
Many system engineers ask what the cumulative ADC conversion error
rate will be within a large complex system that uses a multitude of ADCs.
3
4
Less Than One in a Quadrillion—A Test Method For Measuring ADC Conversion Error Rate
Therefore, a secondary consideration for advanced multisignal acquisition systems is to identify the conversion error rate across not one, but
an array of converters. This may sound like a daunting task at the onset.
Fortunately, after the CER is measured or computed for a single ADC,
extrapolating this rate to multiple ADCs is not too terribly difficult. The
function then becomes a probability expansion equation, based on the
number of converters used in the system.
First, we find the probability that a single converter will not exhibit
an error. This is only slightly less than 1 by the value of the error rate,
(1 – CERSINGLE). Second, this probability is then multiplied by itself for each
ADC in the system, (1 – CERSINGLE)#ADCs. Finally, we can find the rate that an
error will occur in the system by subtracting this value from 1. We get the
following equation:
CERMULTIPLE = 1 – (1 – CERSINGLE)#ADCs
Let’s consider a system using 99 ADCs with a single ADC CER of 10–15.
1 – CERSINGLE = 0.999999999999999
References
Beavers, Ian. “Demystifying the Conversion Error Rate of High Speed ADCs.”
EDN, 2014.
Brannon, Brad. “Analyzing ADC Noise Impacts on Wireless System
Performance.” EE Times, 2003.
Farrelly, Frank and Chris Loberg. “Faster JESD204B Standard Presents
Verification Challenge.” Electronic Design, 2013.
Kester, Walt. “MT-011: Find Those Elusive Sparkle Codes and Metastable
States.” Tutorial MT-011, Analog Devices, Inc., 2006.
Kester, Walt. “MT-004: The Good, the Bad, and the Ugly Aspects of ADC
Input Noise—Is No Noise Good Noise?” Tutorial MT-004, Analog Devices,
Inc., October 2005.
Redd, Justin. “Calculating Statistical Confidence Levels for Error
Probability Estimates.” Lightwave, 2000.
Redd, Justin. “Explaining Those BER Testing Mysteries.”
Lightwave Online, 2004.
CERMULTIPLE = 1 – (0.999999999999999)99 =
9.8999999999995149000000000799095 × 10–14 (~about 10–13)
We can see that the CERMULTIPLE value is now nearly 100× greater than the
CERSINGLE of 10–15. We can glean from this that essentially the conversion
error rate of a system with 99 ADCs scales proportionately to the CER of a
single ADC based upon the quantity of ADCs in the system. It is fundamentally higher than that of a single ADC and is limited both by the conversion
error rate of a single ADC and the quantity of converters used within the
system. Therefore, we can establish that a system composed of many
ADCs may significantly impair the overall conversion error rate compared
to that a single ADC.
Ugalde, Jeffrey and Ian Beavers. “Designing JESD204B Converter Systems
for Low BER.” EDN, 2014.
Wolaver, Dan H. “Measure Error Rates Quickly and Accurately.”
Electronic Design, 1995.
Endnotes
1
While not discussed in detail within this article, the quality of the digital
data eye at the ADC receiver, and therefore the BER of the digital link,
is attributable to many factors including pre-emphasis, PCB material,
intersymbol interference, and the trace length.
2
To examine the confidence level of CER testing in more detail, reference
(Redd, 2000) and (Beavers, 2014).
3
Extrapolation of known data can be done at the expense of the confidence level.
10–7
ADC CERMULTIPLE vs. # ADCs
10–8
10–9
10–10
CERMULTIPLE
10–11
10–12
About the Authors
10–13
Snehal Prabhu has been a product development engineer in the
High Speed Converter Group at Analog Devices since 2012. He
holds a master’s degree in electrical engineering from Arizona
State University and a B.S in electronics and telecommunications
from Goa University, India.
10
–14
10–15
10–16
1
10
100
System ADC Count
1k
10k
Figure 7. The CER of a system using multiple converters proportionately scales the
single CER by the ADC count.
Pinpointing ADC conversion errors can be challenging, but achievable.
The first step is to identify what magnitude a conversion error looks like
in a system. Then, a set of appropriate bounded error limits needs to be
identified that includes the nonlinear benign sources of expected ADC
operation. Finally, specific measurement algorithms can achieve most or
all of the testing. Extrapolation of the measurements can target beyond
the boundaries of the testing for additional approximation.
Ian Beavers [Ian.Beavers@analog.com] is a product engineering
manager for the Automation Energy and Sensors team at
Analog Devices (Greensboro, NC). He has worked for the company
since 1999. Ian has over 19 years of experience in the semiconductor industry. Ian earned a bachelor’s degree in electrical
engineering from North Carolina State University and an M.B.A.
from the University of North Carolina at Greensboro.
Online Support
Community
Engage with the Analog Devices
technology experts in our online
support community. Ask your
tough design questions, browse
FAQs, or join a conversation.
ez.analog.com
Analog Devices, Inc.
Worldwide Headquarters
Analog Devices, Inc.
Europe Headquarters
Analog Devices, Inc.
Japan Headquarters
Analog Devices, Inc.
Asia Pacific Headquarters
Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
U.S.A.
Tel: 781.329.4700
(800.262.5643, U.S.A. only)
Fax: 781.461.3113
Analog Devices, Inc.
Wilhelm-Wagenfeld-Str. 6
80807 Munich
Germany
Tel: 49.89.76903.0
Fax: 49.89.76903.157
Analog Devices, KK
New Pier Takeshiba
South Tower Building
1-16-1 Kaigan, Minato-ku,
Tokyo, 105-6891
Japan
Tel: 813.5402.8200
Fax: 813.5402.1064
Analog Devices
5F, Sandhill Plaza
2290 Zuchongzhi Road
Zhangjiang Hi-Tech Park
Pudong New District
Shanghai, China 201203
Tel: 86.21.2320.8000
Fax: 86.21.2320.8222
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
Ahead of What’s Possible is a trademark of Analog Devices.
TA14171-0-3/16
analog.com