Engineering 43
FETs-1
(Field Effect Transistors)
Bruce Mayer, PE
Registered Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Learning Goals
 Understand the Basic Physics of
MOSFET Operation
 Describe the Regions of Operation for a
MOSFET Device
 Use the Graphical LOAD-LINE method
to analyze the operation of basic
MOSFET Amplifiers
 Determine the LARGE-SIGNAL BiasPoint (Q-Point) for MOSFET circuits
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Learning Goals
 Use SMALL-SIGNAL models to analyze
various FET Amplifiers
 Calculate Performance Metrics for
various FET Amplifiers
 Apply FETs to the
Design and
Construction of
CMOS Logic
Gates
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Transistor  What is it?
 Transistor is a contraction
for “Transfer Resistor”
 These devices have
THREE connections:
• Input
• Output
• Control
 The transistor’s Fluidic-Analog is a
Metering (Needle) Valve (a Faucet)
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
The concept of
voltage-controlled resistance
 An independent Voltage Applied to the
Control connection (the “Gate) regulates
the flow
Drain (or Source)
of Current
Thru
the device
Gate
Source (or Drain)
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Flavors of FETS
 Junction Field
Effect Transistor
→ JFET
• A Normally ON
transistor
 Reverse Biasing
two PN Junctions
will “Pinch Off” a
Conducting Channel
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Flavors of FETS
 Depletion Mode
MOSFET
• Another Normally
ON transistor
 Applying a Gate Voltage Drives Carriers
OUT of the conducting Channel to turn
off the transistor
• No direct Gate↔Channel Connection
– An Isulated Gate Field Effect Transistor
(IGFET)
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Flavors of FETS
 Enhancement
Mode MOSFET
• Normally OFF
transistor
• Another IGFET
 Applying a Gate Voltage Attracts &
Creates carriers to FORM a conducting
Channel to turn ON the transistor
 These Make Great Switches
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
MOSFET  What does that mean?
 M → Metal
 O → Oxide
 S → Silicon
 F → Field
 E → Effect
 T → Transistor
• Short for “Transfer Resistor”
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Enhancement Mode - IGFET
 Insulated Gate Field
Effect Transistors
are Normally-Off
devices
 Applying a Positive
Voltage to the Gate
will attract e− to the
Channel
 Back-to-Back PN
Jcns Between
“source” & “drain”
 IGFETs are Great
Switches
Engineering-43: Engineering Circuit Analysis
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• This will eventually
“invert” a thin region
below the gate to
N-type, creating a
conducting channel
between S & D
• Used in almost all
digital IC’s
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
MOSFET Nomenclature & Dims
 We will consider only Enhancement FETs
n+ ≡ Heavily
Doped n-Type
Engineering-43: Engineering Circuit Analysis
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An n-Channel (nFET)
enhancement mode FET
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
MOSFET: Current & Speed
 In General the
performance of
an Enhancement
Mode MOSFET
• Current Carrying
Capacity Increases with Increasing Width, W
• On/Off Switching Speed Increases with
Decreasing Gate Length, L
– As of 2011 the minimum (best) value
for L was about 22 nm
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
MOSFET On/Off Operation
Step 1: Apply Gate Voltage
SiO2 Insulator (Glass)
Gate
Source
Drain
5 volts
holes
N
N
electrons
P
electrons to be
transmitted
Step 2: Excess electrons surface
in channel, holes are repelled.
Engineering-43: Engineering Circuit Analysis
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Step 3: Channel becomes
saturated with electrons.
Electrons in source are able to
flow across channel to Drain.
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
nMOSFET Circuit Symbol
 n-Channel MOSFET
• electrons move from Source→Drain to
produce the Drain Current
 PN Junction forms between Substrate
and Channel when FET is “ON”
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
MOSFET Operation: CutOff
 As seen in previous
diagrams,
unpowered
MOSFETS have two
OPOSING PN
junctions
• Channel→Source
• Channel→Drain
 With NO Potential
applied to the gate
No current can flow
Engineering-43: Engineering Circuit Analysis
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 From the Previous
slide the Minimum
Gate Voltage required
for current-flow is
called the “Threshold”
Voltage, Vto or Vth
 A MOSFET with
VGS < Vth is “CutOff”
• i.e.; The MOSFET is
Off, and the Drain
Current, iD = 0
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
MOSFET Circuit in CutOff
 The Diagram at
Right shows an
nMOSFET in CutOff
 For vGS<Vto the PN
Jcn between the
Drain & Body is
Reversed Biased by
vDS and NO Current
flows
• Vto is typically 0.5-5
Volts
Engineering-43: Engineering Circuit Analysis
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 Mathematically this
is simple; in CutOff,
the Drain Current
iD  0 for vGS  Vto
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Power MOSFET Data Sheet
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
CutOff Summarized
 VGS < Vto → No Drain Current Flows
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
MOSFET IN Triode (Ohmic) Region
 In this case the nMOSFET Voltage
conditions: vDS  vGS  Vto  and vGS  Vto
 Electrons are ATTRACTED to the
Positive-Gate and a thin Conducting
Channel Forms
 In this Region the
Drain Current depends
on BOTH vDS and vGS
• Fluid Analogy → needle valve
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
nMOSFET in Triode Operation
 When vGS > Vto a conducting channel
forms below the gate
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Triode Operation
 When vGS > Vto a conducting channel
forms below the gate.
• That is the “type” of the silicon is
INVERTED from p-Type to n-Type
– Thus this conducting Channel is often called an
“Inversion Layer”
 The greater vGS The more the
conducting the channel becomes
 The Channel resistance is a fcn of vGS
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Triode Operation
vDS  vGS  Vto  and vGS  Vto
 In the Triode
Region, iD increases
for
• Increasing vGS
• Increasing vDS
 Thus current thru
the device depends
on the voltage at
ALL three
connections as long
as vDS < (vGS − Vto)
Engineering-43: Engineering Circuit Analysis
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• The ThreeConnection
dependency is why
this region is
called TRIODE
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Triode Operation v
DS
 vGS  Vto  and vGS  Vto
 In Triode Operation,
the iD curve is a
concave-down
Parabola given by

2
iD  K 2vGS  Vto vDS  vDS
• Where
W
K 
L
 KP

 2
 The Device
Transconductance
Parameter, KP,
Depends on the
Engineering-43: Engineering Circuit Analysis
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
Construction of the FET
• KP for nFETs is
typically
10-100 µA/V2
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
PinchOff
 In order to form a
complete channel,
every point, x, along
the channel must
have a voltage
difference greater
than Vto
 That is, need
vGS  vchan x   Vto
 The greater this qty,
the thicker the
conducting Layer
Engineering-43: Engineering Circuit Analysis
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x
 Now as vDS is increased
eventually at x = L
where vchan = vDS
vGS  vchan L   Vto
 The Channel Thickness
goes to ZERO. This is
called PINCH-OFF
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
PinchOff Illustrated
 The layer is
THICKEST at the
Source and ZERO
at the Drain when
vGS  vchan L   Vto
or
vGS  vDS  Vto
 At this Point the
channel is Very
Thick at the SourceEnd, and Zero-Thick
at the Drain End →
Pinched Off
at Drain
 Thus Have PinchOff
when
vDS  Vto  vGS
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
TriOde Region Summarized
 vDS ≤ (vGS − Vto) → iD = f(vDS , VGS)
Start of
TriOde →
Channel
Formation
Finish of
TriOde →
Drain
PinchOff
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
PinchOff  iD Saturation
 As vDS increases the
“PinchOff Point”,
xpop, Moves
BACKWARDS
towards the Source
 Once the channel
Pinches Off, the
drain current, iD, NO
Longer increases
with increasing vDS
Engineering-43: Engineering Circuit Analysis
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 In other words, for a
given vGS, the
Current “Saturates”
(stays constant)
After PinchOff as
shown below
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
nMOSFET complete vi Curve
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
MOSFET Operation Summary
1. Cut-Off Region – In this
region the gate voltage is less
than the Threshold voltage Vto
and therefore very little
current flows.
2. Triode Region – In this mode
the device is operating below
pinch-off and is effectively a
variable resistor.
3. Saturation Region – This is
the main operating region for
the device. The drain voltage
has to be greater than the
gate voltage minus the
Threshold voltage.
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Operation in Saturation
 Notice that in SAT iD
varies with vGS
iD  K vGS  Vto 
2
• Note that vDS does
NOT appear in this
Equation
• vDS (on vi curve)
does NOT affect iD
after
Channel-PinchOff
Engineering-43: Engineering Circuit Analysis
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• In SAT a MOSFET is true
3-terminal device; current
depends ONLY on the
CONTROL Signal, vGS
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Saturation Summarized
 vDS ≥ (vGS − Vto) → iD ≠ f(vDS)
PinchOff
Moved
BACK
from Drain
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Triode↔Saturation Boundary
 At the boundary
Line the nMOSFET
just Barely Pinches
Off at the Drain
end thus: vGD  Vto
Boundary Line
 By KVL vGD  vGS  vDS
 Substituting Find
vGD  vGS  vDS  Vto
 Or at the Boundary
vGS  vDS  Vto
Engineering-43: Engineering Circuit Analysis
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 Sub for vGS into iD,sat
Eqn
iD  K vGS   Vto 
2
iD  K vDS  Vto   Vto 
2
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
nFET KVL  𝒗𝑮𝑫 = 𝒗𝑮𝑺 − 𝒗𝑫𝑺
or vGD  vGS  vDS
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Triode↔Saturation Boundary
 Then then iD along
the Boundary
iD  Kv DS2
 The Boundary is
described by a
Concave-UP
Parabola that
passes thru the
origin
Engineering-43: Engineering Circuit Analysis
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Boundary Line
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Example 12.1  make vi Plot
 Use Parameters from Example 12.1 to plot
in MATLAB the vi Curve for an nMOSET
 The Parameters
• W = 160 µm
• L = 2 µm (pretty large)
• KP = 50 µA/V2
• Vto = 2V
 Plot has multiple operating regions
→ must concatenate
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
The completed Plot
nMOSFET vi Curve - Ex 12.1
35
vGS=6V
30
iD (mA)
25
20
vGS=5V
15
10
vGS=4V
5
vGS=3V
VGS<Vto
0
0
1
2
Engineering-43: Engineering Circuit Analysis
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3
4
5
6
vDS (Volts)
7
8
9
10
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
% Bruce Mayer, PE
% ENGR43 * 14Jan12
% file = nMOSFET_Plot_ex12_1_1201.m
W = 160; % µm
L = 2; % µm
KP = 50; % µA/sq-V
Vto = 2' % V
%
% calc Parameter K
K = (W/L)*KP/2; % µA/sqV)
%
% set vGS values that exceed CutOff at 2V
vGS = [3, 4, 5, 6];
%
% calc boundary Triode/Sat boundary by finding iD at the START
of sat
% region
iDsat_uA = K*(vGS-Vto).^2; % in µA
iDsat_mA = iDsat_uA/1000
%
% show cutoff line
vDSco = linspace(0,10, 200);
iDco = zeros(200);
% DeBug Command => plot(vDSco, iDco, 'LineWidth', 3)
%
% Calc iD in Triode Region for vGS>Vto (Pinched off at Drain)
%* use eqn (12.6) in text
vDSsat = sqrt(iDsat_uA/K) % must take care with units
%
plot(vDSsat,iDsat_mA, '--*', 'LineWidth', 3), grid,
xlabel('vDSsat'), ylabel('iDsat')
disp('showing Triode-Sat Boundary - Hit any key to continue')
pause
%
Engineering-43: Engineering Circuit Analysis
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MATLAB
Code-1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
% then iD in triode region
vDSt1 = linspace(0, vDSsat(1)); % V
vDSt2 = linspace(0, vDSsat(2))
vDSt3 = linspace(0, vDSsat(3))
vDSt4 = linspace(0, vDSsat(4))
iDt1_mA = K*(2*(vGS(1)-Vto)*vDSt1-vDSt1.^2)/1000; % mA
iDt2_mA = K*(2*(vGS(2)-Vto)*vDSt2-vDSt2.^2)/1000; % mA
iDt3_mA = K*(2*(vGS(3)-Vto)*vDSt3-vDSt3.^2)/1000; % mA
iDt4_mA = K*(2*(vGS(4)-Vto)*vDSt4-vDSt4.^2)/1000; % mA
%
%
% DeBug Command =>plot(vDSt1,iDt1_mA, vDSt4,iDt4_mA)
%
% use TwoPoint Plots in Sat
iDsat1 =[iDsat_mA(1),iDsat_mA(1)]
iDsat2 =[iDsat_mA(2),iDsat_mA(2)]
iDsat3 =[iDsat_mA(3),iDsat_mA(3)]
iDsat4 =[iDsat_mA(4),iDsat_mA(4)]
vDSsat1 = [vDSsat(1), 10]
vDSsat2 = [vDSsat(2), 10]
vDSsat3 = [vDSsat(3), 10]
vDSsat4 = [vDSsat(4), 10]
%
Engineering-43: Engineering Circuit Analysis
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MATLAB
Code-2
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
%
% Now Concatenate to ocver Triode & Saturation Regions
iD1 = [iDt1_mA,iDsat1]
vDS1 = [vDSt1, vDSsat1]
iD2 = [iDt2_mA,iDsat2]
vDS2 = [vDSt2, vDSsat2]
iD3 = [iDt3_mA,iDsat3]
vDS3 = [vDSt3, vDSsat3]
iD4 = [iDt4_mA,iDsat4]
vDS4 = [vDSt4, vDSsat4]
%
%
% Finally Make Plot
plot(vDSco, iDco,'b', vDS1, iD1,'c', vDS2, iD2,'g', vDS3,
iD3,'m', vDS4, iD4,'r', 'LineWidth', 3),...
grid, xlabel('vDS (Volts)'), ylabel('iD (mA)'),
title('nMOSFET vi Curve - Ex 12.1'),...
gtext('VGS<Vto'), gtext('vGS=3V'), gtext('vGS=4V'),
gtext('vGS=5V'), gtext('vGS=6V')
Engineering-43: Engineering Circuit Analysis
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MATLAB
Code-3
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
pMOSFET
pMOSFET
 A “pMOS” FET is the
Circuit
“Complement” to the
Symbol
nMOS version.
 The channel is normally n-Type and a
hole-populated conducting Channel is
formed by applying a NEGATIVE vGS
 Basically the pMOS version looks like
the nMOS FET with
voltage-polarities
inverted
Engineering-43: Engineering Circuit Analysis
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Channel
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
p & n MOSFET Comparison
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
All Done for Today
3 & 4
Connection
nFET
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Engineering 43
Appendix
Diode vi Curves
Bruce Mayer, PE
Registered Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
W
K 
L
 KP

 2
KP  nCox
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12a_FETs-1.pptx