A Novel Ternary Switching Element Using CMOS Recharge Semi
Floating-Gate Devices
Henning Gundersen, René Jensen and Yngvar Berg
University of Oslo, Department of Informatics,
P.O.Box 1080, Blindern, NO-0316 Oslo, Norway. Fax: +47 22 85 24 01.
E-mail: henningg@ifi.uio.no
Abstract
In this paper we present a novel voltage mode noninverting CMOS Semi Floating-Gate(SFG) Ternary
Switching Element. The design is applicable for reconstructing or refreshing ternary logic signals. The
switching points are tuned using capacitive division.
A preliminary simulation results from Cadence Spectre
with AMS 0.35µmprocess parameters c35b4 is included.
1
Introduction
Multiple-valued logic has in the last few decades
been proposed as a possible alternative to binary logic.
Whereas binary logic is limited to only two states,
”true” and ”false”, multiple-valued logic (MVL)
replaces these with finitely or infinitely numbers of
values.
The history of Multi-valued Logic as a separate object began in the early 1920 by a polish philosopher
Lukasiewicz [1]. His intention was to introduce a third
additional truth-value for ”possible”. The outcome of
this investigation is known as the Lukasiewicz systems.
Parallel to the approach of Lukasiewicz, the American
mathematician Emil Post [2], introduced the idea of
an additional truth degrees, and used this approach to
solve the problems of the represent ability of functions,
also known as the Post Algebra.
1.1 Ternary logic
Ternary logic has three logic states, ”0”,”1” and
”2”, and the optimum radix of a fractional number is
found to be the natural logarithm (e). Ternary logic
uses number representation with radix=3, compared
to binary logic witch uses radix=2, hence the most
economical integer radix which is the closest to the
natural logarithm e, is the number 3 [3]. This special
property of base 3, inspired the early computer
designers to build a ternary computer.
The first approach to build a MV-computer with
ternary architecture was in the early 50th. in the USA.
The earliest published discussion appears in the 1950
book High-Speed Computing Devices, a survey of computer technologies compiler on the behalf of the U.S
Navy, by the staff of Engineering Research Associates
[4]. But the first working ternary computer was built
in Russia at the Moscow State University in 1958. The
computer was design by Nikolai P. Brusentow and his
colleagues and they named it Setun, for a river that
flows near the university campus [5]. From 1958 to
1965 some 50 machines where built.
1.2 Floating Gate (FG) Transistors
The multiple-input FG transistors can be used to
simplify the design of multiple-valued logic [6]. The
initial charge on the floating-gates may vary significantly and therefore impose a very severe inaccuracy
unless we apply some form of initialization. Some work
on floating-gate reset strategies have been presented by
Kotami et.al. [7], and by Berg et.al. [8].
1.3 Recharge Semi-Floating Gate (RSFG) Logic
As mentioned earlier FG circuits need to be initialized, either once initially or frequently. The once and
for all initialization is synonymous with programming.
By recharging the SFG frequently we avoid problems
with any leakage currents and random or undesired
disturbance of the floating-gate charges. The reset
or recharge scheme can be used to overcome some
problems associated with floating-gate circuit design
Clk
Pe
Ci
Vin
Ci
Clk
Vout Vin
Vsfg
Vout
Vsfg
Ne
Figure 1. A SFG recharge binary inverter. The
Clk pulse is given by the recharge frequency which
is twice the frequency of the input signal.
[8]. The recharge condition is different than the reset
in clocked-Neuron-MOS logic proposed by Kotami
et.al. [7].
When reseting or recharging a gate the inputs are
recharged simultaneously and not set to a reference
voltage, normally Vss or Vdd . While recharging the
gates are short-circuited and the output and the
semi-floating-gate of a logic gate is forced to Vdd /2 .
taneously. The recharge current which will pull the
SFG down towards Vdd /2 , is larger than the equilibrium current (Ibec ). We define the recharge rise rime
tr as the time required to recharge the output from 0
to Vdd /2 (and the SFG simultaneously). If the input
signal is initially 0 the SFG voltage is (Vdd /2 ) x (1
- ki ) and the output is 1 . The recharge current will
be reduced compared to the former case due to body
effect of the n-channel recharge transistor. In order to
achieve a correct recharge to the equilibrium state in
a chain of gates we need to recharge all gates, hence
all inputs simultaneously, In addition we need to develop a synchronization scheme for the recharge. We
define the recharge fall rime tf , as the time required
to recharge the output from 1 to Vdd /2 . The recharge
frequency is twice the frequency of the input signal.
2
The Recharge Semi Floating-Gate
(RSFG) Ternary Switching Element
___
Clk
Clk
C
2C
Clk
The recharge scheme is similar to biasing of
single-ended auto-zeroing comparators which have
been used in high-speed flash AD converters. The
main purpose of the recharge scheme is to initialize
or recharge the semi-floating-gates to an equilibrium
state which can be utilized to yield fast binary and
multiple-valued signal processing. In addition we may
reduce the effect of mismatches, especially transistor
mismatches, and power supply noise. The recharge
scheme provides a simple, fast and accurate recharge
to the equilibrium state for all gates regardless of
logical depth. We use the term Recharge Logic (RL)
or Recharge Semi-Floating- Gate Logic (RSFGL) for
the circuits presented in this paper [9]. The SFG
circuits are recharged to the initial equilibrium state.
namely Vdd /2 .
A simple binary single input gate, namely an inverter is shown in figure 1. By equalizing the βs we
obtain an equilibrium state when the recharge signal
is 1. The output and gate are driven towards Vdd/2.
When the recharge signal is 1 we have to distinct cases.
Assume that the input signal is initially 1 (Vdd ), the
SFG voltage can he expressed as (Vdd /2 ) x ( 1 + ki ),
where ki = Ci /Ct and Ct is the total capacitance seen
by the SFG, and the output is equal to 0. The output and the SFG will be forced towards Vdd /2 simul-
DLC
___
Clk
AZC
Clk
C
Cf
Vin
Vout
C
MVL Inverter
___
Clk
Clk
AZC
Clk
2C
C
DLC
Clk
AZC
Figure 2. Schematic diagram for ternary element.
The design comprise three Semi Floating-Gate
AutoZero blocks (AZC), two SFG Down Literal
Circuits (DLC) and one analog MVL SFG inverter at the output.
The schematic diagram in figure 2 shows a novel
voltage mode ternary switching element. The design
uses three AutoZero circuits, two Semi-Floating Gate
(SFG) threshold elements also called a MVL SFG
Down Literal Circuit, and a MVL SFG inverter [10].
This application is suitable to refresh or reconstruct
ternary voltage mode signals.
Figure 3 shows the output signal of the circuit
versus the input signal. The dotted line is the input
2
2
1.8
1.8
1.6
1.6
1.4
1.4
1.2
1.2
Voltage (V)
Voltage (V)
Threshold 1
Threshold 2
1
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
Vin
Vout
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Time (s)
1.6
6
x 10
Figure 3. Simulation over 16 clock periods showing output versus input voltage.
signal. As we notice the output signal is converging
to three logic levels, 0.2 Volt, 1 Volt and 1.8 Volt.
It is also a valid MVL recharge signal. As we notice, in the recharge periods, the output is set to Vdd /2 .
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Vin (s)
Figure 4. Shows the thresholds for internal
switching elements used for building the ternary
element. The thresholds or switching points are
determined by the capacitive division factors associated with each of the two switching elements.
from the AutoZero Circuit, has weight C (C=7.5f F ).
By changing this factor we can fine tune the three logic
levels.
2.1 The SFG AutoZero Circuit (AZC)
2.3 The MVL SFG Inverter
An AutoZero circuit can been seen as a signal converter which either convert a binary , static (Vdd , Vss )
or MVL signal to a valid recharge signal. A SFG
Recharge AutoZero circuit is shown in figure 2. It sets
the input signal to Vdd /2 in the recharge periods and
in the precharge periods the input signal is connected
to the output thru the pass gate transistors. While
recharging the output is driven to recharge state defined by V out = Vdd /2. Note that the recharge frequency is twice the frequency of the input signal.
2.2 The SFG Down Literal Circuit (DLC)
The threshold or the switching point is set by the
MVL Recharge SFG DLC circuit [10] as shown in figure 4. A DLC can be seen as a digital inverter with
two inputs. The dotted line in the figure is the input
signal. The lower threshold or switching point is set by
the output of the AutoZero Circuit(AZC) connected
to the Vss (Gnd), and the upper switching point is set
by the AZC connected to Vdd . The figure shows the
internal switching nodes on the output of the DLC circuit. The switch point is determined by the capacitive
division factor. ki 1 , Vin has weight 2C and VT hreshold
1k
i
P
= Ci / CIn
The circuit shown at the output of figure 2, is called
a MVL recharge SFG Inverter [10]. As we notice it has
two inputs with the same weight (C). The MVL SFG
Inverter will convert the output signal to a valid MVL
recharge signal. The transfer characteristic of a MVL
inverter is given by:
Vout = Vdd − Vin
(1)
Where Vin and Vout are the voltages on the input and
output terminals, Vdd is the supply voltage.
The gain of MVL SFG inverter is determined by the capacitive division
factor ki . The feedback capacitor Cf
P
should be
Cin , hence 2C to make sure EQ 1 is true,
however Cf has to be slightly smaller than 2C due to
the output conductance and the parasitic capacitance,
Cgd .
2.4 The SFG Ternary Switching Element
If we analyze the complete circuit in figure 2, we
find three stable regions given by dVout /dVin , this is
shown in figure 5. These three regions are logic level
’0’ (0 − 0.35V ), ’1’ (0.8 − 1.2V ) and ’2’ (1.65 − 2.0V ).
0.035
This calculation confirms the noise margins of the
ternary circuit. We can see three logic levels ’0’, ’1’
and ’2’ respectively 0.2V , 1V and 1.8V .
0.03
0.025
The switching region or noise is indicated using
gray color, this is where the logic levels are undefined.
As we can see we got better noise margins for the
logic level ’1’, but this can be tuned by changing the
value of the capacitors on the input of the DLC circuit.
diff(Vout) (V)
0.02
0.015
0.01
0.005
0
2
−0.005
Input margins
Output margins
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
’2’
1.8
Vin (V)
1.6
1.4
Margins (V)
Figure 5. A sweep of the derivative of the output
signal Vout . Illustrates three stable regions around
the three voltage levels 0.2V, 1V and 1.8V.
1.2
’1’
1
0.8
0.6
0.4
This gives us, if the input is between 0 − 0.35V it will
converge to logic level ’0’, if the input is 0.8 − 1.2V
the output will be set to logic level ’1’ and if the input
is in the region 1.65 − 2.0V the output will be set to
logic level ’2’. This is also shown in the figure 6 we can
see how the output converge to the three logic levels.
’0’
0.2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Vin (s)
Figure 7. Matlab calculations demonstrating the
noise-margin diagram of the ternary element.
The analysis is based on circuit simulations in
Cadence Spectre. The three logical output values
0, 1, 2 is found as output voltages 0.2, 1, 1.8V
respectively. The noise or switching region is indicated using gray color.
2
1.8
1.6
1.4
Vout (V)
1.2
Figure 8 shows the zero crossing point of the three
logic levels, here is Vin − Vout calculated using Matlab.
The zero crossing point, which gives the three logic
levels, is 0.18V , 1.03V and 1.85V this is possible to
fine tune by changing the capacitive division factor ki
in the DLC circuit.
1
0.8
0.6
0.4
Vin
Vout
0.2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Vin (V)
Figure 6. A sweep of the output signal Vout versus
the input signal Vin . This illustrates how valid input voltage are moved towards the output voltages
0.2, 1, 1.8V.
A graphical illustrations of the noise margins are
calculated in figure 7. The calculations of the noise
margins of the simulated values given by the Cadence
Spectre simulation, are obtained by using Matlab.
3
Conclusions
In this paper we have presented a novel noninverting voltage mode CMOS Ternary Switching Element. This element have shown good noise margins,
and it is easy to fine tune, and it is well suitable to
use of refreshing ternary signals in memory applications and also to reconstruct internal ternary logic signals. All simulation results are obtained from Cadence
Spectre AMS 0.35 µmCMOS device parameters with
10MHz precharge clock frequency and 2V power supply. This application can easily be fabricated using a
conventional CMOS process.
0.25
[9] Y. Berg, S. Aunet, Ø. Næss, O. Mirmotahari, and
M. Høvin, “Binary to multiple-valued recharge converter for multiple-valued cmos logic,” ECCTD’03Euopean Conference on Circuit Theory and Design,Cracow, Poland, pp. 349–352, 2003.
0.2
0.15
0.1
Delta (V)
0.05
[10] H. Gundersen and Y. Berg, “Max and min functions
using multiple-valued recharge semi-floating gate circuits,” Proceedings of the 2004 IEEE International
Symposium on Circuits And Systems in Vancouver
(ISCAS2004), 2004.
0
−0.05
−0.1
−0.15
−0.2
−0.25
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Vin (s)
Figure 8. The delta difference between output and
input voltage (Vout − Vin ). The results were obtained from simulation of the schematic in Cadence Spectre using 10MHz precharge clock.
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