Performance Limits of RF Power CMOS
by
Usha Gogineni
B.Tech. National Institute of Technology, Warangal (1996)
M.S. Auburn University (1999)
Submitted to the Department of
Electrical Engineering and Computer Science
in Partial Fulfillment
of the Requirements for the Degree of
Doctor of Philosophy
ARCHiVES
MASSACHUSETTS INSTITUTE
OF TECHVOLO. N
MAR 10 2011
LIBRARIES
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
February 2011
© Massachusetts Institute of Technology 2011. All rights reserved.
Author
Department of Electrical Engineering and Computer Science
October 28, 2010
Certified by
Jesus A. del Alamo
Professor of Electrical Engineering
Thesis Supervisor
Accepted by.
Terry P. Orlando
Chairman, Department Committee on Graduate Thesis
Performance Limits of RF Power CMOS
by
Usha Gogineni
Submitted to the Department of Electrical Engineering and Computer Science in
Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in
Electrical Engineering
Abstract
Wireless and mobile communication systems have become ubiquitous in our daily life. The need for higher
bandwidth and thus higher speed and data rates in wireless communications has prompted the exploration of
millimeter-wave frequencies. Some of the applications in this regime include high-speed wireless local area
networks and high data rate personal area networks at 60 GHz, automotive collision avoidance radar at 77 GHz and
millimeter-wave imaging at 94 GHz. Most of these applications are cost sensitive and require high levels of
integration to reduce system size.
The tremendous improvement in the frequency response of state-of-the-art deeply scaled CMOS technologies
has made them an ideal candidate for millimeter-wave applications. A few research groups have already
demonstrated single chip CMOS radios at 60 GHz. However, the design of power amplifiers in CMOS still remains
a significant challenge because of the low breakdown voltage of deep submicron CMOS technologies. Power levels
from 60 GHz power amplifiers have been limited to around 15 dBm with power-added efficiencies in the 10-20%
range, despite the use of multiple gain stages and power combining techniques.
In this work, we have studied the RF power potential of commercial 65 nm and 45 nm CMOS technologies. We
have mapped the frequency, power and efficiency limitations of these technologies and identified the physical
mechanisms responsible for these limitations. We also present a simple analytical model that allows circuit
designers to estimate the maximum power obtainable from their designs for a given efficiency. The model uses only
the DC bias point and on-resistance of the device as inputs and contains no adjustable parameters.
We have demonstrated a record output power density of 210 mW/mm and power-added efficiency in excess of
75% at VDs = 1.1 V and f = 2 GHz on 45 nm CMOS devices. This record power performance was made possible
through careful device layout for minimized parasitic resistances and capacitances. Total output power approaching
70 mW was measured on 45 nm CMOS devices by increasing the device width to 640 gm. However, we find that
the output power scales non-ideally with device width because of an increase in normalized on-resistance in the
wide devices. PAE also decreases with increasing device width because of degradation in f. in the wide devices.
Additionally PAE decreases as the measurement frequency increases, though the output power remains constant
with increasing frequency. Small-signal equivalent circuit extractions on these devices suggest that the main reason
for the degradation in the normalized output power and PAE with increasing device width is the non-ideal scaling of
parasitic gate and drain resistances in the wide devices.
Thesis Supervisor: Jesus A. del Alamo
Title: Donner Professor
4
Acknowledgements
This work would not have been possible without the support and guidance of numerous
people. First, I would like to thank my thesis supervisor, Prof. Jesd's del Alamo. It was a privilege
to work with him and learn from him over the past few years. He is a great teacher and an
exceptional researcher. I am sure that the knowledge and skills I learnt from him will serve me
well in my future career.
I would also like to thank my thesis readers, Prof. Dimitri Antoniadis and Prof. Joel Dawson
for their valuable guidance and suggestions that helped me improve the work presented in this
thesis.
I should thank my funding sponsors: MIT Presidential fellowship program, Intel PhD
fellowship program and Semiconductor Research Corporation. The hardware for this thesis was
generously provided by IBM Microelectronics. I need to thank David Greenberg, Alberto Valdes
Garcia and Christopher Putnam for their help and guidance in designing test structures,
coordinating their inclusion on the IBM test vehicles, and helping me with all the necessary
approvals from IBM. I have spent two summers working at IBM in Burlington VT, and Fishkill
NY on projects related to this thesis. Among the many great people I met and worked with
during these summers, I should specially thank Hongmei Li for her help with understanding
CMOS device modeling and small-signal extractions and Susan Sweeney for her expertise on Sparameter and Power measurements.
My stay at MIT has been most pleasant mainly due to the friends and colleagues I met here. I
would like to thank all the former and current members of the del Alamo research group: Jorg
Scholvin, Joyce Wu, Niamh Waldron, Anita Villanueva, Yoshihiro Ikura, Dae-Hyun Kim, Sefa
Demirtas, Jungwoo Joh, Ling Xia, Donghyun Jin, Tae Woo Kim, Jianqiang Lin, Alex Guo, Xin
Zhao and Elizabeth Kubicki. Special thanks are due to Jungwoo Joh for the many long
discussions on RF power devices and amplifiers that have directly contributed to the RF power
model in this thesis.
Finally, I would like to thank my parents, Dr. Ravindranath Tagore and Ramalakshmi and my
sisters Sirisha, and Manisha for their support and motivation. Thanks mom and dad for
encouraging me to pursue my dreams and pulling me through the hardest patches. To you, I
dedicate this thesis.
6
Contents
1. Introduction
21
1.1
RF and Millimeter-wave Applications
21
1.2
Advantages and Challenges in using CMOS
23
1.3
Literature survey of 60 GHz power amplifiers
25
1.4
CMOS technologies for RF power applications
27
1.5
Thesis Goals
29
2. Experimental
31
2.1
Technology Description
31
2.2
Device Layout
33
2.2.1 65 nm Technologies:
33
2.2.2 45 nm Technology:
36
2.3
DC and S-Parameter Characterization
38
2.4
RF Power Characterization
41
2.5
Summary
45
3. RF Power Performance
47
3.1
65 nm Low Power Technology
3.1.1
1.2 V Standard Device
3.1.2 2.5 V 1/0 Device
47
47
52
3.2
65 nm High Performance Technology
54
3.3
45 nm Low Power Technology
60
3.3.1 Old Test Structures
60
3.3.2 New Test Structures
66
3.4
Comparison among different technologies
73
3.5
Comparison with literature
80
3.6
Summary
82
4. Model for RF Power
85
4.1
Model Description
86
4.2
Comparison of Model with Measurements
95
4.3
Discussion
102
4.4
Summary
104
5. Small-signal Circuit Extractions
105
5.1
Small-signal Circuit Extraction Methodology
105
5.2
Width Dependence of Equivalent Circuit Parameters
111
5.3
fT, fmax Sensitivity to Equivalent Circuit Parameters
113
5.4
Analytical Expressions for fT and fmax
115
5.5
Summary
118
6. Conclusions and Suggestions for Further Work
119
Appendix A. Device Library
125
A. 1. 65 nm Test Structures
125
A.2. 45 nm "Old" Test Structures
127
A.3. 45 nm "New" Test Structures
129
Bibliography
131
10
List of Figures
Fig. 1. 1: Illustration of some of the applications in the millimeter-wave regime. (a) High-speed wireless local area
network, (b) High data rate wireless personal area network, (c) Automatic cruise control and collision avoidance
radar in automobiles, (d) Imaging for detection of hidden weapons for airport security applications. ..................
22
Fig. 1. 2: Output power, normalized to device width and supply voltage, as a function of device width. All
previously published device data is shown in this figure.
.........................................
27
Fig. 1.3: Output power as a function of measurement frequency. All previously published device data is shown in
this figu re .....................................................................................................................................................................
28
Fig. 2.1: Illustration of a unit cell in 65 nm devices containing 24 fingers of 2 pm finger width. Gate is contacted on
both sides of the device and is wired out at M3 level. Source and drain fingers are wired out at M4 level...........34
Fig. 2.2: Schematic of a W=8x24x2 Rm device showing 8 unit cells connected in parallel. The diffusion area of the
unit cells is shown as the black outline. Gate, Source and Drain are wired out to the last metal level (LB) before
connecting them to the RF pads...................................................................................................................................35
Fig 2.3 Layout of a unit cell in 45 nm technology containing 20 fingers of 2 gm finger width. Gate is connected on
both sides of the device to reduce gate resistance. Gate, source and drain are wired out on alternate metal levels to
reduce coupling capacitance between terminals .....................................................................................................
36
Fig 2.4 Schematic of a W=4x20x2 pm device in 45 nm technology containing 4 unit cells connected in parallel. A
ground plane on M1 and M2 levels is placed under the gate and drain signal lines to reduce substrate coupling.
Source and substrate are shorted together and connected to the M1+M2 ground plane........................................
Fig. 2.5: Output characteristics (VGS
and VDS
=
=
0.4 V to 1.1 V in steps of 0.1 V) and transfer characteristics
(VDS
=
38
0.05 V
1.1 V ) on 45 nm devices (W = 80 [im ).......................................................................................................39
Fig 2.6 Smith chart showing the S-parameters on a 65 nm standard device (W=96 gm) measured from 0.5 GHz to 40
GHz at
VDD=1
V, ID=2 0 0 mA/mm. The blue solid lines show the S-parameters before de-embedding and the red
dashed lines show the de-embedded S-parameters .................................................................................................
40
Fig 2.7 Current gain and unilateral power gain as a function of frequency for a 96 gm wide device. Blue solid lines
show data before de-embedding, while red dashed lines show the data after open and short de-embedding. f1 and fma
improve w ith de-em bedding........................................................................................................................................4
1
Fig. 2.8 Schematic diagram of Maury Microwave Load pull system at MIT..........................................................42
Fig. 2.9 Sample RF power sweep at 2 GHz showing power gain, PAE and average drain current as a function of
output power................................................................................................................................................................44
Fig. 3.1. Output characteristics (VGS
=
0.2 V to 1.2 V in steps of 0.2 V) and transfer characteristics
(VDS
=
0.05 V
and VDS = 1.2 V) on the standard 65 nm LP device (W = 96 pm)...............................................................................48
Fig. 3.2: Typical power sweep showing PAE and gain as a function of output power on several 65 nm LP standard
devices. The figure also illustrates the maximum Pot, PAE and Put / W obtainable from this technology at VDs = 1.2
V and ID= 200 mA/mm - ... .................. --....
..
.. ---------...
--. ..............................................
48
Fig. 3.3: Output power and PAE as a function of DC bias current illustrating the trade-off between Pout and PAE. ..49
Fig. 3.4: Measured output power, at various DC bias currents, for 65 nm LP CMOS devices of different widths.....50
Fig. 3.5: Normalized output power as a function of device width, measured at various DC bias currents on 65 nm LP
1
CM O S devices.............................................................................................................................................................5
Fig. 3.6: Measured peak PAE, on 65 nm LP CMOS devices, versus device width at different DC bias currents.......51
Fig. 3.7: Typical power sweep showing PAE and gain as a function of output power on several 0.25 gm long I/O
devices in 65 nm LP CMOS technology. The maximum Pow, PAE, and Po,1, / W obtainable from this technology at
VDs =
2.5 V and ID = 200 mA/mm are noted on the figure.
..........................................................................
52
Fig. 3.8: RF power measured at 8 GHz as a function of device width for I/O devices designed in 65 nm LP CMOS
53
techn o lo gy . ..................................................................................................................................................................
Fig. 3.9: Peak PAE, measured at different bias currents, as a function of device width for I/O devices designed in 65
54
nm LP C M O S technology. ..........................................................................................................................................
Fig. 3.10. Output characteristics (VGS
VDs
=
0.2 V to 1 V in steps of 0.2 V) and transfer characteristics (VDs
= 1 V) on the standard 65 nm HP device (W = 96 pm)..
Fig. 3.11: De-embedded
fT
and f.,
0.05 V and
=
...............................................................................
55
measured on 65 nm HP CMOS devices, are shown as a function of device
w id th ............................................................................................................................................................................
55
Fig. 3.12: Typical power sweep on several 65 nm HP devices. The maximum Pow, PAE and Pu, / W are also shown
in th e fig ure ..................................................................................................................................................................
56
Fig. 3.13: Output power, measured at different frequencies, as a function of device width, for 65 nm HP CMOS
devices. VDD =
IV
, ID= 25 mA /m m ............................................................................................................................
57
Fig. 3.14: PAE measured at different frequencies, as a function of device width for 65 nm HP CMOS devices. VDD
1V , ID=
25
mA /m m . ...................................................................................................................................................
58
Fig. 3.15: Output power, measured at different frequencies, as a function of device width, for 65 nm HP CMOS
devices. VDD
=
V,
ID= 200 m A/m m ..........................................................................................................................
59
Fig. 3.16: PAE measured at different frequencies, as a function of device width for 65 nm HP CMOS devices.
1V , ID= 200 m A/mm . . --------------........
Fig. 3.17: Output characteristics (VGS
and VDS
=
Fig. 3.18:
-
=
--...........................
---. . ----.......................................................................
59
0.4 V to 1.1 V in steps of 0.1 V) and transfer characteristics (VDs = 0.05 V
1.1 V) on the standard 45 nm device (W = 90 ptm).
fT
VDD =
..........................
...........
60
and fma as a function of drain current density for single and double gate contact structures in 45 nm
C M O S technology.......................................................................................................................................................6
1
Fig. 3.19: PAE and normalized output power as a function of measurement frequency for single gate and double
gate contact structures in 45 nm CMOS technology.
............................................
62
Fig. 3.20: De-embedded fmax as a function of unit finger width and number of fingers for all the test structures of the
"old test site".
WF =
1.5 pim was found to be the optimum finger width for the 45 nm CMOS technology. ......... 63
Fig. 3.21: Typical power sweep on several 45 nm CMOS devices, designed as part of the old test site. The maximum
Pt, PAE and Po,, / W obtained from this test site at f = 2 GHz,
VDD =
1.1 V and ID= 200 mA/mm are also shown in
th e fig u re......................................................................................................................................................................6
4
Fig. 3.22: Peak PAE, measured at different frequencies, versus total device width. For the figure on the left, device
width is increased by keeping
NF
constant at 60 and increasing
WF
from 0.5 jim to 5 jm. For the figure on the right,
device width is increased by keeping WF constant at 1.5 jm and increasing NF from 20 to 120..........................65
Fig. 3.23: Normalized output power, measured at different frequencies, versus total device width. For the figure on
the left, device width is increased by keeping NF constant at 60 and increasing WF from 0.5 gm to 5 jm. For the
figure on the right, device width is increased by keeping
WF
constant at 1.5 jim and increasing
NF
from 20 to 120. 65
Fig. 3.24: Output characteristics (VGs = 0.4 V to 1.1 V in steps of 0.1 V) and transfer characteristics (VDs = 0.05 V
and VDS
=
1.1 V ) on 45nm devices (W = 80 ptm)........................................................................................................67
Fig. 3.25: De-embedded
fT
and f,
as a function of device width for the new 45 nm test structures, measured at VDD
= 1.1 V and ID= 200 m A /mm ......................................................................................................................................
67
Fig. 3.26: Power sweep showing PAE and P0ut for devices with different widths. The figure also notes the maximum
PAE, Po
0 t and Pout /W obtained the new set of structures in 45 nm CMOS technology...............................................69
Fig. 3.27: Normalized output power as a function of device width for the two impedance matching conditions.
Optimizing for maximum power gives a higher P 111/W at a lower PAE.....................................................................70
Fig. 3.28: Peak PAE as a function of device width for the two impedance matching conditions. Optimizing for
maxim um PAE gives a higher PAE at a lower Pout IW .
.......................................................................................
70
Fig. 3.29: Normalized output power as a function of measurement frequency. Pout /W is relatively independent of
frequency for both impedance matching conditions ...............................................................................................
71
Fig. 3.30: Peak PAE as a function of measurement frequency. PAE decreases significantly with increasing
frequency for both impedance matching conditions ...............................................................................................
Fig. 3.31: PAE versus f/f.
71
for 45 nm CMOS devices of different widths and measured at various frequencies from
2 G H z to 18 G H z.........................................................................................................................................................72
Fig. 3.32: Output power versus device width for 65 nm low-power and 65 nm high-performance devices, measured
at
VDS = VDD,
ID = 50 mA/mm, and f = 8 GHz..........................
................
.................................
Fig. 3.33: PAE versus device width for 65 nm low-power and 65 nm high-performance devices, measured at
V DD, ID =
73
VDS =
50 mA/m m , and f = 8 G H z..........................................................................................................................74
Fig. 3.34:De-embedded f.
versus device width for 65 nm devices and old and new 45 nm device structures.........75
Fig. 3.35: Output power versus device width for 65 nm devices and old and new 45 nm device structures...........76
Fig. 3.36: Extracted normalized on-resistance as a function of device width for 65 nm devices and old and new 45
nm device structures....................................................................................................................................................77
Fig. 3.37: Output power versus on-resistance for 65 nm devices and 45 nm old and new test structures...............78
Fig. 3.38: Output power versus 1/ (RL+Rofl) illustrating the universal behavior of measured data for 65 nm and 45 nm
(old and new ) devices..................................................................................................................................................78
Fig. 3.39: PAE versus f/fma, illustrating universal behavior of measured data for 65 nm and 45 nm (old and new)
d ev ices.........................................................................................................................................................................7
9
Fig. 3.40: Normalized output power versus device width. The figure compares power data presented in this thesis to
the values reported in literature. ..................................................................................................................................
80
Fig. 3.41: Output power versus operating frequency. The figure compares power data presented in this thesis to the
values reported in literature.........................................................................................................................................8
Fig. 4.1: Circuit diagram of a reduced conduction angle power amplifier.
..............................
1
86
Fig. 4.2: Waveforms for input voltage and output current and voltage in the reduced conduction angle amplifier
show n in Fig . 4.1.........................................................................................................................................................88
Fig. 4.3: Illustration of difference between DC and AC load line for RL = 100 Q. The DC operating point is at VDQ
= 1.1 V, IDQ = 200 mA/mm. The AC operating point is at VDC
=
1.1 V,
IDC
Fig. 4.4: Modeled locus of drain efficiency versus output power. Put and
= 212 mA/mm. ...............
71D
............. 94
measurements at different RL are shown
as symbols in the figure and show good agreement with the model........................................................................96
Fig. 4.5: Modeled locus of output power versus load resistance. Output power measurements at different RL are
shown as symbols in the figure and show good agreement with the model.
...................................................
97
Fig. 4.6: Modeled locus of drain efficiency versus load resistance. Drain efficiency measured at different RL is
....... 98
shown as symbols in the figure and shows good agreement with the model..........................
Fig. 4.7: Drain Efficiency as a function of device width. The solid line represents 1D specified in model for
predicting maximum Pu1 and optimum RL. The symbols are the measured
1D
99
at 2 GHz. .....................................
Fig. 4.8: Output power as a function of device width. The solid line represents the maximum output power predicted
by the model. The symbols show the measured Pouk at 2 GHz...................................................................................100
Fig. 4.9: Average drain current as a function of device width. The solid line represents the average drain current
predicted by the model. The symbols show the measured IDC at 2 GHz. ..................................................................
101
Fig. 4.10: Load resistance needed to obtain maximum Pu,. Solid line is optimum R predicted by model. Symbols
are m easured data at 2 G H z.......................................................................................................................................102
Fig. 5.1: De-embedded
fT
and f.,
measured at VDs=1 V and at ID=1 0 0 mA/mm, as a function of total device width.
10 6
...................................................................................................................................................................................
Fig. 5.2: Small-signal equivalent circuit of a MOSFET including parasitic resistances and the substrate network..107
Fig. 5.3: Measured and Modeled s-parameters at
VDD=l
V, ID=100 mA/mm. Measured data is in symbols and the
109
m odel is the solid line. W =2x48 tm..........................................................................................................................
Fig. 5.4: Short circuit current gain and unilateral power gain as a function of frequency. W = 2x48
gtm, VDD =
110
= 100 m A/m m ............................................................................................................................................................
Fig. 5.5: Normalized intrinsic parameters (gm,
gds, Cgs, Cgd)
as a function of device width.
VDD =
1 V, ID
1 V,
m A/m m ......................................................................................................................................................................
ID = 100
111
Fig. 5.6: Normalized parasitic resistances vs. device width. Parasitic resistances are extracted from s-parameters
m easured at
VDD=1
V , ID=
10 0
mA/m m .....................................................................................................................
112
Fig. 5.7: Schematic layout of a 2 cell (W = 96 im) and 8 cell (W = 384 pm) device, showing the need for additional
wiring to connect the 8 cells in parallel. This leads to an increase in parasitic resistance as the device width is
in creased ....................................................................................................................................................................
112
Fig. 5.8: Sensitivity of f1 and fa to the various small-signal equivalent circuit parameters. The figure plots the
percentage decrease in fT and fm, for a 100% change in each of the parameters. W=96 ptm,
VDD=1
V.
m A mm.......................................................................................................................................................................1
ID=100
14
Fig. 5.9: Measured and calculated fT and fma as a function of device width. Measured data in solid symbols and lines
and calculated data in open symbols and dashed lines. .......................................................................................
117
List of Tables
Table 1.1: Comparison of state-of-the-art 60 GHz CMOS power amplifiers
......................................................
26
Table 2.1. Key device and process parameters for the device types studied in this thesis ........................ 32
Table 2.2: Definition of bias currents, voltages and figures of merit of an RF power amplifier.
............... 43
Table 4.1: Measured and modeled values of DC and RF power data on two different test structures designed in 45
nm CMOS technology. Details of the standard device layout can be found in Chapter 2. The spacing between gate
fingers in the new test structure is twice that in the standard structure......................................................................103
20
Chapter 1
Introduction
1.1
RF and Millimeter-wave Applications
Wireless and mobile communication systems have become ubiquitous in our daily life to the
point where we cannot imagine life without them. Some of the more prevalent applications
include cellular and cordless phones, pagers, RFID tags, Bluetooth, wireless local area networks
(WLAN) and wireless personal area networks (WPAN) [1-2]. These applications operate over a
wide range of frequency from 900 MHz to 5.6 GHz.
The need for higher bandwidth, and thus higher speed and data rate, in wireless
communications has prompted scientists and engineers to explore millimeter wave frequencies
(30 GHz to 300 GHz range). Within this frequency range, the 60 GHz band has received a lot of
attention in the past few years because of the availability of 7 GHz of unlicensed spectrum
around that frequency. At 60 GHz, there is an unusually high attenuation of signals due to
atmospheric oxygen adsorption [3-5]. This attenuation precludes long-range communications,
but provides an extra spatial isolation for secure short-range point-to-point links, while reducing
~jjj~
co-channel interference and allowing frequency reuse in an indoor dense local network. Moving
to higher frequencies also reduces the form factor of antennas, as antenna dimensions are
inversely proportional to carrier frequency. Therefore, for a fixed area, more antennas can be
used, thus increasing antenna gain, which in turn helps direct the electromagnetic energy to the
intended target [6].
40
(a)
(b)
(c)
(d)
Fig. 1. 1: Illustration of some of the applicationsin the millimeter-wave regime. (a) High-speed
wireless local area network, (b) High data rate wireless personal area network, (c) Automatic
cruise control and collision avoidance radarin automobiles, (d) Imagingfor detection of hidden
weaponsfor airportsecurity applications.
Some of the applications in the millimeter-wave regime are enumerated below [3-5, 7-10] and
illustrated in Fig. 1.1.
" The 60 GHz band allows bit rates of several Gb/s, with a range of up to 10 meters. This
could be used to create wireless personal area networks (WPANS) and local area
networks (WLANS), allowing wireless Gigabit Ethernet, laptop docking stations, and
mobile
device
synchronization
(cellphones,
ipods,
MP3
players,
cameras,
handhelds/PDAs, etc) (Fig 1.1 (a) and (b))
e
Fig. 1.1 (c) illustrates the use of millimeter-wave frequencies for automotive radar
applications. The FCC has allocated 76-77 GHz frequency band for long range (100 m)
automatic cruise control and automotive collision avoidance systems and the 22 - 29
GHz range for short range automotive radar applications.
* Millimeter-wave imaging in the 94-95 GHz band is being used for radar cloud detection
and all-weather landing, military surveillance, navigation and precision targeting,
detection of hidden weapons for security applications (Fig. 1.1 (d)), and medical
imaging for tumor detection, temperature measurements, blood flow, and water/oxygen
content measurements.
*
Another application where high data rate is a necessity is the wireless transmission of
uncompressed high-definition television (HDTV) signals. Compressed HDTV signals
need data rates of 50 Mbps, while uncompressed signals could need data rates as high
as 1.5 Gbps.
1.2
Advantages and Challenges in using CMOS
Most of the millimeter-wave applications described in the previous section are consumer
applications and hence are very cost sensitive. Traditionally these systems were designed using a
23
combination of Silicon CMOS, bipolar, III-V HEMT, and HBT technologies making them
prohibitively expensive. Recent advances in silicon technology, driven by high performance
digital applications, have made CMOS the ideal candidate for consumer applications in the
millimeter-wave regime. CMOS allows for higher levels of integration (and thus smaller system
size), lower cost and lower power dissipation, all of which are important considerations in
portable applications.
However, designing wireless transceivers in CMOS presents quite a few challenges. The most
difficult component to design in CMOS is the power amplifier. Some of the factors affecting
power amplifier design in CMOS technology are listed below [2, 11-12]:
(a) The low breakdown voltage of deep sub-micron technologies limits the maximum gatedrain voltage and the output power. This is because the output voltage at the transistor's
drain normally reaches 2 times the supply voltage for classes B and F, and around 3 times
the supply for class E operation.
Thus, transistors have to operate at a lower supply
voltage, delivering low power. Additionally CMOS technology has lower current drive and
fmax compared to III-V devices, which means that the gain provided by a single stage is
very low necessitating the need for multiple stages.
(b) Silicon CMOS generally uses a highly doped conductive substrate. This results in substrate
interaction in a highly integrated CMOS IC. The leakage from an integrated power
amplifier might affect the stability of, for example the VCO in a transceiver chain.
(c) Since the inherent output device impedance in CMOS is very low, impedance matching
becomes very difficult, requiring higher impedance transformation ratios. Additionally, the
output matching elements require low loss, and good thermal properties since there are
usually significant RF currents flowing in these elements. If CMOS technology is used, the
losses in the substrate will decrease the quality factor of the passive elements in the
matching network.
(d) Conventional transistor models for CMOS devices have been found to be only moderately
accurate for RFICs, and need to be improved for analog operation at radio frequencies.
Accurate large signal CMOS RF models and substrate modeling are critical to the
successful design and operation of integrated CMOS RF power amplifiers.
1.3
Literature survey of 60 GHz power amplifiers
Despite the challenges outlined in the previous section, universities and companies around the
world have been working on designing millimeter-wave CMOS power amplifiers. Table 1.1
shows a comparison of 60 GHz CMOS power amplifiers published over the past two years.
The most popular technology for designing 60 GHz power amplifiers is the 90 nm CMOS
technology, though a few recent designs have also been demonstrated in 65 nm and 45 nm
CMOS technologies. The power amplifiers typically contain 2 to 4 stages of common-source or
cascode configurations. The cascode topology achieves good isolation, high gain, good stability
and low power consumption, but requires a large power supply voltage. The common-source
configuration maximizes the output voltage and current swings yielding high output power and
good linearity. The first stage of the power amplifier is often designed as a cascode stage to
improve isolation,
and subsequent stages
are usually common-source
configurations.
Transformer coupling and power combining techniques are often employed to further increase
the output power and PAE. Saturated power levels as high as 19.9 dBm [13] and power added
efficiency (PAE) of 25.7% [14] have been demonstrated at 60 GHz.
Tech
Node
Gain
(dB)
P1dB
Psat
(dBm)
PAE
(%)
VDD
(dBm)
45 nm
19
-
7.9
19.4
45 nm
6
11
13.8
45 nm
16
7.6
45 nm
20
65 nm
(SoI)
65 nm
Stages
Topology
Reference
1.2
3
Common source
[15]
7
1.1
2
Push-pull
[16]
12
12.3
1.8
2
Cascode
[17]
11.2
14.5
14.4
2
2
Differential cascode
[18]
16
12.7
14.5
25.7
1.8
2
Cascode
[14]
13.4
12.2
13.8
7.6
1.2
4
Common source
[19]
65 nm
15.8
2.5
11.5
11
1
3
Differential CS
[20]
65 nm
4.5
6
9
8.5
1.2
1
Common source
[21]
90 nm
20
8.2
12
9
1.2
4
Cascode + power
combining
22]
90 nm
26.1
10.5
14.5
10.2
1.8
3
Cascode + DAT
power combining
[23]
90 nm
15
10.2
12.2
19.3
1.2
3
Transformer
coupled CS
[24]
90 nm
10.1
5.1
8.5
7.7
1
2
coupled differtial
[25]
90 nm
30
10.3
13.8
12.6
1.8
3
Cascode
[26]
90 nm
10
8.8
12.6
6.9
1
3
Common source
[27]
90 nm
20.6
18.2
19.9
14.2
1.2
2
4-way power
combining
13]
90 nm
4.2
12.1
14.2
5.8
1
2
4-way current
combining
[28]
90 nm
-
9
12.3
8.8
1
2
Differential CS,
transformer coupled
[29]
90 nm
9.8
7.5
11.2
5
1.2
3
Common source
[30]
90 nm
16.3
10.5
11.5
8.5
1
3
Cascode + CS
[31]
90 nmn
11
8.3
11.2
3.6
1.2
4
Differential CS +
Power combining
32]
(V)
Table 1.1: Comparison of state-of-the-art60 GHz CMOS power amplifiers.
I.. ....
-V-.............
.............................
. .......
.......
1.4
CMOS technologies for RF power applications
The previous section has shown that 60 GHz CMOS power amplifiers exhibit relatively low
power levels (<15 dBm) at very low efficiencies (<20 %). The best way to improve the power
amplifier performance is by improving the power performance of the transistor. However, very
little work has been published on the RF power performance of CMOS devices [33-37]. The
published device data is summarized in Fig. 1.2 and Fig. 1.3.
180
160
N
90 nm [37]
140
VDD=1.5V
120
100
80
* 60
406540
20 -VDD
2090
nm [33]
45 nm [36]
= 1.2 V
,
10
= 1V
nm [34]
VoQ
0'
VDD
= 1 V
100
1000
Device Width (gm)
10000
Fig. 1. 2: Output power, normalized to device width and supply voltage, as a function of device
width. All previously published device data is shown in thisfigure.
Fig. 1.2 shows all the previously published data for normalized output power (normalized to
device width and supply voltage) as a function of device width for CMOS technologies beyond
90 nm. The operating frequency was different for each of these measurements and will be
discussed further in Fig. 1.3. The most comprehensive study over a wide range of device widths
was published in [33]. However, the bias currents in this study were quite low (25 mA/mm) and
...........
...........................
..................
the source and load impedances were optimized for maximum PAE as opposed to maximum
power, resulting in low overall normalized power levels. The 45 nm device shows lower power
density because it was measured at a much higher frequency (35 GHz).
The most common technique used when designing for high power levels is to use a device
with large device width. However, Fig. 1.2 clearly shows that the normalized output power
decreases with increasing device width. This limits the obtainable power level is CMOS devices.
The reasons for the decrease in normalized output power with device width will be investigated
in this thesis.
90
80
,70
E 60
50
0
040
65 nm [33]
L 30
0
45 nm [36]
VDD = 1 V
20
VDD= 1.2 V
10
90 nm [37]
VDD=
0
0
1.5 V
10
20
30
40
Frequency (GHz)
Fig. 1.3: Output power as a function of measurementfrequency. All previously published device
data is shown in thisfigure.
Fig. 1.3 shows the published data for output power as a function of measurement frequency.
The figure shows that the maximum power delivered by a given CMOS device is strongly
dependent on the frequency of operation and decreases significantly with increasing frequency.
The main reason for this decrease is that the parasitic resistances and coupling capacitances,
28
associated with wiring multiple fingers in wide devices, become significant at high frequencies
thus limiting the output power and efficiency.
At first glance, it might look like the data in Fig. 1.3 is in contradiction to the data in Table
1.1. However, when the 60 GHz power amplifier circuit data from Table 1.1 is normalized to
obtain the power per device, we find that most of the designs show an output power of less than
8 mW per device. Further, the output power drops to less than 5 mW per device when the supply
voltage is normalized to 1 V. This is consistent with the data in Fig. 1.3 and illustrates the main
problem with using CMOS devices at high frequencies.
In this thesis, we will explore various device design options to understand the main detractors
to power performance at high frequencies and suggest improvements to device layout that would
enable CMOS use at millimeter-wave frequencies.
1.5
Thesis Goals
The main goal of this thesis is to explore the performance limits of RF power CMOS.
Through a combination of detailed RF characterization, analysis and modeling, we hope to
answer the following questions:
(a) What is the limiting power-frequency locus for 45 nm and 65 nm CMOS generations?
(b) What limits the power in the millimeter-wave regime?
(c) Is there a way to break these limits on a CMOS platform?
The thesis is organized as follows. Chapter 2 describes the technologies and device structures
studied in this thesis and the types of experiments carried out on them. Chapter 3 presents
measured RF power data as a function of device width and operating frequency for a variety of
devices designed in 65 nm high-performance, 45 nm high-performance and 45 nm low-power
technologies. Chapter 4 describes a first order model that predicts output power - drain efficiency
29
locus for any given bias point and device on-resistance. This model will be shown to be
consistent with the measured data of chapter 3. Chapter 5 investigates the reasons for the
decrease in output power with increasing device width and frequency through small-signal
equivalent circuit extractions. The final chapter (chapter 6) draws key conclusions about the RF
power capability of CMOS technologies.
Chapter 2
Experimental
This chapter describes the technologies and devices studied in this thesis, as well as the types
of experiments carried out on them. I will first describe the device technologies used in this
work and the various test structures designed in each of these technologies. I will then broadly
describe the characterization carried out on these devices:
DC, S-parameter, and RF power
characterization.
2.1
Technology Description
The device technologies studied in this work are foundry 65 nm high-performance (65 nm
HP), 65 nm low-power (65 nm LP) and 45 nm low-power (45 nm LP) bulk CMOS technologies
manufactured at IBM [38-41]. Each of these technologies offers thin oxide and 1/0 device
options, as well as multiple VT options in the thin oxide devices. This thesis focuses mostly on
the regular VT thin oxide device (which we will call the standard device), with some data
presented on the 2.5 V 1/0 device in 65 nm LP technology. The devices wil-l be labeled
according to their ITRS equivalent technology node: Lgnn = 45 nm, 65 nm, and 250 nm, with
the understanding that the physical gate length is different from those values. Table 2.1 shows
the key device and process parameters for the different devices studied in this thesis.
Parameter
ITRS Equivalent Node
65 nm
65 nm
45 nm
High Performance
Low Power
Low Power
65 nm
0.25 [tm
65 nm
0.25 im
45 nm
50
230
60
230
40
Oxide Thickness (A)
12.5
52
19.5
53.5
18.2
Nominal Voltage (VDD) (V)
1.0
2.5
1.2
2.5
1.1
0.29
0.41
0.39
0.41
0.46
780
650
600
640
540
10
0.2
0.3
0.2
0.15
Ldesign(nm)
Vtsat (VDS=VDD)
(V)
Ion (VDS=VGS=VDD) (gA/gm)
Ioff (VDS=VDD,VGS=O) (nA/gm)
Table 2.1. Key device andprocess parametersfor the device types studied in this thesis
The 65 nm high-performance technology is a foundry technology developed for SRAM, logic,
mixed signal and mixed voltage input/output (1/0) applications [38]. The standard device in this
technology has a nominal gate oxide thickness (tox) of 12.5
50 nm and a nominal power supply voltage
1/0 device with oxide thickness of 52
(VDD)
A, a minimum gate length
(Ldesign)
of
of 1.0 V. The technology also offers a 2.5 V
A and a minimum
design length of 0.23 gim. The standard
device delivers a drive current (In) of 780 gA/gm with an off-state leakage (Ioff) of 10 nA/gm,
while the 1/0 device delivers Ion = 650 gA/gm at Ioff = 0.2 nA/gm.
The 65 nm low-power technology is primarily targeted towards mobile applications and
focuses on process simplicity, low cost, and reduced power consumption [39]. The back-end-ofthe-line (BEOL) metallization for this technology is identical to that of the 65 nm highperformance technology. The standard device has tox = 19.5
A, Ldesign =
60 nm and VDD
=
1.2V.
The thicker gate oxide and longer gate length, as compared to 65 nm HP technology, help in
reducing
off
(0.3 nA/gm), but also reduce Ion (600 gA/tm). The 2.5 V 1/0 devices in this
technology have very similar specifications to those in the high-performance technology.
The next generation for the low cost, low power applications is the 45 nm low-power CMOS
technology [40-41]. Only the thin oxide, regular VT device was studied in this technology. The
device has tox = 18 A, Ldesign = 40 nm and VDD
=
1.1 V and exhibits an extremely low Ioff (0.15
nA/gm) at Io=540 gA/gm.
2.2
Device Layout
A variety of device layouts were designed to provide a broad range of total device width. The
designs were fabricated at IBM Microelectronics as part of their regular foundry shuttles. The
details of the device layout in each of the technologies are described below.
2.2.1 65 nm Technologies:
The same set of test structures were laid out and studied in both 65 nm HP and 65 nm LP
technologies. The test structures were designed using ten metallization levels. Ml, M2, M3, M4
are thin (iX) Cu levels, BI, B2, B3 are 2X Cu levels, EA, EB are 4X Cu levels and LB is the
final thick Al level. All devices were designed at the minimum gate length (50 nm for the HP
technology and 60 nm for the LP technology). The total device width (W) is the product of the
number of parallel device cells (Nc), times the number of device fingers per cell
(NF),
times the
unit finger width (WF). We will label devices as W = Nc x NF x WF. Device structures with total
device width ranging from 48 gm (Nc =1) to 38 mm (Nc = 792) were designed by connecting
multiple unit cells in parallel.
A schematic of the unit cell can be seen in Fig. 2.1. Each unit cell contains 24 gate fingers of
2 pm finger width. The gate poly fingers were connected together on both sides of the device to
reduce gate resistance. Substrate contacts were placed on either side of the device to minimize
substrate resistance. The two gate contacts were connected together on M2 and M3 levels. The
individual source fingers and drain fingers were connected together at M4 level. Thicker
metallization levels were then used to route the gate, source and drain to the RF pads.
Fig. 2.1: Illustration of a unit cell in 65 nm devices containing 24 fingers of 2 pm finger width.
Gate is contacted on both sides of the device and is wired out at M3 level. Source and drain
fingers are wired out at M4 level.
Fig. 2.2 shows the layout of an 8x24x2 m device, with 8 unit cells connected in parallel. The
layout uses a double-sided source access to the device on the thick Al level (LB). The gates of
the individual cells were connected together at M3 level, the sources at M4 level, and the drains
at B 1 level. The gate, source, and drain were then wired up to LB level and connected to the
signal and ground pads. In connecting the intrinsic device to the RF pads, metal layers were
strapped together, wherever possible, to reduce parasitic wiring resistance.
........................................................
A set of 1/0 devices with thicker gate oxide and gate length of 0.25 gm were also designed.
The I/O devices have the same layout variations as the standard devices. A detailed list of the
various layout variations designed for 65 nm can be seen in appendix A.
Fig. 2.2: Schematic of a W=8x24x2 pn device showing 8 unit cells connected in parallel. The
diffusion area of the unit cells is shown as the black outline. Gate, Source and Drain are wired
out to the last metal level (LB) before connecting them to the RF pads.
In order to facilitate accurate de-embedding of measured S-parameters, open and short deembedding structures, specific to a given device layout, were custom designed for some of the
devices.
e
The open structures do not contain source or drain diffusions or gate polysilicon regions
in the device area. The substrate contact regions and the metallization on the source
fingers (which are eventually connected to the ground pad) are identical to the
corresponding device layout. However, there is no metallization (Ml, M2, M3 levels)
on the drain fingers. The metallization needed to connect the unit cells in parallel
(levels M4 and up) was kept identical to the original device layout.
..................
.......................................................................................................................
*
The short structures are identical to the open structures, but contain an M4 plate that
shorts out the gate, source and drain terminals.
2.2.2 45 nm Technology:
-~W-
Substrate Ring (M1+M2)
M- M M- M--M- M- M- M
Fig 2.3 Layout of a unit cell in 45 nm technology containing 20 fingers of 2 Um finger width.
Gate is connected on both sides of the device to reduce gate resistance. Gate, source and drain
are wired out on alternate metal levels to reduce coupling capacitancebetween terminals.
Two sets of test structures were designed in the 45 nm technology. Both sets were designed
using 7 layers of metallization. M1, M2, M3, M4, M5 are thin (iX) Cu levels, FA is a 6X Cu
level and LB is thick Al level. In the first set of structures, the device width was increased by
either (a) keeping the number of fingers (NF) constant (NF=60) and increasing the unit finger
width (WF) from 0.5 lm to 5 gm, or (b) keeping the finger width constant (WF -. 5 gm) and
increasing NF from 20 to 120. All devices in the set have a gate length of 40 nm and contain a
substrate contact ring that surrounds the device and reduces the substrate resistance. In all other
respects, the layout of each device is similar to the 65 nm unit cell layout described above.
Details of the various layout variations can be found in appendix A.
In the second set of devices, the device width was increased by designing an optimum unit
cell and connecting multiple unit cells in parallel. The layout of the unit cell can be seen in Fig.
2.3. Each unit cell contains 20 fingers of 2 tm finger width. The choice of 2 ptm for finger width
was found to be the optimum in a study of the RF power performance on the first set of 45 nm
test structures. The gate was connected on both sides of the device to reduce gate resistance.
When connecting the gate poly fingers to the first metal level (Ml), the overlap between poly
and Ml was minimized to reduce parasitic gate capacitance. Substrate contacts were placed in a
ring around the device to reduce substrate resistance. To minimize the coupling capacitance
between the device terminals, the gate, source, and drain were wired out on alternate metal
levels: the source was wired out at M3 level, the gate at M5 level, and the drain at FA level. To
further reduce coupling capacitance, M2 level was eliminated on the lower part of the drain
fingers, under the source connection.
Fig. 2.4 shows the layout of a 160 .imwide device with 4 unit cells connected in parallel. The
signal lines from the RF pads were designed in the thick Al level (LB). A ground plane
containing a mesh of Ml and M2 levels was designed to be present under the signal lines and all
around the device to reduce substrate coupling. The source and substrate terminals of the device
are shorted together and connected to the ground pads through the Ml+M2 ground plane. In
connecting the intrinsic device to the RF pads, metal layers were strapped together wherever
possible to reduce parasitic wiring resistance.
.......................................
..........
.. . .........
S
Plane
_Calibration
Fig 2.4 Schematic of a W=4x20x2 pm device in 45 nm technology containing 4 unit cells
connected in parallel.A ground plane on M1 and M2 levels is placed under the gate and drain
signal lines to reduce substrate coupling. Source and substrate are shorted together and
connected to the M1+M2 ground plane.
In order to facilitate accurate de-embedding of measured S-parameters, on-wafer open and
short structures are required. Due to space crunch on the test site, we could not design individual
open and short structures for each device variation. Instead, a common set of open, short, load,
and thru de-embedding structures was designed. The de-embedding structures de-embed all
parasitics up to the end of the signal lines as denoted by the calibration plane shown in Fig. 2.4.
The open structure simply removes the active device from between the signal lines, while the
short structure removes the active device and shorts out the gate, drain, and source terminals. A
complete list of the various layout variations in this set is provided in appendix A.
2.3
DC and S-Parameter Characterization
DC Measurements on all the devices were performed using an Agilent 4155B parameter
analyzer. All measurements were performed on-wafer using standard RF probes (ground-signal38
......
_'N
.......
......
....
....
.............
ground). Sample output characteristics and transfer characteristics on a standard 45 nm highperformance device with W = 80 tm are shown in Fig. 2.5.
600
600
5nmCMOS
500
45nm CMOS
W=2x20x2 jm
500
W=2x2x22 sm
L=40 nm
L 40 nm
E 400
E
-
E 400
E
E300
E 300
200
200
100
100
a
0
0
0.2
0.4
0.8
0.6
VDs (V)
Fig. 2.5:
VDS= 1-V
1
1.2
VDS 50 mV
0
0
0.2
0.6
0.4
0.8
1
1.2
Vs (V)
Output characteristics (VGS = 0.4 V to 1.] V in steps of 0.] V) and transfer
characteristics(VDs = 0.05 V and VDS = 1.1 V) on 45 nm devices (W = 80 pm).
S-parameter measurements, from 0.5 GHz to 40 GHz, were performed using an Agilent
8510C network analyzer. DC bias, during S-parameter measurements, was provided through
bias-tees using Agilent 4155B. S-parameters were often measured at VDS
=
VDD
and VGS Set to
ensure a constant drain current density across all devices. The measurement system was
calibrated till the probe tips by measuring short, open, load and through structures (SOLT) on a
standard calibration substrate. S-parameters were then measured on each device and, if available,
on the corresponding open and short de-embedding structures. The two-port parameters of the
intrinsic transistor were then obtained by de-embedding the on-wafer parasitics according to the
industry standard open and short de-embedding technique described in [42].
Fig. 2.6 shows the S-parameters of a standard 65 nm CMOS device with W = 96 gm,
measured at VDS
=
1 V and
ID
= 200 mA/mm. The solid blue lines show the measured S-
parameters before de-embedding and the dashed red lines show the S-parameters after open and
short de-embedding. It is clear that the on-wafer parasitics significantly impact the measured Sparameters and hence proper de-embedding is essential for extracting the frequency metrics and
small-signal parameters of the intrinsic device.
+jl.0
+j2.0
+jO. 5
S21/10
S22*5
+j0.2
+j5.0
0.0
00
J-50
-jo.2
Si11
-jO. 5
-j2.0
-ji.0
Fig 2.6 Smith chartshowing the S-parameters on a 65 nm standarddevice (W=96 Um) measured
from 0.5 GHz to 40 GHz at VDD=J V, ID= 2 0 0 mA/mm. The blue solid lines show the Sparametersbefore de-embedding and the red dashed lines show the de-embedded S-parameters.
The measured S-parameters allow us to extract the unity current gain frequency (fT) and
maximum oscillation frequency (fma) of the device. Fig. 2.7 shows the current gain (h21) and the
unilateral power gain (U) as a function of frequency for a typical 65 nm device measured at VDS
= 1 V and ID= 200 mA-mm. The figure shows that both h2 1 and U increase after de-embedding,
thus resulting in an improved fT and fma. The extracted fT increased from 112 GHz to 189 GHz,
while the extracted fma increased from 160 GHz to 216 GHz after open and short de-embedding.
40
----
...........
-------:-..
.................
..........
70
50
---
60
-
-
Before Deembedding
-After Deembedding
i40
50
9
40
35
40
I
45
0 300
25 1
C
.c:i 30
20
10
20 -'
65 nm CMOS
W = 2x24x2 gm
15
10
%%%%%%%1
VDD =1 V
ID=
5
%
200 m/
0
0
110
100
Frequency (GHz)
T
f
'""
1000
Fig 2.7 Current gain and unilateral power gain as a function of frequency for a 96 pn wide
device. Blue solid lines show data before de-embedding, while red dashed lines show the data
after open and short de-embedding. fT andfaux improve with de-embedding.
2.4
RF Power Characterization
RF power measurements were made in the 2 - 18 GHz range using a Maury Microwave loadpull system. A schematic diagram of the system can be seen in Fig. 2.8. The RF source provides
a single frequency RF signal to the gate of the device. The input power is measured through a
directional coupler. DC bias at the gate and drain is provided through bias tees. Mechanical
tuners set the source (gate side) and load (drain side) impedances to the device. The RF input and
output power as well as the bias currents and voltages are measured, and allow computation of
all the relevant figures of merit. These are defined in Table 2.2. More details of measurement
setup and procedure can be found in [43-44].
Fig. 2.8 Schematic diagram of Maury Microwave Load pull system at MIT.
Parameter
Definition
VGQ
DC bias at the gate of the device
VDQ
DC bias at the drain of the device
ID
DC drain current in the absence of RF input
IG
Average current in the gate of the device
IDC
Average current in the drain of the device
pi
RF power available at the input of the
device.
IDQ
Expression
power
Pout
RF output power that leaves the device
PDC
DC power into the device
PDC
=
IGVGS + IDCVDS
(2.1)
GT
flD
Gr =
Power Gain
Drain efficiency measures the amount of
Pout
Pout
-- - IGVG +
IGVGS + IDCVDS
PDc
_
riD -
DC power converted to RF output power
PAE
Power-added
PAE
efficiency
measures
(2.2)
out
Pin
=
(2.3)
Pout - Pin
PDC
the
amount to DC power converted to RF
out
power, taking into account the amount of
RF power that enters the device
PDC
(
n
(2.4)
Pout
(1
)
GT
Table 2.2: Definition of bias currents, voltages andfigures of merit of an RF power amplifier.
Most of the power measurements were performed with VDQ=VDD and VGQ set to ensure a
constant drain current density across all devices at low input power conditions. Throughout this
thesis, we will be quoting the bias condition as a combination of VDQ and IDQ (which is achieved
with a gate bias VGQ). During the power measurement, the gate bias is held constant, rather than
the actual IDvalue.
Power measurements were optimized to provide either peak output power or peak PAE, by
alternating source- and load-pull measurements at an input power level that is a few dB below
the level corresponding to peak PAE. Power sweeps were made at the optimum load and source
impedances, and the maximum PAE and associated output power were noted. This optimization
was repeated for each bias point and frequency on each device.
A typical power measurement sweep at 2 GHz is shown in Fig. 2.9. The output power and
PAE initially increase with increasing input power. Once the device enters compression, the gain
drops, leading to an eventual saturation of the output power and a peaking and drop in the PAE.
The peak PAE point is selected as the optimum, and the optimum PAE and associated Pout are
reported.
.................
80
25
70
20
60
Peak PAE
E
+-lc
5
50
XiS
0
015
40 j
30
S10
0
o
5
'
PAE-
45 nm CMOS
20
W = 2x20x2 gm
VDD =.1 V
10
ID
0
-
U
0
2
200
6
4
mA/mm
0
1
8
10
0
Output Power (dBm)
Fig. 2.9 Sample RF power sweep at 2 GHz showing power gain, PAE and average drain current
as a function of output power.
In reduced conduction angle amplifiers, it is common to observe that as the input power
increases, the measured DC drain current changes from its low-power value (the bias current).
This is known as "self-biasing." The origin of self biasing is the non-linearity that enters when
the input signal swings below the device's threshold voltage or above the voltage that leads to
the device entering the linear regime [45]. While the average vGs remains at its bias value (VGQ),
swinging the input below Vt will not result in a negative drain current, but rather in zero current.
Similarly, swinging the input above VGSsat will clamp the drain current at IDsat. This leads to an
asymmetry in the drain current waveform, thus changing the average value of iD from the DC
value. If a device is biased at a vGS close to Vt, the average drain current will increase with
increasing input power. On the other hand, if the device is biased at vGS close to VGSsat, the
average drain current will decrease with increasing input power as is the case in Fig. 2.9. Self44
biasing is important because it affects the measured PAE. For instance, in Fig. 2.9, the average
current decreases because of self-biasing, and this results in an increased value of peak PAE.
2.5
Summary
In this chapter, we have described the layout of device test structures used to study RF power
performance as well as the technologies that were used to fabricate these test structures. A
detailed description of the measurement setup used to characterize the DC, S-Parameter and RF
power characteristics was also provided. The next chapter will show extensive RF power
measurement data on 65 nm HP, 65 nm LP, and 45 nm LP devices.
46
Chapter 3
RF Power Performance
This chapter presents extensive data on the DC, S-parameter and RF power characteristics of
devices in 65 nm low-power (65 nm LP), 65 nm high-performance (65 nm HP), and 45 nm lowpower (45 nm LP) technologies. This data allows us to estimate the maximum power capability
of each of these technologies. Comparison among the three technologies, as well as comparison
to published literature will also be presented.
3.1
65 nm Low Power Technology
We studied both the standard and 1/0 devices in 65 nm low-power technology. The standard
device has a gate length of 60 nm and operates at
length of 0.25 gm and operates at
VDD = 2.5
VDD =
1.2 V, while the 1/0 device has a gate
V.
3.1.1 1.2 V Standard Device
The output characteristics and transfer characteristics on a 65 nm LP standard device with W
=
2x24x2 gm are shown in Fig. 3.1. The normalized drive current of the device is around 653
mA/mm at VGS=VDS=l.2 V.
......
..
....
700
600
500
600
65 nm LP CMOS
W=2x24x2 pm
500
L= 60 nm
VDS=1.2 V
E
E 400
400
300
E 300
200
200
DS=50
100
mV
0
0
0.2
0.4
0.6
1
0.8
0
1.2
0.2
0.4
0.8
0.6
1
1.2
VGS (V)
VDS (V)
Fig. 3.1. Output characteristics (VGS = 0.2 V to 1.2 V in steps of 0.2 V) and transfer
characteristics(VDS = 0.05 V and VDS = 1.2 V) on the standard65 nm LP device (W = 96jum).
70
40
Max. P.,/
=150.8 mW mn
35
60
50
30
4
25
0R40
20
W=481 im
< 30
15 (
20
L
10
10
5
0
0
5
10
15
Output Power (dBm)
Fig. 3.2: Typical power sweep showing PAE and gain as a function of output power on several
65 nm LP standard devices. The figure also illustrates the maximum Pout, PAE and Pau, / W
obtainablefrom this technology at VDS = 1.2 V and ID = 200 mA/mm.
..............
16
14
70
68
L
66
12
6
64
E
~
10
O
-I~062
8 -60
y
58
56
65 nm LP CMOS
Q 4
W = 2x24x2 gm
VDS=1 V
2
f=8GHz
0
0
.50
50
100
150
200
250
52
300
350
Bias Current (mA/mm)
Fig. 3.3: Output power and PAE as a function of DC bias current illustrating the trade-off
between Pont and PAE.
Power measurements were performed at 8 GHz on devices with different widths at various
bias conditions. When making each of these measurements, the source and load impedances
were optimized for maximum power-added efficiency. The input power was then swept and the
maximum PAE and the corresponding output power were noted.
Fig. 3.2 shows such power sweeps on three different devices, with the measured PAE and
power gain plotted as a function of the measured output power. At a DC bias of VDS = 1.2 V and
ID
= 200 mA/mm, a maximum normalized output power of 150.8 mW/mm was measured on the
48 gm wide device, a maximum PAE of 62.8 % was measured on the 96 gm wide device, and a
maximum output power of 87.7 mW was measured on the device with W = 1536 gm.
Fig. 3.3 examines the dependence of output power and PAE on the DC bias current. The
output power keeps increasing as the bias current increases, while the PAE decreases with
............
.
....
.......................
..
....
.
..............
..
.....
..
.
..
......
..
......
...........
.
increasing bias current. For most measurements in this thesis, a bias current of 200 mA/mm was
chosen, to ensure a reasonably high output power at a decent PAE.
25
65 nm LP CMOS
VDS=1.2V
20
E
f=8GHz
15
0
0
-- ID= 25 mA/mm
+ lD = 100 mAmm
-D = 200 mAmm
5
-' = 300 mA/mm
0'
10
100
1000
10000
Device Width (gm)
Fig. 3.4: Measured output power, at various DC bias currents,for 65 nm LP CMOS devices of
different widths.
The measured output power at various bias currents is shown as a function of device width in
Fig. 3.4. The output power scales ideally with device width for small device widths, but starts to
saturate in larger width devices (W > 400 jim). The non-ideal scaling of output power at large
widths is more evident when the normalized output power (Po, / W) is plotted as a function of
device width (Fig. 3.5). Another observation is that the non-ideality increases with increasing
bias currents.
Fig. 3.6 shows the measured peak PAE as a function of device width, for 65 nm LP CMOS
devices, at various bias currents. The peak PAE shows a marked decrease with increasing width.
Also, for any given device width, the peak PAE decreases as the bias current increases (as was
. .....
....
....
.
--
----------
180 -
E
160 -
+
140 ~a
+D = 100 mA/mm
D= 200 mA/mm
S120
+
=
ID
25 mA/mm
= 300 mA/mm
S100
80
-
0
60
*
0
40
20
-
-
65 nm LP CMOS
VDS= 1.2 V
f = 8 GHz
0
100
1000
10000
Device Width (gm)
Fig. 3.5: Normalized output power as a function of device width, measured at various DC bias
currents on 65 nm LP CMOS devices.
80 -
65 nm LP CMOS
70 -
VDS = 1.2 V
f = 8 GHz
60 -
qO50
0
w
40 30 20
+=
100
=
10
mA/mm
mA/mm
200 mA/mm
mA/mm
25
D
+ID
=
3 0 0
0
100
1000
10000
Device Width (gm)
Fig. 3.6: Measuredpeak PAE, on 65 nm LP CMOS devices, versus device width at different DC
bias currents.
.....
. ..........
..
.....
.
also seen earlier in Fig. 3.3). The reasons for non-ideal scaling of output power and decrease in
PAE with device width form the crux of this thesis and are presented in sections 3.3.2 and 3.4
and in chapters 4 and 5.
3.1.2 2.5 V 1/0 Device
60
VDD=
50
ID= 200 mA/mm
f= 8 GHz
Max. P/W
= 267 mW/m
40
2.5 V
Max. PAE
=51.6 %
30
40
4 25
20 %
w3 0
-
Max. Pot"
=9259 mW
g
W0=48 pm
20
15
(
10
W =1536 p
10
5
0
0
0
5
10
15
20
25
30
Output Power (dBm)
Fig. 3.7: Typical power sweep showing PAE and gain as a function of output power on several
0.25 pm long I/O devices in 65 nm LP CMOS technology. The maximum Pout, PAE, and Pout / W
obtainablefrom this technology at VDS = 2.5 V and ID = 200 mA/mm are noted on the figure.
RF power measurements were also made at 8 GHz on the thick oxide 1/0 devices at VDS = 2.5
V. Typical power sweeps at DC bias current of 200 mA/mm are shown for three different device
widths in Fig. 3.7 and illustrate the maximum output power and PAE obtainable from this
technology at the given DC bias and frequency. A maximum normalized output power of 267
mW/mm was observed on the 48 gm wide device, a maximum peak PAE of 51.6% was
measured on the 192 gm wide device, and a maximum output power of 259 mW was measured
52
..
....
....
.......
......
..
. - ......
.
V-W...
...
......
....
.....
.......
. ...
. ....
.....................
................
on the widest device (W=1536 gm). The maximum output power measured on the 1/0 device is
approximately 3 times that measured on the standard device (Fig. 3.2) because of the higher
drain voltage (2.5 V vs 1.2 V). However, the higher output power comes with a significantly
lower PAE, because of the lower frequency response (fT and fmax) of the 1/0 devices compared to
the standard devices. Hence, at relatively low RF frequencies (< 10 GHz), a significant
improvement in RF power can be achieved by using the 2.5 V 1/0 devices instead of the standard
devices. For frequencies greater than 10 GHz, the decrease in PAE might be too drastic to justify
the use of 1/0 devices for increased output power.
30
65 nm LP CMOS
VDS= 2.5 V
25
f=8GHz
E
o 20
0 15
0.
0.10
ID 50
0
mA/mm
ID=100mAmm
ID=200mA/mm
* ID= 300 mA/mm
+
5
0
10
100
1000
10000
Device Width (gm)
Fig. 3.8: RF power measured at 8 GHz as a function of device width for I/0 devices designed in
65 nm LP CMOS technology.
Fig. 3.8 and Fig. 3.9 show the output power and peak PAE as a function of device width for
1/0 devices in 65 nm LP CMOS technology. Measurements at bias currents of 50, 100, 200 and
300 mA/mm are included. The behavior of output power and PAE with device width is similar to
that seen in the standard devices (Fig. 3.4 and Fig. 3.6). The output power scales non-ideally
with device width for W > 400 gim, while the PAE shows a consistent decrease with increasing
device width.
70
65nmLP CMOS
VDS=
60
2 5
. V
f=8 GHz
50
S40
30
-0-
20
10
ID=
50 mA/mm
+ tD =100 mA/mm
+D = 200 mA/mm
D=
1 300 mA/mm
0 1
10
100
1000
10000
Device Width (gm)
Fig. 3.9: Peak PAE, measured at different bias currents, as a function of device width for I/O
devices designed in 65 nm LP CMOS technology.
3.2
65 nm High Performance Technology
In this section, DC, S-parameter and RF power measurements on standard devices, designed
in 65 nm high-performance technology, will be presented. All devices were designed with a gate
length of 50 nm and were measured at a drain voltage of 1 V, unless otherwise noted.
Fig. 3.10 shows output characteristics and transfer characteristics on a standard 65 nm highperformance device with W = 96 pm. The normalized drain current of the device is around 771
mA/mm at VGs
= VDS =
1 V.
...............
...........
- .-.......
......
.....
..
700
700
65 nm HP CMOS
600
600
W= 2x24x2 pm
L= 50 nm
__%
E 500
E 500
E
VDS=1 V
E
400
S400
E
E
* 300
"300
200
200
100
100
50 mV
0
0
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
VGS
VDS(V)
0.8
1
)
Fig. 3.10. Output characteristics (VGS = 0.2 V to I V in steps of 0.2 V) and transfer
characteristics(VDS = 0.05 V and VDs = 1 V) on the standard65 nm HP device (W = 96 pm).
300
N
M
0
250
Is
250
N
200 X
0
x
200
150
a)
E
1)
150
M
100 -D)
E 100
rn
.a
E
50 C)
50
10
100
1000
10000
- 0
100000
Device Width (gm)
Fig. 3.11: De-embedded fT and fax, measured on 65 nm HP CMOS devices, are shown as a
function of device width.
...........
S-parameter measurements were performed at various DC bias conditions in the 0.5 GHz to
40 GHz range. These S-parameters were then de-embedded to the intrinsic device using
measurements on on-wafer de-embedding structures that were custom designed for each device.
Fig. 3.11 plots the extracted de-embedded fT and fma as a function of device width for 65 nm HP
CMOS devices. The figure shows that fT is fairly constant with device width at low bias current
(ID
=
25 mA/mm), but decreases with device width at the higher bias current (ID= 200 mAlmm).
On the other hand, fmax shows a significant decrease with device width at both bias currents. The
reasons for this degradation in the frequency response of wide devices will be explained in
chapter 5.
80
40
70
35
60
30
50
25
0
Uj40
20
30
15
20
10
10
5
0
0
0
5
15
10
20
Output Power (dBm)
Fig. 3.12: Typical power sweep on several 65 nm HP devices. The maximum Pout, PAE and Po, /
Ware also shown in the figure.
Fig. 3.12 shows RF power sweeps at 2 GHz and at a DC bias of VDD
=
1 V and
ID
=
200
mA/mm. The maximum normalized output power at this frequency and bias was measured on
the 48 gm wide device as 122.2 mW/mm. The maximum PAE was 72.4% as measured on the
56
..........
........
192 pm wide device, and the maximum output power was 77.2 mW on the 1536 gm wide
device.
RF power measured in the 2 GHz to 18 GHz range, and at a DC bias of VDD
=
1 V and
ID
=
25 mA/mm, is shown as a function of device width in Fig. 3.13. The source and load impedances
were optimized for peak PAE for each of these measurements. The figure shows that the output
power scales ideally with device width, and is relatively independent of frequency for W < 400
jim. However, for W > 400 jim, the output power starts to saturate, and in some cases even peaks
and then starts dropping. As the frequency of operation increases, the peak of the output power
happens at lower device widths. Thus, as the frequency increases, the maximum output power, at
any given DC bias, decreases. This is similar to the behavior observed in [33].
25
E
-- 2 GHz
-- 6 GHz
-- 10 GHz
20
-+14GHz
+018GHz
15
0
lob
10
65nmHPCMOS
o5
,
VDD =1 V
ID=
25
mA/mm
0
10
100
1000
10000
100000
Device Width (gm)
Fig. 3.13: Output power, measured at different frequencies, as a function of device width, for 65
nm HP CMOS devices. VDD = IV, ID = 25 mA/mm.
.........
.
....
....
..
...........
............
..............
.............
.. ....
...
The measured peak PAE, corresponding to the output data of Fig. 3.13, is shown as a function
of device width in Fig. 3.14. PAE decreases with increasing device width and with increasing
frequency. This behavior is similar to that observed in previous sections and in [33], and can be
attributed to a decrease in fmax in the wider devices. Further details can be found in section 3.3.2
and in chapters 4 and 5.
Higher levels of output power can be obtained by biasing the device at larger drain currents.
Fig. 3.15 and Fig. 3.16 show output power and peak PAE measured at VDD
=
1 V and ID
200
mA/mm. The behavior is similar to that seen at lower drain currents (Fig. 3.13 and Fig. 3.14).
However, there is no discernable peak seen in the output power versus width curves because the
maximum device width that could be measured was limited by the 500 mA current rating of the
bias tees in the power measurement system.
80
+*2G Hz
+6 GHz
+*10G Hz
-o-1 4 GHz
-w-1 8 GHz
-O70
60
5 50
4)
40
030
65 nm HP CMOS
L
020
0
VDD=1V
ID=
-10
0
10
25 mA/mm
0
100
0
1000
10000
1
100000
Device Width (gm)
Fig. 3.14: PAE measured at different frequencies, as a function of device width for 65 nm HP
CMOS devices. VDD = IV, ID = 25 mA/mm.
..........
20 18 -
16 -
E
I 14 -- 2 GHz
12 -
-+6 GHz
-- 10 GHz
-- 14 GHz
+w18GHz
0 10 -
8
6
65 nm HP CMOS
0
VDD=l V
ID=
2 00
mA/mm
.1
100
10000
1000
Device Width (gm)
Fig. 3.15: Output power, measured at different frequencies, as a function of device width, for 65
nm HP CMOS devices. VDD = IV, ID= 200 mA/mm.
80
-- 2 GHz
-6
070
060
0
-50
GHz
+10 GHz
-o14 GHz
-w-18 GHz
-
W 40 -
V
-30
-
C
65 nm HP CMOS
M20 0
VDD = 1 V
0-1 0
ID=
200 mA/mm
100
1000
10000
Device Width (gm)
Fig. 3.16: PAE measured at different frequencies, as a function of device width for 65 nm HP
CMOS devices. VDD = IV, ID = 200 mA/mm.
............
45 nm Low Power Technology
3.3
This section will present DC, S-parameter, and RF power data measured on devices designed
in 45 nm LP CMOS technology. There were 2 sets of designs in this technology. In the first set,
the device width was increased by either increasing the number of gate fingers or the unit finger
width. We will refer to the devices in this set as "old" test structures [46]. In the second set, a
unit cell was created with 20 fingers of 2 jim finger width, and the device width was increased by
connecting multiple unit cells in parallel. The devices in this set will be called "new" test
structures. The unit cell design in the new test structures was optimized for reduced parasitic
resistances and capacitances as described in Chapter 2. All devices in both the "old" and "new"
test sets were designed with a gate length of 40 nm and operate at VDS
1.1 V, unless indicated
otherwise.
3.3.1 Old Test Structures
500
500
450
45 nm CMOS
400
W=60 x1.5sm
L=0nm
350
O 350
E 300
E 300
VDS=l11V
E
E
250
E 250 .
45nm CMOS
W60 x1.5 pm
L40 nm
450
400
, 200
200
150
-9 150
100
100
50
50
0
0
0
0.2
0.4
0.6
VDS (V)
0.8
1
1.2
Vs= 50 mV
0
0.2
0.4
0.6
0.8
1
1.2
VGS (
Fig. 3.17: Output characteristics (VGS = 0.4 V to 1.1 V in steps of 0.1 V) and transfer
characteristics(VDS = 0.05 V and VDS = 1.1 V) on the standard45 nm device (W = 90 m).
.............................................
..........
::. .. ......
.
.. ...............
A variety of test structures were designed with varying number of gate fingers and gate finger
width to explore the optimum design that provides the best frequency and power performance.
Fig. 3.17 shows the output characteristics and transfer characteristics measured on a test structure
with 60 fingers of 1.5 gm finger width, resulting in a total device width of 90 pm. The
normalized drain current density on this device was measured to be around 466 mA/mm at VGS =
VDS= 1.1 V.
300
400
45 nm CMOS
250
W = 20x1.5 gm
VD= 1.1 V
doublecontact
350
300
200
single contac
250
150
double contact
100
200
N
"
150
100
50
50
0
1
10
100
0
1000
D(mAmm)
Fig. 3.18: fT and fax as a function of drain current density for single and double gate contact
structuresin 45 nm CMOS technology.
It is well known that contacting the gate on both sides of the device could result in lower gate
resistance and hence improved fmax. To quantify the improvement in fmax and output power, we
designed test structures in which the gate was contacted on only one side of the device (single
contact), or on both sides of the device (double contact). Fig. 3.18 compares the de-embedded
fT
and fmax of a single gate contact structure with that of a double gate contact structure as a
function of bias current. A double gate contact results in a significantly lower gate resistance,
.-
I
.
-
:
.
ZZ Z
Z
..
I.. II -
I
IIIIIII
.. I
... .. II I.IIII I.III .
but a slightly higher gate capacitance. This leads to a slightly lower fT for the double gate contact
structure compared to single gate contact at the same drain current density. However, fma, is
higher in the double gate contact structure because the reduction in gate resistance more than
compensates for the increase in gate capacitance. The improvement in fmax is more pronounced at
higher current densities.
160
100
140
doublecontact
90
80
g~~~
single contact
70
out
atu. 120
E
E
double contac100
60
50
80
--
single contact
PAE
<
C 40
60
30
W = 20x1.5 gm
20
VD=l1-1V
2 00
ID=
mA/mm
45 nm CMOS
40 C0
200
10
---
0
0
'-
5
20
-
0
-
----
10
15
20
Frequency (GHz)
Fig. 3.19: PAE and normalized output power as a function of measurementfrequency for single
gate and double gate contact structures in 45 nm CMOS technology.
Fig. 3.19 shows the PAE and normalized output power (Pout/W), measured at ID = 200
mA/mm and VDD
=1.1
V, as a function of measurement frequency for the single and double gate
contact structures. The load and source impedances were tuned for optimum PAE and the output
power and PAE were measured at peak PAE. The PAE for the double gate contact structure is
similar to that of the single gate contact structure. The PAE is also remarkably frequency
independent. The output power is slightly higher for the double gate contact structure. All the
..............
.................................................................
.........
test structures discussed in the remainder of this section were designed with double sided gate
contacts.
Fig. 3.20 shows the impact of number of fingers (NE) and finger width (WF) on de-embedded
fmax. In general, increasing the total device width (through increase in WF or NF) results in a
significant decrease in fm.. For a given NF, increasing WF initially leads to an increase in fm, but
eventually fm, decreases as the gate resistance increases. The optimum unit finger width for this
technology is 1.5 pim. On the other hand, for a given WF, increasing NF leads to a decrease in
fma. This is because of the increased parasitic resistance resulting from the additional wiring
needed to connect all the fingers in parallel.
275
275
WFot =1.5 pm
250
250
N225
225
W
0
2200
04-
E 200
45nm CMOS
VDD=.1 V
ID= 200 mA/mm
W= 30 to 90 pm
175
150
0
,
1
a
2
45 nm CMOS
VDD=1,1 V
ID=200 mA/mm
175
WF= 1.5 pm
150
3
4
5
6
0
WF (pm)
20
40
60
80
100
120
140
NF
Fig. 3.20: De-embeddedf,n, as a function of unit finger width and number offingersfor all the
test structures of the "old test site". WF = 1.5 pm was found to be the optimum finger width for
the 45 nm CMOS technology.
Fig. 3.21 illustrates the maximum output power and efficiency that can be obtained from the
structures in the old 45 nm test site at f = 2 GHz, VDD
=
1.1 V, and ID = 200 mA/mm. The source
and load impedances were optimized for maximum PAE when making these measurements and
all other power measurements presented in the remainder of this section. The maximum
normalized output power was measured on the 40
m wide device as 140.6 mW/mm, the
maximum power-added efficiency was measured on the 240 Rm wide device as 72.2% and the
maximum output power, measured on the widest device (W = 640 pm) was equal to 28.8 mW.
The peak PAE, measured at 2, 6, 10, 14 and 18 GHz, is shown as a function of total device
width for all the test structures of the old test site in Fig. 3.22. For the figure on the left, device
width is increased by keeping NF constant at 60 and increasing WF from 0.5 Rm to 5 gm. For the
figure on the right, device width is increased by keeping WF constant at 1.5 pm and increasing
NF
from 20 to 120. The dependence of PAE on device width is similar irrespective of whether
the device width is increased by increasing WF or NF. PAE increases with width for small device
widths (W < 100 pLm) because of an increase in power gain as a result of lower relative
80
Max. PAE = 72.2 %
VDD = 1.1 V
ID= 200mAmm
f = 2 GHz
!6 70
W =240 gm
o60
C
Max. P
0
= 28.8 mW
.o 50
W 40
V
W =40 gm
Max. Pout/W
=140.6 mW/mm
W =640 pm
30
2 20 0
a. 10
0
0
2
4
6
8
10
12
14
16
18
Output Power (dBm)
Fig. 3.21: Typical power sweep on several 45 nm CMOS devices, designed as part of the old test
site. The maximum Pout, PAE and Pou, / W obtainedfrom this test site atf = 2 GHz, VDD = 1.1 V
and ID = 200 mA/mm are also shown in thefigure.
64
...
....
.......
.........
0
w 40
30
NF= 60
10
VD= 1.1V
ID= 200 mAlmm
Constant WF
Ju
Constant NIF
20
............
.
42GHz
70
a6GHz
6
10GHz
14 GHz
5
00
.,
L0j40
18 GHz
I
2GHz
6GHz
10 GHz
18GHz
14GHz
WF=1.5 sm
WFI
VD= 1.1V
200
mA/mm
'D=
NF
t
.
0
50
100
150
200
250
300
350
50
Total Device Width (pm)
100
150
200
Total Device Width (pm)
Fig. 3.22: Peak PAE, measured at differentfrequencies, versus total device width. For the figure
on the left, device width is increased by keeping NF constant at 60 and increasing WF from 0.5
pn to 5 pun. For the figure on the right, device width is increasedby keeping WF constant at 1.5
pum and increasingNFfrom 20 to 120.
Constant WF
Constant NF
160 140
140
10GHz
,120
E
E
GHz
100
100
6 GHz
E80'
80
%E
14GHz
s 60
60'
NF= 60
0
M. AA
VD= 1.1V
20
00
120
ID= 200
50
WFt
mA/mm
100
150
200
Total Device Width (jim)
250
300
50
100
150
Total Device Width (pm)
Fig. 3.23: Normalized output power, measured at different frequencies, versus total device
width. For the figure on the left, device width is increasedby keeping NF constant at 60 and
increasing WF from 0.5 pm to 5 pn. For the figure on the right, device width is increased by
keeping WF constant at 1.5 pn and increasingNFfrom 20 to 120.
parasitics. For W > 100 tm, PAE is constant with width at lower frequencies but tends to
decrease with width at higher frequencies because of the reduction in gain with frequency.
The corresponding normalized output power is shown as a function of total device width in
Fig. 3.23. The output power shows no clear dependence on frequency, as expected, but shows a
gentle decrease with increasing width. This decrease in output power at large widths is because
of the non-ideal scaling of on-resistance in the wide devices, as described in section 3.4.
3.3.2 New Test Structures
A new set of test structures were designed in 45 nm low-power CMOS technology to explore
a wider range of device widths. In this set, the device width was increased by connecting
multiple unit cells in parallel. The unit cell was designed with 20 fingers of 2 gm finger width
(which is close to the optimum finger width found in the previous section). Further
improvements to the unit cell design were made to optimize the parasitic resistances and
capacitances, thus resulting in improved frequency and power performance (please see Ch. 2 for
layout details).
Typical output and transfer characteristics on a 2 cell device (total width of 80 mm) can be
seen in Fig. 3.24. The device delivers a normalized drain current density of 513 mA/mm at
VDS = 1.1 V.
VGS
...................................
600
45nm CMOS
500
W= 2x20x2 pm
500
VDs=1-1 V
L=40nm
400
E 400
E
E
E
E 300
300
200
200
100
100
~-----
-------
0
0.4
0.2
0
0.6
1
0.8
0
1.2
0
0.2
0.4
VDs (V)
0.6
VGS(VM
Output characteristics (VGS = 0.4 V to 1.1 V in steps of 0.1 V) and transfer
characteristics(VDs = 0.05 V and VDS = 1.1 V) on 45nm devices (W = 80 um).
Fig. 3.24:
275
-
250 -
225 N
0 200x
.
175 -
150 -
45 nm CMOS
VDD = 1.1 V
125 100
ID= 200 mA/mm
F -I-----------------u-
0
100
200
300
400
500
600
700
Device Width (pm)
Fig. 3.25: De-embedded fT and f.a as a function of device width for the new 45 nm test
structures,measured at VDD = 1.1 V and ID = 200 mA/mm.
S-parameter measurements were made in the 0.5 GHz to 40 GHz range and were deembedded using data on a common set of on-wafer open, short, load and thru structures. The
extracted de-embedded fT and fmax are shown as a function of device width in Fig. 3.25 for a DC
bias of VDD
=
1.1 V and ID= 200 mA/mm. fT is relatively constant with device width, but
fmax
decreases with increasing device width. This behavior is similar to what was presented on other
technologies in the previous sections.
RF power measurements were performed in the 2 GHz to 18 GHz range at VDD
ID=
=
1.1 V, and
200 mA/mm. Two sets of measurements were made on each device at every measurement
frequency. For the first set of measurements, the source and load impedances were tuned for
maximum PAE (as was the case for all the power measurements presented previously in this
chapter). For the second set, the source and load impedances were tuned to obtain the maximum
output power, while keeping the PAE still relatively high. In other words, it would be possible to
obtain more power from these devices at the expense of PAE.
Fig. 3.26 shows the PAE versus Pou, for three different 45 nm CMOS devices and illustrates
the maximum Pou1 t, PAE, and Pout / W obtainable from this technology at the given frequency and
DC bias. Tuning the load impedance for maximum power results in a maximum normalized
output power of 210 mW/mm at a PAE of 61.6% on the narrowest device, and a maximum total
power of 68.6 mW at a PAE of 48.6% on the widest device. This normalized power density is
the highest reported on any single 65 nm or 45 nm CMOS device. When the load impedance is
tuned for maximum PAE, a PAE in excess of 75% is obtained at 2 GHz, but Pout/W drops to 93
mW/mm.
..........
......
....... ...
...................
. ........
....
................
............
..........
..
.............................................................
80 -
W = 240 m
VDD = 1.1 V
eID = 200 mA/mm
f =2GHz
S70
--
Max. PAE =76 %
opt. PAE
A
o60
~W
C
4)
= 40 gm
opt. Pout
50
Max. Pout/W
W=
= 211.5 mW/mm
W 40
V)
( 30
4
a)
640 m
opt. P0 ut
Max. Pout
=68.6 mW
20
0
o. 10
0
0
2
4
6
8
10
12
14
16
18
20
Output Power (dBm)
Fig. 3.26: Power sweep showing PAE and Pourfor devices with different widths. The figure also
notes the maximum PAE, Po, and Pou, 1W obtained the new set of structures in 45 nm CMOS
technology.
Fig. 3.27 and Fig. 3.28 show Pout/W and peak PAE measured at 6 GHz as a function of device
width for the two impedance matching conditions. Both Pout/W and PAE decrease with
increasing device width. The width dependence is similar across all frequencies. This
dependence is similar to what was observed on other technologies in previous sections of this
chapter, and will be investigated further in section 3.4 and in chapters 4 and 5.
"I.-.......
...
..
....
......
. ..
......
..
..
250 -
45 nm CMOS
VDD = 1.1 V
200
ID=200mAmm
f = 6 GHz
E
150
Optimized for Max. Power
E
100
0
Optimized for Max. PAE
50
0
0
100
200
300
400
500
600
700
Device Width (gm)
Fig. 3.27: Normalized output power as a function of device width for the two impedance
matching conditions. Optimizingfor maximum power gives a higher Pou,/W at a lower PAE.
80 -
F 70 -
Optimized for Max. PAE
60 Optimized for Max. Powe?
0
.- .50-
W 40 V
30 45nmCMOS
20 0
0. 10
VDD= 1.1 V
ID=
200 mAmm
f=6GHz
0
)
100
200
300
.
400
.0
500
600
700
Device Width (gm)
Fig. 3.28: Peak PAE as a function of device width for the two impedance matching conditions.
Optimizingfor maximum PAE gives a higherPAE at a lower PouIWW.
.........
.. . .. ..
..
..
...
............
250 Optimized for Max. Power
200
E
E
150
Optimized for Max. PAE
E
100
s
0
45 nm CMOS
0.
50
-
VDD = 1.1 V
1D=
2 00
mA/mm
W =40gm
0
0
2
4
6
12
8
Frequency (G Hz)
14
16
18
20
Fig. 3.29: Normalized output power as a function of measurementfrequency. Pou, /W is relatively
independent offrequency for both impedance matching conditions.
70
0
45 nm CMOS
VDD= 1.1 V
lD= 200 mA/mm
65
W = 40 gm
60
p4
a)
'-
0
55
V
cc
50
4)
0oM 45
.3
8
10
12
Frequency (GHz)
20
Fig. 3.30: Peak PAE as a function of measurementfrequency. PAE decreases significantly with
increasingfrequency for both impedance matching conditions.
............ . .
. . , ..............
..................
Fig. 3.29 and Fig. 3.30 illustrate the frequency dependence of the normalized output power
and PAE. The normalized output power is independent of frequency, as expected. On the other
hand, PAE decreases significantly with increasing frequency. The frequency dependence of Pom /
W and PAE is similar across all device widths.
80
00ft%70
o60 W 50 -
609
."Optimized
for Max. PAE
50
e
Wi 40 "o
-30
Optimized for Max. Power
-
4 20 -
45 nm CMOS
o
VDD
OD
= 1.1 V
= 200 mA/mm
10
0
0
0.05
0.1
0.15
0.2
0.25
f/fmax
Fig. 3.31: PAE versus f/fma for 45 nm CMOS devices of different widths and measured at
variousfrequenciesfrom 2 GHz to 18 GHz.
The reason for the degradation in PAE with increasing frequency can be attributed to the
decrease in gain with frequency. The same argument can be used to explain the decrease in PAE
as the device width increases (Fig. 3.28). As was shown in Fig. 3.25, fmax decreases with
increasing device width. Hence, at the same frequency of operation, a wider device would be
operating closer to its maximum frequency limit compared to a narrower device, resulting in
lower gain in the wider device and thus degraded PAE.
.....................................................
..
.........
............
PAE has often be shown as a function of the ratio of the frequency of operation to the
maximum oscillation frequency of the device (f/fma) [33]. As f/fm
increases, gain of the device
decreases and hence PAE decreases. Plotted in this way, all the data on devices with different
widths, measured at various frequencies, falls on one universal curve for each of the impedance
matching conditions (Fig. 3.31).
3.4
Comparison among different technologies
So far we have presented a vast amount of frequency and power data on devices designed in
the 65 nm low-power, 65 nm high-performance and 45 nm low-power technologies. Now, we
will compare the power and frequency response of these technologies.
120
50 mA/mm
f =8 GHz
ID=
E 100%E
E
80
65 nm LP
~(1-2)2
VDD=1.2V
a)60 0
40 ,&
65 nm HP
VDD= 1 V
o 20
10
100
1000
10000
Device Width (gm)
Fig. 3.32: Output power versus device width for 65 nm low-power and 65 nm high-performance
devices, measured at VDs = VDD, ID = 50 mA/mm, andf = 8 GHz.
.......
.................
We will start with a comparison between the 65 nm low-power and high-performance
technologies. Fig. 3.32 and Fig. 3.33 show the output power and peak PAE as a function of
device width for devices designed in both 65 nm low-power and 65 nm high-performance
technologies, and measured at VDS
identical in both technologies.
= VDD,
ID
=
50 mA/mm, and f = 8 GHz.. The device layout is
It is clear from the figures that, while the measured PAE is
similar between the two technologies (Fig. 3.33), the measured output power is higher in the 65
nm LP technology (Fig. 3.32). The higher output power is expected because the supply voltage is
1.2X higher in the 65 nm LP technology.
70
60
65 nm HP
50
65 nm LP
VDD
VDD =
40
0- 40
1.2 V
30
20
ID = 50 mA/mm
f = 8 GHz
10
0
10
100
1000
10000
Device Width (gm)
Fig. 3.33: PAE versus device width for 65 nm low-power and 65 nm high-performance devices,
measured at VDS = VDD, ID = 50 mA/mm, andf = 8 GHz.
Fig. 3.34 compares the de-embedded fma versus device width for 65 nm devices and 45 nm
devices (both old and new structures). fma is extracted from S-parameters measured at
mA/mm and VDS
=
1 V on the 65 nm devices, and VDs
=
ID=
200
1.1 V on the 45 nm devices. The figure
..............................
...
..
shows that the 45 nm devices have a higher fmax than 65 nm devices, as expected. For the 45 nm
devices in the old test site, fmax is higher than the corresponding 65 nm devices for small device
widths, but drops sharply in the wider devices due to the presence of large interconnect
parasitics. A significant improvement in fax can be observed in the new 45 nm test structures,
where the device layout was optimized to reduce interconnect parasitic. The layout differences
between the 45 nm old and new test structures were described in Chapter 2.
300
VDS = VDD
N 250
N 250=
0
20 0
mA/mm
E 200
6 150
.0
E
-+-65nm HP
-*-45 nm old structures
- -45 nm new structures
100
S100
50
10
100
1000
10000
Device Width (gm)
Fig. 3.34:De-embeddedf,,a versus device width for 65 nm devices and old and new 45 nm device
structures.
Fig. 3.35 compares the output power versus device width for the 65 nm and 45 nm (old and
new) devices. The data was measured at 6 GHz with ID = 200 mA/mm and VDS
nm devices and VDS
=
=
1 V for the 65
1.1 V for the 45 nm devices. In general, the output power scales ideally
with device width for small device widths, but starts to saturate for the larger device widths. We
also observe that the measured output power on the old 45 nm devices is similar to that on the 65
nm devices, despite the 1.1X increase in VDD. The new 45 nm test structures perform much
75
I
' :::-
- - -Is -
.................
better, delivering a higher output power than the corresponding 65 nm devices. Even higher
output power can be obtained by optimizing the source and load impedances for maximum
power, instead of for maximum PAE. The reasons for this behavior can be understood by
examining the on-resistance of all these devices as a function of device width (Fig. 3.36).
60
VDS = VDD
200 mA/mm
f=6 GHz
50
'D=
E 40
o 30
CL
45 nmnew opt. Power
e 45 nm new opt. PAE
20
CL 20
3
i
A45 nm old opt. PAE
* 65 nm opt. PAE
10
0
0
200
400
600
800
Device Width (pm)
Fig. 3.35: Output power versus device width for 65 nm devices and old and new 45 nm device
structures.
Fig.3.36 shows that the normalized on-resistance, for all devices in both the technologies,
increases with increasing device width instead of being constant with device width as expected
from ideal scaling. This non-ideal scaling of the on-resistance with device width is the main
contributing factor to the non-ideal scaling of output power at large device widths. Fig. 3.36 also
shows that Ron for the 45 nm devices is much higher than that for the 65 nm devices across all
device widths. This increase in Ro1 for 45 nm devices can be attributed to the larger interconnect
resistance associated with the thinner and narrower metal lines and smaller contacts in 45 nm
technology. The higher Ron of the old 45 nm devices would explain the lower output power on
76
those devices, especially on the wider devices, where Ro. plays a more dominant role.
Optimizing the device layout of the new 45 nm structures helped lower their Ro. thus improving
their output power to around (1.1)2 times that on the 65 nm devices.
1
0.9
VDS
0.05 V
0.8
E0.7
E
6 0.6* 0.5
+45nm
0.4
0.3
0.2 1
0
45nm new
ideal scaling
""65nm
o
200
old
HP
400
0
600
800
Device Width (gm)
Fig. 3.36: Extracted normalized on-resistance as a function of device width for 65 nm devices
and old and new 45 nm device structures.
A better way of comparing the output power delivered by 65 nm and 45 nm devices would be
to plot the measured output power as a function of the extracted on-resistance, as shown in Fig.
3.37. When plotted in this way, all the 45 nm device structures show the (1.1)2 times
improvement compared to the 65 nm devices, when compared at the same Ro,. A further
improvement in output power can be obtained by optimizing the source and load impedances for
maximum power instead of for maximum PAE, as seen in Fig. 3.37.
.
..
I,
.
.. ....................
....
80 VDS
-= VDD
200 mA/mm
f =6 GHz
70
ID=
60-
E
50-
1 45
nm new opt. Power
@45 nm new opt. PAE
A45 nm old opt. PAE
0 4
30
* 65 nm opt. PAE
O 2010 0
0
2
4
6
8
10
12
1.
Ron (Ohm)
Fig. 3.37. Output p ower versus on-resistancefor 65 nm devices and 45 nm old and new test
structures.
80
145
nm new opt. Power
70
P45 nm new opt. PAE
60
L45 nm old opt. PAE
0 65 nm opt. PAE
-- 50
E 40
4
30
Z
VDS = VDD
20
10
00.00
eA
,
ID
,*
*
=
200 mA/mm
f=6 GHz
+
0.05
0.10
0.15
.
0.20
1/(RL+Ron) (Ohm-1 )
Fig. 3.38: Output power versus 1/ (RL+Ron) illustratingthe universal behavior of measured data
for 65 nm and 45 nm (old and new) devices.
...........................
............
. ...........
....
.
......................................................................................................
.................
Output power also depends on the fundamental load resistance that the transistor drives. To
first order, the output power is approximately proportional to the reciprocal of (RL + Ron). In fact,
when we plot the measured output power as a function of 1/(RL + Ron), we observe that all the
data fall along a universal line, irrespective of the technology, layout or measurement condition
(Fig. 3.38).
80
~70
60
2 A
IA
40*
*
*
40
5 nm*nw
300
A 20
2 45 nm new opt. PAE
A 45 nm old opt. PAE
~10 -*465 nmopt. PAE
VDS
=VDD
ID =200mrA/rmm
0
0
0.05
0.1
0.15
0.2
f/ max
Fig. 3.39: PAE versus f/fmax illustrating universal behavior of measured data for 65 nm and 45
nm (old and new) devices.
Another universal relationship that was mentioned in the previous section is the dependence
of PAE on f/fmax. We had shown earlier that when PAE is plotted against f/fm
for 45 nm devices
of different widths and measured at various operating frequencies, all the data falls along a
universal curve, with the PAE decreasing with increasing f/fma, because of the decrease in gain
as the operating frequency approaches the maximum oscillation frequency of the device. Now
we extend this comparison to include other technologies. Fig. 3.39 shows the measured PAE at
ID
= 200 mA/mm and VDS
= VDD
for the 65 nm devices and the old and new 45 nm test
79
I
I,- -
I-
- -
- ...........
:: :.........
structures. All these measurements were performed with the source and load impedances
optimized for maximum PAE. It is clear that all the measured data fall along the same straight
line, further confirming the universal nature of this relationship.
3.5
Comparison with literature
In this section, we will compare the output power data presented in this thesis with the RF
power data published in literature [33-37]. Fig. 3.40 compares the normalized output power as a
function of device width for 45 nm, 65 nm and 90 nm devices. The output power is normalized
to both device width and supply voltage. The frequency of operation was not identical for all the
cases. However, we have shown earlier that output power is independent of frequency and hence
this comparison is still valid.
180
160
45 nm (this work)
[37]
nm 1.5
90
VDD=
V
140
/'VDD =1.1
V
120
%-100
65 nm (this work)
80
0
VDD = 1 V
60'O
60
40654045
n
nm [36]
20
[33]
+/VDD=
90 nm [34]
VDD
0
10
100
=
1 V
1000
10000
Device Width (gm)
Fig. 3.40: Normalized output power versus device width. The figure compares power data
presented in this thesis to the values reportedin literature.
It is clear from Fig. 3.40 that the normalized output power measured on the 45 nm devices in
this thesis is the highest ever reported so far. This high value for output power was achieved
through a combination of high DC drain current (ID
=
200 mA/mm), optimized device structures
that reduce interconnect resistance and thus Ron of the transistor, and by optimizing the source
and load impedance for maximum power when making the RF power measurements. The output
power measured on the 65 nm devices is also higher than that reported on similar devices in [33].
The main reason for this improvement is the increased DC drain current used when making the
power measurements (ID
= 200
mA/mm versus ID = 25 mA/mm in [33]).
90
80
70
,6
45 nm (this work)
E060 -VDD
(50
0
CL. 40
15
D- 30
=11V
/m[3
6
VDD = 1 V
o 20
10
65 nm (this work)
VDD = 1 V
45 nm [36]
VDD = 1.2 V
90 nm [37]
5
VDD = 1. V
0
0
10
20
30
40
Frequency (GHz)
Fig. 3.41: Output power versus operatingfrequency. The figure compares power data presented
in this thesis to the values reported in literature.
Fig. 3.41 shows the dependence of maximum output power on the frequency of operation.
The device width and operating voltage was different for each of the cases in the figure. The 90
nm devices in [37] had a device width of 40 jim, while the 45 nm devices in [36] had a device
width of 192 ptm. The 65 nm devices in [33] had different device widths at each operating
frequency: W = 12.288 mm at 2 GHz, W = 6.144 mm at 4 GHz, W = 3.072 mm at 6 and 8 GHz,
W = 768 jim at 14 GHz and W = 384 gm at 18 GHz. In our work, the maximum device width
that could be measured was limited by the 500 mA current rating on the bias tees in the power
measurement system. Hence, W = 1536 gm for the 65 nm devices and W = 640 gm for the 45
nm devices from this work.
The most extensive data among those published before is on the 65 nm devices in [33], and
showed that the output power drops below 10 mW around 20 GHz. Later work on 45 nm devices
showed that it is possible to obtain 10 mW of power even at frequencies as high as 35 GHz [36].
In this thesis, we presented data on 65 nm and 45 nm devices, measured at
VDS = VDD
and ID=
200 mA/mm, as a function of frequency. Fig. 3.41 shows that the measured output power from
our work is lower than that presented in [33] at frequencies below 8 GHz because of the much
higher device widths in [33]. However, at higher frequencies, our data is much higher than
previous reports. The main reason for improvement in 65 nm data is measurement at higher
current levels and that for improvement in 45 nm data is due to higher current levels as well as
optimization of device layout.
3.6
Summary
This chapter has presented extensive RF power data as a function of device width, frequency
of operation, and DC bias conditions, for devices designed in 65 nm low-power, 65 nm highperformance, and 45 nm low-power technologies. In general, the normalized output power is
independent of measurement frequency, but decreases with increasing device width. The main
reason for the non-ideal scaling of output power in wide devices is the increase in on-resistance
in wide devices because of their higher interconnect resistance. On the other hand, the PAE
82
decreases with increasing frequency, as well as with increasing device width. The reason for the
decrease in PAE in wide devices can be attributed to the degradation in fma with increasing
device width. Comparisons of frequency and power performance among the three technologies,
as well as comparison of measured data from this thesis to published literature have been
presented. Normalized output power of 210 mW/mm, peak PAE in excess of 75% and total
output power as high as 68.6 mW were measured on the 45 nm devices at a DC bias of VDS
=
1.1
V and ID= 200 mA/mm. The output power values are the highest reported for any 45 nm or 65
nm CMOS technologies.
84
Chapter 4
Model for RF Power
In the previous chapter we showed that output power decreases with increasing device width
and postulated that the main reason for this decrease was because the on-resistance (R,,) of the
devices does not scale ideally with device width. In this chapter, we will attempt to prove this
theory through a model that predicts the maximum output power delivered by a device for any
given DC operating point and the Ron of the device.
Accurate estimation of the maximum output power for a device at any given bias point is an
onerous task. Power amplifier designers often rely on RF power simulations using compact
device models. These simulations are very time consuming and the need for accurate compact
models means the power estimations are only accurate when designing in mature device
technologies. Moreover, the compact models for CMOS devices are usually tailored for digital or
low power RF applications and hence do not do a good job in modeling the device for large
signal swings beyond the nominal voltage of the technology. Also, power simulations at the peak
PAE point often lead to convergence issues and hence do not predict the peak power very well.
In view of all the challenges described above, it would be ideal to have a simple analytical
model that can accurately predict the maximum output power and the trade-off between output
power and PAE in a device. The analytical models presented in textbooks [45, 47-52] usually
85
ignore Ron and also assume zero
VDSsat.
However, to obtain high power, the device is usually
biased at a high drain current, which means the output power is strongly affected by R,. In this
chapter, we present an analytical model that correctly accounts for the on-resistance of the
device, thus allowing us to make accurate predictions of the output power and PAE. We will also
compare the power and efficiency predictions from this model to the measured loadpull data
from the previous chapter to validate the accuracy of the model.
4.1
Model Description
VDQ
RF
Choke
|DC
High Q "tank"
(tuned@fo)
-,+
VDS
+
VgS
VG
VG S
(N
-
RLV
+i
'2v
~
i37
etcZLz RL+JO
ZL=O
1K
to
2fo, 3fo, .... etc
Fig. 4.1: Circuitdiagram of a reduced conduction angle power amplifier.
The model described in this section is based on the overdriven class AB amplifier discussed
in [45]. Consider the power amplifier circuit shown in Fig. 4.1. The transistor is biased at the DC
operating point, (VGQ, VDQ). The current through the drain in the absence of RF input signal is
IDQ.
The DC bias to the drain is fed through an RF choke, which is assumed to have a very high
reactance at RF frequencies. The DC component of the gate-to-source voltage
(VGQ)
is higher
than the transistor threshold voltage (Vt). The AC component of the gate-to-source voltage (vgs)
is assumed to be a cosine wave with peak amplitude Vgs. The drain current (iD) would then be a
clipped cosine wave containing a DC component which flows through the RF choke
(IDC),
a
fundamental component (-ii) and harmonics (-i2 , -i3, -i4 , etc). The output (drain) of the transistor
is AC coupled to an RF load through the capacitor Cc. Cc is assumed to be large, such that the
voltage across the capacitor is constant and is equal to the average drain voltage,
VDC.
The RF
load consists of a fundamental load resistor RL, and a shunt connected parallel LC "tank" circuit
with its resonant frequency at the fundamental frequency of operation (fe). All harmonics in the
load current are assumed to be shorted by the tank circuit and hence generate no voltage. Hence,
the current flowing through RL is just the first harmonic, ii, and the voltage across RL, is thus
assumed to be sinusoidal, with a magnitude set by the load resistor.
Fig. 4.2 shows the waveforms for key voltages and currents in the power amplifier when
operated in the maximum power condition for a certain bias point and load resistance. The gateto-source voltage waveform can be expressed as
VGS
=
(4.1)
VGQ ± gs CoS &)t
When vGS < Vt, the device enters the cut-off regime and the drain current is zero. When vGS >
VG~sat,
the device enters the linear regime and the drain current is clipped at Iknee. For all other
values of vGS, the drain current is assumed to be cosinusoidal. The shape of the drain voltage
waveform is 180 degrees out of phase with the drain current waveform. When iD
= lknee,
pinned at the minimum value Vmin, and when iD = 0, the drain voltage is clipped at Vmax.
vDS
is
Vssat
-
VGQ
0
tnee
D
0
s/2
a/2
T
2Tr
3
T
2w
3w
Wt
Vmax
YDS
0 P/2
u/2
--
Wt
Fig. 4.2: Waveforms for input voltage and output current and voltage in the reduced conduction
angle amplifier shown in Fig. 4.1.
a denotes the conduction angle and represents the proportion of the RF cycle for which VGS >
Vt and iD> 0. Since the waveform is symmetric about ot = 0, the current cut-off points are at ot
=
--a/2. x = 2xE defines class A operation (the device is always ON), a = a defines class B
operation (the device is cut-off half of the time), a < a < 2a defines class AB operation, and 0 < a
< a for class C operation. 0 denotes the proportion of the RF cycle for which
VGS > VGSsat
and ID
= lknee.
From the shape of the drain current and voltage waveforms, it is clear that the average value
of iD (denoted by IDc) and the average value of vDS (denoted by VDC) depend on (x and P, along
88
with the minimum and maximum values of the waveforms. In general, IDC
t IDQ
and
VDC
#
VDQ,
as illustrated in Fig. 4.2.
Assuming that the drain current follows a pure cosine between G/2 and P/2, iD can be
expressed as:
Iknee
iD (Ot)
IDQ
+ Id
#
2
(4.2)
COS Ot
a
-2 < |wt| 7
0
The values of LI and I"e can be obtained by recognizing that the waveform needs to be
continuous at a/2 and P/2 and by applying the appropriate boundary conditions.
iD (kt
iD
= fl)
(Wt
(4-3)
IDQ + Id COS fl
nee=
(4.4)
= 0 = IDQ + Id CoS a/2
= -)
Solving equations (4.3) and (4.4) results in the following expression for the drain current:
Iknee
2
COSWt
-
iD (WO =DQ
a
COS~
/2
0
where
Iknee - IDQ
(1
2
#
l
-:5
2
lWt|I
a
2
(4.5)
7
cos(-/2)
cos(a /2))
(4.6)
The drain current can be written in terms of its Fourier series components as:
iD OJ
= IDC -
('1 + i2 + i3 +....)
(4.7)
=
IDC
-
Yl COS
t + I2 cos 2t
+ I3 cos 3t + ---)
The DC component of the drain current, IDC, is all the current that flows through the RF choke
and can be computed as
a
1
fDC
D
d(wt)
Imaxd(wt)+2f IDQ(
-2
__
p_
2
2
os a .(sin a
a - Cos fl)+(a-fl)
IDQ[/C
co 2
n
= os
Cos
sm
cs2
2
cos)
-
sin
.
2s
The fundamental component of the drain current is also the current that flows through the load
resistor, because we assumed that the DC component flows through the RF choke and that the
second and higher order harmonics are shorted out at the fundamental frequency of operation.
The magnitude of the fundamental component of the drain current is given by
I1 =f
_Ir
iD (Wt)cos
wt d(wt)
- #/2
=-
a/2
Imax cos wt d(wt) + 2
2
IDQ
0
1-
#/2
=
a
s
(os a
+Csa /si. a si.
+ co sm
-s
Substituting a = 271 and
cos td(ot)
cos9)
Cos
2
7 cos7-
a
)
2)
(a 4
P = 0 in equations
p)
-
(sin a - sin)
4
(4.8) and (4.9) gives IDC
IDQ
and 11
IDQ,
which
are the correct values for class A operation. Also, when fl = 2w - a, the waveform is symmetric
about IDQ and hence IDC
=
IDQ. For any other values of a or P, the average drain current that flows
through the RF choke (IDC), is not equal to the drain current at low power condition (IDQ) because
the drain current waveform is no longer symmetric about IDQ-
For calculating output power delivered to the load, we also need expressions for the drain-tosource voltage, VDS. Our model describes the maximum power situation for any given value of a(
and P. Hence, we assume a maximum voltage swing for vDS, that is symmetric about VDQ. In
other words,
Vmax - Vmin = 2(VDQ
(4.10)
- Vmin)
This assumption is valid for Class A, Class B and Class AB amplifiers and is consistent with
the assumptions in most power amplifier textbooks [45, 48, 50].
Thus Vmax can be written as
(4.11)
Vmax = 2VDQ - Vmin
where Vmin can be expressed in terms of Iknee and the on-resistance of the device (Ron) as:
(4.12)
Vmin = Iknee Ron = IDQRon 1 - cos(fl/2)
cos(a/2))
In general, the drain voltage waveform can be expressed as:
V<
VDS(Jt) =
Iwt|
0
Vmin
cs
<-
2
a
(max
-<IJWtI:
2
a
2
(4.13)
7
The value of Vo and Vd can be determined by applying the following boundary conditions:
vDS
VDs (aft =
Vmin
Vo +VdCOS
-Vmax= Vo + V CoS
Solving for Vo and Vdgives the following expression for vDS:
(4.15)
Vmin COS
VDS
-
0 < |at
Vmin
a
2
/
Vmaxcos
+
0
(ymax Vmin)cosWt
/a
a
cos -cscsos
CO2 -CS2
CO
(4.16)
2-2
COS 2
a- Iw !IT
Vmax
The magnitude of DC component of the drain voltage can be obtained by Fourier analysis of
equation (4.16) and is given by:
IT
f VDS(wt)d(Wt)
VDC
a
22
f
0
E
-
2
2
_
1
-
COS
__Ii
+ )min)
-
d(w) +
CO
ft COS -COS
+
X
[m
(Vmax - Vmin) (sin
C
-
f
OS
)
d(wt)
Vmax d(wt)
(4.17)
a
(-
Vmi - + Vmax (7
(COs
COS
a
COS- amin
Vmind(t) +
+(Vmin cos
2
+
- Vmax cos)
2(cos
-
(a-
p)
cos
-sin2)
-COS
The fundamental component of the drain voltage is the same as the voltage across the load
resistor, because we assumed that the average value of VDS drops across the capacitor Cc, and
that the second and higher order harmonics are shorted out at the fundamental frequency of
operation. The magnitude of the fundamental component of the drain voltage is given by:
7r
ffvDS(t)cos wt
Vi =
d(wt)
- T
2
=-
2Vmin cos wt d(wt) +
cos wt d(wt)
0
+
(Vmax
-
Cos
Vmin)
cos
t d(wt)
(4.18)
+
Vmax cos wt d(wt)
- cds
2
a
a
sin-+
Vminsin 2l- VmaxVmx2
(Vmax - Vmin)(a
4 (cos
-
(Vmin
Cos 7
Vmax COS 2
a
(COS 2 -COS
sin Z - sin)
/)
4 (cos
- COS
- COS
The output power and efficiency can be directly computed using the expressions for the DC
and fundamental components of voltage and current. The DC power is given by
PDC = VDQ ' IC
where
IDC
(4.19)
is given by equation (4.8).
The RF output power is given by
I1
out
-- - V-1
(4.20)
where 11 and V1 are shown in equations (4.9) and (4.18) respectively.
Finally, the drain efficiency can be computed as
7D
(%)
= Pot *
100
(4.21)
Pnc
The fundamental load resistance value that is associated with a particular choice of alpha and
beta can also be readily computed as
........
................
2
VD
-IDRon
1
Cos E
(4.22)
cos()
RL = Vmax - Vmin
'knee
cos(#/2))
600
Ron
45 nm CMOS
W=40gm
VGS=1.1V
500
imax
Ron = 9.59 Q
VGS = 1.0 V
400
E
E
VGS = 0.9 V
300
E
(VDQI DQ)
200
(VDC, 'DC)
VGS =0.7 V 4O%%
100
%
%
VGS = 0.5 V
--- --
0
0
~I.
-min
0.5
1
-1/R
1.5
L
7/%
%%
'I
2 max
VDs (V)
Fig. 4.3: Illustration of difference between DC and AC load line for RL = 100 2. The DC
operatingpoint is at VDQ = 1.1 V, IDQ = 200 mA/mm. The AC operatingpoint is at VDC = 1.1 V,
IDC = 212 mA/mm.
An examination of the drain current and drain voltage waveforms in Fig. 4.2 and the
expressions for IDC and VDC in equations (4.8) and (4.17) reveals that under large-signal AC
conditions, the average value of voltage and current through the drain of the device shifts from
the DC bias point under low input power conditions. This effect is called "self biasing" and
arises due to the asymmetry of the voltage and current waveforms. Hence, for any given RL, the
94
AC load line could be different from the DC load line. This difference is illustrated in Fig. 4.3,
drawn on the output characteristics of a typical NMOS studied in this thesis for the case when
VDC > VDQ
and IDC >
IDQ.
It should be noted that it is perfectly possible for IDC to be lower than
and similarly for VDC to be lower than VDQ.
IDQ
4.2
Comparison of Model with Measurements
The model equations presented above can be used to generate the drain efficiency - output
power locus for any given device. The inputs to the model are the DC operating point
(VDQ, IDQ)
and Ron of the device. Ron was calculated from measured DC data as VDS/ID with VDS = 50 mV
and the device biased in the linear regime. For any given value of ax and P, describing a random
maximum power condition, the value of output power, drain efficiency, average current and load
resistance can be computed using the expressions in section 4.1. This exercise was repeated for
multiple pairs of alpha and beta to construct the drain efficiency - output power locus.
Fig. 4.4 shows the modeled
11D -
Pout
locus for a wide range of ai and
0, along with
measured
data on a 45 nm device with W = 40 Jtm. To obtain the experimental power data, an initial power
sweep was performed, with the source and load conjugate matched, to determine the input power
level at which peak PAE is obtained. Next, the input power was fixed at this level and the load
impedance was varied across the Smith chart while keeping the source conjugate matched. From
this load pull data, the load impedance that delivers the maximum output power was determined.
A final power sweep was then performed to note the peak PAE and corresponding Pt. This
procedure was repeated for multiple values of RL.
The measured power data shows reasonable agreement with the modeled locus as seen in Fig.
4.4. The shape of the
11D -
Pout locus makes intuitive sense. For any given X,as
P is
increased,
more of the current waveform gets clipped at I"e, and more of the voltage waveform gets
95
clipped at Vmin. This leads to a decrease in the peak of the current waveform and a corresponding
increase in peak of the voltage waveform, which in turn leads to a decrease in IDC and 11 and a
corresponding increase in VDC and V 1. Since Pont =
2
, as
P increases,
P0 ut initially increases
because of the increase in V1, but then starts decreasing as the decrease in I1 starts to dominate.
On the other hand, since IDc decreases with increasing beta, the drain efficiency keeps
increasing. As a decreases towards class B operation (a = a), the peak of the current waveform
increases, thus leading to higher power.
8070a= 240
60 ~
a= 220
a= 190
=20
a= 260
a= 290
C 50QV
a=320
0
a=360
4030-
45 nm CMOS
W = 40 m
-1V
VDQ
20.
IDQ = 200 mAlmm
Ron = 9.59 Q
2
3
4
5
6
7
9
8
10
11
12
Output Power (mW)
Fig. 4.4: Modeled locus of drain efficiency versus output power. Pow, and riD measurements at
different RL are shown as symbols in the figure and show good agreement with the model.
Fig. 4.5 and Fig. 4.6 show the Po
0 t - RL locus and the
lD
- RL locus respectively, along with
the corresponding measured data. A reasonable agreement between the measured data and the
model is seen. For any given x, as
P is increased,
more of the current waveform gets clipped at
.................................................
....
...
....
.......
................
.....
..
...
Iinee, and more of the voltage waveform gets clipped at Vmin. This leads to a decrease in the peak
of the current waveform (Iee) and a corresponding increase in peak of the voltage waveform
(Vmax). Since RL
, RL increases for increasing values of
= Vmax-Vmin
'knee
0.
As a decreases, Iknee
increases leading to a decrease in RL. The evolution of Pout and ID with a and
P was
already
described in the previous paragraph. Hence, in general, Pout decreases with increasing RL, while
ID increases as RL is increased.
12a= 190
11 -
45 nm CMOS
W = 40 pm
10-
VDQ= 1.1 V
E
0
(D
=0
a= 210
0 7CL
6-
a= 220
a= 240
a=260
5L
0
= 200 mA/mmn
DQ
D
Ron = 9.59 Q
a = 00
a= 00
9-
a=290
4
a=32
a =360
32
0
I
50
I
I
I
100
150
200
250
300
R (Ohm)
Fig. 4.5: Modeled locus of output power versus load resistance. Output power measurements at
different RL are shown as symbols in the figure and show good agreement with the model.
....................
.......................
p =nC a=190
a = 200
70-
a= 210
a = 220
60-
a =240
a 260
5S50-
x =290
40-
2 30-
OW
a =320
a =360
45 nm CMOS
= 40 gm
VDQ = 1.1 V
= 200 mA/mm
20
Ro, = 9.59 Q
0
50
100
150
200
250
300
R (Ohm)
Fig. 4.6: Modeled locus of drain efficiency versus load resistance. Drain efficiency measured at
different RL is shown as symbols in the figure and shows good agreement with the model.
It should be noted that the model does not impose any constraints on the maximum current
drive of the device. In a real device, the drain current cannot exceed a certain saturated value.
This explains why the measured output power is not as high as the maximum Pout predicted by
the model.
Fig. 4.4 suggests that for a given drain efficiency, the model can predict the maximum output
power the device can deliver, or vice versa. We will use this fact to compute Pout as a function of
device width and compare the modeled values with the measured data. Fig. 4.7 shows the
measured TID (under both optimized power and optimized PAE conditions) as a function of width
for 45 nm CMOS devices. The measured data is shown as symbols. The solid lines show the
...
............
.
.... ..........................
values of lD that were used as input to the model, to predict the maximum output power at that
efficiency. The appropriate Ron and DC operating points were used in the model for each device.
The model assumes that only the first harmonic of the drain current flows through the load
resistance and that all the other harmonics are shorted out through perfect impedance matching at
the fundamental frequency. However, in practice the impedance match need not be perfect and
could result in non-zero values of second and higher order harmonics of the current. This would
result in an increased value of the output power and drain efficiency. This explains why the
maximum modeled drain efficiency was less than the measured values for some of the devices.
In such cases, the maximum modeled efficiency closest to the measured value was selected.
90
80
Optimized for PAE
model input
70 _0
60
Optimized for power
C
M 50 " 40
C
S30 20 -
45nm CMOS
VDD= 1-V
ID
10
200
mAmm
f=2GHz
0
0
100
200
300
400
500
600
700
Device Width (pm)
Fig. 4.7: Drain Efficiency as a function of device width. The solid line represents 77D specified in
model for predicting maximum Pout and optimum RL. The symbols are the measured 77D at 2 GHz.
...
...
..
.............
.....
.....
For any given drain efficiency, the maximum possible power predicted by the model, for any
combination of alpha and beta values, is recorded. The corresponding values of alpha and beta
are also noted and are used to calculate the average drain current and the load resistance.
Fig. 4.8 shows excellent agreement between the modeled values for maximum output power
and the measured data, across all device widths. Both the modeled and the measured data show
non-ideal scaling with device width, especially at large widths. Since the normalized DC
operating point is the same for all device widths, the only parameter that can explain the nonideal scaling of the output power is the on-resistance. Hence, we can conclude that the main
reason for the decrease in normalized output power with device width is because the onresistance of the devices does not scale ideally with device width.
80
VDD= 1-V
ID200
70
mA/mm
f=2 GHz
60
E
model output,,
Optimized for power
50
O 40 CL
= 30 -
Optimized for PAE
0.
02010 0
I
0
100
200
400
300
500
600
700
Device Width (gm)
Fig. 4.8: Output power as a function of device width. The solid line represents the maximum
0 , at 2 GHz.
output power predicted by the model. The symbols show the measured Po
100
............
...
.
....
.........
....
.................
..................
...............
....
The measured Pout on the 640 gm device is significantly lower than the modeled value (Fig.
4.8). This could be because of self-heating effects, which become dominant in the wide devices.
The self heating explanation is further borne out in Fig. 4.9, where the modeled and measured
values of the average drain current (IDC) are shown as a function of device width. In general, the
modeled IDC closely matches the measured values, thus validating the model. The measured IDC
on the 640 gm device is much lower than the modeled value, indicating the presence of self
heating in the device. This could be verified by measuring Ron at the expected temperature and
using that in the model to check if it predicts the measured value.
160
VDD= 1.1 V
140
ID= 200mAmm
f=2GHz
120
100
E
-
Optimized for power
model output
80
60
40
Optimized for PAE
20
0
100
200
300
400
500
600
700
Device Width (gm)
Fig. 4.9: Average drain current as a function of device width. The solid line represents the
average drain currentpredictedby the model. The symbols show the measuredIDC at 2 GHz.
Fig. 4.10 shows the load resistance used in the power measurements (symbols), as well as the
value of RL computed from the model (solid lines). The modeled values show reasonable
agreement with the measurements. This means designers can use this model to not only predict
101
the maximum output power of a device for any given drain efficiency, but also to accurately
compute the load resistance needed to achieve the required power. Output matching networks
can then be designed to present this resistance to the load.
180
45 nm CMOS
160 -
VDD=l1l V
E41
E 140-
'D=
200
mA/mm
f=2 GHz
.
0 120
C 100
0
model output
60
0
40 -
Optimized for PAE
20
0
I
0
100
200
300
400
500
I
I
600
700
Device Width (pm)
Fig. 4.10: Load resistanceneeded to obtain maximum Po,. Solid line is optimum RL predicted by
model. Symbols are measured data at 2 GHz.
4.3
Discussion
The model presented in this chapter shows that the maximum output power is strongly
affected by the Ron of the device. Hence, the power capability of a device can be improved by
designing it to have a lower Ro,. One way to decrease source and drain resistance and thus Rn is
by placing additional contacts in the source and drain regions of the device. We designed a test
structure where the distance between the gate fingers was increased to twice that in a standard
device. This allowed us to place twice as many contacts in the source and drain regions. A
102
comparison of the Ron and the power parameters of the two structures is shown in the table
below:
Parameter
Standard test structure
New test structure (W = 2x20x2 gm)
(W = 2x20x2 gm)
2X spacing between gate fingers
Measured
Modeled
Measured
Modeled
VDQ (V)
1.1
1.1
1.1
1.1
IDQ (mA/mm)
200
200
200
200
Ron (Q)
5.3
5.3
4.7
4.7
Pout (mW)
15.3
15.3
17.9
17.4
67.6
65
66.5
65
IDC (mA)
20.6
21.4
24.5
24.4
RL (A)
38.6
39.6
30.3
33.9
1iD
(%)
Table 4.1: Measured and modeled values of DC and RF power data on two different test
structures designed in 45 nm CMOS technology. Details of the standard device layout can be
found in Chapter2. The spacing between gate fingers in the new test structure is twice that in the
standardstructure.
The table shows that increasing the number of source and drain contacts decreases the onresistance of the device. This in turn leads to a considerable increase in output power at the same
drain efficiency. The table also shows that the modeled Pont,
T'D,
IDC,
and RL are quite close to the
measured values. Thus, the model does an excellent job at predicting the power performance of
devices with different layouts.
In a CMOS device, Ron can be approximated as the sum of the source resistance (Rs) and
drain resistance (RD), since the channel resistance is typically much smaller than RD or Rs.
Hence, if we can estimate RD and Rs for any device layout, through parasitic extractions from
layout, we can predict the maximum Pout and 11D for that device. Thus, circuit designers can
103
estimate the power capability of their designs and optimize the design to achieve the necessary
power or efficiency targets.
4.4
Summary
A simple analytical model for the output power and drain efficiency of a CMOS device has
been presented. The model uses the DC operating point and on-resistance of the device as inputs
and gives out the maximum output power and the load resistance required to achieve that power
for a given drain efficiency. We have shown that the modeled values of Pout, 11D, and RL show
excellent agreement with the measured data on 45 nm CMOS devices, across a wide range of
device widths and device layouts. Circuit designers can use this model to estimate the power and
efficiency of their device, and optimize their device layout to meet performance targets.
104
Chapter 5
Small-signal Circuit Extractions
The previous chapters have shown that the primary reason for the non-ideal scaling of output
0 ) of the device with
power in wide devices is the increase in normalized on-resistance (Ro
increasing device width. It was also shown that PAE decreases with increasing device width,
mainly because the maximum oscillation frequency (fmax) of the device decreases with increasing
device width. In this chapter, we will explore the reasons for the increase in Ro
0 and decrease in
fmax in wide devices. This will be accomplished through small-signal equivalent circuit
extractions from measured S-parameters. We will also discuss the sensitivity of fT and fmax to the
different small-signal parameters and present analytical expressions for calculating fT and fma
from these parameters.
5.1
Small-signal Circuit Extraction Methodology
Accurate extraction of intrinsic device parameters requires appropriate de-embedding
structures. We used 65 nm devices in this chapter because of the availability of custom designed
open and short de-embedding structures for every device in this technology. The 45 nm devices
use a common set of de-embedding structures, and hence would require a much more
complicated equivalent circuit and extraction methodology to arrive at the intrinsic parameters of
the device.
105
.........
S-parameter measurements, from 0.5 GHz to 40 GHz, were performed on 65 nm devices of
different device widths, and the corresponding open and short de-embedding structures, at
various DC bias conditions. S-parameters were then de-embedded using the standard open and
short de-embedding technique, described in [42].
200
200
max
180
150
160
wN
N
N
--
100 Z:
0
&I fT"a
. 140
'4:WE
V
120
D_=
= 1V
50
100 mAlmm
100
10
Fig. 5.1: De-embeddedfT andfm,
total device width.
100
1000
Device Width (srm)
- 0
10000
measured at VDS=l V and at ID=100mA/mm, as a function of
Fig. 5.1 shows the de-embedded fr and fmax as a function of total device width at VDS
and ID=100 mA/mm. We find that
fT
=
1V
decreases from 142 GHz to 110 GHz and fmax decreases
from 190 GHz to 90 GHz as the device width is increased from 96 gm to 1536 in.
To understand the reasons for the degradation of fT and fmax in wide devices, we extracted the
small-signal equivalent circuit for these devices from the measured S-parameters. Several
different equivalent circuits and the corresponding high frequency parameter extraction
methodologies have been published in the literature [53-61]. We found that the equivalent circuit
topology shown in Fig. 5.2 works best for our devices. The circuit includes parasitic resistances
in the gate (RG), source (Rs) and drain (RD), transconductance (gm), output resistance (ro),
106
.........
. I'll .....
....
.....
.. .....
....
.......
.............
intrinsic gate-source (Cgs) and gate-drain (Cgd) capacitances, substrate resistance (Rsx), and
parasitic capacitances from the body to gate (Cgb), source
(Csb)
and drain
(Cdb).
C9d
Rg
Rd
G oQ^^^^
cgs
gV
: Cdb
Cgb-Fr
B
S 0O/
Fig. 5.2: Small-signal equivalent circuit of a MOSFET including parasitic resistances and the
substrate network.
The following methodology was followed to extract the small-signal parameters [62-64]:
1. The parasitic resistances were first extracted from the S-parameters measured at VGs=
VDS
= 0 V using the following expressions [53]:
RG = real(Z1 1 - Z1 2 )
(5.1)
RD = real(Z2 2
(5.2)
-
Z12)
Rs = real(Z1 2 )
107
(5.3)
2. Next, S-parameters measured at VDS
=
1 V, ID= 100 mA/mm, were converted to Z-
parameters. The parasitic resistances extracted in step 1 were subtracted from these Zparameters to obtain the intrinsic Z-parameters.
3. The intrinsic Z-parameters were then converted to Y-parameters. The rest of the
equivalent circuit parameters were then extracted from the intrinsic Y-parameters
using the expressions given below [53, 57]:
gm = real(Y2 1 )
=
Rs, =
c
1
real(Y22 )
(5.4)
(5.5)
real(Y22 + Y1 2 )
-)2(5.6)
(imag(Y22 + Y1 2 ))2
imag(Y11 + Y1 2 )
C9a =
Cd = Csb -
imag(Y1 2 )
imag(Y22 + Y12 )
(57)
(5.8)
(5.9)
(0)
4. Finally, the value of Cgb was determined by fitting the equivalent circuit model to the
measured S-parameter data in Agilent ADS. We found that the extracted value of Cgb
was usually very small (several fF). However, inclusion of Cgb in the equivalent circuit
was crucial for accurate modeling of the unilateral gain (U) versus frequency.
The equivalent circuit parameters of a 96 tm wide device (2 unit cells of 48 gm width),
extracted using the methodology described above, from S-parameter measurements at VDS = 1V,
and
ID =
100 mA/mm are listed below:
108
. ..
............. ..............
..
........
. .....
................
.
RG=2.5 Q, Rs=2 Q, RD=3.25 Q, gm=0.107 S, ro=83 Q, Rsx=75 Q, Cgs= 5 6 if, Cgd=3 4 iF,
Cdb=Csb=1
20
fF, Cg=
3 8
.
f.
An equivalent circuit, with parameter values listed above, was input into Agilent ADS, and Sparameters were simulated in the 0.5 GHz to 40 GHz range. Fig. 5.3 compares the simulated Sparameters with measured S-parameters (VDs
=
1 V, ID= 100 mA/mm) on the 96 pm wide
device. It can be seen that the model shows excellent agreement with the measured data over the
entire frequency range.
Measred
Fig. 5.3: Measured and Modeled s-parametersat VDD=] V, ID=100 mA/mm. Measureddata is in
symbols and the model is the solid line. W=2x48 pm.
109
.......
...
..
..
..............
...........
Fig. 5.4 plots the modeled and measured short-circuit current gain (h21) and the unilateral
power gain (U) for the same device. It is clear that the model does an admirable job at predicting
not only the
fT
and fmax of the device, but also h2 1 and U over the entire frequency range. It
should be mentioned that the figure plots the absolute value of the unilateral gain. U is actually
negative at low frequencies (< 10 GHz) because of the positive feedback path between gate and
drain formed by Cgb, Cdb and Rsx Our model predicts even this negative U accurately.
its
1E18
IE11
Frequency (Hz)
Fig. 5.4: Short circuit current gain and unilateralpower gain as a function of frequency. W =
2x48 pm, VDD = 1 V, ID 100 mA/MM-
110
..............
'::
........
...
..
............
5.2
.............
......
......
Width Dependence of Equivalent Circuit Parameters
Small-signal equivalent circuit parameters were extracted for devices with total width ranging
from 96 jim to 1536 jim. The extracted gm,
gds,
Cgs and Cgd, normalized to device width, are
shown as a function of device width in Fig. 5.5. All these extracted intrinsic parameters are
relatively constant with device width.
Fig. 5.6 shows the normalized parasitic resistances across device width. Rs is constant across
width, but RG and RD increase with increasing width. Normalized RG increases by 120% and
normalized RD increases by 180% as the device width is increased from 96 gm to 1536 gm.
1.2
1
9m
0.8 E
E
E0.8
0.6
E
'U
0.6
0.4
E0.4
CL
.U
0.2
0
0
-- I 0
10
100
1000
10000
Device Width (gm)
Fig. 5.5: Normalized intrinsicparameters (g,,
1 V, ID = 100 mA/mm.
gds,
111
Cgs, Cgd)
as a function of device width. VDD =
..
...
........
.....
.........
.......
.............
800
700
1V
ID=lO0mA/mm
VDD =
-
E 600
Q
500
RD
400
RG
--
'300
a 200
100
0
10
1000
100
Device Width (sm)
10000
Fig. 5.6: Normalized parasitic resistances vs. device width. Parasiticresistances are extracted
from s-parametersmeasured at VDD=J V, ID=100 mA/mm.
2 cells
8 cells
Fig. 5.7: Schematic layout of a 2 cell (W = 96 pm) and 8 cell (W = 384 pm) device, showing the
need for additionalwiring to connect the 8 cells in parallel. This leads to an increasein parasitic
resistanceas the device width is increased.
112
The reason for the increase in normalized RG and RD with device width can be understood by
examining the layout of these devices. The device width in these transistors is increased by
wiring multiple unit cells in parallel. Fig. 5.7 shows the layout of a 2 cell device (W = 96 gim)
and an 8 cell device (W = 384 m). The additional wiring required to connect the extra unit cells
in the 8 cell device leads to an increase in the parasitic resistances in this device. Also, the drain
current needs to travel further to get to the unit cells on the left of the layout, and thus increases
the drain resistance even further. The ideal scaling of the source resistance can be explained by
the de-embedding structure design for these devices. When designing the open and short deembedding structures, the source metallization was kept identical to that in the corresponding
device, thus allowing de-embedding of the source up to the intrinsic diffusion layer. Hence, the
normalized source resistance is constant across device width. On the other hand, the gate and
drain can only be de-embedded till the metal 3 level, and hence show an increase in normalized
resistance with increasing device width.
We are now in a position to explain the reason for the non-ideal scaling of output power in
wide devices. We had previously shown that the reason for the power degradation is an increase
in normalized Ro, in the wide devices. For very short CMOS devices, R," ~ RD + Rs. Hence,
the main reason for the degradation in output power can be attributed to the increase in
normalized RD in the wide devices. Thus, a parasitic-aware approach is required when laying out
wide devices to avoid an increase in parasitic resistance and a corresponding decrease in the
power performance of the device.
5.3
fT, fmax Sensitivity to Equivalent Circuit Parameters
To examine the effect of the various small-signal parameters on
fT
and fmax, a sensitivity
analysis was carried out in ADS. The parameters were changed one at a time by 100% in a
113
..........................
.......
.......................................
.....
....
: .......
direction that would result in degradation in fT and fmax. Thus, the parasitic resistances and all the
capacitances were increased by 100%, while the transconductance and output resistance were
decreased by 100%.
-50
* f-r
m
-40
--,0
E -30
C
-20
C
-10
O
1
-j-
0
-
10
-RG
x2
20 JI
RD
x2
Rs
gm
ro
x2
2
2
C.,
x2
Cgd
x2
II
Scale ideally
Rsx Csb
x2
I|I|
x2
Cdb
Cgb
x2
x2
Minor Impact
Fig. 5.8: Sensitivity offTand fma to the various small-signal equivalent circuit parameters. The
figure plots the percentage decrease infT and fa,,xfor a 100% change in each of the parameters.
W=96 pm, VDD=l V, ID=100 mA/mm.
The results are shown in Fig. 5.8. The intrinsic parameters,
gm,
Cgs, Cgd, and to some extent ro,
show the most impact on both fT and fmax. However, Fig. 5.5 showed that these parameters scale
ideally with device width and hence could not be responsible for the degradation in f
with
device width. The substrate parameters, Rx, Cdb, Csb, and Cgb show very minor impact (less than
5%) on either fT or fmax. A 100% increase in Rs degrades fT by around 7% and improves fmax by
8%. But again Rs scales ideally with device width (Fig. 5.6) and thus cannot explain the
degradation in fma. This leaves the parasitic resistances RG and RD. fT shows no dependence on
RG and a small dependence on RD (13% decrease in fT for a 100% increase in RD). However, fmax
shows a much stronger dependence on both RG and RD (24% degrade in fmax with 100% increase
114
in either RG or RD). It was shown earlier in Fig. 5.6 that the normalized RG and RD increase with
device width. Thus, the improper scaling of RG and RD is responsible for the degradation of fmax
in wide devices.
To further validate our argument, we carried out the following exercise in Agilent ADS. The
equivalent circuit with small-signal parameter values equal to those extracted from the measured
S-parameters on the 96 gm wide device was simulated in ADS. The simulated
fT
and fm
were
found to be very close to the measured values (142 GHz and 180 GHz versus 142 GHz and 190
GHz respectively), lending credence to the model. Now the values of RG and RD were increased
by 120% and 180% respectively, keeping all other parameters constant. This increase in RG and
RD
correspond to the increase seen in the measured values for normalized RG and RD when the
device width was increased from 96 gm to 1536 pim (Fig. 5.6). The equivalent circuit with the
modified RG and RD is then simulated, resulting in
respectively. These simulated values for
fT
fT
and fmax of 112 GHz and 95 GHz
and fmax are very close to the measured values of 110
GHz and 90 GHz on the 1536 jim wide device. This means the decrease in the measured
fT
and
fmax, when the device width is increased from 96 jim to 1536 jim can be attributed entirely to the
increase in normalized RG and RD. Hence it can be concluded that the main reason for the
degradation in
fT
in the wide devices is an increase in parasitic RD and the reason for degradation
in fmax is the increase in parasitic RG and RD. The degradation in fmax leads to a corresponding
decrease in the output power and PAE in the wide devices.
5.4
Analytical Expressions for fT and fmax
A complete y-parameter analysis of the small-signal equivalent circuit shown in Fig. 5.2 was
carried out in an effort to obtain simple analytical expressions for
fT
and fma that correctly
account for the width scaling of the relevant elements. The substrate parameters, Rsx, Cdb,
115
Csb,
and Cgb were not considered in this analysis because they have negligible impact on
fT
or
fmax
(Fig. 5.8).
In the absence of these elements, and ignoring o and higher order terms, the y-parameters
can be approximated by:
Y1 '
jo>Cgs(1 + gds(RD + Rs)) +jO>Cgd(l
+ (9M + gds)(RD + RS))
(5.10)
D
-jwOCgs(gdsRs) UW&Cgd(l + (9in + gds)RS)
Ygn -j)Cgs(gdsRs) -jW)Cgd(l
D
9ds + jo>Cgs(gds(RG + RS))+
(5.11)
+ (gm + gds)RS)
(5.12)
j>Cgd(1 + (9m + gds)(RG + Rs))
(5.13)
D
Where:
D = 1+ YmRs + gds(RD + Rs + RGRs + RGRD + RDRS)
+joCgs(RG + Rs + gds(RGRS + RGRD + RDRS)
+jWCgd(RG
(5.14)
+ RD + gds(RGRS + RGRD + RDRS)
The short-circuit current gain, h 21 and the unilateral gain, U, can be expressed in terms of yparameters as:
h2
=
(5.15)
21
Y12
2
Y12 -Y211
4[real(Y 1 )real(Y22 ) - real(Y12 )real (Y2 1 )]
Approximate expressions for fT [65] and fmax can then be derived as:
116
(5.16)
...............
JT
2
C
1
+ R + Rs) + Cyd
1 + (RD + RS) ( m
...................................
..
))]
(5.17)
9mV1 + 9mRs + gds(RD + RS)
CgS(RG + Rs)gds(1 + 9mRs)
max
47
+Cg2d(( RG
D) (gm + ds) + (g
+CgsCgd(RG(grm +
2
+gds)
gds) + gmgds(SRGRS +
2
(2
(5.18)
RGRS + RGRD + 2RsRD))
+ 2RSRD) + g2RG Rs)
3 RGRD
The above expressions allow technologists and circuit designers to easily determine the
frequency metrics for a given device design. The traditional derivations for U and fm, [66] only
consider the effect of RG. We have also included the effect of Rs and RD to improve the accuracy
of the calculated fT and fmax.
200
200
180
calc fmax'A meas fmax
0
1-140
4eN
-
calc fT
150
10
o-
meas fT
50
120
VDD= 1 V
ID 100 mAlmm
100
10
.
.
100
1000
0
10000
Device Width (pm)
Fig. 5.9: Measured and calculatedfT and f,,, as a function of device width. Measured data in
solid symbols and lines and calculateddata in open symbols and dashed lines.
117
Fig. 5.9 shows the measured data for fr and fmax along with the values calculated using the
above expressions. The calculated values show excellent agreement with the measured data over
the entire range of device widths studied in this work.
5.5
Summary
In this chapter, we investigate the reasons for the decrease in fmax and increase in normalized
on-resistance, with increasing device width.
Small-signal equivalent circuit parameter
extractions across device width show that the main reason for
fT
and fmax degradation is the
increase in parasitic gate and drain resistances with width because of the presence of nonscalable parasitics in wide devices. The increase in parasitic drain resistance is also responsible
for the non-ideal scaling of on-resistance in wide devices. We have shown in previous chapters
that the non-ideal scaling of Ron leads to a decrease in output power with increasing device
width, and that the degradation in fmax with device width is the main contributor for the decrease
in PAE in the wide devices. Thus, the key to enabling CMOS for millimeter-wave applications is
a parasitic-aware approach when designing wide devices. The chapter also presents simple
analytical expressions for
fT
and
fmax
that allow circuit designers and technologists to easily
determine the frequency metrics of any device designed in a given technology.
118
Chapter 6
Conclusions and Suggestions for
Further Work
We have studied the frequency and power performance limits of RF CMOS devices in the 65
nm and 45 nm technologies. Most of the RF power measurements were performed with the
source and load impedances optimized for maximum power-added efficiency at a DC bias of
VDS = VDD
and
ID =
200 mA/mm. A maximum output power density of 122 mW/mm, a peak
PAE of 72% and a maximum total output power of 77.2 mW was measured on the nominal 65
nm high-performance devices
(VDD =
1 V) at 2 GHz. Higher output power levels at similar PAE
values were obtained on the 65 nm low-power devices, because of the higher supply voltage
(VDD =
1.2 V). A record output power density of 210 mW/mm, PAE in excess of 75%, and
maximum total power of 68.6 mW was measured on the 45 nm devices at VDS
=
1.1 V,
ID =
200
mA/mm, and f = 2 GHz. This record power density was made possible by optimizing source and
load impedances for maximum output power and through careful device layout for minimized
parasitic resistances and capacitances. If supply voltage is not a constraint, even higher power
levels can be obtained by using the 1/0 devices. The 2.5 V I/O devices in the 65 nm low-power
119
technology demonstrated a maximum output power density of 267 mW/mm and total power of
259 mW at ID
=
200 mA/mm and f = 8 GHz.
We have demonstrated that gate width scaling is an effective means to increasing total output
power in a device. However, output power does not scale ideally with increasing device width.
Instead, the output power density (Pout / W) decreases as the device width is increased. The
reason for this decrease in power density can be attributed to the non-ideal scaling of onresistance in wide devices. Increasing device width also results in a decrease in PAE because of
fmax degradation in wide devices. A decrease in fmax means that for a given operating frequency,
the device is operating closer to its maximum frequency limit and hence exhibits lower power
gain, which in turn leads to a decrease in the PAE. Power measurements across a broad
frequency range (2 GHz to 18 GHz) indicate that output power is independent of frequency, but
PAE decreases as the frequency increases.
A simple analytical model was developed for estimating the output power and efficiency of a
CMOS power amplifier. The model uses the DC operating point and on-resistance of the device
as inputs and gives out the maximum output power and the load resistance required to achieve
that power for a given drain efficiency. We have shown that the modeled values of Pout, TD, and
RL show excellent agreement with the measured data on 45 nm CMOS devices, across a wide
range of device widths and device layouts.
Power amplifier designers often rely on RF power simulations using compact device models
to predict the output power and PAE of their circuits. The compact device models are usually
very complex, containing more than 100 parameters to accurately model the device
characteristics. Hence the power simulations are a drain on both designer's time and
computational resources. Our simple analytical model would allow designers to quickly estimate
120
the maximum power and efficiency of their devices and circuits. They could even optimize their
device layouts to meet or improve on the power performance targets.
The measured power data and the analytical model suggest that the maximum output power
delivered by a device at any given bias point is only limited by the on-resistance of the device.
The device capacitances play a role in degrading the efficiency of the device. However, as long
as extra input power can be provided to charge the capacitors, one can always obtain the same
maximum output power. Hence, the key to obtaining high power levels in the millimeter-wave
regime is to design devices with minimized parasitic resistances.
Small-signal equivalent circuit extractions were performed on 65 nm devices to understand
the reason for degradation in on-resistance and fmx with increasing device width. The results
indicate that the non-ideal scaling of parasitic RD is responsible for the increase in normalized
Ro, in wide devices, while the non-ideal scaling of RG and RD contribute to the degradation in
fmax in the wide devices. The non-ideal scaling of RG and RD is due to the parasitics associated
with the additional wiring needed to connect multiple unit cells to obtain the required width.
Hence, the key to obtaining high power and efficiency levels from CMOS devices at high
frequencies is a parasitic aware approach when designing large devices.
Several device layouts were explored in an effort to reduce parasitic resistances and
capacitances. We found that designing an optimum unit cell and connecting multiple unit cells in
parallel was the most effective approach to design wide devices. When designing the unit cell, it
is essential to determine the optimum finger width for that technology. We found the optimum
finger width to be 1.5 jim for 45 nm technology. One approach to decreasing the parasitic source
and drain resistances is to increase the distance between gate fingers, thus allowing placement of
additional contacts in the source and drain regions. We demonstrated that increasing the gate
121
finger pitch to two times the minimum pitch specified in the design manual for 45 nm devices,
resulted in a decrease in Ron from 5.3 Q to 4.7 Q, and a corresponding improvement in output
power from 15.3 mW to 18 mW. We also reduced parasitic capacitances in 45 nm devices by
minimizing the overlap between gate poly silicon and metal levels and by wiring the gate, source
and drain regions using alternate metal levels. These layout modifications allowed us to
demonstrate significant improvement in fmax, Pout and PAE of 45 nm devices.
Future research can explore many of the aspects discussed in this thesis. The maximum
operating frequency in this thesis was limited by our load-pull measurement setup to 18 GHz.
Given the increased interest in using CMOS devices for millimeter-wave power applications, it
would be worthwhile to perform an extensive characterization of these devices in the 60 GHz to
80 GHz range. Also, all the devices explored in this thesis employ a poly silicon gate and thus
exhibit significant gate resistance. It would be interesting to study metal gate devices to quantify
the improvement in gate resistance and corresponding improvement in fmax, Pout and PAE in
these devices.
Several improvements could also be made to the analytical model for output power presented
in this thesis. At present, the model allows us to estimate the maximum output power and drain
efficiency for a device. Incorporating power gain and frequency into the model would allow us to
determine the PAE and also the evolution of efficiency with increasing frequency. Another area
to explore would be to extract parasitic RD and Rs from device layout and use those values in the
analytical model to predict maximum Pout and flD for that device. That would enable circuit
designers to estimate the power capability of their designs and optimize the design to achieve the
necessary power or efficiency targets.
122
Compact models for RF CMOS devices typically model the device behavior up to the
nominal operating voltage. However, for power amplifiers, the maximum voltage of operation
could be over twice the nominal voltage. Hence, it is worthwhile to study the validity of the
compact models in predicting the output power and PAE at millimeter wave frequencies. This
could be accomplished by simulating a single stage amplifier, that uses the compact model for
the device, at millimeter-wave frequencies, and comparing the simulation results to measured
load-pull data.
123
124
Appendix A
Device Library
A.1. 65 nm Test Structures
This section gives a listing of device structures designed for fabrication in IBM's 65 nm
technologies. The same device structures were fabricated in both 65 nm low-power and 65 nm
high-performance technologies. The only difference was the absence of open and short deembedding structures in the 65 nm low-power test site. Each device has a unique identifier (id) to
help locate it on the wafer. A map of device locations on wafer is shown at the end of the section.
A number of test structures were designed with increasing device width for the standard and
1/0 devices. The device width was increased by connecting multiple unit cells in parallel. The
details of the unit cell design were discussed in Chapter 2. The cell orientation column in the
tables below describes the orientation of the cells in each structure (The unit cells are arranged in
an X x Y array and wired together). Test structures with varying device lengths were also
designed for the standard devices to study the impact of gate length on frequency and power
performance. The 65 nm technology has three different threshold voltage options for the thin
oxide devices. The impact of the VT implant was also studied using appropriate test structures.
125
Open and short de-embedding structures were custom designed for some of the standard and
1/0 devices. The design of these de-embedding structures was discussed in chapter 2. A list of
the de-embedding structures can be found in the map at the end of this section.
Device Width Scaling (Standard Device):
Identifier
Gate Length
(nm)
Unit finger
width (jim)
# fingers
per cell
# cells
Cell Orientation
(X x Y)
Total
Width (gm)
N 001
50
50
50
50
50
50
50
50
50
50
50
50
50
50
2
2
2
2
2
2
2
2
2
2
2
2
2
2
24
24
24
24
24
24
24
24
24
24
24
24
24
24
1
2
4
8
16
32
64
128
216
336
440
528
640
728
1xi
2x1
2x2
2x4
2x8
4x8
4x16
4x32
6x36
8x42
10x44
12x44
16x40
18x44
48
96
192
384
768
1536
3072
6144
10368
16128
21120
25344
30720
38016
# fingers
# cells
Cell Orientation
Total
(X x Y)
Width ( m)
N002
N 004
N008
N016
N032
N064
*N128
N216
N336
N440
N 528
N640
N792
Device Width Scaling (1/0 Device):
Identifier
Gate Length
(nm)
DG 001
DG 002
DG 004
DG 008
DG 016
DG 032
DG 064
DG 128
DG 216
DG 336
DG 528
DG 792
230
230
230
230
230
230
230
230
230
230
230
230
Unit finger
width
( m)
per cell
2
2
2
2
2
2
2
2
2
2
2
2
24
24
24
24
24
24
24
24
24
24
24
24
1
2
4
8
16
32
64
128
216
336
528
728
1xI
2x1
2x2
2x4
2x8
4x8
4x16
4x32
6x36
8x42
12x44
18x44
48
96
192
384
768
1536
3072
6144
10368
16128
25344
38016
Unit
finger
width (gm)
2
#
fingers
per cell
24
#
cells
Cell
Orientation
(X x Y)
4x8
Total
Width (gm)
Device Length Scaling:
Identifier
LG 040
Gate
Length (nm)
40
126
32
1536
45
65
80
130
250
330
00
LG 045
LG 065
LG 080
LG 130
LG 250
LG 330
LG 5500
24
24
24
24
24
24
24
2
2
2
2
2
2
2
4x8
4x8
4x8
4x8
4x8
4x8
4x8
32
32
32
32
32
32
32
1536
1536
1536
1536
1536
1536
1536
VT Variations:
SLVT
SNFET
SHVT
Gate
Unit finger
# fingers
#
Cell Orientation
Lnmh
width (gm)
per cell
cells
50
50
50
2
2
2
24
24
24
32
32
32
(X x Y)
Total
i
VT
Implant
4x8
4x8
4x8
1536
1536
1536
Low VT
Regular VT
High VT
Placement of Various Test Structures on Wafer:
A.2. 45 nm "Old" Test Structures
This section gives a listing of device structures designed for fabrication in IBM's 45 nm low-
power technology. These test structures were part of the "Old" test site and were used to
investigate the impact of gate length, number of fingers, unit finger width, substrate ring
placement, and number of gate contacts on the frequency and power performance of 45 nm
devices. All device structures were designed containing a single cell and the gate width of the
127
devices was increased by increasing either the number of fingers or the unit finger width. Open
and Short de-embedding structures were also custom designed for each of the test structures to
allow proper de-embedding of S-parameter measurements to the intrinsic device. Further details
on the layout of these structures can be found in chapter 2.
Identifier
Gate Length
(pm)
Unit finger
width (gim)
# fingers
per cell
STD 101
STD 102
STD 103
STD 104
STD 105
STD 106
STD 107
STD 108
STD 109
STD 110
STD 111
STD 112
STD 201
STD 202
STD 203
STD 204
STD 205
STD 206
STD 207
STD 208
STD 209
STD 210
STD 211
STD 212
STD 301
STD 302
STD 303
STD 304
STD 305
STD 306
1
0.5
0.2
0.1
0.06
0.04
0.04
0.04
0.04
0.04
0.04
0.04
0.26
0.2
0.16
0.1
0.04
0.04
0.04
0.04
0.04
0.04
0.04
0.04
0.5
0.2
0.1
0.04
0.04
0.04
1
1.5
1.5
1.5
1.5
1,5
1.5
3
1.5
3
3
9
1.5
1.5
1.5
1.5
0.5
1.5
3
3
3
5
5
9
3
3
3
1.5
1.5
3
20
20
20
20
20
20
20
20
60
10
10
10
20
20
20
20
60
40
6
6
40
6
60
10
60
60
60
80
120
60
128
Total
Width
(m)
20
30
30
30
30
30
30
60
90
30
30
90
30
30
30
30
30
60
18
18
120
30
300
90
180
180
180
120
180
180
Gate Contact
(2 or 1 sides)
2
2
2
2
2
2
1
2
2
2
1
2
2
1
2
1
2
2
2
1
2
2
2
1
2
2
2
2
2
2
Substrate ring
to device
distance (gim)
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
...............
:.........
STD
STD
STD
STD
STD
STD
307
308
309
310
311
312
0.04
0.04
0.04
0.04
0.04
0.04
3
0.42
1
1
1.5
1.5
60
60
60
120
60
60
180
25.2
60
120
90
90
1
2
2
2
2
2
0.53
0.53
0.53
0.53
0.575
0.625
Placement of Various Test Structures on Wafer:
A.3. 45 nm "New" Test Structures
This section gives a listing of device structures designed as part of the "New" test site for
fabrication in IBM's 45 nm low-power technology. In this set, the device width was increased by
connecting multiple unit cells in parallel. The unit cell was designed with 20 fingers of 2 gm
finger width (which is close to the optimum finger width found from the study on the "old" test
structures). Further improvements to the unit cell design were made to optimize the parasitic
resistances and capacitances, to help improve the frequency and power performance. Due to
space limitation on the test vehicle, separate de-embedding structures could not be designed for
129
each of the device structures. Instead, a common set of de-embedding structures were designed
to allow proper de-embedding of S-parameter measurements to the intrinsic device. Further
details on the layout of these structures can be found in chapter 2.
130
Bibliography
[1] H. S. Bennett, et al., "Device and technology evolution for Si-based RF integrated circuits," Electron
Devices, IEEE Transactions on, vol. 52, pp. 1235-1258, 2005.
[2] M. I. Mona M. Hella, RF CMOS Power Amplifiers - Theory, Design and Implementation, 2002.
[3] M. Cooke, "CMOS reaches for 60 GHZ+ applications," Semiconductor Today, vol. 3, pp. 76-80,
2008.
[4] D. R. Vizard, "Millimeter-wave Applications: From satellite communications to security systems,"
Microwave Journal,vol. 49, pp. 22-27, 2006.
[5] J. Laskar, et al., "The Next Wireless Wave is a Millimeter Wave," Microwave Journal, vol. 50, pp.
22-39, 2007.
[6] C. H. Doan, et al., "Design considerations for 60 GHz CMOS radios," Communications Magazine,
IEEE, vol. 42, pp. 132-140, 2004.
[7] A. Cathelin, et al., "Design for millimeter-wave applications in silicon technologies," in Solid State
Circuits Conference, 2007. ESSCIRC 2007. 33rd European, 2007, pp. 464-471.
[8] H. H. Ali M. Niknejad, Ed., mm-wave Silicon Technology - 60 GHz and Beyond. 2008, p.App. Pages.
[9] A. Cathelin, et al., "Deep-submicron digital CMOS potentialities for millimeter-wave applications,"
in Radio FrequencyIntegrated Circuits Symposium, 2008. RFIC 2008. IEEE, 2008, pp. 53-56.
[10] B. G. Duixian Liu, Ullrich Pfeiffer, Janusz Grzyb, Ed., Advanced Millimeter-wave Technologies Antennas, Packagingand Circuits.2009, p.App. Pages.
[11] A. Niknejad, "Siliconization of 60 GHz," Microwave Magazine, IEEE, vol. 11, pp. 78-85, 2010.
[12]
B. Razavi, "Design of Millimeter-Wave CMOS Radios: A Tutorial," Circuits and Systems I:
Regular Papers,IEEE Transactions on, vol. 56, pp. 4-16, 2009.
131
[13] C. Y. Law and A. V. Pham, "A high-gain 60GHz power amplifier with 20dBm output power in
90nm CMOS," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE
International,2010, pp. 426-427.
[14] A. Siligaris, et al., "A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak
PAE in CMOS 65 nm SOI," Solid-State Circuits,IEEEJournal of, vol. 45, pp. 1286-1294, 2010.
[15] E. Cohen, et al., "60GHz 45nm PA for linear OFDM signal with predistortion correction achieving
6.1% PAE and &#x2212;28dB EVM," in Radio Frequency Integrated Circuits Symposium, 2009. RFIC
2009. IEEE,2009, pp. 35-38.
[16] K. Raczkowski, et al., "50-to-67GHz ESD-protected power amplifiers in digital 45nm LP CMOS,"
in Solid-State Circuits Conference - Digest of Technical Papers,2009. ISSCC 2009. IEEE International,
2009, pp. 382-383,383a.
[17] T. Kjellberg, et al., "A Compact Cascode Power Amplifier in 45-nm CMOS for 60-GHz Wireless
Systems," in Compound Semiconductor Integrated Circuit Symposium, 2009. CISC 2009. Annual IEEE,
2009, pp. 1-4.
[18] M. Abbasi, et al., "A broadband differential cascode power amplifier in 45 nm CMOS for highspeed 60 GHz system-on-chip," in Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE,
2010, pp. 533-536.
[19] T. Quemerais, et al., "A CMOS class-A 65nm power amplifier for 60 GHz applications," in Silicon
Monolithic IntegratedCircuits in RF Systems (SiRF), 2010 Topical Meeting on, 2010, pp. 120-123.
[20] W. L. Chan, et al., "A 60GHz-band 1V 11.5dBm power amplifier with 11% PAE in 65nm CMOS,"
in Solid-State Circuits Conference - Digest of Technical Papers,2009. ISSCC 2009. IEEE International,
2009, pp. 380-381,381a.
[21]
A. Valdes-Garcia, et al., "60 GHz transmitter circuits in 65nm CMOS," in Radio Frequency
IntegratedCircuits Symposium, 2008. RFIC 2008. IEEE, 2008, pp. 641-644.
[22] D. Dawn, et al., "60GHz CMOS power amplifier with 20-dB-gain and 12dBm Psat," in Microwave
Symposium Digest,2009. MIT '09. IEEE MTT-S International,2009, pp. 537-540.
132
[23] J. Yung-Nien, et al., "Design and Analysis of a 55&#x2013;71-GHz Compact and Broadband
Distributed Active Transformer Power Amplifier in 90-nm CMOS Process," Microwave Theory and
Techniques, IEEE Transactions on, vol. 57, pp. 1637-1646, 2009.
[24]
T. LaRocca, et al., "60 GHz CMOS Amplifiers Using Transformer-Coupling and Artificial
Dielectric Differential Transmission Lines for Compact Design," Solid-State Circuits, IEEE Journal of
vol. 44, pp. 1425-1435, 2009.
[25] J. Brinkhoff, et al., "A 60 GHz transformer-based variable-gain power amplifier in 90nm CMOS,"
in Radio-Frequency Integration Technology, 2009. RFIT 2009. IEEE InternationalSymposium on, 2009,
pp. 60-63.
[26] K. Jing-Lin, et al., "A 50 to 70 GHz Power Amplifier Using 90 nm CMOS Technology," Microwave
and Wireless Components Letters, IEEE, vol. 19, pp. 45-47, 2009.
[27] N. Kurita and H. Kondoh, "60GHz and 80GHz wide band power amplifier MMICs in 90nm CMOS
technology," in Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE, 2009, pp. 3942.
[28] M. Bohsali and A. M. Niknejad, "Current combining 60GHz CMOS power amplifiers," in Radio
FrequencyIntegrated CircuitsSymposium, 2009. RFIC 2009. IEEE, 2009, pp. 31-34.
[29] D. Chowdhury, et al., "A 60GHz 1V + 12.3dBm Transformer-Coupled Wideband PA in 90nm
CMOS," in Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE
International,2008, pp. 560-635.
[30] L. Jau-Jr, et al., "Wideband PA and LAN for 60-GHz Radio in 90-nm LP CMOS Technology," in
Compound SemiconductorIntegratedCircuits Symposium, 2008. CSIC '08. IEEE, 2008, pp. 1-4.
[31] K. Maruhashi, et al., "60-GHz-Band CMOS MMIC Technology for High-Speed Wireless Personal
Area Networks," in Compound Semiconductor Integrated Circuits Symposium, 2008. CSIC '08. IEEE,
2008, pp. 1-4.
[32] Y. Yoshihara, et al., "A 60-GHz CMOS power amplifier with Marchand balun-based parallel power
combiner," in Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian, 2008, pp. 121-124.
133
[33] J. Scholvin, et al., "Fundamental Power and Frequency Limits of Deeply-Scaled CMOS for RF
Power Applications," in Electron Devices Meeting, 2006. IEDM '06. International,2006, pp. 1-4.
[34]
J. Scholvin, et al., "Performance and limitations of 65 nm CMOS for integrated RF power
applications," in Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International,2005, pp.
369-372.
[35]
J. Scholvin, et al., "RF power potential of 90 nm CMOS: device options, performance, and
reliability," in Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International, 2004, pp.
455-458.
[36] M. Ferndahl, et al., "Deep Submicron CMOS for Millimeter Wave Power Applications," Microwave
and Wireless Components Letters, IEEE, vol. 18, pp. 329-331, 2008.
[37] M. Ferndahl, et al., "90-nm CMOS for microwave power applications," Microwave and Wireless
Components Letters, IEEE, vol. 13, pp. 523.-525, 2003.
[38]
Z. Luo, et al., "High performance and low power transistors integrated in 65nm bulk CMOS
technology," in Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International,2004, pp.
661-664.
[39]
A. Steegen, et al., "65nm cmos technology for low power applications," in Electron Devices
Meeting, 2005. IEDM Technical Digest. IEEE International,2005, pp. 64-67.
[40] J. Yuan, et al., "A 45nm Low Cost Low Power Platform by Using Integrated Dual-Stress-Liner
Technology," in VLSI Technology, 2006. Digest of Technical Papers.2006 Symposium on, 2006, pp. 100101.
[41] J. Wang, et al., "RF Modeling of 45nm Low-Power CMOS Technology," presented at the Workshop
on Compact Modeling, 2009.
[42] M. C. A. M. Koolen, et al., "An improved de-embedding technique for on-wafer high-frequency
characterization," in Bipolar Circuits and Technology Meeting, 1991., Proceedingsof the 1991, 1991, pp.
188-191.
[43] J. Scholvin, Deeply Scaled CMOSfor RF PowerApplications, 2006.
134
[44] "Maury Microwave Corporation Automated Tuner System: Operating Manual," ed.
[45] S. C. Cripps, RF Power Amplifiers for Wireless Communications, 2006.
[46]
U. Gogineni, et al., "RF power potential of 45 nm CMOS technology," in Silicon Monolithic
IntegratedCircuits in RF Systems (SiRF), 2010 Topical Meeting on, 2010, pp. 204-207.
[47] B. J. Baliga, Siliicon RF Power MOSFETs, 2005.
[48] M. K. Kazimierczuk, "RF Power Amplifiers," 2008.
[49] D. M. Pozar, Microwave Engineering,1998.
[50] J. L. B. Walker, Ed., High-Power GaAs FETAmplifiers. 1993, p.App. Pages.
[51] M. Albulet, "RF Power Amplifiers," 2001.
[52] A. Grebennikov, RF and Microwave Power Amplifier Design, 2005.
[53] D. Lovelace, et al., "Extracting small-signal model parameters of silicon MOSFET transistors," in
Microwave Symposium Digest, 1994., IEEE MTT-S International,1994, pp. 865-868 vol.2.
[54] G. Dambrine, et al., "A new method for determining the FET small-signal equivalent circuit,"
Microwave Theory and Techniques, IEEE Transactionson, vol. 36, pp. 1151-1159, 1988.
[55] L. Seonghearn, "Direct extraction of small-signal model parameters for nanoscale MOSFETs," in
Future of Electron Devices, 2004. InternationalMeeting for, 2004, pp. 111-112.
[56] L. Seonghearn, et al., "A small-signal RF model and its parameter extraction for substrate effects in
RF MOSFETs," Electron Devices, IEEE Transactionson, vol. 48, pp. 1374-1379, 2001.
[57] C. Yuhua, et al., "MOSFET modeling for RF IC design," Electron Devices, IEEE Transactionson,
vol. 52, pp. 1286-1303, 2005.
[58]
Y. S. Chi, et al., "An Analytical Parameter Extraction of the Small-Signal Model for RF
MOSFETs," in ElectronDevices and Solid-State Circuits,2005 IEEE Conference on, 2005, pp. 555-558.
[59] K. Ickjin, et al., "A simple and analytical parameter-extraction method of a microwave MOSFET,"
Microwave Theory and Techniques, IEEE Transactionson, vol. 50, pp. 1503-1509, 2002.
135
[60] R. Torres-Torres and R. Murphy-Arteaga, "Straightforward determination of small-signal model
parameters for bulk RF-MOSFETs," in Devices, Circuits and Systems, 2004. Proceedings of the Fifth
IEEE InternationalCaracasConference on, 2004, pp. 14-18.
[61] M. T. Yang, et al., "Broadband small-signal model and parameter extraction for deep sub-micron
MOSFETs valid up to 110 GHz," in Radio Frequency Integrated Circuits (RFIC) Symposium, 2003
IEEE, 2003, pp. 369-372.
[62] U. Gogineni, et al., "Effect of Substrate Contact Shape and Placement on RF Characteristics of 45
nm Low Power CMOS Devices," Solid-State Circuits,IEEE Journal of, vol. 45, pp. 998-1006, 2010.
[63] U. Gogineni, et al., "Effect of substrate contact shape and placement on RF characteristics of 45 nm
low power CMOS devices," in Radio FrequencyIntegrated Circuits Symposium, 2009. RFIC 2009. IEEE,
2009, pp. 163-166.
[64] U. Gogineni, et al., "Modeling Frequency Response of 65 nm CMOS RF Power Devices," presented
at the TECHCON, Austin, TX, 2009.
[65]
P. J. Tasker and B. Hughes, "Importance of source and drain resistance to the maximum
fT
of
millimeter-wave MODFETs," Electron Device Letters, IEEE, vol. 10, pp. 291-293, 1989.
[66]
B. Razavi, et al., "Impact of distributed gate resistance on the performance of MOS devices,"
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on, vol. 41, pp. 750754, 1994.
136