In-situ Deposition of High-K Dielectrics on III-V Compound
Semiconductor in MOCVD system
by
Cheng-Wei Cheng
LIBRARIES
B.S. in Materials Science and Engineering
National Tsing-Hua University, 2001
ARCHPVEs
M.S. in Materials Science and Engineering
National Tsing-Hua University, 2003
Submitted to the Department of Materials Science and Engineering in Partial Fulfillment of the
Requirements for the Degree of
Doctor of Philosophy in Electronic Materials
at the
Massachusetts Institute of Technology
JUNE 2010
© 2010 Massachusetts Institute of Technology, All rights reserved.
Signature of Author
Department of Materials Science and Engineering
May 11 ,2010
Certified by
/7
Merton C. Flemings-SUA Pr fessor o
Eugene A. Fitzgerald
atei Is cience and Engineering
Thesis Advisor
Accepted by
Christine Ortiz
Chair, Departmental Committee on Graduate Students
In-Situ Deposition of High-K Dielectrics on I-V Compound
Semiconductor in MOCVD system
by
Cheng-Wei Cheng
Submitted to the Department of Materials Science and Engineering on
May I1 , 2010 in Partial Fulfillment of the Requirements for the Degree
of Doctor of Philosophy in Electronic Materials
ABSTRACT
In situ deposition of high-k materials to passivate the GaAs in metal organic
chemical vapor deposition (MOCVD) system was well demonstrated. Both atomic layer
deposition (ALD) and chemical vapor deposition (CVD) methods were applied in this
research.
The CVD aluminum nitride (AIN) was first selected to be in situ deposited on GaAs
surface by using trimethlyaluminum(TMA) and dimethylhydrazine (DMHy). However,
the frequency dispersion of Capacitance-Voltage (C-V) curves for in situ AIN/GaAs
samples are always large because of the existence of high interfacial defect state density
(Dit) due to the nitridization of the GaAs surface during the AIN deposition. In order to
avoid the surface reaction, in situ ALD of aluminum oxide (A120 3) on GaAs in MOCVD
system was proposed. Isopropanol (IPA) was chosen as the oxygen source for A12 0 3 ALD
and the mechanism was investigated. Pure A12 0 3 thin film was obtained and no arsenic or
gallium oxide was observed at the interface. Both frequency dispersion of C-V curve and
the Di, of oxide/p-GaAs interface are low for this process. In situ CVD A1 2 0 3 on GaAs
was also performed. Gallium oxide (Ga 2O 3) was observed at the interface. The Ga 2O 3
was enriched in the A1 2 0 3 above the interface during the deposition process and a
possible mechanism was proposed. This layer reduces the frequency dispersion of the
C-V characteristics and lowers the Dit of n-type GaAs sample.
After the in situ method had been successfully established, ex situ experiments was
also performed to compare the results with in situ process in the same MOCVD system.
Annealing native oxide covered GaAs samples in Arsine (AsH 3) prior to ALD A12 0 3
results in C-V characteristics of the treated samples that resemble the superior C-V
characteristics of p-type GaAs. Besides, both TMA and IPA show self-cleaning effect on
removing the native oxide in ex situ process. The discrepancy in the C-V characteristics
was observed in in situ p- and n-type GaAs samples.
Finally, the entire Dit energy distributions of interfaces from different processes were
determined
by
conductance
frequency
method
with temperature-variation
C-V
measurement. The existence of Ga 2O 3 at interface was found to be the possible source to
lower the density of mid-gap defect state. From the C-V simulation, the mid-gap defect
states are acceptor-like (Gallium Vacancies) and the source to cause high frequency
dispersion of the C-V curves for n-type substrate. The relation between the interfacial
defect state distribution and the processes was correlated.
Thesis Supervisor: Eugene A. Fitzgerald
Title: Merton C. Flemings-SMA Professor of Materials Science and Engineering
Table of Contents
List of figures.............................................................
8
--...........--
14
List of tables...............................................................
List of common Acronyms and Abbreviations in this thesis...............................15
17
Acknowledgements...................................................
Chapter 1 Introduction and Motivation.....................................................19
............ 20
1.1 Intro duction ..................................................................
1.2 Background (Fermi level pinning).........................................................21
................... 2 1
1.3 M otiv atio n ............................................................
1.4 O rganization of this thesis.................................................................
27
Chapter 2 Materials Growth and Characterizations........................................29
30
2.1 M aterials G row th.........................................................................
2.2.1MOCVD of GaAs and Surface Reconstruction structure of GaAs in MOCVD
sy stem ..................................................................................
31
2.1.2 ALD in MOCVD system..........................................................35
2.2 M aterials C haracterizations................................................................40
2.2.1 High-Resolution Transmission Electron Microscopy (HRTEM)..............40
2.2.2 Atomic force microscopy (AFM).................................................42
2.2.3 X-Ray Reflectivity (XRR)...........................................................43
2.2.4 Secondary ion mass spectroscopy (SIMS).......................................44
2.2.5 X-ray Photoelectron Spectroscopy (XPS)......................................45
2.3 C-V Characteristics of MOSCAP and Characterization...............................47
2.3.1 Ideal C-V Characteristics of MOSCAP..........................................48
2.3.2 Real C-V Characteristics of MOSCAP..........................................52
2.3.3Conductance-Frequency method to extract the Di, from C-V
measurements.............................................59
Chapter 3 In Situ CVD AlN on p-GaAs.......................................................62
.......... 63
3.1 Experim ental procedure.....................................................
3.2. Microstructure of AlN/GaAs interface................................................65
3.3 The chemical stoichiometry and bonding state of the AIN thin film.................66
3.4 C-V measurements and band structure of AIN/p-GaAs.................................68
3.5 C-V measurements and Interfacial defect density (D t)......................-71
Chapter 4 In Situ ALD A12 0 3 on p-GaAs.....................................................76
4.1 Experimental Procedure.................................................................77
4.2 Experiments of ALD with TMA and IPA................................................79
........ 82
4.3 Mechanism of ALD with TMA and IPA......................
4.4 Structure of the ALD A12 0 3 thin film.................................85
4.5 The chemical stoichiometry and bonding state of the A1 2 0 3 and A12 0 3/GaAs
...............
interface................................
....... 88
4.6 The C-V characteristics and the Di at ALD A12 0 3/p-GaAs interface................91
4.7Current-Voltage measurements and band structure of A12 0 3 / p-GaAs..............93
4.8 Thermal Stability of ALD A12 0 3 thin film and A12 0 3/GaAs interface...............98
4.9 Structure Defects in the ALD A120 3...................
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..101
Chapter 5 In and Ex Situ ALD A12 0 3 on p- and n-GaAs..................................110
..... 1 1
5.1 Experimental procedure....................................
3
5.2 Self-Cleaning effect of precursor set TMA/IPA.....................................11
5.3 Surface recovery by baking sample under AsH 3 ..............
. . . . . . . . . . . . . . . . . . . . . . . . 115
5.4 The bonding states of Gallium atoms at the interface................................117
5.5 The C-V characteristics and the Dit at in and ex situ ALD Al 2 0 3/GaAs interface
w ith IPA or H 20 as oxygen source.......................................................119
5.5. 1C-V characteristics of in and ex situ samples with IPA as oxygen source... 119
5.5.2C-V characteristics of ex situ samples with IPA or H20 as oxygen source. 121
5.5.3C-V characteristics of ex situ samples with surface recovery by annealing in
22
arsine before ALD of Al 2O 3 with TMA/IPA...................................1
5.5.4Dit distributions in the bang-gap for the samples extracted by the
room-temperature conductance-frequency method...........................1
23
Chapter 6 In Situ CVD A12 0 3 on GaAs.......................................................126
................... 127
6.1 Experim ental procedure...........................................
6.2 Experiments of CVD with TMA and IPA...
.....................
.... 129
6.3 Mechanism of CVD with TMA and IPA...................................
6.4 SIM S depth profile analysis.............................................................1
.... 130
31
.... 132
6.5 Structure of the CVD A12 0 3 thin film...........................
6.6 Surface morphology and defect status in the CVD A12 0 3 thin film.................1 34
6.7 The chemical stoichiometry and bonding state of the A12 0 3 and gallium rich Al 2 0 3
at CVD A1 2 0 3 /GaAs interface and possible mechanism of formation.............1 37
6.8 The C-V characteristics and the Di at CVD A120 3/n-GaAs interface...............139
Chapter 7 Interfacial defect states distributions in the band-gap with different
processes..............................................................................143
7.1 The characteristic time and response frequency of the defect state charge in the
144
band-gap of G aA s..........................................................................
7.2 The distribution of interfacial defect density with different processes.............146
7.3 The source of the interfacial defect state in the band-gap of the GaAs............149
7.4 The interfacial defect states and C-V characteristics..................................151
Chapter 8 Summary, Conclusion, and Suggestions for Future Work..................159
........... 164
References..........................................................
List of figures
Figure 1.1 The roadmap of the transistor development (from Intel website).........21
Figure 1.2 (a) Left figure: Thermal oxide (native oxide) of GaAs (b) Right figure:
Ternary phase diagram for Ga-As-O ....................................................................
22
Figure 1.3 The Exposure of the oxygen and the movement of the Fermi level on n- and
p-type G aA s surface...........................................................................23
Figure 1.4 (a) Left figure: Illustration of native-oxide/compound semiconductor interface
with the source of traps in the band-gap (b) Right figure: The diagram of the defect
24
states for A U D M .............................................................................
Figure 1.5 (a) The Current Si based CMOS (b) The proposed CMOS with GaAs as
N M O S and G e as the PM O S..................................................................25
Figure 2.1 Schematic growth steps of GaAs with TMG and Arsine as precursors in
M OC V D system .............................................................................
32
Figure 2.2 Surface structure of GaAs(100)-c(4x4) and GaAs(100)-(2x4)....................33
Figure 2.3 (2x4)-c(4x4)/d(4x4) phase diagram of surface reconstruction as a function of
substrate temperature and incorporation rate of As atom, determined from partial
pressure of As-containing precursors. Dot, crosses, and circles represent
........... 35
(2x4)-c(4x4)/d(4x4), and marginal structure, respectively...........
Figure 2.4 Schematic illustration of one ALD cycle. Precursor and oxidant can refer to
the reactant A and B described in the content...........................................37
Figure 2.5 Schematic diagram of (a) Conventional ALD system (b) Our MOCVD system
in SEL.
38
........................................................
Figure 2.6 Simulated XRR measurement results.The hypothetic structure is 20 nm A1 20 3
on GaAs substrate. The roughness of surface (o(surface)) and interface(G(interface))
was added into the simulations.......
.....
......
43.............43
....
Figure 2.7 Plot of sampling depth versus electron kinetic (binding) energy for GaAs and
A 120 3............................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 47
Figure 2.8 Schematic figure of the XPS system.............................................47
Figure 2.9 (a) MOS structure ,(b) Equivalent Circuit of MOS device shown in (a), (c)
Small ac bias of amplitude superposed on the gate DC bias applied to the terminals
on the MOS capacitor in (a) to measure its capacitance or conductance as a function
o f gate b ias..................................................................
.............. 4 9
Figure 2.10 Energy band diagrams and charge distributions of the MOSCAP in (a)
accumulation (b) depletion (c) inversion conditions......................................52
Figure 2.11 Theoretical high- and low-frequency curves in (a) C-V plot and
high-frequency curve in (b) C- 0, plot.......................................................52
Figure 2.12 (a) Measurement circuit of the MOSCAP (b) Typical C-V curves from our
experiments, includes capacitance (C) and conductance (G)...........................53
Figure 2.13 (a) Measurement circuit including a series resistance R, (b) Theoretical C-V
curves that affected by a series resistance................................................55
Figure 2.14 Charges associated with the Oxide/Semiconductor structure................57
Figure 2.15 (a) Energy band diagrams the MOSCAP with interfacial defect state (b) A
theoretical high-frequency C-V curves with interface defect state stretch-out
compared to a theoretical C-V curve, with no interface defect state. The interfacial
defect state is assumed to uniformly distribute in the band-gap and contains both
electron and hole traps......................................................................
58
Figure 2.16 (a) Equivalent circuit with interfacial defect state capacitance Cit, C1i is
frequency dependent (b) The theoretical C-V curves with frequency dispersion.....59
Figure 2.17 Response frequency of the interfacial defect charge at interfacial defect state
in GaAs at room tem perature.............................................................
60
Figure 3.1 The growth rates of AIN thin films at different deposition temperature........64
Figure 3.2 Process Flow of the In situ CVD AIN on p-GaAs...............................65
Figure 3.3 HRTEM image of AIN on GaAs grown at 400'C, 500'C, and 600'C...........66
Figure 3.4 XPS spectra of (a) N Is and (b) 0 Is core level of CVD AIN....................67
Figure 3.5 (a) The J-E curve of the AIN thin film (b) Fowler-Nordheim plot (c) Schottky
plot (d) Poole-Frenkel plot...................................................................69
Figure 3.6 (a) The J-E curves measured from 298K to 368K (b) The Arrhenius plot of the
leakage current density .......................................................................
70
Figure 3.7 XPS spectrum from the GaAs, AIN and AIN/GaAs interface...................71
Figure 3.8 (a) Capacitance-Voltage curves for different treatment (a) Turn off the AsH 3
flow for 1Ominutes (b) Turn off the AsH 3 flow for 1Ominutes and flow TMA for 60
seconds (c) Turn off the AsH 3 flow for 10 minutes and flow DMHy for 60 seconds
(d) Keep the AsH3 flow before depositing the AIN....................................72
Figure 3.9 The C-V curves of AIN on GaAs grown at 500C......................................74
Figure 4.1 Process Flow of the In situ ALD A120 3 on GaAs................................78
Figure 4.2 Growth rate of ALD A120 3 on GaAs at 4000C vs. precursor pulse time.......80
Figure 4.3 Thickness of the thin film grown with different cycles........................80
Figure 4.4 (a) Dependence of ALD A120 3 growth rate on temperature. The pulse time for
TMA and IPA are both 5s (b) The relation between the growth temperature and the
refractive index of the ALD A120
3
thin film................
..... 82
.............
Figure 4.5 The schematic demonstration of the ALD process...............................85
Figure 4.6 (a) Cross-section TEM image of A12 0 3/GaAs structure (b) Cross-Section
HRTEM image of the interface between GaAs substrate and A1 2 0 3 thin film grown
at 370 0C. The TMA and IPA pulse time were both 5s..............
........ 86
Figure 4.7 X-Ray Reflectivity of 20nm (250 cycles) ALD Al 20 3/GaAs structure, with
experimental data (blue point) and theoretical fitting curve (red line).................87
Figure 4.8 AFM image of 20.36nm ALD A12 0 3 surface grown on GaAs at 370'C for 250
88
cycles. The RM S roughness is 0.213 nm................................................
Figure 4.9 Auger depth-profiling of ALD A120 3/GaAs structure which the oxide
89
thickness is 20nm .............................................................................
Figure 4.10 The XPS spectra of Al 2p and Ol s signals.....................................90
Figure 4.11 XPS depth-profiling spectra of (a) As 3d (b) Al 2p core level from A12 0 3
...........................
... ........
surface to the A12 0 3/GaAs interface........
91
Figure 4.12 (a)C-V characteristics of in situ ALD A12 0 3/p-GaAs MOS capacitor
measured at different frequencies from 10kHz to 1MHz. (b) Gp/o-Vg-f map of the
same sample in (a). The dashed white line is guide to the eyes......
..... 92
Figure 4.13 Interfacial defect density vs. defect level in band-gap, determined by the
conductance-frequency method from the in situ ALD A12 0 3/p-GaAs MOS
3
c a p a c ito r.........................................................................................9
Figure 4.14 J-E curves of the 20 A1 2 0 3 and 28.6nm AIN thin film...........................94
Figure 4.15 Leakage current density (J) as a function of gate bias (VG) for Al-
95
A12 0 3-GaAs MOS device of to, = 11 .5nm..............................................
Figure 4.16 Fowler-Nordheim tunneling plot of the J-V data shown in figure 4.15.......96
Figure 4.17 0
Is energy loss spectra for A12 0 3. The cross point (obtained by linearly
extrapolating the segment of maximum negative slope to the base line) denote the
energy gap Eg value............................................................................97
Figure 4.18 Engrgy band profile for the Al/A12 0 3/GaAs MOS structure....................98
Figure 4.19 HRTEM images of the samples annealed by RTA for 15s at (a)7500C (b)800
0
C (c) 850 C ....................................................................................
99
Figure 4.20 (a) Thermal-evaporated Al electrode on as-deposit sample (b) E-Beam
deposited Mo electrode on as-deposit sample (c) and with RTA for 15s at (c)750 C
(d)800 'C and (e)850 C ......................................................................
100
Figure 4.21 Leakage current behavior of in situ n+Ge/ ALD A120 3/GaAs structure.....102
Figure 4.22 A schematic representation of the proposed mechanism.1...........
Figure 4.23 (a) SEM image of the etched oxide (b) XTEM of the sample annealed at
03
850 0 C for 15s in RTA under N 2 . (c) SEM image of the etched oxide annealed in 02
at 500 0C for 20m ins..........................................................................105
Figure 4.24 (a) The AFM image of the A12 0 3 thin film of the sample (a) as-deposit and
02 annealing for 20mins at (b) 350'C (c) 400'C and (d)450 C.All samples were
etched by HCI: H 20 2 :HF:H 20 = 10:5:1:35 for 30s......................................106
Figure 4.25 Leakage current of the samples with Al and Ti as electrodes and with
different treatm ents..........................................................................107
0
Figure 4.26 Cross-Section HRTEM image for A12 0 3 deposited with TMA/IPA at 370 C
for 20 ALD cycles. The sample was in situ capped by GaAs (a) Low-Magnification
image (b) Enlarged image from the white box labeled in (a), (c) FFT image from the
dashed w hite box labeled in (b).............................................................109
Figure 5.1 Process Flow of (a) in situ ALD A12 0 3 on GaAs (b) ex situ ALD A12 0 3 on
GaAs (c) ex situ ALD A12 0 3 on GaAs with AsH 3 pre-treatment........................113
Figure 5.2 HRTEM image of the interface between (a) native-oxide/GaAs (b) ex situ
A12 0 3/GaAs, and (c) ex situ A12 0 3/Si. The A12 0 3 was grown with TMA and IPA. The
scales are the sam e in all figures..........................................................
115
Figure 5.3 Native oxide desorption process....................................................116
Figure 5.4 (a) Ga 2p3/2 XPS spectrum for clean GaAs surface (b) Ga 2p3/2 XPS spectrum
at in situ A12 0 3/p-GaAs interface.The oxide above the interface was thinned by the
argon ion gun with etching rate of 0.021 nm/min in XPS system and the residual
thickness was estimated as 2.4 nm The Shirley background subtraction was included
in all XPS fittings....................................................................119
Figure 5.5 C-V characteristics of in situ ALD A12 0 3 on (a) p- GaAs and (c) n-GaAs; ex
situ A12 0 3 on (b) p- GaAs and (d) n-GaAs. All the A12 0 3 were grown with
TMA/IPA......................................................................121
Figure 5.6 C-V characteristics of ex situ ALD A120 3 grown with (a)TMA/IPA and (b)
......
TM A/H 20 on p-GaAs..........................................................
Figure 5.7 C-V characteristics of ex situ ALD A120 3 grown with AsH 3 annealing
122
treatment before the A120 3 growth on (a) p-type (b) n-type GaAs.....................123
Figure 5.8 The summary of Di, distribution of all samples in the band-gap. (closed and
open symbols: in and ex situ process, respectively). A120 3 was deposited with
TMA/IPA unless specified. The open square represents the sample which AsH 3
annealing treatm ent was perform ed........................................................124
Figure 6.1 Process Flow of the In situ CVD A1 20 3 on GaAs................................128
Figure 6.2 Deposition rate of CVD A120 3 vs. Temperature.................................130
Figure 6.3 SIMS depth profile of elements C, Ga, and Al. The Ga, and Al were plotted in
relative intensity (left Axis) while the C was plotted in atomic concentration (right
Axis). The open square symbols represent the fitted error function of gallium
13 2
p ro file ...................................................................................
Figure 6.4 TEM image of the CVD oxide/GaAs structure................
...........
133
Figure 6.5 X-Ray Reflectivity of ALD A12 0 3/GaAs structure (Red line) and ALD
A12 0 3/GaAs structure (Green line) ..............................................
Figure 6.6 AFM image of the as-deposit CVD A12 0 3 thin film.........
134
............... 135
Figure 6.7 Surface line scan of AFM image of the as-deposit CVD A12O 3 thin film....135
.............. 136
Figure 6.8 AFM image of the etched CVD A] 2 0 3 thin film..........
Figure 6.9 Surface line scan of AFM image of the etched CVD A12 0 3 thin film.
136
Figure 6.10 XPS spectra of (a) Ga 2p3 2 (b) As 2p3 2, and (c)AI 2p at oxide/GaAs
interface. The open hexagons and curves represent the raw data and fitting peaks.
The Shirley background subtraction was included in all XPS fittings. (d) HRTEM
image of the interface between GaAs substrate and CVD A1 20 3......
. .. .. . .. .. . . .
138
Figure 6.11 C-V characteristics of in situ (a) CVD and (b) ALD A1 2 0 3 on GaAs........140
Figure 6.12 Dit distribution of CVD samples in the band-gap extracted by the
conductance-frequency m ethod.............................................................141
Figure 6.13 Gp/o-Vg-f map of CVD (a) and ALD (b) samples. The dashed white line is
guide to the eyes and the scale of maps (c) and (d) is different........................1 41
Figure 7.1 Characteristic measurement frequencies (response frequency of trap) for both
electrons (dashed lines) and holes (solid lines) at -80 0C, 25'C, and 150 0C. The
horizontal black dashed lines represent the frequency range that is usually applied in
C-V measurement. The horizontal colored solid and dashed lines represent the traps
that can be accessible in the band-gap during the C-V measurements at different
............. 145
temperatures......................................
Figure 7.2 Interfacial defect state density of A12 0 3/p-GaAs interface of four process that
described in previous chapters as determined from conductance-frequency method at
low- (-80 0C ), room, and high-(150 0 C) temperature. The temperature regions labeled
in the diagram represent the temperatures that the C-V measurements were
p erfo rm ed ......................................................................................
14 7
Figure 7.3 C-V characteristics of in situ ALD and CVD samples measured at room and
...... 148
high-(l 50'C) tem perature.......................................................
Figure 7.4 Schematic diagram of interfacial defect state distributions of Si and GaAs. 151
Figure 7.5 Diagram of C-V characteristics of the MOS structure with donor-like defect
states locate at 0.1 eV above valence band edge..........................................152
Figure 7.6 Diagram of C-V characteristics of the MOS structure with acceptor-like defect
states locate at 0.1eV below conduction bandedge.......................................152
Figure 7.7 Diagram of C-V characteristics of the MOS structure with donor-like defect
states locate at m id-gap of GaA s............................................................153
Figure 7.8 Diagram of C-V characteristics of the MOS structure with acceptor-like defect
states locate at m id-gap of G aA s............................................................153
Figure 7.9 C-V characteristics of in situ ALD A12 0 3 on both p- and n-GaAs.............154
Figure 7.10 Possible distribution of interfacial defect state for our samples..............155
Figure 7.11 Possible distribution of interfacial defect state for in situ ALD A12 0 3/GaAs
156
in te rfac e ........................................................................................
Figure 7.12 Surface structure of GaAs (I 00)-c(4x4) surface reconstruction..............156
Figure 7.13 Possible distribution of interfacial defect state for in situ CVD and ex situ
57
ALD A12 0 3/GaAs interface.........................................1
Figure 7.14 Possible distribution of interfacial defect state for in situ CVD with flowing
TMG for 1 min prior to oxide deposition..................................................158
List of tables
Table 1.1 The mobility of electron and hole and lattice constants of semiconductors.....26
Table 2.1 The table of the relations between the transportation time and the carrier gas
flow rate..........................................................................
Table 3.1 The sum m ary of D i.........................
.
....... 40
. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .
73
List of common Acronyms and Abbreviations in this thesis
AUDM
Advanced unified defect model.............................................................
................ A l
Alum in um ........................................................................
A120 3
Aluminum oxide............................................................................
.............. A IN
A lum inum nitride................................................................
..AsH 3
As
Arsine..................................................................................
Arsenic....................................................................................
As2O 3 or As 20 5
Arsenic oxide.........................................................................
Atomic force microscopy........................................................................AFM
LD
A tom ic-layer-deposition.........................................................................A
........................................................
C apacitance-Voltage...................
...............
CPU
..................
CVD
Central Processing Unit ...............................
Chemical-vapor-deposition.........................
.............................
Complementary metal-oxide-semiconductor..
C -V
CMOS
Di-ethylzinc(Zn(CH 3) 2).....................--.................DEZn
Di-methylhydrazine((CH3(NH)(NH)CH3))..................................................DMHy
...
... S i2 H 6
. .. G a
G allium arsenide.................................................................................G
aA s
D i-silane...............................................................................
G allium ..........................................................................................
Gallium(Gadolinium) oxide..........................................................Ga
Gallium oxide........................................................................Ga
(Gd 2 O3 )
20 3
2O 3
or Ga 20
Ge
G erm anium ...........................................................................................
High-Resolution Transmission Electron Microscopy....................................HRTEM
Interfacial defect state density.....................................................................D
i
Isopropanol............................................................................IPA
Metal-oxide-semiconductor Capacitor...................................................MOSCAP
Metal-oxide-semiconductor Field Effect Transistor....................................MOSFET
Metal-organic-chemical-vapor-deposition................................................MOCVD
Molecule-beam-epitaxy.....................................................................-..MBE
....... NMOS
N-Channel Metal-Oxide-Semiconductor Field Effect Transistor............
Nitrogen ..
..................................................................
N
.. .... 0
Oxygen.........................................................................
P-Channel Metal-Oxide-Semiconductor Field Effect Transistor.........................PMOS
Scanning Electron Microscopy..............................................SEM
....... SIMS
Secondary ion mass spectroscopy...........................................
Si
S ilic o n ..................................................................................................
....... SiO 2
Silicon dioxide............................................................
Tri-methylaluminum(A(CH 3)3)................................................
Tri-methylgallium(Ga(CH 3)3)............................................
............ TMA
................. TMG
U nified defect m odel............................................................................U
Water.......................................................................................H
DM
20
X-ray Photoelectron Spectroscopy......................................XPS
XRR
X-ray Reflectivity...... ............................................
Acknowledgements
There are lots of people whom I need to acknowledge here, but the first has to be my
advisor, Gene Fitzgerald, for mentoring, encouraging, and providing plentiful resources,
inspirations, kindness, freedom, and unwavering supports. I also gratefully acknowledge
my thesis committee, professor Samuel Miller Allen, professor Lionel C. Kimerling, and
professor Dimitri Antoniadis, for their comments and suggestions on my research. I
would also like to acknowledge Provost L. Rafael Reif and professor Akintunde Ibitayo
(Tayo) Akinwande to help and give me the chance to come here for pursuit of my Ph. D.
degree. I acknowledge professor Edwin L. Thomas the helps and supports when I was
first-year graduate student. Without their kind helps, I can not make it today. I
acknowledge all the professors and teaching assistants who ever taught me at MIT for
their teaching and knowledge. I also acknowledge my research funding sources from
MARCO SRC FCRP MSD Focus Center.
I appreciate the discussions, inspirations, helps, and encouragements from Professor
Minjoo Lawrence Lee, Dr. Mayank Bulsara, Dr. Arthur Pitera, Dr. Carl Dohrman, Dr.
Michael Mori, Dr. Kenneth Lee, Dr. Steven Boles, Yu (Albert) Bai, Li Yang,. Nan
Yang,Adam, Prithu Sharma and all the other members in Fitzgerald's lab. With all of you,
I have good memory for my life in the lab. I also appreciate all the helps and assistances
from my collaborators and classmates, Henry Koh , Xiaohua Ma, Mr. Jianfei Wang, Jing
Cheng, Dr. Jifeng Liu, Dr. Juejun Hu, Dr. Shih-wei Chang, Dr. Dai-Yin Li, and Dr. John
Hennessy.
Thank my Taiwanese friends in DMSE at the MIT, Dr. Chung-Yi Chiang, Amy Chi,
Chia-Hua Lee, Yu-Hua Kao, Yi-Chun Lu, Liang-Yi Chang, and Hsien Chen. Especially
the Dr. Chung-Yi Chiang, I have no relatives in the USA but he gave me lots of helps and
suggestions when I just arrived here. Because of him, I can sustain the challenges and
finally get my degree at MIT. For me, he is like my brother in the USA. I would also like
to thank other Taiwanese friends, Shu-Wei Huang, Liang-Yu Chen, Yu-Chih Ko,
Tsung-han Tsai, Tien-Yun Lee, Chien-Jen Lai, Hsiang-Chieh Lee, Peggy Chi, Podo Chen,
Hsien-Chung Tseng, Cheng-Hsun Wu, Sidney Tsai, Hung-An Chang, Chia-Wei Lin,
I-Wen Hong, Vivan Chung, Yen-Jie Lee, Jacky Chen, Sam Chun-te Peng, Joyce Yang,
Chun-Hao Tseng, and all the other members in ROCSA at the MIT and all the friends in
Boston and in USA, for making my MIT life memorable. I would like specially to thank
Shu-Wei Huang. You and Tracy did help me a lots and we made lots of good memory
together. I can not imagine that if I did not know you here, how my life would possibly
be. I will never forget the dinner that we had in Taiwan Cafd in Chinese New Year's Eve
in our first year. I specially would also like to thank all the members in RLE. With all of
you, I felt very happy and have nice memory in my last two years.
I also thank people in Taiwan who offered me the supports and helps even I was in
USA, Professor Tai-Bor Wu, Professor Jau-Ho Jean, Professor Tri-Rung Yew, Professor
Minghwei Hong, Professor Chien-Neng Liao, Professor Yu-Lun Chueh, and Dr. Mao-Lin
Huang and any people who supported me.
Finally, I would like to thank my parents, wife, sister, brother, a sister-in-law, and
my cute new-born nephew. I always remember the moment that you saw me off in the
airport for the first time. I also wanted to cry but I didn't because I knew that I need to
face all the challenges by myself in the USA and can not cry in front of you to make you
worry. I smiled at you and left even though all of you were crying. Now I can smile at
you to say I make it with your supports. I really thank all of you and please forgive me
not sharing the family loads in these years. Thank you for staying with me here in the last
year, I-Hua.
Five years is not a long time compared to the whole life, but it is long enough for me
to make good memory with all of you. Study at MIT really changes my life.
Again, I would like to thank all of you.
6Aex -74/ ei
05/11/2010
Chapter 1 Introduction and Motivation
1.1 Introduction
Ultra thin dielectric layer/semiconductor interfaces have attracted much attention
due to their importance in fundamental understanding and commerical application.
Commerical interest is driven by the continued scaling of MOSFETs(Moore's law),
which predicts that the number of the transistors would double every 24 months. The
performance and power consumption of single transistor improves as the size of the
transistor shrinks in addition to the economic benefit. Intel's Roadmap (Figure 1.1)
depicts the past changes, and possible future change to the MOSFETs as it scales
Transistor gate length of
about 20 nm was to arrive by year 2009, and the SiO2 gate
oxide thickness is reduced to 1.Onm, which is the quantum tunneling limit. Beyond this
point, leakage current due to tunneling (1-10 A/cm 2) becomes the dominant leakage
mechanism in device design. There is another physical limit below which SiO 2 no longer
maintains its bulk electronic structure and is less electrically insulating at approx.7A.
Further scaling of CMOS demands that high dielectric constant (K) material replaces SiO 2
to alleviate these constraints. Due to the inpending gate oxide limit, much research and
development has been focused in this area in the past five years. Recently, Intel announce
their 45 nm CPU products, which incorporate high-k material and a metal gate. The trend
will likely continue for the next 10 years.
Improving the gate insulator is not sufficient to remain on the Roadmap. Strained
silicon has been incorporated to enhance drive current through enhanced mobility and
carrier velocity at source injection. However, further improvement will soon require even
higher mobilities. Compound semiconductors offer the advantages of high electron
mobility. One of the key challenges in compound semiconductor device technology is to
20
find a thermodynamically stable insulator on the semiconductors that provides a low
interfacial defect state density (Dt) and also results in low electrical leakage. One of the
most successful dielectrics on GaAs had been Ga 2 O3 (Gd 2O 3 ), grown by MBE.
Enhancement
mode p- and n-channel
demonstrated[1-.1 -3].
GaAs MOSFETs
with
inversion
were
Recently, A120 3 grown by ALD on GaAs has resulted in good
device performance for depletion mode n-channel GaAs MOSFETs[ L4].
90
rom
20036S
nr
20054S
efc2007
nrn
32 nt
2011+
SiGe S/D
Strained
Silcon
SiGe S/D
Strained
Silicon
Tri-Gate'
More Non-Silicon Elements Introduced
Future options subject to change
Figure 1.1 The roadmap of the transistor development. Figure reproduced from Intel
website.
1.2 Background (Fermi level pinning)
Unlike the oxidization of the silicon, which just forms silicon dioxide, GaAs (and
other Ill-Vs) has complex oxidized products. The structure of the GaAs oxide is shown in
21
Figure
1.2(a), which
be understood
can
using the ternary
phase diagram
of
Ga-As-O(Figure 1.2(b)).The various layers are formed due to the kinetics of oxidation
and the thermodynamically stable phases in the phase diagram. The dielectric constant
and resistivity of each layer in the oxide may cause severe frequency dispersion in C-V
curves, which is called the Wagner- Maxwell multi-dielectrics effect. The complex oxide
also creates a very large Dit at oxide/GaAs interface and "pins" the fermi level in the
energy band-gap.
GaAsC4
Ga20,
As 2 0 3
As203
oGo
GcAsO4-i
0
^
t AsO31
A5205
G_",
%3
Ga2 0 3 : As
GaAs
Go
GcAs
As
Go-As-O
Figure 1.2 (a)Left figure: Thermal oxide (native oxide) of GaAs (b) Right figure: Ternary
phase diagram for Ga-As-O.
Although the Fermi level is pinned when the native oxide forms, the Fermi level
could also be pinned without the formation of significant oxide thickness. Very small
amounts of oxygen absorbed on the surface leads to strong pinning of the Fermi level on
both n- and p-type Ill-V compound, as shown in figure 3[1.6].
1.2
gGa~s
1.4 (eV)
IE
* n-TYPE
A p-TYPE
S0.44
CLEAN
10'
10
10
OXYGEN EXPOSURE
107
10 G
V
(Langmuirs)
Figure 1.3 The Exposure of the oxygen and the movement of the Fermi level on n- and
p-type GaAs surface. Figure reproduced from W.E. Spicer 11.61
Numerous ex situ approaches have failed to produce a suitable passivation with a
low Dit between the gate dielectric and GaAs. One of the main reasons is the fermi level
pinning at compound semiconductor interface. The pinned surface limits the band
bending and therefore the semiconductor channel can not be inverted. Figure 1.4(a)
shows the illustration of native-oxide/compound semiconductor interface with the source
of traps in the energy bands.
According to Spicer UDM and AUDM theory[] .7,i.8], which is widely accepted as
a mechanism of Fermi level pinning on III-V semiconductors,the
ASGa
antisite (an As
atom on a Ga site in the GaAs lattice) formation will produce pinning at 0.75 and 0.5 eV
above the valance band maximum.The ASGaantisite defect is formed by the arsenic at the
interface, occupying Ga vacancy sites. Native defects are important for pinning the Fermi
level at Ill-V compound interface with both metal and non metal over-layers (ex. the
oxygen absorbed on Ill-V surface).AUDM theory states that the formation of both donors
and acceptors within the band-gap pins the Fermi level [1.9]. Figure 1.4(b) shows the
energy level diagram for AUDM. The
ASGa
antisite double donor with levels of 0.75 and
0.5eV and the compensating acceptor with energy level below 0.5eV are shown. Both
defects are located in the same spatial region near the surface. The surface Fermi level
position, Efi, for the free surface will be determined by the relative densities of the two
defects in the near surface region. The origin of excess arsenic at the interface is
speculated to be the decomposition of arsenic oxide, especially As 2O3. It is generated by
the oxidation of GaAs surface and thought to be the source of the defect state. Reducing
the defect formation at the oxide/ semiconductor interface is crucial for the performance
of GaAs MOSFET.
interface
trap
~sto"
~
CBM
Fermi energy
n
b
IA
f.s
Probable GaA aniSo
ev
Dou-e ACO
-
sufcrlneon
ADANCED UNIF;ED DEFECT MODEL
Figure 1.4 (a) Left figure: Illustration of native-oxide/compound semiconductor interface
with the source of traps in the band-gap (b) Right figure: The diagram of the defect states
for AUDM. Figure reproduced from W.E. Spicer 11.91
1.3 Motivation
Current CMOS is fabricated on the Si substrate and it is shown in figure 1.5(a). In
order to improve the performance of the CMOS, scaling down the size of the transistor or
the use of the stress and strain on transistor to increase the mobility of the carriers is
currently applied. However, replacement of the channel materials with higher mobility
materials will be required in the future because of the limitation of the size of the
transistor and the stress that can be applied on the transistor. Table 1.1 shows the table of
some semiconductors with their mobility and lattice constants. Because all the III-V
semiconductors have higher electron mobility than Si and Ge has the highest hole
mobility, some people propose the ultimate CMOS platform would use Ill-V for the
NMOS channel and Ge as the PMOS channel (shown in figure 1.5 (b)). Both channels
would need to be deposited on the Si substrate in order to use current infrastructure.
Among the III-V semiconductors,
good compromise
Ino. 53Gao. 47As has been studied by researchers due to a
of high electron
mobility
and band-gap.
InGaAs
has been
experimented at the device level to see if MOSFETs can be made which extend the
current Roadmap. Drive currents have been improving, and are much better than reported
GaAs drive currents. However, the real challenges for InGaAs integration on silicon are
unknown, as no credible integration scheme with low defect density has be conceived of.
In addition, high drive currents in inversion are obtained due to the nature of the high
interfacial defect state density moving into the conduction band. Thus, from a basic
science perspective, it is difficult to study the connection between interface formation and
electrical defect density. In this thesis, we use GaAs as a model system for explore the
connection between.
p-MOS
N-MOS
--
(a)
-1
mM-
p-MOS
N-MOS
1 AM
Mr
(b)
Figure 1.5 (a) The Current Si based CMOS (b) The proposed CMOS with III-V as NMOS
and Ge as the PMOS
Mobility at 300k
Semiconductor
(cm2NVs)
Hole
Electron
constat (A)
Si
Ge
1500
3900
450
1900
5.431
5.658
GaAs
8500
400
5.653
12000
300
5.868
5400
200
5.868
Ino
0 Ga
47As
InP
Table 1.1 The mobility of electron and hole and lattice constants of semiconductors
According to past thirty-years of research on GaAs, interfacial defect density is
very sensitive to the processing methods and materials. The AlxGa 1 xAs was proven as the
best material to passivate the GaAs surface.[l.10] Because both GaAs and AlxGa 1 xAs
have approximately the same lattice constant and similarity of the chemical properties
and bondings, the Dit can be as low as 109 (eV'cm-2) at AlGa1 xAs/GaAs interface, while
the Dit of Si/SiO2 interface is 1010(eV'cm-2 ). However, the band-gap of AlxGa 1 -As is not
large enough to provide enough conduction or valence band offset to support the
inversion layer. Other materials need to be considered instead of AlxGaIAs
As
mentioned before, numerous ex situ approaches have failed to produce a suitable
passivation with a low Di, between the gate dielectric and GaAs. Recently, ex situ ALD of
a high-k insulator on GaAs has achieved better interfacial properties due to the
self-cleaning effect [1 11]. The native oxide was removed during the ALD process with
TMA/H 20 or TEMHf/H20, but the best Dit near the mid-gap is about 10' 2(eV-Icm- 2). The
best dielectrics/GaAs process result to date is an in situ deposition of Ga 2 0 3(Gd 2O 3) on
as-grown GaAs in ultra-high vacuum[
.
GaAs is deposited in MBE chamber and
1-1 13].
then the wafer is transferred in vacuum to another deposition chamber to deposit the
dielectric. As the processes were in ultra high vacuum, this prevented the oxidation of the
GaAs before the oxide deposition. The Dit of this interface near the mid-gap is
10 1 (eV'cm 2 ), similar to the Si/Si0
2
interface. Throughput of MBE is limited and does
not scale in a cost-effective way.
MOCVD had been widely used in industry to fabricate the light-emitting-diode
because of favorable economics. Some researchers have applied CVD to deposit high-k
materials on GaAs and achieved low Dit between GaAs and high-k material. Zhi Chen, et
al. [I 121 used Ge or Si deposited at low temperature as the interlayer before depositing
0
the high-k (silicon nitride) insulator on GaAs at low temperature (below 400 C). Their
C-V results were analyzed by conductance- frequency method and Di, as low as
10
0(eV cm ) near the mid-gap. But Ge or Si diffuses away from the interface during
high temperature annealing. The samples could not sustain high temperature annealing,
for example,
since activation annealing
is
required
after
ion implantation.
A
thermodynamically stable high-k material with a low Dit at the interface is required to be
directly deposited on Ill-V materials.
In situ deposition of high-k material on GaAs in MOCVD system achieves the goals
listed above. An in situ process will allow us to control process variables and correlate
those variables to interface defectively. In addition, the use of MOCVD will allow
successful research to have commercial impact.
1.4 Organization of this thesis
This introduction has included the motivations and challenges for the passivation of
the GaAs for MOSFET applications. Chapter 2 introduces the materials growth and
27
characterization techniques that were applied in this work. Emphasis is placed on how we
can perform ALD in a MOCVD system and on how we can applied C-V measurement to
characterize the Dit in the band-gap of the GaAs at oxide/GaAs interface. In chapter 3, in
situ passivation of GaAs in MOCVD using AIN as an insulator is discussed. Chapter 4
discusses the use of in situ ALD A12 0 3 with TMA and IPA as precursors to form A1 2 0 3
on GaAs. Chapter 5 compares the differences between the in and ex situ passivation of
GaAs with in situ ALD A12 0 3 and how we can reverse the oxidation of GaAs surface in
an ex situ process. In Chapter 6, in situ CVD A12 0 3 is applied to passivate the GaAs and
the differences of growth mechanisms and experimental results between the ALD and
CVD will be discussed. Chapter 7 first shows the distributions of D, at the oxide/GaAs
interfaces that are grown by the methods described in chapter 4, 5, and 6. The sources of
the interfacial defect state are discussed and the relations between these defect states and
the processes and how these interfacial defect states affect the C-V characteristics are
proposed. Finally, in Chapter 8, we summarize the thesis.
Chapter 2 Materials Growth and Characterizations
In this chapter, we briefly describe materials growth, including the growth of
GaAs and high-k materials, and some characterization methods that we applied to
understand the microstructure and chemical bonding states of the elements near the
oxide/semiconductor interface of our samples. The basic theory of the MOSCAP device
is introduced and we focus on the C-V characteristics of the MOSCAP device. Because
the interfacial defect states affect the C-V characteristics, and we can extract the
information about the interfacial defect state distribution from the C-V measurements.
The conductance-frequency method is applied in our research to extract the Dit and this
method is introduced in this chapter.
2.1 Materials Growth
The growth experiments were all performed in a low pressure AIXTRON/Thomas
Swan 6x2" As/P close-coupled showerhead cold-wall MOCVD system in a facility at the
Massachusetts Institute of Technology (MIT) called the Substrate Engineering Laboratory
(SEL).
The GaAs buffer layer was grown in the CVD mode in an arsenic rich environment.
After the growth of the GaAs buffer layer, high-k material was deposited immediately
without interrupting for in situ process. For ex situ process, the wafers were taken out
from the reactor after the buffer GaAs growth and stored in the air for two days before
reloading into MOCVD system to deposit the high-k material. The chosen high-k
materials are AIN and A12 0 3 in our experiment. The AIN was deposited by CVD mode
while the A1 2 0 3 was deposited by both CVD and ALD modes.
In this section, we will not focus on the detail about the theory of MOCVD and the
operations of our MOCVD system. The reader can be directed to other sources, such as
Stringfellow's classic text[2.l ] and for Fitzgerald Group alumni theses [2.2,2.3] , for a
detailed treatment. We will briefly review the GaAs growth in MOCVD system and show
what the surface reconstruction structure of the GaAs grown in the MOCVD system is.
Then, the operations of ALD in our MOCVD system will be discussed.
2.2.1 MOCVD of GaAs and Surface Reconstruction structure of GaAs in MOCVD
system
MOCVD of GaAs
MOCVD is one kind of CVD that utilizes metal-organic chemicals as the precursors
to grow the Ill-V compound semiconductor. Our reactor is a "cold" wall system, with the
precursor being delivered to the heated substrate by a carrier gas. A group III source,
TMGa, is stored in bubblers with the nitrogen (or hydrogen) flows. The bubbler
0
temperature is precisely controlled at 5 C to keep the vapor pressure of TMG constant.
Carrier gas will flow into the bubbler and saturate with vapor from the TMG and
transport vapor to the heated substrate. The gaseous hydride, AsH 3 is used as group V
source for GaAs growth. Dopant materials can be metal organic precursors such as DEZn
as a p-dopant, or silicon hydride such as Si2H6 as n-dopant in our growth. The basic
MOCVD reaction describing the GaAs deposition process can be written:
Ga(CH 3 )3 (g)+AsH3(g) --+ GaAs(s)+3CH4(g)
Where (g) =gas and (s) =solid
The optimization of GaAs growth can be done by empirical studies of external
parameters such as growth temperature, V/III ratio, and mass flow rates. However, the
0
typical GaAs growth temperature in our system is 650 C with V/III ratio as 20. This may
not be the optimal GaAs growth condition in our system, but the quality of the grown
GaAs is good enough for our following study. At 650'C, the growth rate is limited by
mass transport of the TMG precursor to the growing interface. Pyrolysis and diffusion of
group Ill source arising through boundary layer is the main pathway controlling growth
rate. The GaAs growth rate is also found to be linear proportional to the TMG flow rate
in our system. Figure 2.1 shows the schematic growth steps of GaAs with TMG and AsH 3
as precursors in MOCVD system.
T Horizontal Gas Flow
CH3
N2-+.
GasCH3
GaH
CH3
N2
N2
H
2
As
Hp...H
CH
H
N2 -+
2-.
t
H
CH3 -radical
Ga
3
Atomic Step
CH3
s port
tesrface
ZH
As
-radical
Layer
t
dffusion
CH3
Boundary
Wafei
Surface
H
N2
-
r
CH4<,
CH3+,H
Surface diffusion
and reaction
H + H -H
rsor
sition
incorporation
and growth
Figure 2.1 Schematic growth steps of GaAs with TMG and Arsine as precursors in MOCVD
system
Surface Reconstruction structure of GaAs in MOCVD system
Knowing the surface reconstruction of GaAs(100) in MOCVD system is important
because the oxide is directly deposited on these reconstructed surface in in situ ALD
processes. This can help us determine what kinds of reactions happen on the surface
during ALD process and help us determine bonding states between the oxide and GaAs.
Surface Reconstruction of the GaAs(001) had been widely studied in MBE with the
aid of the surface analytical tools such as reflection high-energy electron diffraction
(RHEED) and low energy electron diffraction (LEED). Various surface reconstructions
were should to occur on the surface of GaAs in ultra high vacuum (UHV) and two of
well-known structures are GaAs( 100)-c(4x4) and GaAs(100)-(2x4) and are shown in
figure 2.2.However, these tools are typically not found as part of an MOCVD system.
Very little is known about the structure of surfaces in non-UHV ambient for example
MOCVD.
GaAs (100) (2x4)
GaAs (100) c(4x4)
(Top View)
(Top View)
o
0
;~ po
~C O$ ~ C5,0
.
o'~b o oc1b
- 0 O
I
0 0
Qo0o0 0
o
oQ~
O
o
0.
....
Qc Q
o
O
o. o
g
.
.
.
.
o
[110]
(SideView)
(Side View)
Figure 2.2 Surface structure of GaAs(100)-c(4x4) and GaAs(100)-(2x4).Figure reproduced
from D. K. Biegelsen[2.41
Recently, some researchers have utilized Reflectance-difference spectroscopy (RDS)
to study the surface reconstruction of GaAs(100) in MOCVD system. RDS was proven to
be capable of studying the surface structure in various environments from UHV to
atmospheric pressure [2.5,2.6].From their results, they found that the surfaces are also
reconstructed under the gas phase condition. GaAs(100) in UHV and MOCVD show
similar surface reconstruction structure. Similarities between the surface in UHV and in
MOCVD can further be seen in the (2x4)-c(4x4)/d(4x4) phase diagram of surface
reconstruction shown in figure 2.3. This data in this figure were taken from both MBE
and MOCVD grown surface. The surface structures are determined by the substrate
temperature and As supply rate and the nature of the GaAs (100) surface is the same in
both UHV and MOCVD systems.
From their results, the surface of the GaAs (100) surface always shows a c(4x4)
structure above 4500 C under the supply of the AsH 3.They also indicated that the AsH3
reacts relative weakly with the GaAs surface and the gas decomposition rate is low at
temperature at 400-450'C [2.7]. They suggest that a Ga- or GaAs-covered graphite
susceptor cracks AsH 3, into As 4 or As 2 while simultaneously desorbing these species,
thus acting as an As reservoir to supply the As to the GaAs wafer and form the d(4x4)
surface reconstruction in MOCVD system. The d(4x4) structure is very similar to c(4x4)
structure but the surface is covered by several layers of As atoms, not only two layers in
c(4x4) structure. The d(4x4) structure is an equilibrium phase and it can remain for
several hours even after the AsH 3 supply is cut off[2.8]. Heating the substrate up to
6000C without AsH 3 flow is required to desorb the As species from the surface to form
the (2x4) surface in our MOCVD.
T/ *C
600
500
700
6
uJ
0
0
0
X
X
IQ
0
0
0
X
X
X
X
0
400
X
X
4
0
X
X
X
OMCVD
<2 -
c(4x4)/d(4x4)
(2x 4)
MBE
0 - -0e0009
.69
.0
9.6 X
X XXX X
X XX X
X
~
0
-2
X.. O0
-
1.00
1.40
1.20
X
X x
1.60
1000K/ T
Figure 2.3 (2x4)-c(4x4)/d(4x4) phase diagram of surface reconstruction as a function of
substrate temperature and incorporation rate of As atom, determined from partial pressure
of As-containing precursors. Dot, crosses, and circles represent (2x4)-c(4x4)/d(4x4)
,
and
marginal structure, respectively. Figure reproduced from ltaru Kamiya 12.81
2.1.2 ALD in MOCVD system
ALD has recently gained more attention since it has found utility in a wide range of
applications, such as catalysts, electroluminescent displays, and microelectronics etc., due
to its capability to coat extremely complex shapes with a conformal material layer of high
quality, a capability unique among thin-film deposition techniques
[2i.2.1I ].For
example. Intel had announced that its 45nm transistors process an ALD Hafnium-based
oxide[2. 2]. Although the major limitation of the ALD is its growth rate ( usually only a
fraction of a monolayer is deposited in one cycle), this has not become an issue due to the
scaling down of the devices.
ALD has similar chemistry to CVD, except that the ALD reaction divides the CVD
35
reaction into two half-reactions by keeping the precursors separate during the reaction
[2.13].Usually, the deposition temperature of ALD is lower than CVD because the
precursors perform a ligand exchange
reaction, and this results in the incomplete
decomposition before depositing on the wafer. However, the precursors are required to be
fully decomposed prior to deposition on the substrate in CVD process. ALD is also a
self-limiting deposition process and therefore the amount of film material deposited in
each reaction cycle is constant. This behavior allows the ALD process to control film
thickness at the atomic scale.
[2.14]ALD can be defined as a film deposition technique that is based on the
sequential use of self-terminating gas-solid reactions. The growth of material layers by
ALD consists of repeating the following characteristic four steps:
(1) A self-terminating reaction of the first reactant (Reactant A).
(2) A purge or evacuation to remove the non-reacted reactants and the gaseous reaction
by-products.
(3) A self-terminating reaction of the second reactant (Reactant B)-or another treatment
to activate the surface again for the reaction of the first reactant.
(4) A purge or evacuation.
Steps 1-4 constitute a reaction cycle. Steps I and 3 are sometimes referred to as hal/
reactions of an ALD reaction cycle. One ALD cycle is illustrated schematically in figure
2.4 [2. 15 ].
1) Precursor pulse
2) Purge
3) Oxidant pulse
4) Purge
Figure 2.4 Schematic illustration of one ALD cycle. Precursor and oxidant can refer to the
reactant A and B described in the content. Figure reproduced from [2.151
In our work, ALD was performed in a MOCVD system. Controlling of timing of
flowing precursors into the reactor is very important for our experiments. For the
conventional ALD reactor shown in figure 2.5(a), the volume of the reactor is usually
small and the operational pressure of ALD reactor (1 Torr or less) is usually lower than
the vapor pressure of the precursors (For example, TMA, 8.7 Torr: H2 0, 22 Torr at 20'C).
The precursors flow into the reactor spontaneously without carrier gas because of the
differential pressure between the bubblers and reactor. The precursor bubblers are usually
installed near the reactor and the distance between the bubblers and reactor is short. The
precursors reach and saturate the reactor immediately after the bubbler valves open. After
the precursor pulse, the excess precursor and by-product of ALD reaction can be pumped
out from the reactor very fast due to the small size of the reactor.
For our MOCVD system (shown in figure 2.5(b)), the pressure of the reactor is
determined by total carrier gas flow rate and the position of the butterfly valve between
the reactor and pump during growth. Because the ALD reaction is usually performed in a
low pressure system, the pressure of reactor should be as low as possible. Our MOCVD
system is designed to perform growth under higher reactor pressure, >I0 Torr. However,
considering the accuracy of the (Mass-flow Controllers) MFCs (5% of the naximui
flow rate), balance of gas flows in carrier lines, and the transportation times of precursor
from bubbler to the reactor (will be discussed later), the pressure of reactor and gas flow
rates of carrier lines were set to 50 Torr and 2500-500-2000 scem (Standard Cubic
Centimeter per Minute) for upper-middle-lower carrier lines, respectively. The carrier gas
is also used as the purge gas between the precursor pulses.
U
r CarrierLine
ALD Reactor
.
.
.
.
...
Reactor
MVOCVD
h Puity
PumpNitrogen
Pump
LowerCarrder
Line........
(a)
precursor
line
Exhaust
reactor
-The distance between source and reactor is "short"
precursor
reactor
-The distance between source and reactor is "long"
Figure 2.5 Schematic diagram of (a) Conventional ALD system (b) Our MOCVD system in
SEL
Because the pressure of the reactor (50 Torr) is always higher than the vapor
pressure of the precursors, the carrier gas (ultra high pure nitrogen) is needed to transport
the precursors from the bubblers to the reactor during the ALD process. Unlike the
conventional ALD system, the distance between the precursor bubblers and reactor is
long and time is needed for the precursors to flow into the reactor after the bubbler valve
is opened. The timing of each ALD step needs to be controlled carefully to make each
precursor flow be separate in the carrier lines and reactor. The transportation time (T) that
38
is needed for precursors to be transported from bubblers to the reactor can be calculated
by equation (I) for our system:
T
LxD
V
2
304.02
(s)
(1)
Here, L, D, and v are the length of the carrier line from injection valve of precursor
bubbler to the reactor (cm), diameter of the carrier line (inch), and carrier gas flow rate
(scem).
The D is 1/4 inch for the pipes of the three carrier gas lines and L is about 310 +/- 25
cm (285- 335 cm) for all precursors in our MOCVD system (The exact values are
different for all precursors because the injection valves of the precursors are at different
positions of carrier lines but all of them would be in this range). The only parameter that
we can control is the carrier gas flow rate v. '[able 2.1 shows the relation between the
transportation time and the carrier gas flow rates calculated by the equation (1).
In our ALD process, precursors were separately transported in upper and lower
carrier lines and the flow rates are 2500 and 2000 sccm during the process. This means
that the precursors need 2.95s +/-0.24s (2.71 - 3.19 s) and 2.36s +/- 0.19s (2.17 - 2.55s)
to reach the reactor. In order to separate the precursors flows and prevent 'parasitic' CVD
deposition on the substrate, Is purge time is required between each precursor pulse. In
our experiment, the purge time was set at least 3s to guarantee the separation of the
precursors.
1000
1.18
0.10
0.59
0.05
Table 2.1 Table of the relations between the transportation time and the carrier gas flow
rate
2.2 Materials Characterizations
In order to understand the physical oxide/III-V interfaces or the quality of the oxide
thin film, several analytical techniques were used after the sample growth. These
techniques will be briefly discussed below.
2.2.1 High-Resolution Transmission Electron Microscopy (HRTEM)
TEM is an important tool for examining the micro-structure of the films we grow.
Imaging is achieved by passing a high-energy electron beam through a very thin
specimen. When the electron beam passes through the materials, some electrons would be
possibly absorbed or diffracted by the material lattice, the rest of the electrons will just
directly pass through the specimen without lost of energy. HRTEM is one of the TEM
imaging modes and all electron beams (transmitted and diffracted electron beam) are used
to form the image with atomic resolution. In order to create the HRTEM image, the
specimen needs to be tilted first to "on-axis" position, so that the lattice planes are
parallel to the electron optics axis. The contrast in the image is formed due to the
differences of the transmitted and diffracted electron beams.
In our work, cross-section HRTEM,or X-HRTEM, was applied to study the
micro-structure of the high-k material/GaAs interface by using JEOL 2010 which the
acceleration voltage is 200kV. The X-HRTEM sample preparation procedure is described
below:
(1) The specimen was cut into two 5 mm
x
5 mm in size, rectangular in shape pieces.
(2) The cut pieces were blown by the N2 gas to clean the particles generated during the
cutting.
(3) The one piece was coated with a thin layer of AB glue and bonded to another piece
(film to film). Two silicon dummies were also bonded to the double sides of the stack.
Then, the stack was cured for 5min on a hot plate .When the curing process
completed, the specimen was cooled to room temperature.
(5) The specimen was mounted with wax on a copper pillar or a glass piece.
(6) The specimen was polished to less than 1mm thick with 500, 1200, 4000 grit abrasive
papers in this succession. Finally, the specimen was polished with 0.3-pIm suspension
alumina powders.
(7) The specimen was flipped over and mounted with wax on a copper pillar or a glass
piece again.
(8) The specimen was polished to less than 50 rn thick (The silicon dummy looks red
and transparent) with 500, 1200, 4000 grit abrasive papers in this succession. Finally,
the specimen was polished with 0.3-pm suspension alumina powders.
41
(9) The specimen was bonded by epoxy on a copper ring.
(10) The specimen was dissolved with acetone.
(11) The specimen was milled by argon ions until a hole was developed near the center of
the specimens. The argon ion energy, milling angle and ion current were 3-5 keV,
2~5 and 15-30nA.
2.2.2 Atomic force microscopy (AFM)
Atomic force microscopy is a very useful way to characterize
the surface
morphology of samples over relatively large areas with nanometer-level precision. The
method relies on the use of a cantilever tip that interacts with the atoms on the sample
surface, leading to a force being registered by the cantilever which is then translated into
an image containing information about the surface. AFMs can be operated in several
modes, but the mode we used was tapping-mode AFM, in which the AFM cantilever is
continuously vibrated as it is swept over a surface, and a feedback loop adjusts the height
of the cantilever so that it experiences a constant force from its interaction with the
surface. The most physically direct measurement is of relief, where the topology of the
surface causes the cantilever tip to displace by varying amounts as it traverses across the
surface. This was the data that we sought most often, as the AFM was used to quantify
the surface roughness of our samples. The instrument used in this work was a Digital
Instruments Dimension 3000 Nanoscope Ila AFM.
2.2.3 X-Ray Reflectivity (XRR)
When X-rays strike a surface at glancing incidence they can reflect off the surface.
However, if the surface is rough or covered by a film, then the X-ray reflectivity of a
surface can change. XRR takes advantage of this effect by measuring the intensity of
X-rays reflected from a surface as a function of angle. Thin films on a surface can give
rise to oscillations of the X-ray intensity with angle. XRR was performed to measure the
thickness of the thin film and roughness of the interface and the surface. Figure 2.6 shows
the typical XRR measurement results.
10000000
10000
1000
100
10
1
04 0
20 nm Aluminum Oxide on GaAs
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
1.8 2.0 2.2 2.4 2.6 2.8 3.0
Incident Angel (Degree)
Figure 2.6 Simulated XRR measurement results. The hypothetic structure is 20 nm A12 0 3 on
GaAs substrate. The roughness of surface (aT(surface)) and interface(a(interface)) was added
into the simulations
The fringes in the figure arise from the interference of the X-ray though the oxide
thin film and the spacing of the fringe can be used to calculate the thickness of the thin
film follows by the equation (2) shown below:
250
(2)
here, 1, { ,and 50 are the thickness of the thin film, the wavelength of the X-ray, and
the spacing of the fringe. The presence of the surface roughness decreases the specular
intensity of the whole curve progressively, while the roughness gives rise to progressive
damping of the fringes. These effects can also be observed in figure 2.6.
By using theoretical model to do the fitting on experimental XRR data, the
information (density of the substrate and thin film, thickness of the thin film, surface and
interfacial roughness) can be extracted. The applied fitting software is X'Pert Reflectivity
which is provided by the CMSE X-Ray Lab. The mode that combines segment fitting and
genetic algorithm fitting method was used to fit the data in the software.
2.2.4 Secondary ion mass spectroscopy (SIMS)
SIMS is a destructive analytical technique in which the chemical concentrations of
constituent elements and contaminants in a material can be determined as a function of
depth. It can therefore be used to determine alloy compositions and predict electronic
carrier concentrations, assuming that the species under investigation has been properly
calibrated for measurement. The measurement is affected by sputtering material from the
sample as individual ionized atoms (or in some cases molecules), using an ion beam.
These secondary ions are detected according to their charge/mass ratio through
conventional mass spectroscopy, and their relative yield is analyzed to provide
information about each species' chemical concentration as a function of sputter depth.
44
Depending on the species being measured, concentrations as low as 1015 cm- can be
detected. In our work, SIMS was mostly carried out to determine the presence of
contaminants such as carbon or the gallium atoms in our ALD oxide film, or to quantify
the dopant concentrations in our grown GaAs layers.
2.2.5 X-ray Photoelectron Spectroscopy (XPS)
XPS is a popular surface analytic technique due to its high information content, its
flexibility in addressing a wide variety of samples, and its sound theoretical basis. It can
be used to provide the information of elemental composition, chemical state and
electronic state of the elements that exist within a material. XPS is based on the
photoelectric effect where the concept of the photon was used to describe the ejection of
electrons from a surface when photons impinge upon it. For XPS, Al Ka (1486.6eV) or
Mg Ka (1253.6eV) photons is often applied as exciting photon source. The XPS
technique is highly surface specific due to the short range of the photoelectrons that are
excited from the solid. The sampling depth (The depth where the 95% of the
photoelectrons could be detected) of the XPS is considered as three times the Inelastic
Mean Free Path (IMFP, The average distance that an electron with a given energy travels
between successive inelastic collisions)[ 2.16]. Seah and Dench developed an equation
that relates IMFP to electron energy and the inorganic compounds:
IMFP =2170KE 2 + 0.72(aKE) 0 '
(3)
Where IMFP is in units of monolayer, a is the monolayer thickness (nm), KE is the
45
electron kinetic energy (eV). The calculated sampling depth of GaAs and Al 20 3 is shown
in figure 2.7. For our materials (GaAs and A12 0 3) ,most photoelectrons that escape from
the top I to 10 nm of the material are analyzed and the energy of these photoelectrons
leaving the sample are determined using a electron energy analyzer. The electron binding
energy EB of the initial state can be determined from the energy conservation statement of
the elastic process:
E
=hv-KE-
DspJ
(4)
where Dsp is the work function of the electron energy analyzer. In core-level XPS the
intensity of those photoelectrons emitted from the sample is measured as a function of
their kinetic energy, and typically plotted as a function of the electron binding energy
following equation (4). The binding energy of the peaks is characteristic of each element.
The peak areas can be used (with appropriate sensitivity factors) to determine the
composition of the materials surface. The shape of each peak and the binding energy can
be slightly altered by the chemical state of the emitting atom. Hence XPS can provide
chemical bonding information as well. XPS must be carried out in ultra high vacuum
environment or the energy of the photoelectron would be affected by the gas molecules in
the system. The schematic figure of the XPS system is shown in figure 2.8.
In our work, XPS measurement was performed in Kratos AXIS Ultra Imaging
system using a monochromatic Al Kal source (1486.6 eV) in center of materials science
and engineering(CMSE).
Binding Energy EB (eV)
600
1400 1200 1000 800
15
-
E
13
12
0
Al 20 3 a = 0.204 nm
GaAs a = 0.283 nm
-
14
200
400
11
-
-----
10
. 9
ci
08
tM7
.E
E
4
(/
3
2
IMFP
SamplingDepth= 3x
+ 0.72(aKE)" monolayers
IMFP= 217OKE'
0
200
400
600
800
1000 1200 1400
Kinetic Energy KE (eV)
Figure 2.7 Plot of sampling depth versus electron kinetic (binding) energy for GaAs and
A120 3
ElecronfnetgyAnalyzi (0-1.5kV)
Photo-EmrittedElectrons (< 1.6 V)
escape only from the very top surface
(70 - 110A) of the sample
Detector
EecrEectno
(onrM
Collection
Lens
fcrm
Focused Beam of
X-rays (1. 5kV)
ElectronTake-Off-Angle-
N
Si (2p)
Sij02 Si'
Sample
Samples are usually solid because XPS
requires ultra-high vacuum (<10-*torr)
St(2) XPSSAIS
fm a Silicon Water
11b
Figure 2.8 Schematic figure of the XPS system[2.171
2.3 Capacitance-Voltage Characteristics of Metal-Oxide (Insulator)- Semiconductor
Capacitor (MOSCAP) and Characterization
In a real MOS device, the oxide/semiconductor interface is not perfect and contains
many defects, as we introduced in chapter 1.These defects would generate interfacial
defect states in the band-gap of the semiconductor at the oxide/semiconductor interface
and affect the electrical properties of the device. The interfacial defect states can be
measured by many methods, the most popular being the C-V measurement of a
MOSCAP.
In our work, we used the conductance-frequency method to get information about the
interfacial defect states. This method was proposed by Nicollian and Goetzberger in 1967
and it extracts the information of Dit from C-V characteristics of the MOSCAP. Hence,
understanding of the basic principle of the MOSCAP and how the interfacial defect states
affect the C-V characteristics is important for our research. In this section, we will briefly
review the principle of the ideal MOSCAP and then include two non-ideal terms
(interfacial
defect state and series resistance) to see how these affect the C-V
characteristics of MOSCAP.
2.3.1 Ideal C-V Characteristics of MOSCAP
Figure
2.9(a) shows a typical
MOS
structure.
This
structure consists
of
semiconductor substrate with an oxide layer and a top metal contact, also referred to as
the gate. A second metal layer forms an ohmic contact to the back of the substrate to
decease series resistance. The substrate is a n-type semiconductor. The equivalent circuit
of the MOSCAP is shown in figure 2.9(b). The total capacitance C of the MOSCAP can
be simplified as a series connection of two capacitors, Cox and CD- Cox is the capacitance
of the oxide layer and CD is the capacitance in the substrate.Usually, the capacitance of
the depletion region underneath the gate is controlled by the gate DC bias. So, the
capacitance of MOSCAP can be expressed as C =(Cj + C)-'.
The capacitance C can also be defined as:
dQ
C
dV
The capacitance is the change of charge due to a change of voltage. During a capacitance
measurement, the signal, which contains small ac voltage superposed on the gate DC bias,
is applied to the terminals on the MOS capacitor in figure 2.9(a).The small-signal ac
voltage results in a charge variation giving rise to the capacitance. C= dQGIdVG, where
Q; and
V(; are the gate charge and the gate voltage, respectively. The DC bias is a result
of the variation of the static charges, including the space charge created by the depletion
of the carriers underneath the gate in the semiconductor.
(a)
r-----------,
(b)
_meta'
Oxide(
(C)
V(t) =V
Bias (V)
+
Cox
v exp(i.)t)
Bias (v)
VDC
V
N
M
Bias (V)
AA
~VD
+
I
v(t)= v,,exp(lawst)
Time N A
o,Time
Measurement Signal =
DC Bias
+
VV
Time
AC Bias
Figure 2.9 (a) MOS structure ,(b) Equivalent Circuit of MOS device shown in (a), (c) Small
ac bias of amplitude superposed on the gate DC bias applied to the terminals on the MOS
capacitor in (a) to measure its capacitance or conductance as a function of gate bias
The physics of the MOS structure can be easily explained by an energy band
diagram. The energy band diagrams and charge distributions of the MOSCAP are shown
in figure 2.10. Figure 2.10 (a) shows an accumulation layer of electrons induced by an
applied positive voltage. In this case, the valence band edge is closer to the Fermi level
due to band bending downward that is caused by the applied DC bias signal. The
electrons accumulate at the interface, and CD is very large because the thickness of
accumulation layer is very thin. The total capacitance in accumulation is close to the Cox.
Figure 2.10 (b) shows band bending upward when negative voltage is applied to the gate.
The positive space charge region is induced by an applied negative voltage. In this state,
the MOS capacitance is the series combination of Cox and CD, which is contributed by the
space charge region of semiconductor and varies with the applied negative DC gate bias.
The capacitance in this region can be calculated from the equation we described above:
C = (C( + C/)')- . Here, C, = eOEA/W ,where WD is space charge width and c, is
semiconductor dielectric constant. Now consider the case when a larger negative voltage
is applied to the gate (figure 2.10 (c)). The conduction band and valence band bend more
so that the intrinsic Fermi level has moved above the Fermi level. In this situation, where
the valence band is closer to the Fermi level than conduction band, the semiconductor
adjacent to the oxide-semiconductor interface becomes p-type. This inversion layer of
holes is formed as shown in figure 2.10 (c).When this happens, the inversion charge can
shield the DC bias to penetrate in the semiconductor to make the Fermi level move
further and the width of the space
charge (WD)
becomes
maximum
(CD
is
minimum).Further increasing the DC bias will increase the inversion charge density but
not the width of the space charge region. When the inversion charge is unable to follow
the ac voltage, the equivalent circuit is Cox and CD in series. By changing the voltage
through whole regimes, a high-frquency C-V curve is generated.If the inversion charge is
able to follow the ac voltage, the inversion layer induced by large negative gate voltage
will be neutralized by ac voltage. The equivalent circuit is formed only by a capacitor of
oxide Cox, and this is the same as the low-frequency C-V curves. The typical C-V
measurement changes frequencies from 104-106 Hz.
Figure 2. 11 shows the theoretical high- or low-frequency C-V curves in (a) C-V plot
and (b) C-#0, plot. The three conditions shown in 2.10 are labeled on the C-V curves.
#
is the surface Fermi level and equal to Ers-Eis ( Efs and Eis are the Fermi level and intrinsic
level at the surface of the semiconductor). Considering the physics of the MOSCAP,
#, is
a better parameter instead of gate bias V to describe the behavior of the MOSCAP. The
capacitance C of the MOSCAP is usually a function of the
#,
the gate bias V. For example, In figure 2.11 (b)(at C point), the
and
#,
#,
is a function of
always almost stays at
-0.6eV even if we apply a very large negative gate bias (shown in figure 2.11(a)).
Because capacitance is a function of
inversion region.
#,
the capacitance remains almost constant in the
+
Real MOS
Band-Diagram
Charge Distribution
(a)
Negative
Charge
Accumulation
Posiive
Charge
-- Metal
E,;
(b)
Ef
E,
-V
x
Depletion
0
Depletion
Region
APosltlve charge)
E,
.-
(c)
Inversion
Inversion
+-Oxide
Accumulation
Region
(Negative charge
Ej
E,
Invrio
charge
Depletion
Region
,Poaitive charge)
Wo
Space(Depleton)
charge
T -V,,
Inversion
charge
0
w
oo
Space(Depletion)
Wcharge
Metal -Oxide- Semicnductor (n-type)
Figure 2.10 Energy band diagrams and charge distributions of the MOSCAP in (a)
accumulation (b) depletion (c) inversion conditions
Figure 2.11 Theoretical high- and low-frequency curves in (a) C-V plot and high-frequency
curve in (b) C- , plot
2.3.2 Real C-V Characteristics of MOSCAP
In real device measurements, there are two modes that are used to measure the C-V
characteristics of a MOSCAP, one is the series circuit model and the other is the parallel
circuit model, depending on the characteristics of the device. The parallel circuit model is
involved in C-V measurement because there is high leakage current through the real
MOSCAP, the equivalent circuit model that of a parallel connection of a capacitor and a
resistor (shown in figure 2.12(a)) For DC bias, the resistor represents the total resistance
of the MOSCAP device. For AC bias, we connote the resistance as "impedance" and it is
derived from the loss of the displacement current due to the response of the interfacial
defect charges to the measurement AC signals. The conductance is the inverse of the
resistance (impedance)). The interfacial defect state charge can also affect the measured
capacitance (C) of the MOSCAP. By measuring the capacitance (C) and conductance (G)
of the MOSCAP, we can get the information of the interfacial defects. Figure 2.12(b)
shows the typical C-V and G-V curves from our experimental results.
(a)
(b)
200
40
~-
180.
CIIo
Cox
1000kHz
10kHz
--
--
G
0)
OkHz
140
go 100
2.
-...
1.5 C
......
M 60
0
1.0
60
Measurement
Circuit of MOS
Circuit
3.0
~1202.
C
Equivalent
3.5 E-
40
0.6
.
V4
v)
-
0
Figure 2.12 (a) Measurement circuit of the MOSCAP (b) Typical C-V curves from our
experiments, includes capacitance (C) and conductance (G)
In theory, all the C-V curves measured at different frequencies should coincide.
However, the existence of the series resistance in the C-V measurement system or the
interfacial defect states at oxide/semiconductor interface may cause a shift of the C-V
curves measured at different frequencies. This phenomenon is called frequency
53
dispersion.
2.3.2.(a) Series Resistance R,
As discussed in previous section, a parallel circuit model was used as the
measurement circuit for MOSCAP. However, there is always a series resistance in the
measurement system. The real measurement equivalent circuit should connect the parallel
circuit with a series resistance in series and this is shown in figure 2.13(a). The series
resistance (Rs) can cause a serious error in the extraction of interfacial properties from the
C-V measurement. It will affect the C-V curves measured at high frequency and cause the
frequency dispersion of the C-V curves in the accumulation region. Figure 2.13(b) shows
the theoretical C-V curves affected by series resistance. In order to get accurate C-V
results, the series resistance should be as low as possible during the measurement.
Series resistance can arise from five different sources: (1) the contact made by the
probe to the gate; (2) the back contact to the substrate (3) a dirt film or particulate matter
between the back contact and the probe stage; (4) the resistance of the substrate (5) an
extremely non-uniform doping distribution in the substrate underneath the gate.
Non-uniform doping is usually not an important issue[2.19].
To minimum the source (1), we slightly scratched the top surface of the gate electrode
to remove the native oxide and made the probe needle contact directly during the C-V
measurements. For source (2) and (3), we could make ohmic contact to the back side of
the substrate by depositing Au-Ge or Au-Zn contact metal on the back side of n- or
p-type substrate. However, this step was lengthy and the sample was exposed to
high-temperature annealing in order to form the ohmic contact. This process could
54
change the electrical properties of the MOSCAP. To avoid these drawbacks, we applied
an In-Ga eutectic alloy (495425 Gallium-Indium eutectic from Sigma-Aldrich) to make
the back contact. This alloy is easy to spread on the substrate because of the low melting
point. We scratched the substrate with this alloy using a diamond pen to remove the
native oxide of the substrate and thereby make direct contact to the substrate. For source
(4), it is possible to render the bulk series resistance negligible by using a thin epitaxial
layer of low resistivity grown on a degenerate substrate. In our experiments, we usually
grew a thin n- or p-type GaAs layer on N+ or P+ GaAs substrates to minimum this bulk
resistance. By caring for these sources of the series resistance, we minimized the series
resistance effect in our C-V measurements and this can be observed in figure 2.12(b). No
significant frequency dispersion is observed in the accumulation region of the C-V curve.
(a)
C
m
(b)
4
Gm-
-1000kHz
600kHz
100kHz
50kHz
CL-
0
v 0.3
-
C
-
-
10kHz
n-ype Si
Idea C-V
N = 1 Si
C x
m
0.5 (,Ficm)
go
0.1
Ideal Measurement
Real Measurement
Circuit
Circuit
-
Series Resistance
.
R=0.2 (0 cm')
2
1
V (V)
Figure 2.13 (a) Measurement circuit including a series resistance R, (b) Theoretical C-V
curves that affected by a series resistance
2.3.2.(b) Interfacial defect state
In an ideal MOSCAP, the charges only exist in the metal and the bulk of the
semiconductor. However, the oxide and oxide-semiconductor
interface are never
completely electrically neutral. There can be mobile ionic charges, electrons, or holes
trapped in the oxide layer. There can also be fabrication-process-induced fixed oxide
charges near the oxide-semiconductor interface. Since every device has some regions that
are covered by oxide, the C-V characteristics of the device of a device are very sensitive
to the density and properties of the charges inside its oxide regions and at its
oxide-semiconductor interface.
The nomenclature for describing the charges associated with the oxide in real
devices is standardized [2.181. The net charge is termed by
Q.
Thus, Qm denotes the
mobile charge, Qot denotes the oxide trapped charge, Qfdenotes the fixed oxide charge,
Qit denotes the interface defect charge. The names and location of these charges are
illustrated in Fig. 2.14. Because the Dit is usually very high at the oxide/GaAs interface,
the Qit can be the dominant charge in our MOSCAP. Here, we now focus on how
interfacial defect charge Qit (interfacial defect state) affects the C-V characteristics of the
MOSCAP. In general, the "stretch-out" and frequency dispersion of the C-V curves are
mainly caused by the existence of the Qit.
Mobile ionic charge
++ +
Oxide trapped charge
Oxide
+ + ++++++ Fixed oxide charge
Interrace defect charge
emiconductor
Figure 2.14 Charges associated with the Oxide/Semiconductor structure. Figure reproduced
from B.E. Deal[2.181.
If the frequency of the AC measurement signal is very high in the C-V measurement,
the interfacial defect charge can not follow to the AC voltage. Although the interfacial
defect charge does not follow the high-frequency AC gate voltage, it does follow the DC
bias as the MOSCAP is swept from accumulation to inversion. As a result, the interfacial
defect state will fill and empty with the charge (electron or hole) as Efs moves through it
and this could be understood by figure 2.15(a). Because the interfacial defect charge does
not respond to the AC voltage, it contributes no capacitance to the high-frequency C-V
curve. However, as the interfacial defect charge does follow changes in DC bias (or 0.),
they cause the high frequency C-V curve to stretch out along the gate bias axis because
the interfacial defect charge must be changed in addition to changing space charge. This
stretch-out is illustrated in figure 2.15(b), which shows a hypothetical high-frequency
C-V curve with different densities of the interface defect state to an ideal C-V curve. The
magnitude of the stretch-out (compare to the ideal C-V curve) is given by Qj, / Cox.
57
As figure 2.15(b) shows, distortion of the shape of the C-V curve will be observed
even if interfacial defect states are uniformly distributed in energy over the band-gap. The
other extreme, an interfacial defect state distribution with pronounced structure will be
reflected in pronounced shape distortion of high-frequency C-V curve. For example, if Di
increases abruptly somewhere in the band-gap, capacitance will change much more
slowly with the gate bias (flatten out) as the abrupt increase in interface defect state
density is swept past the Fermi level at semiconductor surface by the gate bias [2
Interfacial
Space Charge
defect charge (Q)
Region
_V9
Interfacial
Reio
defectE C
~ ~ES
.1
C
5x10" (eVc
0 10 (eV m"
.4
state0.
.
(b)
#sdWO
0.5
Ielv
-a
U
Er
Oconinlfsbt~c
0.2
A V =Q, i
-
E
n-type Si
9L 1N
104 (cm)
Co= 0.5 (pFcm')
(a)
E.
-3
-2
-1
0
1
2
3
Vg (v)
Figure 2.15 (a) Energy band diagrams the MOSCAP with interfacial defect state (b) A
theoretical high-frequency C-V curves with interface defect state stretch-out compared to a
theoretical C-V curve, with no interface defect state. The interfacial defect state is assumed
to uniformly distribute in the band-gap and contains both electron and hole traps
However, in reality, the interfacial defect charge does respond to the AC voltage
even up to 100MHz. It does contribute capacitance Cit to the high-frequency C-V curve
and the equivalent circuit with interfacial defect state capacitance Ci, is shown in figure
2.16(a). The magnitude of the Ci depends on the interfacial defect state density (D, ,
Cz, qD,, ())
and the measurement frequency. The distribution of the interfacial defect
state in the band-gap is usually not uniform and Cit therefore varies with frequencies and
58
gate DC bias (or 6). When we measure the capacitance C of the MOSCAP, it will
include both CD and Cit into account and this leads to the frequency dispersion of the C-V
curves at different frequencies. The theoretical C-V curve with frequency dispersion is
shown in figure 2.16(b).
The existence of the interfacial defect state will stretch the C-V curve out and cause
the frequency dispersion of the C-V curves. The higher the Dit, the larger the frequency
dispersion of the C-V curves and stretch-out. This provides us an easy and intuitive way
to evaluate the level of the Dit of an oxide/semiconductor interface.
(a)
0
0
T
CoxE
CDF1.f
eu
c
i
w
E
0.
Aimd
kH
i
0.4
sevta
C0.2
.1kHZ
D
0IS 3 10
.cDO~~
f0eV'Mo')
0.5.5(Fim
ns both
e
S nih rp
.10~~
/ntPO
capacitance
Firen
.16c(a)
Equivalent circuit withneraca deec
stat
caaia
1
C
C2 is
frequency dependent (b) The theoretical C-V curves with frequency dispersion
AC
sladeichfeunyadtersos
interfacial fte
defect
charge in the
2.3.3 Conductance-Frequency method to extract the Di from C-V measurements
As mentioned in previous section, the interfacial defect charge can respond to the
AC signal at high frequency and the response of the interfacial defect charge in the
band-gap of the GaAs follows the Shockley-Read-Hall (SRH) model and they can be
characterized by their density and capture probabilities for both electron and hole as
function of band-gap energy [2.19]. In this process, the characteristic time and response
frequency of the charges (electron or hole) that are trapped in the energy state E, in the
band-gap can be determined by from the Fermi-Dirac statistics and is shown in following
equation:
S
exp (AET)
2rf
U-vN
where f is the response frequency, r is the characteristic time , AE is the energy
difference between the majority carrier band edge energy and the trapping state energy E,,
k is the Boltzmann constant, T is the semiconductor temperature, c is the interaction cross
section of the defect state, v, is the thermal velocity of the majority charge carriers, and N
is the density of states in the majority carrier band. Figure 2.17 shows the response
frequency of interfacial defect in GaAs as a function of the position of the trap in the
band-gap. Here, we assume the interaction cross section of the defect state as
108
N
--
-
L
).
0
25 C a
= 10
1
cm
2
/
2
10
/
10
U_
2
Electron
Hole
107
10-"(cm
10
ntp
ptp
LT10
o 10
0 10
,)p-type:
0.0
EV
0.2
0.4
0.6 EiO.
/
8
E - E (eV)
-ye
1.0
1.2
1.4
EC
Figure 2.17 Response frequency of the interfacial defect charge at interfacial defect state in
GaAs at room temperature
In the C-V measurements, the measuring signal consists of two components: the DC
gate bias and small AC signal bias with frequency fs. Only the charge in the interfacial
defect state that the response frequency f is equal to the frequency of the AC signal fs can
respond during the C-V measurement and contribute to the conductance response and the
capacitance. This response gives a significant conductance peak in the C-V measurement
result and this can be seen in figure *9(b).The magnitude of this conductance response is
proportional to the Dit. We can extract the Dit from our measured capacitance Cm and
measured conductance Gm, by following equations:
D, = 2.5
(G
Aqco
; G=
(G,/coC,
2
"
+(I -C,/C, })
Here, A is the area of the MOSCAP, co =2rf and q is the unit charge [2.20].
This means that we can probe different positions of the interfacial defect state in the
band-gap by changing the measurement frequencies and extract interfacial defect state
densities at those positions from C-V curves measured at different frequencies. This is the
conductance-frequency method that we applied to extract the distribution of interfacial
defect state density from the C-V results in our experiments.
Chapter 3 In Situ CVD AIN on p-GaAs
Oxide is the most common material to be used to passivate the semiconductor
surfaces. However, AIN was first chosen as the passivation material in our MOCVD
system. AIN has a wide band-gap (6.2 eV) and has become increasingly important in the
field of optoelectronics [3. 1]. Because of the piezoelectric properties, and high thermal
and chemical stability of this material, AlN films may have application in dielectric
insulators, surface acoustic wave devices, second harmonic generation [3.2]. The first
AIN thin film grown in MOCVD system was reported in 1971 by reacting TMA and NH 3
at high temperature (1500K).
Passivation of GaAs by a AIN thin film has following advantages:(i) the thermal
expansion coefficient is close to that of GaAs; (ii) its ionicity is close to that of GaAs, and
it is homovalent with GaAs ; (iii) its deposition does not result in the oxidation of GaAs
AIN thin films were grown by low-temperature in situ MOCVD via TMA and
DMHy on p-GaAs. Applying DMHy as the nitrogen source instead of NH 3 lowers the
deposition temperature from 1500K to 650K. Based on these advantages, the AlN was
our first trial to in situ deposit on the GaAs in MOCVD system.
3.1 Experimental procedure
The growth experiments were all performed in our MOCVD reactor, including the
buffer p-GaAs and the passivation AlN layer by CVD. High-purity N 2 gas was used as the
carrier and the purge gas. GaAs epilayers with a Zn doping of 2
on Zn doped GaAs (l
0 18
cm-3 ) two-inch substrates at 650
x1017
cm-3 were grown
C with TMG and AsH 3
(V/111= 23). Following the buffer layer growth,the temperature of substrates decreased to
63
400-600
0
C. CVD AIN was grown with
TMA and DMHy
as the precursors
(DMHy/TMA=100, molar ratio).The growth rate of AIN thin film is shown in figure 3.1
The brief process flows for the growth of these experiments are shown in figure 3.2. The
microstructure and interface between the CVD AIN films and the GaAs substrates were
investigated by HRTEM.
XPS was also performed to determine the bonding state of the
elements at the interface and on the surface of AIN thin film. The C-V characteristics of
MOSCAP were measured using HP4192A LF impedance analyzer at frequencies(f) from
IMHz to 10kHz and the capacitors were fabricated by depositing the Al electrodes 250
[tm in diameter by thermo-evaporation.
0.12
=100 torrs, TMA=40 sccm, UDMHy = 425.8 sccm
P
ea
0.10
E
0.08
40.060.04
0.06
O
0.02
0.00
I
.
I
.
I
,
350 400 450 500 550 600 650 700 750 800
To (c)
Figure 3.1 The growth rates of AIN thin films at different deposition temperature
CVD GaAs
0
650 C
CVD AIN
0
400 C 0
550 C
Time
Figure 3.2 Process Flow of the In situ CVD AIN on p-GaAs
3.2. Microstructure of AlN/GaAs interface
Smooth high-k/semiconductor interface is a very important for MOSFET to lower
the Di, at interface.Figure 3.3 shows the XHRTEM pictures of the samples grown at
400,500 and 600 0C. All the AlN thin films are poly-crystalline and the interfaces are
smooth and sharp, no interfacial layer
is observed. The grain size of the AIN thin film is
larger when the growth temperature is higher.
5 *C
T,. = 500
Ta = 400*C
T, = 600 *C
Figure 3.3 HRTEM image of AIN on GaAs grown at 40 0 "C, 500"C, and 600"C
3.3 The chemical stoichiometry and bonding state of the AlN thin film
The AIN thin film is very sensitive to humidity in the air. It would react with the
water to perform the hydrolysis reaction to from the aluminum hydroxide. Figure 3.4
shows the narrow scan XPS spectra of N Is (a), and the 0 Is (b) states of the AIN thin
film with sputter cleaned, respectively. The spectra have been processed with software to
fit the Gaussian peak components mixed with Lorentzian shapes. The spectra were
calibrated on C Is binding energy of 284.5 eV. Two deconvoluted peaks in N Is spectrum
correspond to binding energies 396.6 eV and 398.0 eV. The peak with lower binding
energy corresponds to the nitride state (Al-N bond) and the other peak shifted by 1.4eV to
higher binding energy originates from the ammonia (N-H bond).Similarly, two peaks
were observed in 0 Is spectrum. The major peak centered at 531.4 eV corresponds to the
66
L__- -
__ .__
- 7:3
-
AI(OH) 3 ( O-H bond) , while the smaller peak shifted to higher binding energy comes
from the absorbed water (0-H bond).
is(a)
AM
A--O-H(Al(OH)3)
0
396.6 eV
ls(b)
531.4 eV
/
N-H-
398.0 eV
- O-H(H 20)
533.6 eV
402
398
400
396
Binding Energy (eV)
394
392
536
534
532
530
528
Binding Energy (eV)
Figure 3.4 XPS spectra of (a) N Is and (b) 0 Is core level of CVD AIN
The AI(OH) 3 thin film was formed on the AIN surface due to the hydrolysis reaction
shown below:
AlN + 2H 20 -+*AlOOH(amorph) + NH 3 (1)
AIOOH(amorph) + H2Q --+ Al(OH) 3(xstal)
(2)
This layer was formed when the sample was taken out from the reactor and exposed
to air before depositing the Al top electrode. The thin film is therefore composed of two
layers: thin AI(OH) 3 and AIN. The AIN and AOOH have different dielectric constants
and conductivity and the Maxwell-Wagner effect will create vertical frequency dispersion
in the C-V curve.
3.4 C-V measurements and band structure of AlN/p-GaAs
To be a good passivation oxide material for MOS devices, low leakage current
through the gate oxide must be achieved. The first basic requirement for this condition is
that the conduction and valance band-offsets (AE and AE,,) should be at least larger than
IeV. Second, these energy barriers do play their role to be effective barriers for both
electrons and holes. This means the conduction mechanism in the oxide should follow the
behavior of Fowler-Nordheim (F-N) tunneling.Figure 3.5(a) shows the current-voltage
curves of the sample grown at 500 0C and thickness is 28.6 nm. The raw data was
compared to simulated curves based on different conduction mechanisms. Figure 3.5(b) is
the F-N tunnelling plot, figure 3.5(c) and figure 3.5(d) are the Schottky plot and the
Poole-Frenkel(P-F) tunnelling plot. There are linear regions in the Schottky and the P-F
plot but not in F-N plot. These results imply
that F-N tunnelling is not the dominate
mechanism. To determine the real dominant one, in the remaining options, the dielectric
constant of the insulator was calculated from the slope of the plots. The dielectric
constant calculated from figure 3.5(c) is 8.9 and dielectric constant calculated from figure
3.5(d) is 2.28. The dielectric constant of AIN is about 8.5, so the dominaNT leakage
mechanism is the Schottky mechanism.
IE-14
0.1 Raw
'"" t
AIN
IE-3
data
Fowler-Nordhim
1E-15
=28.6 nm
JAexp (A/ E)
1E46
1E-4
1E47
1E-4
1E--13
1E-4
-
1E4
b
1E-19
1E-20
1E-10
0.0000010
0000005eoo
1E0
0..000016
1/E (cmN)
E(MVcmn)
1E-7
104-
Poode-Frenkel
1E4
J=A 2 EexP Eq elkll
2
29
1E-10
1E-3
10
IE41
1E-6
1E-12
1E-7
IE43
1E-0
(C
0
m
1000
1100
E*2((Vlcmr)')
2000
(d)
1IE-15
2'NO
0
SDO
1000
I=A
2000
2000
E "((Vcmn)')
Figure 3.5 (a) The J-E curve of the AIN thin film (b) Fowler-Nordheim plot (c) Schottky plot
(d) Poole-Frenkel plot
The Schottky barrier height can be determined by measuring the leakage currents at
different temperatures. The result is shown in Figure 3.6. From figure 3.6(b), the Schottky
barrier height is determined from the slope to be 0.15 eV, which is close to the barrier
height of a grain boundary. The possible conducting path is the grain boundary, not the
hulk AIN.
-295
IE-4
_E- 323I
= -15.35- 1736.74 X
.8Y
*OleV
ey
g
-4I
1E4
-338K
a
EIE4
IE-?
IE-8
-
M@03
6160
616M
A@
2
A
61678
A32
61034
IIT (IK)
E'"((V/cm)" )
Figure 3.6 (a) The J-E curves measured from 298K to 368K (b) The Arrhenius plot of the
leakage current density
Because of high leaky current in the AIN thin film, it is hard to obtain the
information of the band structure from current-voltage measurements. In order to
determine the valance and conduction band offsets between the AIN and GaAs, the core
level to VBM binding energy difference and the bandgap fo the AIN must be determined.
The method for determining these is proposed by Kraut et al. and others [3.4][3.5]. The
valence band offset could be determined by following equation:
AE
Where(EGAEA*), (EcI-N
=(E
VB
CIL _AIN
VB )-(E AIN
CIL -E GaAs
v GaAs
)+AE
CL
) ,and AECL ,are the core level to VBM binding energy
difference for GaAs and AlN, respectively. The last term is the core-level to core-level
separation at the AIN/GaAs interface.
The bandgap of the AIN can be measured from the onset of electron loss signal for the
N Is core level peak. The Eg is determined as the energy separation between the zero loss
and their threshold of inelastic energy loss due to the band to band excitations. Fig 3.7
shows the XPS spectrum from the GaAs, AIN and AlN/GaAs interface. By fitting the
70
peaks and measuring the energy difference between core levels and the (valence band
maximum) VBM core-level to core level energy difference, the valance and conduction
band offsets were calculated to be 2.56eV and 2.34.eV, respectively. Both conduction and
valance band offsets are larger than I eV and therefore suitable for a gate dielectric.
However, the results of current-voltage measurements show that the conducting path is
through the grain boundary of the AIN grains, not the barriers of the conduction and
valance band. If the polycrystalline nature of the AIN could be overcome (full
crystallinity or fully amorphous), then the leakage problem might be solved.
AIN film
GaAs
E
= 40.48 eV
-as
E G"
2
X 15
X10
z
86420-2
4846444240383
Binding energy(eV)
AIN-GaAs interface
E
VB
VB
2p
VBAl
= 70.88 eV
- EA
A 2p
As3d
VM
As 3d
E
3 876 7472 70 1210 8 6 42 0 -2-4
Binding energy(eV)
N 1S
Energy loss spectrum
- EA." = 32.96 eV
Eg(AIN)
r
6.12 eV
As 3d
Al2p
7
80 78 76 4 27O
46 44
40 38 3
12
10 En
4rgy
Loss(eV)
Figure 3.7 XPS spectrum from the GaAs, AIN and AIN/GaAs interface
3.5 C-V measurements and Interfacial defect density (Dit)
We determined how the surface treatment before the deposition of the AlN affects the
interface properties, includes the Dit and the trap relaxation time.
Before growing the AIN layers, Zn-doped p-type buffers are grown at 650 C. Then,
the sample was cooled down to 500C and treated by the following way before further
cooling down and depositing the AIN at 400 0C:
(a)Turn off the AsH 3 flow for 10minutes
(b)Turn off the AsH 3 flow for 10 minutes and flow TMA for 60 seconds
(c)Turn off the AsH 3 flow for 10 minutes and flow DMHy for 60 seconds
(d)Keep the AsH 3 flow before depositing the AIN
The C-V characteristics are measured at room temperature and the dc bias is swept
from depletion to the accumulation region from -6V to 6 V. All measurements were
performed in the dark without illumination. Figure 3.8 shows the C-V results of the
samples with different treatment ways.
10rD
of AIN
depositin
100, out AsH.before
-
N
eoeop
U
n
sot
-
10OWk
500k:
gok
go
11
100k.
100
1000
Go
50-
(a)
30 ----------- 4----
-2
0
(b)
30 - -
.....
---- -----
4
0
4
-4
--
-2
0
loo0k
loo0k
Ia.
-~
a
0
L70
50Ok
10000k
so
- 500k
-100k
fl.
6
-4
With AsH,Nlowbeforedepositto.of AN
100
RwUDittiyOtobeforedeposgonof AIN
110
g.o
2
Vg(V
Vg(V)
W
60
0
----d
---
---
24
4
Vg(V
4 -42
0
6
Vg(V)
Figure 3.8 (a) Capacitance-Voltage curves for different treatment (a) Turn off the AsH 3 flow
for 10minutes (b) Turn off the AsH3 flow for 10minutes and flow TMA for 60 seconds (c)
Turn off the AsH 3 flow for 10 minutes and flow DMHy for 60 seconds (d) Keep the AsH3
flow before depositing the AIN
All samples show large frequency dispersion and the capacitance in accumulation
decreases when the measuring frequency increases. The vertical shift of the C-V curves in
accumulation can be due to several reasons: an interfacial layer on the AIN thin film, Dit,
and high series resistance. The horizontal shift of the curves is mainly from interfacial
defect states. Because the frequency dispersion is very significant in the C-V curves, we
would not apply the conductance-frequency method we discussed in section 2.3.3 to
extract the Dit. But, we employed an easier method to extract the Dit from the voltage
shift with different measurement frequencies by applying the following equation (if we
assume the Dit distribute uniformly in the band-gap [3.6])
AV =I+
C,
) I n 1O,where Ci is the capacitance of the insulator.
q
We set 60pF as the reference point to evaluate the voltage shift (AVG) between
100kHz and 1000kHz and the Di, could be extracted by these values. All of the
information are summarized in Table 1.
Table 3.1 The summary of Dit
Treatmentment
(a)
(b)
(c)
AVG (V)
1.6
1.875
2.1
Dit (eVcm- 2 )
3.18 x 10"
4 x 10'3
4.46 x
(d)
10 3
X
**
X
**
** The C-V curves do not horizontally shift and this does not fit the model. But it should
be with the same order as (a),(b), and (c).
Dit of all samples (except (d)) are all above 1013 (eV'cm- 2 ). The sample (a) has the
minimum Dit compares to sample (b) and (c). This may be the evidence that shows the
precursor used to grow the AIN would react with the substrate to make the Dit high. The
nitrogen source, DMHy, can nitridize the surface during the AIN deposition and release
the As to the interface [3.7]. This reaction is very similar with the oxidation of the GaAs
surface which creates a high Dit. In order to prove this hypothesis, another sample was
treated in the same way as (a) but deposition of the same thickness of the AIN on GaAs
was done at 500 C. The C-V curve of this sample is shown in figure 3.9.
100
--- --- --
-
-
-
9L
-
-
-100k
g
--
70-
50k
5D -
~4010100
30
-1044-9-744- 4-3-2-10
1.23
4
Vg(V)
Figure 3.9 The C-V curves of AIN on GaAs grown at 500"C
The voltage shift (AVG) of this sample is 2.4 V and the Dit is 5 x 1013 (eV'cm 2 ),
which is larger than the sample (a). These results imply that the reaction creates higher Di,
at higher temperature.
Finally, the sample (d) could not be analyzed by this model. But we could analyze it
qualitatively. The higher the Dit, the more serious the distortion of the C-V curves at high
frequency. In comparing the C-V curves of the all samples measured at 1000kHz, we find
that the distortion of the C-V curve of the sample (d) is the most serious, the highest Dit
of sample (d) may have.
In summary, surface treatment before the deposition of AIN affects the the Dit. The
DMHy could nitridize the substrate and cause high Di,. The AIN is very leaky due to the
poly-crystal structure. Based on these two drawbacks, we have concluded that AIN is not
a good dielectric candidate until these two fundamental issues are resolved.
Chapter 4 In Situ ALD A12 0 3 on p-GaAs
The AIN research resulted in a couple of important observations: First, we must avoid
any reaction between precursors and substrate during the dielectrics deposition; and
second, a completely amorphous or completely crystalline dielectric is preferable. One
solution for these two guidelines is to choose an amorphous high-k material that can be
deposited with appropriate precursors, and these precursors would be compatible with the
MOCVD system but not react with the substrate during the deposition. Thus, we began to
investigate the possible use of ALD A12 0 3 in our MOCVD system.
H20 is the most common oxygen source for ALD oxides formed with metalorganics.
However, in our studies, we have chosen alcohol as the oxygen source for the in situ
experiments.
We have two reasons for pursuing this path of research. First, water is the
common impurity in epitaxial deposition systems and degrades the quality of the Ill-V
thin films grown in such a system, e.g. a MOCVD system. The residual H20 in the tubing
system can react with the precursors to form small particles which affect the gas
transportation [4, 1]. After a thorough study of Al-containing prrecursors, IPA as the
oxygen source for our ALD experiments in the MOCVD. IPA will not react with the
semiconductor surface during the ALD process, [4.2] and this aids in lowering the
interfacial defect density at the oxide/GaAs interface.
4.1 Experiments Procedure
The
growth
experiments
were
all
done
in an
AIXTRON/Thomas
Swan
close-coupled showerhead cold-wall MOCVD reactor, including the buffer p-GaAs
growth by CVD mode and passivation oxide growth by ALD mode. High-purity N 2 gas
was used as the carrier and the purge gas. GaAs epilayers with a DMZn doping of 2 xl'
77
7
cm~3 were grown on Zn doped GaAs (lxlO18 cM-3) two-inch substrates at 650 0C with
TMG and AsH 3 (V/Ill= 23). Following the buffer layer growth, the temperature of the
substrate decreased to 500'C, where the arsine flow into the growth chamber was turned
off. Then the temperature continued to decrease and after the temperature stabilized at
growth temperature, A12 0 3 films were grown using TMA and IPA under a deposition
pressure of 50 Torr. The partial pressures of the TMA and IPA in the reactor were kept at
0.02 and 0.15 Torr during ALD, respectively. The pulse time of the TMA and IPA
change from Os to 10s and the N 2 purge time kept 5s. The brief process flow is shown in
Figure 4.l.The thickness of the oxide films were evaluated by TEM and XRR. The XRR
software was used to fit the x-ray reflectivity spectra. The microstructure and interface
between the deposited A12 0 3 films and the GaAs substrates were investigated by HRTEM.
The depth profile XPS was also performed. The samples for electrical measurements
were
fabricated
by
the
depositing
electrodes
Al
250
tm
in
diameter
by
thermo-evaporation and the C-V characteristics was measured using HP4192A LF
impedance analyzer at room temperature.
CVD GaAs
700
' 600
00
ALD A2,O
650*C
0'
300
200
0E 100
0
00
700
400
0 200
100
S 0
100
u 50
200
E100
S
50
0
Time
Figure 4.1 Process Flow of the In situ ALD A120 3 on GaAs
78
4.2 Experiments of ALD with TMA and IPA
The major characteristic of ALD is a self-limiting surface reaction (monolayer
growth), which means the surface reaction would saturate and additional reactant
exposure would not increase the growth rate further if the precursors pulse times are long
enough. The growth rate of ALD is usually expressed as thickness increment per cycle.
Usually, the growth rate is determined by dividing the measured film thickness by the
number of the deposition cycles after the film growth.
Figure 4.2 shows the growth rate of A1 2 0 3 ALD depending on the pulse time of TMA
and IPA at 400C. The ALD A12 0 3 shows the typical self-limiting behavior .The red and
black dash lines in the diagram represent the fitting line of the function Rox (-e-Bt)
precursors IPA and TMA, here the R,
for
B, and t are the saturation growth rate, time
constant, and pulse time. This equation represents the simple form of the adsorption
kinetics which based on the irreversible Langmuir adsorption model. The fitted R" for
both TMA and IPA are about 0.81 (A/cycle) and they both reach the saturation growth
rate when the pulse times of TMA and IPA are longer than 2s. B is a process dependent
time constant which is linearly dependent on the partial pressure of the precursor in the
reactor and is fitted as 1.749(1/s) in our experiment. The growth rate slightly increases
(0.83 A/ cycle at 10s pulse time), which may be due to the thermal decomposition of the
adsorbed precursors on the surface if the pulse time is too long or if there is an
insufficient purge time. Insufficient purge time between the precursor pulses may result
in an overlap of precursor exposure, producing CVD-like growth and an increase in
growth rate.
1.0
(D
0.4
TMA
0.24.
eIPA
0.0
0
2
4
6
8
10
Precursor Pulse time (s)
Figure 4.2 Growth rate of ALD A12 0 3 on GaAs at 400"C vs. precursor pulse time
Figure 4.3 shows the thickness of the thin film grown with different cycles at 400C
when the precursor pulse times and purge times are kept at 5s. The data can be fitted
linearly and the slope represents the growth rate, which is 0.8085 (A/cycle). This value is
almost the same as the saturation growth rate, R. The growth does not show a significant
surface inhibition effect, which is usually observed in ALD oxide depositing on hydrogen
terminated silicon[4.3]. Both TMA and IPA can initialize the growth easily on the GaAs
surface.
22
20
- Y = 0.00126 + 0.08085 X
18
-
.'
Growth Rate = 0.8085 (Al cycle)
16 C
14
(n
12 -
)
10
8
-
~
26
'7
4
U
2
.
0
0
50
100
150
200
250
No. of Cycles
Figure 4.3 Thickness of the thin film grown with different cycles
80
Figure 4.4(a) shows the dependence of the ALD A120 3 growth rate on growth
temperature. The pulse times for TMA and IPA are both 5s. Two kinds of growth rate vs
temperature dependences can be observed in the figure. The major temperature regime
for the ALD is the one which proceeds in self-limiting behavior and produces the same
growth rate (temperature independent growth rate). Our results show that ALD is
occurring when the deposition temperature is higher than 350'C and the growth rateis
0
near 0.8 (A/cycle). In the lower temperature regime (below 350 C), the growth rate
decreases with decreasing temperature and this behavior is usually due to kinetics ; the
precursor adsorption or growth reaction rate becomes too slow and the reaction can not
complete within one pulse period. If the pulse time increases, in theory, the reaction
might have enough time to reach self-limiting behavior. However, this would increase the
cycle and total growth time.
The quality of film can be monitored by measuring the refractive index of the thin
film. Figure 4.4(b) shows the relation between the growth temperature and the refractive
index of the ALD A12 0 3 thin film. The refractive index remains almost constant at the
temperature above 350'C, showing that a good quality film can be deposited above
3500C.
0
Based on these results, our ALD growth temperature was set at 370 C for all of our
experiments.
0.9
0.
- - - - - - - - -
----------
0.8 -- - - - - - - --
>% -8--
-
2.0
Self-limiting reaction
- -----
1.9
----
0.6
0.4
4)
-
0.3
W
1.7
0.6
0.2
0
1.8
0.7
0.5 -
00.5
Growth Rate,
--
1.6
0.1
300
320
340
360
380
400
420
340
440
350
360
370
380
390
400
T (C)
T (C)
(b)
(a)
Figure 4.4 (a) Dependence of ALD A12 0 3 growth rate on temperature. The pulse time for
TMA and IPA are both 5s (b) The relation between the growth temperature and the
refractive index of the ALD A120 3 thin film
4.3 Mechanism of ALD with TMA and IPA
The saturation growth rate of the common ALD A12 0 3 which is grown with TMA
and H 20 as the precursors is around 1 A /cycle. However, the saturation growth rate of
ALD A12 0 3 with IPA as the oxygen source is measured as 0.8
A
/cycle. Also, the
dependence of the ALD A1 2 0 3 growth rate on growth temperature is also different for
these two precursor sets [4.4]. These results imply the growth mechanism may be
different depending on whether IPA or H20 is used as the oxygen source. The mechanism
of the ALD A1 2 0 3 with TMA and H2O as precursors had been widely studied by other
researchers and this deposition is achieved by separating a binary reaction for A120
(2A(CH 3) 3 + 3H20
->
A1 2 0
3
+
6CH 4 ) CVD into two half-reactions(Eq. I and Eq. 2):
AIOH*+AI(CH 3)3
> AlOAI(CH 3) +CH 4
(1)
3
AICH* +H 2 O
>AlOH*+CH 4
,where the asterisks indicate the surface species to be the bridge for the following
reaction.
The TMA-IPA ALD mechanism is more complicated and can be understood by the
following reactions. The main reaction of this ALD reaction is relative to the reaction of
aluminum isopropoxide (AI(OCH(CH 3) 2) 3) and TMA (Eq. 3):
AI(OCH(CH,)2)3+Al(CH 3)3
>A1 203+3CH 3CH(CH 3 )2
Ritala et al, successfully deposited A12 0
3
(3)
on Si without forming an interfacial oxide
by using the TMA and aluminum isopropoxide (Eq. 3).The interfacial oxide layer usually
forms during the ALD reaction with H20 as the oxygen source. Because the H 20 is a
strong oxidant can oxidize the substrate in the H 20 pulse cycle in the initial stage of
growth. But, this is not observed in Ritala's experiments and the reason is that the oxygen
is always strongly bonded to the aluminum for the aluminum alkoxide and it does not
have the chance to react with the substrate during the deposition
L45.
However, unlike the TMA, aluminum isopropoxide is white solid source with low
vapor pressure at room temperature. The aluminum isopropoxide must be heated to at
least 120'C to obtain a suitable vapor pressure (around 1.7 torrs) for deposition. However,
compared to the vapor pressure of TMA at 20'C (8.74 torrs), it is still too low and would
need a longer pulse time. Also, the MOCVD system may suffer the risk of aluminum
isopropoxide condensation in the carrier lines if they are not heated or if some cold spots
exist in the line.
In order to avoid this risk, , IPA was chosen as the precursor instead of aluminum
isopropoxide because it is a liquid source and the vapor pressure is high (33 torrs) at 20C.
Furthermore, the IPA is not an oxidant that can oxidize the substrate during the
deposition. Even though the IPA dehydrates at high temperature in an oxygen-free
environment, it decomposes to acetone ((CH 3)2CO) and hydrogen (H 2); no H20 or
oxygen would be generated. By choosing the IPA as the oxygen source, the intermiediate
alkoxide (aluminum isopropoxide) forms by the proto-dealuminum reaction (Eq. 4)
during cycle [4.6]:
Al(CH 3)3+3(CH 3) 2CHOH
>Al(OCH(CH 3)2)3+3CH
4
(4)
The difference between TMA-IPA and Aluminum isopropoxide-TMA ALD is that
the aluminum isopropoxide is formed during the IPA pulse cycle in the case of TMA-IPA,
while the aluminum isopropoxide is used directly as the precursor in aluminum
isopropoxide-TMA ALD. These reactions imply that our process is a non-water process
and should not oxidize the surface of the GaAs during the ALD A1 2 0 3 . The schematic
demonstration of the ALD process is shown in figure 4.5.
Purge
The first TMA Pulse
CM3
CH3
Al
CH 3
CH3
CHs
tL
Purge
The IPA Pulse
C
CH(CH 3)2
H
CH3 V
Al
CH(CH3) 2
3
-0 V1
The TMA Pulse
CH3
CHz4
CH(CH,3)
GaAs
Purge
CH 3
C
C4H
U
CH
\
CH(CHs)2
0"AN
o0
CH(CH 3)2
3
AE Al
C 3CH
M
Ga
GaAs
CH 3
As
A
NPOEMMOOMMMIff
Figure 4.5 The schematic demonstration of the ALD process
4.4 Structure of the ALD A12 0 3 thin film
Low surface and interfacial roughness is a very important for MOSFET to lower the
D1 at oxide/semiconductor interface.Figure 4.6 (a) shows the cross-section TEM image of
the as-deposited ALD A12 0 3/GaAs interface. The oxide was grown at 370'C for 250
cycles. The smooth surface and abrupt interface are observed in the image. Figure 4.6 (b)
shows the cross-section HRTEM image of the interface between A120 3 and GaAs. The
interface is atomically flat and abrupt. The A12 0 3 thin film is uniform and there is no
lattice points observed in the A120 3 thin film, which indicates the amorphous structure.
No interfacial layer is observed at the interface.
(b)
Figure 4.6 (a) Cross-section TEM image of A1 2 0 3/GaAs structure (b) Cross-Section HRTEM
image of the interface between GaAs substrate and A12 0
3
thin film grown at 3700 C. The
TMA and IPA pulse time were both 5s
The XRR was performed to measure the thickness of the thin film and roughness of
the interface and the surface. As shown in the figure 4.7, the XRR of ALD Al 2 0 3 /GaAs
shows a well-behaved fringe pattern. The fringe can be clearly seen at high angle
(0 = 2.5") indicates that the quality of the oxide is good and the interface is abrupt
between as-deposited in situ A12 0 3 and GaAs. The data at higher angle become blurred
due to the instrument limitation. By using theoretical model to fit the experimental XRR
data, the information (density of the substrate and thin film, thickness of the thin film,
surface and interfacial roughness) can be extracted. By doing the fitting, the surface
roughness is 0.548nm and a very small interfacial roughness (0. 123nm) is obtained and
this indicates that the interface of A12 0 3/GaAs is atomicly flat and matches the
observation of the HRTEM image shown in figure 4.5(b).
10.107
Raw data
Fitting curve
6---
P(g/Cm 3); t (nm)
X
Substrate: 5.634
20.36
: 3.287
0
2
10
S105
0 10Al
U
4
;
(nm)
0.123
0.548
10
103
2
C10
4)
'W10 1
0
0.0
.
.
0.5
1.0
1.5
2.5
2.0
3.0
Incident Angle (degree)
Figure 4.7 X-Ray Reflectivity of 20nm (250 cycles) ALD Al 20 3/GaAs structure, with
experimental data (blue point) and theoretical fitting curve (red line)
Figure 4.8 shows the surface morphology of the A12 0
3
surface measured by AFM.
The root-mean-square (RMS) roughness over an area 1 pm x 1 pm is about 0.213nm,
which is a very small surface roughness. This result is different from the surface
roughness measured by the XRR fitting and may be due to the difference of the
measurement region.
5.0 nm
m
n
0.0 nrn'0
50
1000 nmC
500
750
250
500 ',
250~-
-,1000 nm
2750
Figure 4.8 AFM image of 20.36nm ALD Al 2 0 3 surface grown on GaAs at 370 0C for 250
cycles. The RMS roughness is 0.213 nm
4.5 The chemical stoichiometry and bonding state of the A12 0 3 and A12 0 3/GaAs
interface
As mentioned before, the segregation of the As to the interface would cause high Dit
in the bandgap of GaAs. Hence, the chemical composition and bonding state of the
elements near the interface will be strongly relative to the device performances.The
chemical composition of the ALD Al 2O3 thin film was analyzed by the XPS and Auger
spectra. The auger spectrum was taken into account for the chemical and compositional
analysis by means of the Auger-peak-to-peak height. The atomic concentrations were
determined by the relative sensitivity factor method (RSF) where the sensitivity factors
were determined using a single crystal sapphire as a reference. Figure 4.9 shows the
Auger depth-profiling of ALD A12 0 3/GaAs structure. The Al and 0 atomic concentrations
keeps constant in the oxide film and are about 56.86 and 37.68%.The atomic composition
ratio of the Al : O ;
2 : 3, which is very close to the pure A1 2 0 3 thin film. The carbon
signal remains background intensity through the oxide and GaAs thin film except the
interface region. The carbon signal slightly increases at the interface and this may be due
to the accumulation of the carbon in the reactor during cooling down. This observation
suggests that IPA is a very efficient reactant for TMA, and leaves no hydrocarbon residue.
The composition ratio of the Ga and As is not equal to one in the interface region and this
is due to the sputter yield differences at the interface.
60 -0
20nm Al 20 3
Ga
50 "
As
0Al
40
30 -
0
20 10 C
0
0
1
2
3
4
5
6
7
Sputter Time (min)
Figure 4.9 Auger depth-profiling of ALD A120 3/GaAs structure which the oxide thickness is
20nm
The XPS spectra of Al2p and 01 s were also applied to quantify the composition of
the ALD A1 2 0 3 thin film, which is shown in figure 4.10.The film was sputtered by Ar+
5mins to remove the contamination on the top of the surface and 1.15nm of the A1 20
3
was estimated to be removed. A single crystal sapphire substrate was also used as a
reference to determine the relative sensitivity factor. The Shirley background subtraction
was included in the calculation. The atomic ratio was calculated based on the peak area
and the RSF. The oxide film is slightly oxygen-rich with the composition ratio of AI:0 =
1:1.54.
6k
5k Peak
FWHM
4k -Al 2p 1.853eV
0 1s 2.082eV
b3k
C
'S
C
Raw Area Atomic conc.%
2036.0
12861.8
39.31
60.69
-
2k
1k -AlI2p
01s
--
--
0
72
74
76
78
526 528 530 532 534
Binding Energy (eV)
Figure 4.10 The XPS spectra of Al 2p and Ols signals
The bonding states of the A12 0 3 and A12 0 3/GaAs interface were measured by
the depth profiling XPS. The XPS depth profiles of As 3d and Al 2p core level spectra
from A1 20 3 surface to the A12 0 3/GaAs interface are shown in Figure 4.11. From the
figure 4.1 1(a), strong As 3d signal from the GaAs substrate is observed while both As 2O3
or As 20s are not detected at the interface, which are commonly thought of as the source
of the Fermi level pinning. From this result and the observation of the TEM images, it is
clear that the growth of the interfacial oxide can be prevented by the use of IPA during
the film deposition. In the figure 4.11(b), the Al 2p spectrum from the surface is fitted and
two peaks are revealed. One is the Al 2p in A120 3 with the binding energy about 74.6 eV
and another is with the binding energy of 72.8eV, which corresponds to the Al-Al bond.
This result suggests that an oxygen-deficient A120
3
layer was formed on the surface,
resulting in the formation of an Al cluster. This layer can be removed by I min Ar
sputtering. A detail of the formation of this thin oxygen deficient Al 2O 3 layer is unknown.
The Al 2p peaks remain at 74.6 eV (corresponding to the Al-O bond in A120 3 ) in the
Al20 3 thin film and gradually shift to 75.3eV near the interface. This shift may be due to
the interfacial states [471.
As 3d
-
F
L
Al 2p
AlO, Surface
Film
Al20 Surface
0 Fit2 3
Al 0 F
inr
Al-OinAl,
AraeIGaAsInterface
Interface
A1
203 fGaAa
C0
A203 A23 5
38
40
44
42
Binding Energy (eV)
(a)
46
48
80
78
76
74
72
70
Binding Energy (eV)
(b)
Figure 4.11 XPS depth-profiling spectra of (a) As 3d (b) Al 2p core level from A12 0 3 surface
to the A120 3/GaAs interface
4.6 The C-V characteristics and the Dit at ALD A12 0 3/p-GaAs interface
The C-V curves and parallel conductance G,/a) with contours of the as-deposit
sample with 11.5nm ALD A12 0 3 on p-GaAs were plotted under different frequencies
from 10kHz to 1MHz and gate bias in figure 4.12 (a) and (b). In figure 4.12(a), the
frequency dispersion of the C-V curves on accumulation capacitance and on voltage shift
in depletion region are about 1.5% and 0.05V per decade, respectively. The accumulation
capacitance dispersion is small for our sample and it may be caused not only by the
voltage shift of the C-V curves due to the charge of the interfacial defects but also the
effect of the series resistance in the measurement. The C-V curve dispersion in the
accumulation and depletion regions are primarily due to the interfacial defects near the
valance band edge and interfacial defect at mid-gap in the band-gap. In figure 4.13(b), the
dashed white line in the middle of conductance plot represents the local conductance
peaks and the sign of the fermi level moving across part of the semiconductor band gap.
Combining the data of C-V curves and parallel conductance
G,/co measured at
different frequencies and gate bias at room temperature, the Dit can be determined by the
conductance-frequency method and is shown in the figure 4.13.Of note, only the
interfacial defects located at 0.27-0.4 eV below mid-gap for p-type GaAs samples can be
accessible in the frequency region 10 kHz to 1MHz at room temperature by this method.
The Dit increases as the trap energy (Et) moves toward the valance band edge and these
defects cause the frequency dispersion in the accumulation region of the C-V curves. The
minimum interfacial defect density in this energy region is about 2.5 x 10"(eV-cm-2 ) and
as the trap energy is 0.32 eV below the mid-gap. The interfacial defect density slightly
increases when the trap energy moves close to the mid-gap.
240
220
--
-
200
Frequencyt
180
o
160
16 0------------140 Al 20, on p-GaAs
L)
120 -17
CL
100
M
o
--
.
8
60
40
-5
N =2 x 10
-
1000k
500k
100k
50k
N'
10k
0 -------k
>
.
-3)
(C
(cm)
0
---
t0 =11.5 nm
2
A = 4.91 x 10 (cm )
''
-4
-3
-2
-1
0
1
2
Vg(V)
(a)
Gate Voltage (V)
(pF)
(b)
Figure 4.12 (a)C-V characteristics of in situ ALD A1 20 3/p-GaAs MOS capacitor measured at
different frequencies from 10kHz to 1MHz. (b) GP/AO-V9-f map of the same sample in (a).
The dashed white line is guide to the eyes
5.x101"
A
4.5x10"-
4.Ox10"
E
AA
2.0x10"
-0.40 -0.38 -0.36 -0.34 -0.32 -0.30 -0.28 -0.26
Et-E, (eV)
Figure 4.13 Interfacial defect density vs. defect level in band-gap, determined by the
conductance-frequency method from the in situ ALD A] 20 3/p-GaAs MOS capacitor
4.7 Current-Voltage measurements and band structure of Al 2O3/p-GaAs
To be a good passivation oxide for MOS devices, low leakage current through the
gate oxide must be achieved. The first basic requirement for this condition is that the
conduction and valance band-offsets (AEc(and AEV) should be at least larger than leV.
Second, these energy barriers must be effective barriers for both electrons and holes. It is
desirable that the conduction mechanism in the oxide should follow the behavior of
Fowler-Nordheim (FN) tunneling. This type of the field-assisted tunneling can be
described by carriers tunneling through a triangular barrier with:
J= AE, exp
,here A = l.54 xl 0-6
,
m*(.
BE
and
B= N
3qh
(4B)
.
MUM
m* is the effective mass of the charge carrier, E., {=[VG -QID, -%X)/q],
VG
is the gate
bias, ID,and X, are the metal work function and semiconductor electron affnity} is
electric field in the oxide, and (D is the barrier height.
As we discussed in Ch.3.2 and Ch.3.3, the conduction and valance band offset of the
AIN / GaAs interface are 2.34 and 2.56 eV, respectively. These barriers are large enough
to prevent the carriers from flowing through the AIN if the conduction mechanism of the
AIN obeys the Fowler-Nordheim (F-N) tunneling. However, the schottky conduction was
the dominant mechanism in the AIN thin film due to the poly-crystalline structure and the
grain boundaries provide the low-resistance path for carriers to flow through. Figure 4.14
shows the J-E curves of the 20nm A12 0 3 thin film and the 28.6nm AIN thin film. This
A12 0 3 thin film is a good insulator and the leakage current of the A120 3 thin film is about
2500 times smaller than that of AIN thin film at the E= 3 MV/cm. Also, the breakdown
electrical field of A120 3 is about two times higher than that of AIN thin film. These results
indicate that the current A120 3 we are depositing is a better high-k material than our
current AIN for the passivation of GaAs. What remains is to check if the leakage
mechanism of the A120 3 obeys F-N tunneling.
0.1
OA1
11-3
1E-4
x 2500
1E-4
AIN (28.8 nm)
-A~~(20 nm)
114
1E10
IE-10
0
1
2
3
4
5
6
7
a
E (MWcm)
Figure 4.14 J-E curves of the 20 A120 3 and 28.6nm AIN thin film
94
Figure 4.15 shows the J-VG curves at both biases (positive and negative VG) of the
Al-Al 20 3 -GaAs MOS structure. The leakage current density remains an almost constant
level of 10-7 (A/cm 2) and 10~8 (A/cm 2) for the to, = 11.5 nm at positive and negative bias,
respectively. When the biases increase to around at 6.5 V and -4V, an abrupt increase in
current density is observed. The rise in current density observed in the figure at higher
applied potentials is consistent with F-N tunneling.
0.01
1E-3
1E-4
I E-5
1E-6
1E-7
I E-8
-8
-6
-4
-2
0
2
4
6
8
V (V)
Figure 4.15 Leakage current density (J) as a function of gate bias (VG) for Al- A12 0 3-GaAs
MOS device of t(, = 11.5nm
Figure 4.16 shows a plot of (J / Eox2) vs. I / Eox resulting from the data in Figure
4.15 and the curves exhibit a linear region at high electric field for both positive and
negative biases. The plot has a slope of -B. These two slopes can be used to calculate the
barrier heights. The barrier heights for positive and negative bias (c,*
D8+ = AE, =
(X, - X) and (D.- = (," - X),
and
",-
) are:
where the
AE(.
is the conduction band offset at the A12 0
oxide electron affinity. The work function (<D,,)
we then
can
3
/ GaAs interface,
is the
v
of the Al is 4.28 eV. By inserting the
calculate
the
conduction
band offset
value
of the slope of curves,
AE(,
1.48eV at the interface, the oxide electron effective mass m*~0.29 me(me is free
X - 2.59eV.
electron mass) and
10-21
H
m
~=
102
0.29 m0
,,=16e
** =A E=
x
x,-x-=1.48eV
10
2
4
6
8
10
1/E2m (nmN)
Figure 4.16 Fowler-Nordheim tunneling plot of the J-V data shown in figure 4.15
For the valance band offset (AE,.), the band-gap of A120 3 should be obtained first
and then the conduction band offset and the band-gap of the GaAs are subtracted. To
determine the value of the A12O3 band-gap,
XPS oxygen energy loss spectra is applied
and shown in figure 4.1 7.The energy loss is caused by the the outgoing photoelectrons
suffering
inelastic losses to collective
oscillations (plasmon)
and single
particle
excitations (band to band transitions)[4.8]. The energy gap values for the oxide can be
determined by the onsets of energy loss from the energy-loss spectra. By this method, the
band gap value of the Al 2O3 is measured as about 6.9 eV.
.
n
eV
S~-6.9
-4
E (Al2 03 )
0
12
8
4
Energy Loss (eV)
16
Figure 4.17 0 Is energy loss spectra for A12 0 3. The cross point (obtained by linearly
extrapolating the segment of maximum negative slope to the base line) denote the energy
gap Eg value
Taking this value (6.9eV) into consideration and subtracting the values of conduction
band offset and band-gap of GaAs, the valance band offset AE,. is calculated as 3.8 eV.
The details resulting band structure of the Al- A12 0 3-GaAs system are shown in figure
4.18.
Band structure
4.28eV
1.69eV
Vacuum
level
2.59eV
1.48eV
1.42eV
AlA
3.8eV
Figure 4.18 Engrgy band profile for the Al/A 20 3/GaAs MOS structure
4.8 Thermal Stability of ALD A12 0 3 thin film and A12 0 3/GaAs interface
For a standard fabrication process, the self-alignment process is an important step to
define the drain and source regions automatically without an extra photolithography step
to minimize the overlap between the gate and the drain and source region. This process
reduces the gate-source and gate-drain capacitance for a high-performance transistor.
High temperature annealing is required to activate the implant after the self-alignment
implantation. The stability of the ALD A12 0 3 thin film and the A12 0 3/GaAs is very
important during high temperature processing.
0
0
Figure 4.19 shows the HRTEM of as-deposit samples annealed at 750 C (a), 800 C
(b), and 850 0C (c) by Rapid-Thermal-Annealing (RTA) under the nitrogen atmosphere for
15s. Lattice images can be observed in the A12 0 3 thin film in figure 4.19 (c) indicating
0
that the A12 0 3 re-crystallizes at 850'C while the samples annealed below 850 C remain
amorphous. All of the interfaces are rougher than that of as-deposit sample (See figure
98
4.6). This may be due to the decomposition of the GaAs during the high temperature
annealing without any arsenic protective atmosphere, or to some residual oxygen inside
the RTA chamber. The residual oxygen may diffuse through the Al 20
3
thin film and
oxidize the interface during high temperature processing. The results suggest that a low
RTA annealing temperature or annealing in ultra- high-vacuum (UHV) environment is the
preferable process.
Ga~s
5 nmGas
5nGas
====
5m
Figure 4.19 HRTEM images of the samples annealed by RTA for 15s at (a)750"C (b)800"C (c)
850 "C
To check the thermal stability between the oxide and the electrode, and to avoid the
effect of residual oxygen in the RTA chamber, Molybdenum is chosen as the gate
material for our gate stability experiments. The molybdenum was deposited by e-beam
evaporation under the vacuum of 3 x 10 Torr with a growth rate 1 (A/s). The samples
were then annealed at 750'C, 800C and 850 0C by RTA under nitrogen atmosphere for
15s. For comparison, an aluminum electrode was also deposited but not cycled through
the high temperature annealing process. The C-V measurement results at frequencies of
l00k, 500k and 1000kHz are shown in figure 4.20.
200
240
10
100k
--
c
500k
-140
22
--
200
1
-
100k
500k
-100k
1000k
120
20100
0.
-4
-6
8
00
40180
0
2
--
.- 1
2
120
4
3-
.2
-1
40
14k
----- 5 0 kk
00k
.......
( 0
4md)
i.Cot
-3 0-
-A1
A
.4
-0
-2
-1
D
Voltage (V)
tae
so
(V
A.6
Voltage (0J)
00000
I.
100O~
"0
100
1000
5
F
3
.
-
0.
5
100k
--
..
ou
2
120
.1.0...................
- 160
100k
1
0
Voltage (V)
Voltage (V)
1
2
0
-0
.4
-3
.2
.1
1
2
3
Voltage (V)
Figure 4.20 (a) Thermal evapo rated Al electrode on as-deposit sample (b) E-Beam deposited
0
Mo electrode on as-deposit sample (c) and with RTA for 15s at (c)750 'C (d)800 C and
(e)850 0C
The quality of the interface can be judged by the frequency dispersion of the C-V
curves. For the as-deposit samples, the sample with Al electrode shows very small
frequency dispersion (figure 4.20 (a)) while the sample with Mo electrode shows large
frequency dispersion (figure 4.20 (b)). This implies that the interface is degraded during
the Mo deposition. As addressed before, the Mo was deposited by the E-beam system
while the Al was deposited by the thermal evaporation. High energy photons (X-Ray)
could be released when the electron beam bombards the source metal and this could
cause damage at the A12 0 3/GaAs interface during the E-Beam deposition. The following
RTA annealing helps to cure the damage to the interface (figure 4.20(c) and 4.20(d)). But
the quality of interface is still not comparable with that of as-deposit sample with
thermal-evaporated Al electrode. The frequency dispersion becomes larger for the sample
annealed at 850C, implying that the interface would be degraded if the annealing
temperature is higher than 800C. These results suggest that the gate material should be
chosen carefully to avoid the degradation of the interface and the processing temperature
should be lower than 800C if the self-alignment and implantation are employed in the
device process.
4.9 Structural Defects in the ALD A12 0
3
As discussed in previous section,high temperature activation annealing is a critical
step for the self-aligned MOSFET fabrication process when implantation is used. Because
the Ill-V compound semiconductors decompose in high temperature processes, the
quality of the oxide must be high to prevent III-V surface exposure.
We identified some sort of leakage-path defects when the heavily doped Ge was
used as the gate material In situ n+Ge was deposited at 500C following the deposition of
ALD A1 2 0 3. Figure 4.21 shows the leakage current behavior of the in situ n+Ge/ ALD
A120 3/GaAs structure. Five points were chosen to measure the leakage currents and not
all of them behave as F-N tunneling. Unlike the case of ex situ Al electrodes, which
shows almost 100% yield of the sample, this structure does not show 100% yield. Some
n+Ge electrodes are short. This suggests that weak spots or "pinholes" exist in the ALD
A1 2 0 3 thin film.
716 N+Ge electrode small area
10
I
0.1
S0.01
CI*4
E IE-3
1 E-4
1E-5
1E-6
I E-7
1E-8
I E-9
-12 -10
-8
-6
-4
-2
0
2
4
6
8
10
12
E (MV/cm)
Figure 4.21 Leakage current behavior of in situ n+Ge/ ALD A12 0 3/GaAs structure
A model is proposed to explain this behavior and is shown in figure 4.22. There are
many initial weak spots that exist in the ALD A120 3 thin film. When the Al deposited by
E-beam or thermal-evaporation is used as the gate electrode, no leakage failures are seen
despite the presence of the weak spots. When CVD poly-n+Ge is used as gate electrode,
there is a potential interaction between the weak spots and the gas source (GeH 4) used in
CVD process. This interaction may cause the formation of short paths that may be related
to Ge inter-diffusion.
Initial weak points
CVD poly-Ge deposition
-Potential for interaction
No high-leakage failures
Possible 100% yield
CVD poly-Ge deposition
-Creation of leakage paths
Figure 4.22 A schematic representation of the proposed mechanism 14.91
In order to observe and calculate the density of these weak spots, an etching process
was applied. An acid that combines with an oxidant is usually used as a GaAs etchant.
However, only HF can etch the Al 2O3 thin film bases on our observation. We combined
HCl:H 20 2:H20 =10:5:35 as a GaAs etchant and dilute HF as an ALD A120 3 etchant to
reveal the weak spots in the oxide. The dilute HF would prefer to attack the weak spots in
the oxide thin film, but not etch out all of the oxide thin film. The GaAs etchant starts to
etch the GaAs underneath the weak spots if they were etched through by the HF. The
weak spots could be clearly observed by this method.
Figure 4.23(a) shows the SEM image of the oxide etched by the etchant
HCI:H 20 2 :HF:H 20 = 10 : 5 : 1: 35 for 30s. After the etching, the weak spots of the oxide
were revealed and the density of the defects was about 2 x 109 (cm~2 ) calculated from the
SEM image. The weak spots in the oxide may come from the island growth at the initial
stage of the ALD process. Figure 4.23(b) shows the XTEM of the sample annealed at
850 0C for 15s. Some pits are shown at the oxide/GaAs interface, and decomposition of
the GaAs is a consequence. Also, the density of the pits could be calculated from the
TEM image based on the statistics and is about 2.7 x 109 (cm-2). This value is very close
to the density of the weak spots in the oxide. T.E. Haynes et. al.[4.10] found that the loss
of the As during the high temperature annealing was relative to existence of cracks in the
cap layer(SiO 2 or Si 3N 4). Our results match their conclusion. This implies that the thermal
stability of the sample could be improved by improving the quality of the oxide.
The
weak spots could be cured by an appropriate post-annealing process. Figure 4.23(c)
shows the SEM image of the oxide annealed in 02 at 500 0 C for 20 mins and etched by the
same etchant. No weak spots are found in the image. The sample was also annealed in a
N 2 atmosphere as s reference; however, the weak points could not be cured without the
presence of oxygen.
(a)
(b)
(c)
Figure 4.23 (a) SEM image of the etched oxide (b) XTEM of the sample annealed at 850*C for 15s in
RTA under N2. (c) SEM image of the etched oxide annealed in 02 at 500*C for 20mins
The weak spots could be cured by the 02 annealing. Unfortunately, high temperature
(500 'C) 02 annealing could also degrade the interfacial quality of oxide/GaAs interface
and cause larger frequency dispersion of the C-V curves. Appropriate annealing
conditions at lower temperature should be found.
Figure 4.24 shows the AFM image of the samples annealed in different conditions.
All samples were etched by HCI:H 20 2 :HF:H 20 = 10 : 5 : 1: 35 for 30s to reveal the weak
spots in the oxide thin film. Figure 4.24(a) shows that many etch pits were found in the
as-deposit A1 2 0 3 thin film. This result matches the observation of the SEM image. The
samples annealed in 02 for 20 mins at 350 C , 400 0C and 450 C show no etch pits in the
images(Fig 4.24(b),(c) and (d)). This implies the weak spots could be cured at lower
temperature with 02 annealing; this is required before any high temperature processing.
This annealing condition will not cause any degradation of the interface and the C-V
characteristics.
Figure 4.24 (a) The AFM image of the A12 0 3 thin film of the sample (a)as-deposit and 02
annealing for 20mins at (b)350"C (c)400"C and (d)450"C. All samples were etched by HCI:
H20 2:HF:H 20 = 10:5:1:35 for 30s
Figure 4.25 shows the leakage current of the samples with Al and Ti electrodes and
with different process treatments. Because of the high reactivity of Ti, the deposited Ti
atoms would reduce the Al20
3
at the interface to form a TiO 2 interfacial layer between Ti
electrode and the A120 3.This reaction would release the metallic Al atoms. These reduced
Al atoms diffuse into the oxide film through the weak spots and cause high leakage
106
current. This phenomenon is similar to the case of the n+Ge as the gate electrodes. For
the Ti electrode, the leakage current is much lower for the sample with 02 annealing than
that without 02 annealing in accumulation region. This behavior is because the weak
spots are cured by the 02 annealing and the reduced Al atoms would not have the chance
to find the weak spots to diffuse into the oxide to form the leaky path. The leakage
currents of the samples for Al and Ti electrodes with the same 02 annealing are similar
and shown in the figure.
1
Ti electrode,0 2 Annealed
electrode,0 2 Annealed
Ti electrode,As-deposit
0.1 -Al
0.01
E
1E-3
1^
1E-4
I:
1 E-5
1E-6
1 E-7
1 E-8
-12 -10 -8
-6
-4 -2
0
2
4
6
8
10 12
E (MV/cm)
Figure 4.25 Leakage current of the samples with Al and Ti as electrodes and with different
treatments
The fundamental assumption for the ALD is a saturated layer-by-layer growth. The
precursor saturates the surface and the absorbed precursor waits for the following
reaction. However, the nucleation of the ALD reaction on the substrate would cause
non-saturation growth and the island structure of the oxide if the oxide is thin. This is
usually observed in the case when the hydrogen terminated Si substrates were applied
because the hydrogen blocks the adsorption of the metal-organic precursors and
107
following reactions. This growth mode would cause the existence of the structure defects
in the oxides.
In our experiments, the oxide was deposited with our in situ MOCVD process on the
fresh GaAs. The surface of substrate is usually terminated by As atoms. These As atoms
serve as the bridge between the GaAs substrate and the oxide during the first TMA pulse.
In theory, the TMA could completely cover the surface and the island structure would not
form during the ALD process. To prove this hypothesis, HR-XTEM images were
recorded to investigate the initial growth in the ALD A12 0 3 process. Figure 4.26 are TEM
images for A12 0 3 samples prepared with 20 ALD reaction cycles and capped in situ with
a GaAs layer.
In figure 4.26(a), the thin A12 0 3 is uniformly deposited on the GaAs surface.
However, some, but not many, discontinuities in the A12 0
3
film can be found in the
image. Figure 4.26(b) shows the enlarged image of one of these discontinuous regions.
The in situ grown GaAs has aligned epitaxially with the lattice of the substrate through
the A1 2 0 3 layer, indicating the presence of holes in the A1 20 3 layer. This can be easier to
see by doing the fast fourier transformation (FFT) of the image in this region and is
shown in figure 4.26(c).
These results suggest that the weak spots observed in the etching and annealing
experiments come from the incomplete coverage of the precursors and is related to the
island growth of the A1 2 0 3 in initial ALD growth.
_...
.............
................
..
FFT
Epitaxial growth
Figure 4.26 Cross-Section HRTEM image for A12 0
3
deposited with TMA/IPA at 370"C for
20 ALD cycles. The sample was in situ capped by GaAs (a) Low-Magnification image (b)
Enlarged image from the white box labeled in (a), (c) FFT image from the dashed white box
labeled in (b)
Chapter 5 In and Ex Situ ALD A120 3 on p- and n-GaAs
In situ deposition in ultra high vacuum prevents direct oxidation of the channel,
which pins the Fermi level at the oxide/GaAs interface. Some ex situ methods such as
ALD high-k oxide on GaAs have achieved some success due to the self-cleaning effect of
the GaAs surface. Most of these processes use metalorganics and water as the precursors
for the ALD oxide growth [5.1]-[5.3]. In charpter 4, the in situ ALD A12 0 3/GaAs in
MOCVD without using water as a precursor was demonstrated. The room temperature
C-V characteristics for p-GaAs clearly showed a lower C-V frequency dispersion and Dit
than typical results from ex situ A12 0 3/GaAs [5.4].
TMA/H 20 is the most widely used precursor set for ex situ ALD A12 0 3 on III-V
substrates [5
1]
However, the MBE results previously discussed suggest that
strongly oxidizing the Ill-V channel will create a strongly pinned interface.
oxidizer may create a larger process window for these interfaces.
A weaker
In this work, IPA was
used as the oxygen source for in and ex situ A1 2 0 3 on both p- and n-GaAs. our purpose is
to compare in and ex situ ALD A12 0 3 on GaAs. For reference, TMA/H 20 was used to
deposit ex situ A1 2 0 3 in a commercial ALD system (not in our MOCVD reactor; on the
2 "nd
floor in MTL). HRTEM and C-V measurement were performed to evaluate if the
TMA/IPA is also a good self-cleaning agent in the ex situ case. Annealing air exposed
GaAs samples under AsH 3 at high temperature is an alternative method which has been
shown to remove the native oxide [5.5]. A AsH 3 pre-treatment step was introduced into
the ex situ process before the oxide deposition to study its influence on interface quality.
5.1 Experimental procedure
GaAs substrates were prepared in the MOCVD system.
111
The buffer epilayers of
GaAs were grown on 2-inch heavily doped GaAs(00 l) substrates at 650 0C with TMG and
Arsine (V/11= 23) with Si 2 H 6 and DMZn as the n- and p-type dopants with doping
concentration of 2-6 x 1017 cm 3. For the in situ experiments, the detail procedure has
been described in chapter 4. For the ex situ growth experiments, the substrates were
stored in the atmosphere for two days between the buffer and oxide growths and no wet
cleaning was performed prior to ex situ A1 2 0 3 deposition. TMA/IPA and TMA/ H20 were
chosen as the precursors for ex situ ALD A12 0
3
deposition. The samples with A1 20 3
grown with TMA/IPA and AsH 3 annealing treatment were performed in the MOCVD
reactor with the same parameters as were chosen in the in situ process.
Ex situ
TMA/-120 was applied in a Cambridge NanoTech Savannah ALD Reactor to deposit
ALD A1 2 0 3 . The thicknesses of all A12 0 3 layers were grown with thickness of 11.5nm in
all processes except the samples for HRTEM analysis. The brief process flows for the
growth of these experiments are shown in figure 5.1. Aluminum electrodes 200 ptm in
diameter were evaporated on samples and the C-V characteristics were measured using a
HP4192A LF impedance analyzer at frequencies from IM to 10kHz at room temperature
in the dark. The XPS was performed in Kratos AXIS ultraimaging system using a
monochromatic Al Kal source (1486.6 eV) with argon ion gun.
CVO GaAs
700
0t
-
4.0
ALOAlO,
700
650C
000370C
So
600
00rator
400
D 300
2 300
200
200
E0100
0
W
-
000
S700
CVD GaAs 0ubire&
650*C 'weeretaken
,
-
\g0
ALO AlO,
nst rn Iand,
l
ltrdnl
'fo
Ir 2 days
-
7~
-
650*C
700
600
00
400
300
202
re taken 650 C
o
:trIn ALGAl 0
relactorand1
370'C
stred in i
days
100
-800
800
700
700
.
/
S00
o 100
M 100
z oo
0.
0.
. .
100
00L
o 50
10
100
U
0 50
5
S0
15~0
0
Time
(a)
Tm
(b)
Time
(c)
Figure 5.1 Process Flow of (a) in situ ALD A1203 on GaAs (b) ex situ ALD Al 2O3 on GaAs (c)
ex situ ALD Al2O3 on GaAs with AsH 3 pre-treatment
5.2 Self-Cleaning effect of precursor set TMAIPA
Figure 5.2(a), (b), and (c) show the HRTEM image of the native oxide/GaAs
substrate, an ex situ A2O 3/GaAs and A12 0 3/Si interface using TMA/IPA as the precursors,
respectively. The H-passivated Si substrate was used as a reference to check the effect of
the self-cleaning effect our precursor set TMA/IPA. The thickness of A1 2 0 3 grown on the
Si and native-oxide covered GaAs are almost the same and sharp A12 0 3/GaAs interfaces
were observed. This result shows that the native oxide was completely removed after the
ALD deposition and the self-cleaning effect did occur in our deposition. It is believe that
the self-cleaning effect involves ligand exchange (substitution) reactions between the
TMA and the native As 2 O3 , providing a pathway for the interfacial cleaning by forming
Al 20 3 and volatile trimethylarsine (As(CH 3) 3). These reactions have been understood in
alkylating As 2O 3 with aluminum alkyls to form trialkylarsines in common ALD A1 2 0
3
process with TMA/H 20 as the precursor set.The self-cleaning effect in passivation of the
GaAs surface is attributed to the removal of arsenic oxide and the arsenic, which are
believed as one source to cause Fermi level pinning [5.21, [5.3]. In common ALD process,
the precursors are usually the metal-organic
and water. Only specially chosen
metal-organic precursor will perform the self-cleaning effect, while the H20 play as an
oxidant during the cycle. For example, in the ALD of HfO 2 with HfCl 4 as the metal
precursor, due to the highly ionic character of the Hf-Cl polar covalent bond, it may be
relatively too strong to break and trigger such a ligand exchange reaction with the native
oxides. The metal amide derivatives, such as As[N(CH 3)2] 3 and Sb[N(CH 3) 2] 3,have been
used as precursors for III-V homo- and heteroepitaxial films prepared by chemical beam
epitaxy and atomic layer epitaxy, because these precursors can provide chemical
reactions for in si/u cleaning and etching of native oxide and substrates as well as
interfacial
hydrocarbons
of
tetakis(ethylmethylamido)hafnium,
GaAs
and
other
III-V
compounds.
The
Hf[N(CH) 3 (C 2HS)] 4 , i.e., TEMAH, is one of the
important metal amide precursors used for the ALD of HfO2 and may provide the desired
self-cleaning reactions in ALD of HfO 2 on the GaAs surface.[5.31
In our experiments, IPA, unlike the H20, is not an oxidant and can react with the
native oxide and free arsenic atoms on the surface to form the volatile products, arsenic
alkoxides (As(OCH(CH 3)2) 3).(eq. (2) and (3))TMA had been reported to be a good
self-cleaning agent in several publications and it will form volatile products, Tertiary
arsines (As(CH 3) 3)(eq. (3)), by reacting with arsenic oxide. Both TMA and IPA could
remove the arsenic oxide and arsenic directly [5.6]-[5.8] and this doubles the cleaning
effect. The details of the reactions are shown below:
As203 +2Al(CH3)
As203 +6(CH 3 )2CHOH
As+3(CH 02CHOH
"" >2As(CH3 )3 T +A1,0
3
31 0"C
3,01C
>2As(OCH(CH3 )2 )3
>As(OCH(CH3)2)3
Epoxy
(b)
(I)
3
T +3H 0
(2)
2
H2
T+
(3)
(C)
Epoxy
Al2Oa
GaAs
S
i
Figure 5.2 HRTEM image of the interface between (a) native-oxide/GaAs
(b) ex situ
Al 2 O3/GaAs, and (c) ex situ A120 3/Si. The Al 2O3 was grown with TMA and IPA. The scales
are the same in all figures
Furthermore, in figure 5.2(c), there is no discernable interfacial SiO 2 layer between
silicon and A12 0 3. This indicates that it is possible to avoid oxidizing the substrate surface
during the growth process without special care with this precursor.
5.3 Surface recovery by baking sample under AsH 3
Heating an Air-exposed (native oxide covered) GaAs substrate can desorb the native
oxide (Ga 20 3, As 2O3, etc.) in oxygen free environment. This process could be
115
contributing into three successive desorption reactions happen at different temperatures at
the native oxide / GaAs interface.
The first desorption reaction start at 390'C.The oxygen atom originally bonded to As
changes sites so as to be bonded with Ga. The arsenic oxide decomposes at this step and
desorb from the surface. This is shown in figure 5.3(a). When the temperature reaches at
475 C, the Ga 20 in the gallium oxide starts to desorb from the surface due to the high
vapor pressure of Ga 20 (figure 5.3(b)).The final step is the simultaneously desorption of
Ga 20 and elemental arsenic, which are produced in the reaction between the Ga 2O 3-like
surface oxide and the GaAs substrate expressed as below (figure 5.3(c)) at the
temperature above 500 0C[5.9]:
Ga,0 + 4GaAs
-
3Ga2 0
1 +2As 2 t
or
Ga,0, + 4GaAs
->
3GaO i +As4
i
As2/As4
GaAs
oxide
As2/As4
Ga2O
Ga~
GaAs
(a) 3900C
(b) 4750C
Ga2O
Ga
/As
(C) >5000C
Figure 5.3 Native oxide desorption process
Once As oxides and some Ga 2O desorb thermally at lower temperature (390 C and
475 'C,respectively),
the reaction of the more Ga 20
3
with bulk GaAs at higher
temperature (>500 'C) is responsible for the surface roughening observed during thermal
cleaning[5.10]. Flowing AsH 3 is required to prevent the decomposition of the GaAs and
keep the surface smooth during the desorption process. Annealing the native oxide
covered GaAs under AsH 3 atmosphere could undo the oxidation process and recover the
surface when the ex situ procedure was performed. The surface could also show the c(4x4)
reconstruction structure, which is usually the same as the surface of the GaAs grown in
the MOCVD reactor with flowing AsH 3[5.5].
5.4 The bonding states of Gallium atoms at the interface
The bonding states of the Ga-O bonds at the oxide/GaAs interface were recently
shown to correlate with the C-V characteristics for n-type GaAs. The removal of the Ga
3
oxidation state at the interface was shown to result in the reduction of frequency
2
dispersion in n-type sample [5.11 ]. Figure 5.4 (a) shows the Ga P3/2 spectrum from clean
GaAs surface. This fitted single peak (Ga-As) provides the reference to the following
spectrum fitting. For the XPS measurement of in situ A12 0 3/GaAs interface, the oxide
above the interface was thinned by the argon ion gun with the etching rate of
0.02 nm/min and the residual oxide thickness was estimated as 2.4nm. In Figure 5.4(b),
the Ga 2p3/2 spectrum from the in situ A1 20 3/ p-GaAs interface is fitted carefully and two
2
peaks are revealed. The major peak is the Ga p3/2 in GaAs with the binding energy about
1117.1 eV and the smaller one is with the binding energy of 1117.7 eV. The existence of
the small peak could also be contributed from plasmon loss and inelastic scattering of the
photoelectrons. But the plasmon loss usually produces a distinct and rather sharp hump
20-25 eV above the binding energy of the parent peak [5.12] Besides, the sampling depth
(The depth where the 95% of the photoelectrons could be detected) of the XPS is
considered as three times of Inelastic Mean Free Path (IMFP, The average distance that
an electron with a given energy travels between successive inelastic collisions)[5.
13.
Seah and Dench developed an equation that relates IMFP to electron energy and the
inorganic compounds: IMFP = 2170KE
2
+ 0.72(aKE)0 5 , where IMFP is in units of
monolayer, a is the monolayer thickness (nm), KE is the electron kinetic energy (eV). In
this measurement, the KE of the Ga
2
P3/2
is about 370 eV and the monolayer thickness of
A12 0 3 is about 0.204nm, this gives IMFP and sampling depth as 1.28nm and 3.84nm. As
described above, the residual oxide on the interface is 2.4 nm and this indicates that some
photoelectrons coming from "deep" GaAa do suffer the inelastic scatting before detected
and the traveling distance of photoelectrons coming from interface is shorter than the
IMFP. In order to eliminate the affection of the inelastic scattering, Shirley model [5.14]
was applied to determine the background and did the fitting of the reference peak and Ga
2P 3/2 peak of A12 0 3/GaAs interface.
The binding energies of the Ga+1 and Ga+3 states were measured as 0.55eV and 1.2
eV above the bulk peak [5.11] , indicating Gal' state could be the possible peak located at
11 17.7eV and no Ga+3 state was seen in the spectrum. It was shown that the oxide grown
on n- and p-type GaAs substrates is identical when exposed to the same environmental
and chemical conditions [5. 15].
-
p-OaAs sub trate
>Ga 2p
Al 2
pGa s
t
Ga2p
Ga-AsA
(b)
S (a)
1120
11 1 1116 1
Binding Energy (eV)
1118
1120
1116
1114
Binding Energy (eV)
2
XPS spectrum for clean GaAs surface (b) Ga P3/2 XPS spectrum at
in situ AI 2 O3/p-GaAs interface. The oxide above the interface was thinned by the argon ion
gun with etching rate of 0.021 nm/min in XPS system and the residual thickness was
Figure 5.4 (a) Ga
2
P3/2
estimated as 2.4 nm The Shirley background subtraction was included in all XPS fittings
Some researchers showed the existence of Ga 20
3
residues from the native oxide
detected at the ex situ A12 0 3 /I-V compound semiconductor interface (TMA and H2 0 as
the precursors) [5.2]. Our ex situ samples were not sent to do the XPS measurements but
we believe there is also some gallium residual left at the ex situ ALD A12 0 3/GaAs
interface.
5.5 The C-V characteristics and the Dit at in and ex situ ALD A120 3/GaAs interface
with IPA or H 2 0 as oxygen source
5.5.1 C-V characteristics of in and ex situ samples with IPA as oxygen source
Figure 5.5 shows the C-V curves of the in situ p- (a) and n-GaAs (c) samples, and ex
situ p-(b) and n-GaAs(d) samples, respectively. In situ p-GaAs sample shows small
frequency dispersion at flat band voltage (20mV/decade), but the ex situ p-GaAs one
shows larger dispersion (153 mV/decade), although the complete removal of the native
oxide was observed for the ex situ oxide growth with TMA/IPA. Interestingly, the
situation of n-GaAs is totally different from that of p-GaAs. All the C-V curves are
inferior to their p-type counterparts.
A clear transition from accumulation to depletion
was observed in the C-V curve of the ex situ n-GaAs sample, but this was not observed in
that of the in situ n-GaAs sample. The C-V curves of the in situ n-GaAs sample show a
large frequency dispersion in accumulation region and this suggests that a very high
defect density exists at the interface. The capacitance in accumulation region of the ex
situ ALD sample with TMA/IPA is slightly lower than that of in situ ALD sample with
the same precursor set. This may be due to some residual oxide remained on the top of
the surface. If we take the capacitance in accumulation region and calculate the dielectric
constant of the A1 2 0 3, the dielectric constant extracted from the ex situ sample is 7.1 and
the dielectric constant of the in situ A1 2 0 3 thin film is 7.45 ( a 2A residual native oxide
layer was estimated). This is a very thin layer and hard to be observed in HRTEM image
shown in figure 5.2. The difference between these two interfaces is that there is a very
small amount of the Ga 2O 3
residual at the ex situ ALD A12 0 3/GaAs interface while the
in situ ALD A12 0 3/GaAs interface is Ga 2O 3 free. The gallium oxide may play a key role
to lower the frequency dispersion of C-V curves of the n-type sample.
180
200
-- 10kHz
180
50kHz
160
--
.40
100kHz
120.
-o--500kHz
140-
LL
n-GaAs(c) so
-100
1000kHz
-=
120
80
10o
60
80 6040
L)
C
20
48(a)p-GaAs
180
M
10
140
160
140 -120
A100
100
120
-80
.*
100
-60
80
n-GaAs(d
" (b) p-GaA
-4
-3
-2
-1
0
1
-1
0
1
2
3
40
4
Gate Voltage (V)
Figure 5.5 C-V characteristics of in situ ALD A120 3 on (a) p- GaAs and (c) n-GaAs; ex situ
Al 20 3 on (b) p- GaAs and (d) n-GaAs. All the A120 3 were grown with TMA/IPA
5.5.2 C-V characteristics of ex situ samples with IPA or H2 0 as oxygen source
The C-V characteristics of ex situ ALD A120 3 grown with TMA/IPA and TMA/H 20
are shown in figure 5.6(a) and 5.7(b), respectively. Less dispersion and higher
capacitance are observed for the TMA/IPA sample. The incomplete removal of residual
native oxide may be the reason for the lower accumulation capacitance and larger
frequency dispersion for the sample with H20 as oxygen source. Because TMA is the
only self-cleaning agent in the ALD A12 0 3 with TMA/H 20 precursor set, this implies the
optimal condition for self-cleaning effect should be carefully controlled to remove the
native oxide.
200
- 160
CL
160
a)
TMA /IPA
-1000kHz
140
I
(U)
120
500kHz
o-
-1
M 120
I ~
TMA / H 0
2
140
* 100
o. 80
100
80
0kHz
0kHz
60
o60
40
-4
An
-3
-2
-1 0
V (V)
1
2
Figure 5.6 C-V characteristics of ex situ ALD
-4
A12 0 3
-3
-2
-1 0
V9(V)
1
2
grown with (a) TMA/IPA and (b)
TMA/H 20 on p-GaAs
5.5.3 C-V characteristics of ex situ samples with surface recovery by annealing in
arsine before ALD of A12 0 3 with TMA/IPA
As discussed in section 5.3, heating GaAs substrates above 500 C could also
desorb the native oxide completely, but the surface become rough due to the reaction
between the substrate and the native oxide. Annealing in AsH 3 is required to prevent the
decomposition of the GaAs and keep the surface smooth during native oxide desorption.
This process could reverse the oxidation process and recover the surface after an ex situ
procedure was performed. C-V characteristics of ex situ ALD Al 20 3 grown with a AsH3
annealing treatment before the A12 0 3 growth on GaAs are shown in figure 5.6. The
resemblance of the C-V characteristics (figure 5.7(a) and 5.7(b)) with that of in situ
sample (figure 5.5(a) and 5.5(c)) clearly shows the surface recovery. This result suggests
that the ex situ process that introduces the thermal cleaning process with AsH 3 can imitate
the in situ process for all commercial ALD reactors.
200
18
(a)
-180
160 (b)
-160,10
' 140
0 120
~60
10010
8.
600
4010
140
10
_160_(b)
60
Vg(V)
of ex situ ALD
characteristics
c-v
Figure 5.7
Vg(V)
A12 0 3 grown with AsH 3 annealing treatment
before the A12 0 3 growth on (a) p-type (b) n-type GaAs
5.5.4
Dit distribution in
the bang-gap
for
the samples
extracted
by
the
room-temperature conductance-frequency method
1002
Figure 5.8
shows the Dit distribution
in the band-gap extracted
by the
conductance-frequency method. The Dit of the ex situ sample grown with TMA/IPA is
low compared to that grown with the conventional TMA/H 2 0 demonstrating that the
TMA/IPA is superior to a water-based process, and in situ use of these precursors
produces an interface with a lower Dit. The Dit of the ex situ n-GaAs sample is half of that
in the in situ n-GaAs sample and this unexpected result implies the ex situ process helps
to improve the interface quality for the n-GaAs samples. The Di is around 5xI1
(i/cm2
eV) for the in situ and AsH 3-annealed p-GaAs samples in the measureable trap energy
range [5.1I7]. Of note, the measurable trap state energy in the band-gap follows the
equation: f=l/2nt!
P(AkT)OvtN 5 where f is the measure frequency, AE is the
energy difference between the majority carrier band edge energy and the trapping state
energy FE,k is the Boltzmann constant, T is the semiconductor temperature, G is the
interaction cross section of the trapping state, v, is the thermal velocity of the majority
123
charge carriers, and N is the density of states in the majority carrier band. Although only
0.27-0.4 eV below and the 0.29-0.38 eV above the mid-gap for p and n-type GaAs
samples can be accessible in the frequency region 10 kHz to IMHz at room temperature,
the sufficient comparisons can be made.
12
loX 10
-+-p-GaAs
-o-p-GaAs
p-GaAs-TMA/H 0
2
8
6
-'-p-GaAs -AsH 3
-4- n-GaAs
E4 4 en-GaAs
20
-0.4 -0.3 -0.2 0.2 0.3 0.4
Trap energy Et - Ei(eV)
Figure 5.8 The summary of Dit distribution of all samples in the band-gap. (closed and open
symbols: in and ex situ process, respectively). A120 3 was deposited with TMA/IPA unless
specified. The open square represents the sample which AsH 3 annealing treatment was
performed
In summary, interfacial self-cleaning and surface recovery in ex situ ALD of A12 0
3
are demonstrated. The concept of using the TMA/IPA as precursors to remove the native
oxide was confirmed by both HRTEM and the C-V measurement, which shows small
dispersion and high capacitance. Ex situ A12 0 3/n-GaAs sample shows better C-V
characteristics than that of in situ case. Moreover, annealing native-oxide covered GaAs
samples in AsH 3 is shown to undo the oxidation process incurred when the ex situ
procedure is performed.
The C-V characteristics of the AsH 3 treated sample resemble
124
that of the sample under in situ process. The ex situ process introduces the thermal
cleaning process with AsH 3 can imitate the in situ process. No Ga'3 oxidation state was
detected at the in situ Al 2O3/GaAs interface. The Dit is around 5x10" (1/cm
2
eV) for both
in situ and AsH 3 annealed p-GaAs samples in the measureable trap energy range.
Chapter 6 In Situ CVD A12 0 3 on GaAs
In this chapter, the GaAs surface was be passivated by in situ CVD A12 0 3 using the
same precursors as in the ALD A12 0 3 process. Unlike the ALD A12 0 3 film, a
self-enriched gallium region was found above the oxide/GaAs interface
in the case of
CVD A1 203[6, I]. A XPS was utilized to detect the bonding state of the gallium and also
to determine the composition of the oxide film above the interface. The origin of the
self-enriched gallium region and possible chemical reactions leading to this structure
were proposed. C-V measurements were performed to examine the quality of interface
and to determine the D1 .
6.1 Experimental procedure
N-type GaAs buffer layers were first grown by CVD followed by aluminum oxide
deposition using either ALD mode or CVD mode in an AIXTRON/Thomas Swan
close-coupled showerhead cold-wall MOCVD reactor with high-purity N 2 gas as the
carrier and purge gas. The n-GaAs buffer epilayers with a Si doping of 2-5 x 1017 cm-3
were grown on Si doped GaAs(1-4
x101
8
cm~3) two-inch wafers at 650
C with
trimethyaluminum (Ga(CH 3)3) and arsine(AsH 3) (V/11= 23, molar ratio). The reactor
pressure was maintained at 100 Torr during the GaAs buffer growth. Following the GaAs
buffer layer growth, the reactor pressure and the temperature of substrates was decreased
to
50
Torr and 550
C, respectively.
14.5nm
CVD
grown
A12 0 3 was
with
trimethyaluminum (TMA) and isopropanol (IPA) as the precursors (IPA/TMA=20, molar
ratio). The brief process flows for the growth of these experiments are shown in figure
6.1.
For comparison, a control sample with 11.5 nm ALD-grown A120
3
was prepared
following the detailed growth procedure which has been described in previous work [4,7].
127
Depth profiles of the elements (C, Al, Ga) were determined by SIMS with Cs' ions of
energy of 1keV. The microstructure and interface between the CVD A120 3 films and the
GaAs substrates were investigated by High-Resolution TEM (HRTEM). XPS was also
performed in a Kratos AXIS Ultra Imaging system using a monochromatic Al Kal source
(1486.6 eV) to determine the bonding state of the elements at the interface. To enhance
the signal intensity from the interface and avoid sputtering damage during the
depth-profile measurements, 2nm of CVD A120 3 on GaAs was prepared using the same
procedure and precursors described above and then the sample was transferred to XPS
system within 10 minutes via a vacuumed container. The C-V characteristics of
metal-oxide-semiconductor capacitors were measured using HP4192A LF impedance
analyzer at frequencies from IMHz to 10kHz and the capacitors were fabricated by
depositing 200-ptm-diameter Al electrodes using thermo-evaporation.
CVD GaAs
CVD A120,
a.
0
0.
E
0
0
Time
Figure 6.1 Process Flow of the In situ CVD A12 0 3 on GaAs
128
6.2 Experiments of CVD with TMA and IPA
Control of the deposition temperature is potentially the most important variable in
the CVD process because CVD is a thermally activated process. Temperature will affect
the reaction rate of the precursors in the gas phase and on the wafer surface during the
deposition and thereby the deposition rate as well. Furthermore, the growth rate is also
determined by the precursor transportation rate to the wafer surface because the CVD
process is a sequential combination of two processes: transportation of precursors to the
wafer surface and reaction on the wafer surface.
Figure 6.2 shows the relation between the growth rate and the deposition
temperature of the CVD A12 0 3 in MOCVD reactor. The growth rate remains almost
constant (-0.056 nm/s) at growth temperatures below about 560'C and starts to drop as
the temperature increases above 560'C. In the constant growth rate regime (<560 C), the
chemical reaction rate is much higher than the rate of the precursors transported to the
wafer surface. The growth rate is therefore controlled by the precursors flux from the gas
phase to the wafer surface in this regime. When the deposition temperature is higher, the
growth rate decreases. This behavior is usually attributed to the depletion of the
precursors in the gas phase by particle formation. This behavior also suggests that the rate
of precursor desorption becomes significant in comparison to the reaction on the wafer
surface at higher temperature and this resuts in the decrease of the growth rate.
0.060
Preactor=
50 torrs, TMG=50 sccm, IPA
=
150 sccm (350 torrs)
0.055
-
E
0.050
Flux-Limited
High-T
Region
Region
0.045 .io
0.040 -
0.035 0.030
0.025 0.020 -
1. Precursors decompose in gas phase
2. Surface desorption
0.015
620 600 580 560 540 520 500 480 460 440
T, ( 0C)
Figure 6.2 Deposition rate of CVD A12 0 3 vs. Temperature
6.3 Mechanism of CVD with TMA and IPA
The two precursors flow into the reactor simultaneously in the CVD process while the
precursors flow into the reactor in sequence in the ALD process. The precursor flow is
intentionally separated in the ALD process to prevent gas phase reaction. In the CVD
process, the precursors mix and may react in the gas phase prior to reaching the wafer
surface. In our process, the initial precursors TMA and IPA are mixed and react in the gas
phase to form the intermediate precursor, aluminum isopropoxide [Eq. (1)][6.2]. Then,
the aluminum isopropoxide transports to the substrate and thermally decomposes at the
growth surface [Eq. (2)][6.3]. In this stage, one product of the decomposition reaction is
H2 0 and it is a strong oxidant that could oxidize the GaAs during the deposition. The
CVD process, unlike the ALD process, is a water-related process.
Al(CH 3 )3 +3(CH 3 ) 2 CHOH -+ Al(OCH(CH)
2 )3
+3CH 4
( 1)
-+ Al 2 03 +6CH4+3H 20
2A(OCH(CH,)
(2)
6.4 SIMS depth profile analysis
Figure 6.3 shows the SIMS depth profile from the surface of the CVD A12 0
3
to GaAs
substrate. The transition region (the A12 0 3/GaAs interface) is clearly shown in the figure.
The gallium signal near the substrate can be fitted with an error function and illustrates
the A120 3/GaAs interface is sharp; the center of error function is the location of the
interface. The depth resolution was found to be 2nm by measuring the depth difference
between the 84 and 16% levels of the intensity scale [6.4]. A 5.3nm gallium rich-region
was observed above the interface.
This thickness is greater than the depth resolution.
This gallium-rich region could also be observed by TEM. The inset of the figure 1 shows
the TEM image and a 5nm slightly darker region can be seen in the A12 0
3
film above the
interface and the contrast originates from the atomic mass differences between heavier
gallium and aluminum atoms. Residual carbon concentration is low (5 x 1019
A12 0
3
cm
3
) in the
thin film which compares well with the oxide film deposited by a single CVD
precursor [6.5] [6.6]. The carbon concentration is slightly higher (1.5 x 1020 cm 3 ) near
the gallium-rich region and this may be due to the accumulation of carbon in the reactor
during the post-deposition cool-down. As mentioned above, only TMA was applied as the
metal source to deposit the A120
3
and the TMG flow was shut down immediately after
completion of buffer GaAs growth. As no gallium source existed in the reactor during the
A1 2 0
3
growth, this implies that enriched gallium above the interface may come from the
GaAs substrate itself. Chemical reactions may occur between the precursor gases and the
131
substrate to enrich the gallium above the interface.
1023
=100
d
90
1022c?
80
E
70
GaAs
60
- 50
.
A
40
310
Al
30
n5 20
20
10.
1-
Ga-Rich
0
2
Ga
101
-egion
-0
1021.
0
10
4
-'1-
104
6 8 10 12 14 16 18
Depth (nm)
Figure 6.3 SIMS depth profile of elements C, Ga, and Al. The Ga, and Al were plotted in
relative intensity (left Axis) while the C was plotted in atomic concentration (right Axis).
The open square symbols represent the fitted error function of gallium profile
6.5 Structure of the CVD A12 0 3 thin film
Figure 6.4 shows the cross-section TEM image of the as-deposited
CVD
A12 0 3/GaAs interface. The interface is flat and abrupt. The A120 3 thin film is uniform and
there is no lattice image observed in the A12 0 3 thin film, which indicates the amorphous
structure. A 5nm slightly darker region can be seen in the A1 20 3 film above the interface
and the contrast comes from the atomic mass differences between heavier gallium and
aluminum atoms. This region correlates with the Ga-rich region observed in the SIMS
depth-profile analysis.
Figure 6.4 TEM image of the CVD oxide/GaAs structure
XRR was also performed to measure the thickness of the thin film and roughness of
the interface and the surface of the CVD A12 0 3 /GaAs structure and it is shown in figure
6.5. For comparison, the XRR of ALD A12 0 3 /GaAs structure is also shown in the
figure.The XRR of CVD A12 0 3 /GaAs shows a well-behaved fringe pattern at lower angle
and these fringes steadily disappear when the angle is greater. As described in section 4.4,
this fringe disappearance indicates that the interfacial roughness is higher than that of
ALD sample. The XRR curve was also fit with a theoretical model and the extracted
surface and interface roughness are 1.522nm and 0.366nm, respectively. Both values are
higher than the ALD values. (0.548 and 0. 123nm). This is due to the inherent difference
of the growth modes of ALD and CVD. The higher interfacial roughness may be due to
the existence of H20 in the gas phase and oxidization of the wafer surface during the
deposition.
1
2
3
4
5
6
Angle 20 (0)
Figure 6.5 X-Ray Reflectivity of ALD Al 2 O3/GaAs structure (Red line) and ALD A12 0 3/GaAs
structure (Green line)
6.6 Surface morphology and defect status in the CVD A12 0 3 thin film
In section 4.9, structural defects were found to exist in the in situ ALD A12 0 3
thin
film on GaAs due to the incomplete coverage of the precursors on the wafer surface
during the ALD growth. In the CVD process,we might expect a more complete coverage.
Figure 6.6 shows the AFM image of the as-deposit CVD A1 2 0 3 thin film. The
root-mean-square (RMS) roughness over an area
1 pm
x I pin is about I.394nm,
which is close to the value extracted from the XRR measurement (l.522nm). Some
particles were observed in the image and these were not seen in the ALD sample. As we
discussed in section 6.2, these particles may be generated in the gas phase due to the
decomposition of the intermediate precursor and deposited on the surface. Figure 6.7
shows the surface line scan of AFM image of the as-deposit CVD A12 0 3 thin film. The
particles have a diameter of about 1-4 nm and are randomly distributed on the surface,
resulting in a higher RMS in both XRR and AFM measurements.
Figure 6.6 AFM image of the as-deposit CVD A12 0 3 thin film
Figure 6.7 Surface line scan of AFM image of the as-deposit CVD A12 0 3 thin film
Figure 6.8 shows the AFM image of the oxide etched by HCI:H 20 2 :HF:H 20
=
10
5 : 1: 35 for 30s. After the etching, no pin holes in the oxide are revealed and the particles
almost disappear. This phenomenon is due to the HF in the etchant as it preferentially
attacks the particles on the surface. Figure 6.9 Surface line scan of AFM image of an
etched CVD A12 0 3 thin film. Because the particles were removed, the surface becomes
smoother and RMS was calculated as 0.273nm, which is close to the value of ALD A12 0 3.
These results suggest that there are no weak points in the CVD A12 0 3 thin film, but a high
density of small A12 0 3 particles that are generated and deposited on the oxide surface.
Figure 6.8 AFM image of the etched CVD A12 0 3 thin film
Figure 6.9 Surface line scan of AFM image of the etched CVD A12 0 3 thin film
136
6.7 The chemical stoichiometry and bonding state of the A12 0 3 and gallium rich
A12 0 3 at CVD A12 0 3 /GaAs interface and possible mechanism of formation
The XPS spectra of the Ga2p3s2, As2p 3
2, and
Al2p at the oxide/GaAs interface are
shown in Figure 6. 10 (a) (b) (c), respectively. In order to increase the surface sensitivity
of XPS measurement, Ga2ps 2 and As2ps 2 spectra were measured because the kinetic
energy (KE) of the photoelectron is low (Ga, KE-369eV; As, KE~164eV) and most of
these photoelectrons originate from near surface region [6.7]. In Figure 6.10(a), the Ga
2P3 2 spectrum is fit with 2 peaks. One is the Ga
2Ps,
in GaAs with the binding energy
3
about 1117.5 eV and another one is 1.1 eV higher, which corresponds to the Ga+ state in
Ga 2O 3. However, only the strong As
2P3a
signal from the GaAs substrate is observed in
Figure 6.10(b) and can be fit with a single peak which is center at 1323.1eV. No
As
(As 2O3) states were detected in the spectrum. A lack of As 2O3 formation is important
to avoid high interfacial state densities, and the missing XPS peak is correlated with a
lower presence of interfacial states in previous studies. In Figure 6.10(c), the Al
3
state in
A12 0 3 is detected via the Al2p spectrum with binding energy of 74.9eV. No Al-Al
bonding or Al-Ga bonding is observed in the spectrum. These results suggest that the
gallium rich region observed in SIMS consists predominately of only A12 0
3
and Ga 2 0 3.
Fig 6. 10(d) shows the HRTEM image of the A12 0 3/GaAs interface. The interface remains
sharp and is atomically smooth even though we suspect that several chemical reactions
happen at the interface.
Ga 2p 312
As 2P32
Ga-O
As-Ga
Ga-As
(a)
As-O(b
e
1124
1122
C
1120
1118
1116
1114 1328
Binding Energy (eV)
1326
1324
1322
Bindin Ener
1320
1318
e
Al 2p
C)
80
78
76
74
72
Binding Energy (eV)
70
Figure 6.10 XPS spectra of (a) Ga 2p32 (b) As 2p31, and (c)Al 2p at oxide/GaAs interface.
The open hexagons and curves represent the raw data and fitting peaks. The Shirley
background subtraction was included in all XPS fittings. (d) HRTEM image of the interface
between GaAs substrate and CVD A120 3
A possible mechanism is proposed based on the SIMS and XPS analysis. In the
CVD process, a product of the reaction is H 20, and it could oxidize the GaAs, generating
both Ga 2O 3 and As 2O3 [Eq. (3)].Because the growth condition has a high IPA/TMA molar
ratio during the oxide deposition, excess IPA might remain in the gas and result in a
",self-cleaning effect" by reacting with the As 2O3 to form the volatile compound
As(OCH(CH 3)2)3 that will be removed from the substrate surface by the N2 carrier gas
flow [6.1][6.81. The remaining Ga 2O 3 mixes with the deposited A120 3 and diffuses out
toward the A120
3
surface as film deposition continues, resulting in a gallium rich (Ga 2O3-
A120 3 mix) region above the interface. No Ga 2O 3 is observed at the in situ ALD/GaAs
interface due to the different growth mechanism, as described in section 5.4 [6. 1]. Figure
6.10(d) shows the HRTEM image of the A120 3/GaAs interface. The interface remains
138
fairly sharp even though several chemical reactions happen at the interface.
2GaAs +6H 20 -
Ga203
+ As 2 0 3 +6H
(3)
2
One problem with this proposed mechanism is that no Ga 2O 3 was observed at the in
situ ALD-formed interface.
It is possible that no Ga2O3 can form during the ALD
process due to different growth mechanism [7]. However, many complex reactions can be
occurring at the surface during deposition, and therefore we can only speculate as to the
mechanism of Ga enrichment at the interface.
6.8 The C-V characteristics and the Dit at CVD A12 0 3/n-GaAs interface
The C-V characteristics suggests the existence of the Ga 20 3-Al 2 0
3
region above
the oxide/GaAs interface helps to reduce the frequency dispersion and lower the
interfacial state density. The C-V characteristics of the in situ CVD and ALD A12 0
3
samples on GaAs are shown in figure 6.11 (a) and 6.11(b), respectively. A clear transition
from accumulation to depletion is observed in the C-V curve of the CVD A12 0
but this transition is not observed in that of the ALD A12 0
3
3
sample,
sample. The Dit of CVD
sample can be extracted by the conductance-frequency method [6.8] and is shown in the
figure 6.12, approximately 2.5 x 101 (cm
2
eV-1).
conductance-frequency method is valid for Dit
Of note, the Dit extracted from the
Cox/q, Cox and q are the oxide
capacitance per unit area and unit charge, otherwise the extracted values are lower limits
to the real Dit [6.91. From the capacitance measured in the accumulation region of the
CVD sample(~ l30pF), the boundary for this experiment is calculated to be Di,
139
K
2.6 x
10 2(cm2 eV'), which means that Dit extracted from the CVD sample is in a reasonable
range. However, the Dit of the ALD sample is inconclusive due to large stretch-out of the
C-V curve induced by a very high Dit and the loss of clear conductance peaks in the
measurement. Figure 6.13(a) and 6.13(b) show a G,/o-Vg-f map of the CVD and ALD
samples, where Gp, o and Vg represent the parallel conductance, angular frequency and
gate voltage, respectively. The position of the normalized conductance peak can be
transformed to determine the trap energy level and fermi-level in the bandgap
[6.10] [6.11]. The dashed white lines represent the movement of the Gp/o peaks versus
gate voltage and demonstrates that the fermi-level of our CVD A12 0 3/GaAs capacitor is
unpinned and controllable by the gate bias, while the fermi level of the ALD sample
cannot be moved and pinned due to high Dit. The Dit of the ALD sample is estimated to
be at least three times higher than that of CVD sample from the low frequency part of the
map.
-
14 0
%
120
140
E-120
-e1kHz
-OkHz
100
-100
80
60
00-OkHz
-500kHz
80 -m-1000KHz
0
60
~4020
-3
.
VD Al
.
-2
-1
0
1
O,(a)
2
DA 03b
-2
-1
Gate Voltage Vg (V)
0
1
2
40
20
3
Figure 6.11 C-V characteristics of in situ (a) CVD and (b) ALD A120 3 on GaAs
4(1012
CVD
"M
E
*~
1
0.40
0.36
0.32
E - E, (eV)
0.44
Figure 6.12 Di, distribution of CVD samples in the band-gap extracted by the
conductance-frequency method
1a
12 30
10 25
N
I
8
4--
N
42
5106
106
U106
~6
15
z
4
10
0
0
0C
L
LL
104
-3 -2 -1 0 1 2
Gate Voltage Vg (V)
3
Gp/w
(pF)
-3
-2 -1 0 1 2
Gate Voltage Vg (V)
A104
3
Figure 6.13 G,/o-Vg-f map of CVD (a) and ALD (b) samples. The dashed white line is guide
to the eyes and the scale of maps (c) and (d) is different
In summary, in situ deposition of A120 3 on GaAs was performed by CVD with TMA
and IPA as precursors. A gallium rich region in the CVD A1 20 3 thin film above the
interface was observed in SIMS depth profile measurement. The XPS results show that
gallium rich region consists of the A120 3 and Ga20 3, but no As2O3 was observed, possibly
due to a self-cleaning effect during the CVD process. The analysis supports the proposed
chemical reaction mechanism and suggests the existence of the Ga 2O 3- Al 2O3 mix region
above the A12 0 3/GaAs interface helps to reduce the frequency dispersion of the C-V
characteristics and lower the interfacial state density.
Chapter 7 Interfacial defect state distributions in the band-gap
with different deposition processes
We have presented the physical and electrical properties of MOS capacitors in
which the oxides were deposited with either an ALD or CVD process . The C-V
characteristics
were
strongly
on
dependent
the
oxide
deposition
process
and
pre-treatments. These different processes may change the interfacial defect density
distribution in the band-gap and affect the C-V characteristics. Understanding the link
between the process and defect states generated is important to further improve on the
performance of the material and device.
In the previous chapter, the C-V measurements were performed at room-temperature.
We can
extract the information
conductance-frequency
method.
of Dit from the C-V
However,
the
measurements
measurements
by the
performed
at
room-temperature can not provide the complete Dit information in the band-gap. To
measure the Dit near the mid-gap and conduction or valence band edge of GaAs, the
measurements performed at high (-I 50 0C) and low (~-80'C) temperature are required.
In this chapter, the Di, information from the samples with different processes were
summarized and analyzed. The potential source of the interfacial defect states will be
discussed and how the interfacial defects affect the C-V characteristics will also be
presented. Finally, the relation between the processes and interfacial defect state
distributions is established.
7.1 The characteristic time and response frequency of the defect state charge in the
band-gap of GaAs
The detail physics of the characteristic time and response frequency of the defect
charge in the band-gap has been described in chapter 2.3.3.The applied frequencies of the
144
Wk-
C-V measurements usually range from 100Hz to 1MHz and these conditions result in
only a portion of the defect states in the band-gap being accessible at room temperature.
In order to access the whole interfacial defect state distribution in the band-gap, the C-V
measurement must be performed at different temperatures and on both p- and n-type
GaAs substrates. Figure 7.1 shows the characteristic measurement frequencies (response
0
frequency of defect charge) for both electrons and holes at -800C, 25 0C, and 150 C.Based
on this figure, only the traps located at 0.32-0.57 eV and 0.91- 1.16 eV for holes and
electrons,
respectively, above the valence band edge can be accessible with
room-temperature (25 0C) C-V measurements. To measure the defect state density near the
mid-gap, C-V measurements must be performed at high temperature for GaAs.
N
p-type
108
M
250C
10io
a) 10
LL
n-ype
*-80,C
\ 1500C
1
c7=10 cm
i
I
A
10
- 10
e
10 0
E2
a) 102
. .
i.
~\'
cnl 10
c)
0.0
EEt-
0.2
0.4
0.6 E 0.8
E (eV)
1.0
1.2
1.4
E
Figure 7.1 Characteristic measurement frequencies (response frequency of trap) for both
electrons (dashed lines) and holes (solid lines) at -80*C, 25*C, and 150*C. The horizontal
black dashed lines represent the frequency range that is usually applied in C-V
measurement. The horizontal colored solid and dashed lines represent the traps that can be
accessible in the band-gap during the C-V measurements at different temperatures
7.2 The distribution of interfacial defect density with different processes
In chapter 5.5, we have shown that the Dit distribution in the band-gap extracted by
the conductance-frequency method at room temperature. In order to determine the entire
distribution of the interfacial defect states in the band-gap, high-(150 0C) and low-(-80'C)
temperature C-V measurements were performed.
The Dit distributions of A12 0 3/p-GaAs interfaces of different processes that was
determined
from
low-(-800 C),
room-
(25 0C),
and
high-(I 50'C)
conductance-frequency method are shown in figure 7.2. The 12 nm A1 2 0
temperature
3
layer was
deposited by in or ex situ ALD or in situ CVD. Among these curves, the defect state
density of in situ ALD sample is the lowest near the valence band edge (E,-Ei < -0.3 eV,
E, and Ei are the defect state trapping level and intrinsic level of GaAs at the interface,
respectively).However, there is a large mid-gap defect state that exists for in situ ALD
sample. The Dit of other processes near the mid-gap is lower compare to the in situ ALD
sample.
12
12 v -4fl .
10"
mid-oa
mid-gap
X
-
253C
150 C
10
8-I--Ex situ ALD
CVD
> 8 --- -In nsitu
situ CVD with TMG flow
- -*-In situ ALD
S 6-
0
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
E, Trap EnergyEt-E (eV)
Figure 7.2 Interfacial defect state density of A12 0 3/p-GaAs interface of four process that
described in previous chapters as determined from conductance-frequency method at low(-80"C ), room, and high-(150"C) temperature. The temperature regions labeled in the
diagram represent the temperatures that the C-V measurements were performed
Figure 7.3 shows the C-V characteristics of the in situ ALD and CVD samples
measured at room and high-(150'C) temperature. For C-V curves measured at room
temperature, the in situ ALD sample (figure 7.3(a)) shows smaller frequency dispersion
near the accumulation region compared to the in situ CVD sample (figure 7.3(c)). For
C-V curves measured at high-temperature, there is a significant hump which appears in
the depletion region of the C-V curves of the in situ ALD sample(figure 7.3(b)); no hump
is observed in that of in situ CVD sample(figure 7.3(d)).
ISO
(a)
.
~120
ALD
ALD
25 0C
CL
150 0C
so
40
-4
2
2
1
V (V)
0
1
40L
-4
2
3
.2
-
V, (v
200
2M4
'ooko-
(c)
140
0
CVD
250C
a
c0
.4
4
.21 -
ADa
a.,
Go10
.1
0
1
40
.4
0
V, (V)
CVD
~ 00
.2
y (V)
42
.1
V MV
10
a
1
2
Figure 7.3 C-V characteristics of in situ ALD and CVD samples measured at room and
high-(150'C) temperature
From these observations, the frequency dispersion near the accumulation region and
the hump near the depletion region of the C-V curves may be caused by an interfacial
defect state near the accumulation region and the mid-gap defect states. Gallium plays an
important role to lower the mid-gap defect state as we observed in the CVD case.
In order to prove that Ga 2 O 3 in the region above the interface lowers Di,, we
prepared a sample by flowing TMG for I min prior to in situ CVD Al 20 3 on p-GaAs. The
interfacial defect state density distribution is also shown in figure 7.2(Green curve). The
intent for this process is to have more gallium incorporated intentionally near the
A120 3/GaAs interface. This sample has the lowest mid-gap defect state density we have
measured to date However, the exact mechanism of lowering the level of mid-gap defect
state by the existence of Ga 20
3
or by flowing a pre-layer of TMG at the interface is still
unknown.
C. L. Hinkle recently suggested that the existence of the Ga 2 0
148
3
instead of Ga 20 at
the oxide/GaAs interface would cause high Dit at the interface and large frequency
dispersion of C-V curves of n-type MOSCAP [7.1]. In their experiments, they deposited
ALD A12 0 3 directly on the HF treated GaAs wafer and observed that both Ga 2 O 3 and
Ga9 O states existed at the interface from XPS measurements. The C-V curves of this
sample showed large frequency dispersion. Then, they applied ex situ remote plasma
chemical vapor deposition system to deposit amorphous Si on a GaAs wafer and followed
that process with the A12 0 3 deposition. They observed that Si getters the oxygen from
the Ga 2O 3 and also provides a barrier to further interface oxidation from subsequent
processing, including ALD process. After Si passivation, only Ga 20 and Ga-Si bonding
were observed at the interface in the XPS spectrum. The C-V curves of this sample
showed very low frequency dispersion. Finally, they compared the C-V characteristics
and the bonding states at the interfaces of two samples. However, they did not discuss
how the existence of the Ga-Si bonding at the interface affects the C-V characteristics of
the MOSCAP. They also observed that the Ga 2O always exists at all interface and agree
that it does not play a key role in the Fermi level pinning. Hence, the improvement of the
C-V characteristics may not be due to the removal of the Ga 2O 3 but due to the existence
of the Ga-Si bonding at the interface.If this is true, our results do not contradict theirs.
7.3 The source of the interfacial defect states in the band-gap of the GaAs
The source of the interfacial defect states are usually derived from the imperfection
of the crystal structure at the interface. For example, dangling bonds are the most
important defect identified in the (100) Si/SiO 2 interface. The dangling bond is an
unpaired electron and it is a result of an effective mismatch between the crystalline Si
149
substrate and the amorphous SiO 2 layer. This kind of defect is called a
Pbo
center and it is
an amphoteric defect that can trap holes or electron, depending on the position of the
Fermi level in the Si band-gap. The common interfacial defect distribution for Si can be
approximated by two Gaussian distributions and are shown in Figure 7.4[7.2]. No
mid-gap defect states exist in the band-gap of the Si and the dangling bonds can be
passivated by annealed in a hydrogen-containing atmosphere [7.3].
John Robertson recently proposed a model for the density of interface states at Ill-V
oxide interfaces [7.4].The large number of the mid-gap defect states is formed due to
gallium
or arsenic vacancies. The gallium and arsenic vacancies would
cause
acceptor-like traps (electron traps) and donor-like traps (hole traps), respectively. Some
researchers also suggest that defect states in the band gap are generated whenever the
process of adsorption itself, disrupting the morphology of the reconstructed GaAs(OO I)
surface, induces structural defects on the surface, e.g. distorted bonds[7.5,7,6].They
propose that the oxidation process will create some native defect states at the interface
because not all of the Ga-As bonds are converted into Ga-O or As-O bonds by oxidation.
Summarizing their model, the mid-gap states are due to vacancies, anti-sites, and the
disrupted bonds. The dangling bonds of the surface Ga and As atoms produce defect
states near the conduction and valence band edge. Because oxygen has a higher affinity to
bond to the Ga atom, the like-atom bonds may also be generated during the oxidization
(generation of local arsenic-rich region). These like-atom bonds (As-As and Ga-Ga) will
also create defect states near the conduction and valence band edge. The schematic
diagram of the interfacial defect state distribution of GaAs is shown in figure 7.4.
Vacancy
-(Acceptor-ULke)"-
disrupted
bonds
Vacancy
GaAs
Si
E,
E.
Donorike
E,
Ec
1.Ga Dangling bond
2As-As anti-bonding
(Acceptor-Like)
Dangling bond 1.As Dangling bond
(Acceptor-Like) 2.G.-Ga anti-boning
(Donor-Like)
{Electron trap)
Dangling bond
(Donor-Like)
(Hole trap)
Figure 7.4 Schematic diagrams of interfacial defect state distributions of Si and GaAs
7.4 The interfacial defect states and C-V characteristics
In order to know how the interfacial defect states affect the C-V characteristics of
the MOSCAP device, a theoretical simulation of the C-V characteristics with interfacial
defect states were done. The software we used is called "MISfit", which is a program for
analyzing
simultaneously
C-V
conductance-voltage
and
(G-V)
curves
from
metal-insulator-semiconductor (MIS) structures [7.7]. In all simulations, the distribution
of
the
(D,, (E,)
interface
defect
state
D,, x exp[(E, E)2/AE2]
was
assumed
to
be
Gaussian
distribution
, Here, Et, Dito, Eo, and AE are the defect state
energy (eV), peak value (eV'cm-2 ), center of the peak in the band-gap (eV), and standard
deviation (eV). The intrinsic level (Ei) is set to be 0 eV as the reference to other energy
states.
The peak value and AE of the peak were assumed to be 2 x 10" (eV cm-2 ) and
0.2 eV, respectively. The doping level of the substrates for both p- or n-type is set as 1017
2
(cm-3) and the capacitance of the insulator is set as 0.5 (pFE/cm ). The scale of the diagram
of the C-V curves is the same for all plots.
Figure 7.5 shows the diagram of C-V characteristics of the MOS structure with
donor-like (hole trap) defect states locate 0.1 eV above valence band edge. The frequency
dispersion is observed in p-type, but not in n-type samples. Such high Dit causes a parallel
frequency shift near the accumulation region of the C-V curves in the p-type sample and
generates a kink near the accumulation/depletion transition region of higher-frequency
C-V curve. These defect states would only stretch the C-V curves out in the depletion
region for the n-type sample (compared to the ideal C-V curve (black dashed line) shown
in the diagram). For the acceptor-like (electron trap) defect states locate at 0. 1eV below
conduction band edge, the results are the opposite as the p-type case and shown in figure
7.6.
n-typeGaAs
p-type GaAs
E,
E
E
-E
(a
.....
iOkH
&
30303
Donor4.Jke
Hol ap
vGv
v 9v
Figure 7.5 Diagram of C-V characteristics of the MOS structure with donor-like defect
states locate at 0.1 eV above valence band edge (The X-axis of the simulated C-V curves is
subjected to adjustment)
n-type GaAs
p-type GaAs
cr
C-V
ideal
I
Acceptor-uke
->a
o
u -----
,.
a
//
(
30~
Figure 7.6 Diagram of C-V characteristics of the MOS structure with acceptor-like defect
states locate at 0.1eV below conduction band edge (The X-axis of the simulated C-V curves
is subjected to adjustment)
Two possible types of mid-gap states could exist in the band-gap: one is donor-like
(hole trap) and another is acceptor-like (electron trap). For mid-gap donor-like defect
states, a larger frequency dispersion for p-type samples would occur as compared to the
donor-like defect states near the valence band edge. The degree of the frequency
dispersion could also be affected by the AE of the defect peak and the cross-section
area of the carriers. Simulations for mid-gap defect states are shown in figure 7.7 and
figure 7.8.
Donor-Like
HoM trap
p-typ!e GaAs
n-type GaAs
0,
.I
C.3.)
Aea C-V
t0.03
0,0
v,(v)
v,(v)
Figure 7.7 Diagram of C-V characteristics of the MOS structure with donor-like defect
states locate at mid-gap of GaAs (The X-axis of the simulated C-V curves is subjected to
adjustment)
Acceptor-Like
Electron Trap
0.5
p-type GaAs
4pe GaAs
0
E
=$1
"kHz
(a)
"JI
0500ko
U
U
Ideal C-1V
0.0
-3
00
-330-3
Figure 7.8 Diagram of C-V characteristics of the MOS structure with acceptor-like defect
states locate at mid-gap of GaAs (The X-axis of the simulated C-V curves is subjected to
adjustment)
In situ ALD on GaAs
In chapter 7.2, a high density of mid-gap defect states for in situ samples. Based on
the simulation results, this mid-gap defect state would cause significant frequency
dispersion of C-V curves in the accumulation region, and
depends on the type of the
defect state. Figure 7.9 shows C-V characteristics of in situ ALD Al 20 3 on both p- and
n-GaAs and we find that the frequency dispersion is very large for the n-type sample.
This behavior implies that the mid-gap defect state found in our samples is acceptor-like
(electron trap).If these traps are mainly caused by the existence of vacancies at the
interface, they would therefore be gallium vacancies. Although both types of the mid-gap
defect state can exist simultaneously, the acceptor-like mid-gap defect state is the
dominate one. The possible distribution of interfacial defect state for our samples is
shown in figure 7.10.
n-type GaAs
p-type GaAs
2001
(a)
'180
Ci6
-160
8140
,120
Q100
a 80
0
402
U
-4 -3
4
140-
120
1060(b
100
0
8
60
-2 -1
Vg(V)
80
160(
0
1
2
-
A
0 1
Vg(V
2
3
4
Figure 7.9 C-V characteristics of in situ ALD A12 0 3 on both p- and n-GaAs
Vacancy (Ga or As?)
(Acceptor-Like)
E,
EC
1.As Dangling bond
2.Ga-Ga anti-bonding
(Donor-Like)
1.Ga Dangling bond
2.As-As anti-bonding
(Acceptor-Like)
Figure 7.10 Possible distribution of interfacial defect state for our samples
During the in situ ALD process,
GaAs was deposited with TMG/AsH 3 and then the
AsH 3 flow was turned off during the cooling. In arsenic rich environment, the surface of
the GaAs would form c(4x4) surface reconstruction, which is an arsenic rich surface
(figure 7.12)[7.8].For the following ALD process, the TMA was first introduced into the
reactor and the arsenic atoms on the GaAs surface serve as a bridge between the GaAs
and the A12 0 3 to form Al-As bonding, absorbing the TMA. This process is similar to the
ALD of AlAs with TMA and arsine [7.9]. However, the surface gallium atoms and some
excess As-As bonding would cause a high density of defect states near the conduction
band edge. Also, the density of mid-gap defect state is very high because no Ga 2O 3 exists
at A12 0 3/GaAs interface. The possible distribution of interfacial defect state for in situ
ALD A12 0 3/GaAs interface is shown in figure 7.11. This distribution would result in a
very high frequency dispersion in the C-V curves for the n-type substrate, but for low
frequency dispersion for p-type samples, the C-V curve is expected to be close to ideal
since there are few arsenic dangling bonds.
Vacancy (Ga or As?)
1.Ga Dangling bond
2.As-As anti-bonding
(Acceptor-Like)
1.As Dangling bond
2.Ga-Ga anti-bonding
(Donor-Like)
Figure 7.11 Possible distribution of interfacial defect state for in situ ALD A12 0 3/GaAs
interface
GaAs (100) c(4x4)
(Top View)
0
00
0
0
n0
O0 0
dO*b
0
0
0
0 0 0
0
0
..
0
0
0
00 00
0
0
0
cO@'O
0~
0
0
o
X8
0
0
0
0
0
(Side View)
0-
As
As
Ga
As
Ga
Figure 7.12 Surface structure of GaAs (100)-c(4x4)
reproduced from Wolfgang Richter
surface reconstruction.
Figure
17.71
In situ CVD A12 0 3 or ex situ ALD A12 0 3 on GaAs
In in situ-CVD or ex situ ALD A12 0
3
process, the surface of the GaAs would be
oxidized during the CVD process due to existence of the H20 or exposed to the oxygen in
the air. In this process, both the Ga 2O3 and As 2O3 would be produced but the As 2O3 will
be removed by the TMA or IPA during the deposition due to the self-cleaning effect. A
gallium oxide rich interface will form in these processes and lower the density of the
mid-gap defect state. However, some arsenic dangling bonds may not be fully passivated
and this may cause the higher density of defect state near the valence band edge than that
in in situ ALD process. The possible distribution of interfacial defect state for this kind of
interface is shown in figure 7.13. This distribution would result in a smaller frequency
dispersion of the C-V curves for n-type substrates but a larger frequency dispersion of the
C-V curves in accumulation region for p-type samples, as we observed in figure 5.5.
{
EV
Vacancy (Ga or As?)
(Acceptor-Like)
EC
1.As Dangling bond
1.Ga Dangling bond
2.Ga-Ga anti-bonding
(Donor-Like)
2.As-As anti-bonding
(Acceptor-Like)
Figure 7.13 Possible distribution of interfacial defect state for in situ CVD and ex situ ALD
A120 3/GaAs interface
The additional flow of TMG is similar process to the in situ CVD process, but more
gallium can be incorporated near the A12 0 3/GaAs interface. This lowers the density of the
acceptor-like mid-gap defect state further and this was observed in figure 7.2. The
possible distribution of interfacial defect state for this kind of interface is shown in figure
7.14.
Vacancy (Ga or As?)
(Acceptor-Like)
Ee
1.As Dangling bond
2.Ga-Ga anti-bonding
(Donor-Like)
1.Ga Dangling bond
2.As-As anti-bonding
(Acceptor-Like)
Figure 7.14 Possible distribution of interfacial defect state for in situ CVD with flowing
TMG for I min prior to oxide deposition
Chapter 8 Summary, Conclusion, and Suggestions for Future
Work
In situ deposition of high-k materials to passivate GaAs in a MOCVD system has
been demonstrated. Both ALD and CVD methods in the MOCVD tool were applied in
this research. The CVD AIN was first selected to be in situ deposited on GaAs to
passivate the surface by using TMA and DMHy. However, the frequency dispersion of
C-V curves for in situ AIN/GaAs MISCAP samples are always large because of the
existence of a high density of the interfacial defect states in the band-gap. Nitridization of
the GaAs surface by the DMHy precursor during the CVD AIN appears to be the case.
The AIN is also leaky since it is poly-crystalline. Based on these two reasons, CVD AIN
currently is not a good candidate for passivation of GaAs.
In situ ALD A12 0 3 on GaAs in MOCVD system was demonstrated by using TMA
and IPA as the precursor. The saturation growth rate is about 0.8
A /cycle
while the pulse
time of TMA and IPA are longer than 2s and the growth temperature is higher than about
350 0C. Aluminum alkoxide was formed as the intermediate species during the ALD cycle
and the IPA-ALD is a non-water process, which would not oxidize the GaAs surface
during the ALD process. No arsenic oxide and gallium oxide is observed at the
A12 0 3/GaAs interface and the surface of the A12 0 3 consists of a thin layer of
oxygen-deficient A12 0 3 . The frequency dispersion on accumulation capacitance and on
voltage shift in depletion region are about 1.5% and 0.05V per decade, respectively .The
lowest interfacial defect density probed with room temperature C-V measurements is
about 2.5 x 101 (eV cm ), which was determined by the conductance-frequency method.
The ex situ process was also investigated to compare the results with that of the in
situ process. Interfacial self-cleaning and surface recovery in ex situ ALD of A12 0 3 was
demonstrated. The concept of using the TMA/IPA as precursors to remove the native
oxide was confirmed by both HRTEM and the C-V measurement, which showed small
160
dispersion and high capacitance. Ex situ A12 0 3/n-GaAs showed better C-V characteristics
than that of the in situ case. Moreover, annealing native-oxide covered GaAs samples in
AsH 3 is shown to undo the oxidation process incurred when the ex situ procedure is
performed.
The C-V characteristics of the AsH 3 treated sample resemble that of the
sample under in situ process. No Ga 20 3 was detected at the in situ A12 0 3/GaAs interface.
However, it is reported that there is residual Ga 20 3 at the oxide/GaAs interface and this
may be reason for increased frequency dispersion in the C-V curves for the n-type
sample.The lowest Di, is around 5x10" (1/cm2 eV) for both in situ and AsH 3 annealed
p-GaAs samples in the measureable trap energy range.
In situ deposition of A12 0 3 on GaAs was also performed by CVD with TMA and IPA
as precursors. A gallium rich region in the CVD A12 0 3 thin film above the interface was
observed in SIMS depth profile measurement. The XPS results show that the gallium rich
region consists of the A120 3 and Ga 2O 3, but no As 20
3
was observed due to the
self-cleaning effect. The analysis supports the proposed chemical reaction mechanism
and suggests the existence of the Ga 2O 3- A12 0 3 mixed region above the A12 0 3/GaAs
interface helps to reduce the frequency dispersion of the C-V characteristics and lower
the interfacial defect density.
Following the experiments, the Dit energy distributions of A120 3/p-GaAs interfaces
of different processes were determined by the conductance frequency method with
temperature-variation C-V measurements. The Dit near the valence band edge of in situ
ALD sample is the lowest among the processes discussed in chapter 4, 5, and 6. However,
there is a very large mid-gap defect state exists for in situ ALD sample. The Dit of other
processes near the mid-gap is lower compared to the in situ ALD sample. Introducing Ga
near the interface appears to lower mid-gap defect states. CVD growth or CVD growth
161
plus a TMG pre-layer both reduce mid-gap defect trap density From the C-V simulations,
these mid-gap defect states are acceptor-like (electron trap) and are the major source of
high frequency dispersion in n-type samples.
Finally, the relation between the interfacial defect state distribution and the
processes are correlated. The in situ ALD process helps to passivate the dangling bonds
of surface arsenic atoms; however, the As-As anti-bonding
and Ga 2O 3-free interface
would result in a high density of acceptor-like defect states near the conduction
band-edge and mid-gap of GaAs band-gap, respectively. In situ CVD or ex situ ALD
process both result in the passivation of surface arsenic or surface gallium atoms. The
density of mid-gap defect states, as we mentioned previously, is lower due to the
existence of Ga 2O 3 near the interface.
With the knowledge generated from this thesis, we have a guide to improve the
interfacial quality of oxide/GaAs interface in the future experiments. In order to achieve
low Di at the oxide/GaAs interface, the dangling bonds of surface gallium or arsenic
atoms should be passivated as much as possible to lower the defect state near the valence
or conduction band edges and the Ga 2 O 3 should be incorporated into the interface to
lower the mid-gap defect state. This can be achieved by following proposed method.Jn
situ deposit A12 0 3 with ZnO to form Al(Zn)O mixed-oxide by CVD mode with TMA,
DMZn,and IPA as precursors in our MOCVD system. Since the lattice constant of the
oxide can be changed by mixing two (or even three) oxides, the optimal composition of
the oxide can be tuned to let as many as the dangling bonds of surface atoms be
passivated by the mixed-oxide. This could also incorporate the Ga 2O 3 automatically into
the oxide at the interface. Of note, the best way to do this is by using the TMG and TMA
with IPA to deposit the AI(Ga)O mix-oxide by CVD mode. Unfortunately, TMG can not
162
react with IPA to deposit Ga 2O 3 in our MOCVD system.
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