A Wirelessly Powered System with Charge Recovery Logic
∗
†
∗
Leo Filippini , Emre Salman , Baris Taskin
University,
†Stony
Brook University
Introduction
TABLE I
inverter chain power consumption
= 0.2
= 0.4
= 0.6
= 0.8
=1
f
WP-ECRL
CMOS
NTV-CMOS
(nW)
(nW)
(nW)
10
58
732
52
12.6×
0.9×
50
174
2814
231
16.2×
1.3×
100
333
5417
457
16.3×
1.4×
500
1677
26240
—
15.7×
—
1000
3446
52270
—
15.2×
—
(MHz)
100
Average
VDD
CMOS
NTV-CMOS
(Normalized to WP-ECRL)
15.2×
1.8
1.2×
10−1
Non ideal condition
102
CMOS
gnd
(a) A typical wirelessly powered system built with an inductive link power
supply, and CMOS as the logic component
CRL
103
Frequency (MHz)
104
0.5
Simulation of proposed system
k1
Figure 1: Differences between CMOS and the proposed solution.
k2
RS
φ2
k
k
k
k
0.2
Time (µs)
0.3
101
102
0.95
0.4
φ4
0.9
64
256
0.85
10−1
100
101
102
Q
60
I2
Figure 2: The schematic of the proposed wirelessly powered system. The
dashed line separates the power source, on the left, from the low-power
circuit, on the right side. RL and CL represent the equivalent circuit of
the CRL, RS the parasitic resistance of inductor L2, and φ the power clock.
The circuit of Figure 2 can be solved in the Laplace domain,
bringing the expression for the voltage of inductor L2
r
L2
k(sCLRL + 1)
VL2 = VS
· 2
.
(1)
2
L1 s L2CL(1 − k ) + sCLRL + 1
Equation (1) can be rewritten assuming L1 = L2 and also
f 1/2πL2CL(1 − k 2) to get
(2)
φ1
φ2
φ3
φ4
Power (nW)
VS
VS0
VL2 = kVS .
0.1
Figure 5: The 64th output of the inverter chain of the system of Figure 4
with k1 = k2 = k, 100 nH inductors, and VS = 1 V at 10 MHz with 100 %
activity factor. For k = 0.8, k = 0.6, and k = 0.4 the output swing is
reduced to 0.4 V, 0.3 V, and 0.2 V, respectively.
CL
medium
100
100
1
= 0.4
= 0.6
= 0.8
=1
φ
L2
101
Figure 7: Parasitic series resistance RS and normalized power consumption
for different values of Q when the system operates at 1 GHz. The power is
normalized over the case when Q = ∞.
0
φ3
RL
L1
1.2
Q
0
VS0
VS
1.4
10−1
φ1
ECRL logic
102
1
VS
Theoretical Analysis
RS
Power
-0.5
M
1.6
Figure 3: L1 = L2 = 100 nH, CL = 10 fF, RL = 100 Ω, RS = 0, and
VS = 1 V. Note that
√for decreasing k the resonance frequency of the system
gets closer to 1/2π L2CL ≈ 5 GHz. Moreover, as expected, VL2 ≈ kVS
for frequencies well below the resonance.
(b) The proposed solution uses charge recovery logic, or CRL
I1
103
|φ1| (V)
Regulator
Out 64 (V)
Rectifier
104
2
Normalized Power
101
|VL2| (V)
Low power is important in every electronic system. Some applications, e.g. bio-implantable devices, not only have a strict
power budget but also require wireless power delivery. Although static CMOS logic can be successfully used for such
tasks, its main disadvantage is that it operates with a DC
voltage. A rectifier and regulator are necessary to convert the
wirelessly delivered AC power to DC, and even assuming an
ideal wireless link, the conversion stage leads to a energy loss.
Charge recovery logic, or CRL, can be used to overcome the
limitations of CMOS.
k
k
k
k
k
In order to evaluate the parasitics of actual inductors, a series
resistance RS is added to each inductor of Figure 4, hence
the quality factor Q of the coils is defined by the well known
equation
Q = ωL/RS .
(3)
40
Conclusions
20
1
0.8
1
Figure 4: An implementation of the proposed solution, using the ECRL
logic family. This system, coined WP-ECRL, is used during the simulation.
The voltage supplies VS and VS0 are 90◦ out of phase and have a dedicated
RF link each. The two inductors on the right side of each link are configured
such that their voltages are 180◦ out of phase, thus providing the four power
clocks suitable for ECRL. For the sake of simplicity, a 64 stage inverter
chain is used as a logic load for the system (the ECRL logic block).
Figure 8: Magnitude of the power clock φ1 for different number of inverters
as load, when the system operates at 1 GHz.
0.8
0.6
0.6
k2
0.4
0.4
0.2
0 0
0.2
k1
Figure 6: Power dissipated by the WP-ECRL system of Figure 4 with
100 nH inductors and VS = 1 V at 10 MHz with 100 % activity factor, under
variation of the coupling coefficients k1 and k2. For coupling coefficients
lower than 0.4, the system loses its functionality.
Conversion Loss
Rectifier/Regulator
Load Independence
Link Independence
Q Independence
CMOS
WP-ECRL
≈ 20 %
Yes
No
No
No
0%
No
Yes
Yes
Yes
RS (Ω)
∗Drexel