1
A Transformerless PCB Based Medium-Voltage
Multilevel Power Converter with a DC Capacitor
Balancing Circuit
Luke A. Solomon, Member, IEEE, Alfred Permuy, Nicholas D. Benavides, Member, IEEE, Daniel F.
Opila, Member, IEEE, Christopher J. Lee, Member, IEEE, and Gregory F. Reed, Member, IEEE
Abstract—This paper presents a new method of constructing a
transformerless, voltage-sourced, medium-voltage multilevel converter using existing discrete power semiconductor devices and
printed circuit board technology. While the approach is general,
it is particularly well-suited for medium-voltage converters and
motor-drives in the 4.16 kV, 500 - 1000 kW range. A novel way
of visualizing the power stage topology is developed which allows
simplified mechanical layouts while managing the commutation
paths. Using so many discrete devices typically drives cost and
complexity of the gate drive system including its control and
isolation; a gate-drive circuit is presented to address this problem.
As with most multilevel topologies, the dc-link voltages must
be balanced during operation. This is accomplished using an
auxiliary circuit made up of the same power stage and an
associated control algorithm. Experimental results are presented
for a 4.16 kV, 746 kW, five-level power converter prototype.
Index Terms—Inverters, Motor drives, Power conversion, Pulse
width modulation converters, Variable Speed drives.
I. I NTRODUCTION
M
EDIUM-VOLTAGE motor-drives are a workhorse in
the power electronics industry with revenues exceeding
$2.72 billion in 2013, of which applications at or below
3 MW make up 52% [1]. This market segment demands
a cost effective, transformerless and bi-directional multilevel
converter that minimizes dv/dt and common-mode voltage
system stresses while continuing to meet high power quality
requirements [2], [3].
Many multilevel converter topologies can be used without a transformer including the neutral-point-clamped (NPC)
[4], active neutral-point-clamped (ANPC) [5], neutral-pointpiloted (NPP) [6], capacitor-clamped [7], generalized multilevel inverter topology [8], and modular multilevel converter
(MMC) [9]–[14] topologies. These topologies require external
filtering to both interface properly with the ac systems and
to sufficiently choke unwanted high frequency common-mode
currents. If these filtering requirements are met, transformer
isolation is not required in many applications. Others topologies like the “cascaded multicell with separate dc sources” [15]
use a multi-winding transformer and diode rectifier to maintain
the dc voltage levels, with the drawbacks of unidirectional
power flow and the transformer cost and size.
Most medium-voltage drives are constructed using packaged “semiconductor modules.” A semiconductor module is
a device which contains more than one semiconductor die
arranged in a common housing to achieve a specific voltage
and current rating from the module [16]. Thus semiconductor module manufacturers address the challenges associated
with networking multiple semiconductor devices rather than
converter designers.
This paper presents a fundamentally different approach to
constructing power converters in this medium-voltage, low
power class: using the discrete semiconductor devices that
comprise 70% of the power semiconductor market [17]. This
paper uses Transistor Outline (TO) and Diode Outline (DO)
247 package discrete devices [18], [19] in conjunction with
widespread printed-circuit board (PCB) technology to leverage
economies of scale compared to converters built with semiconductor modules. It also enables the use of standard automated
PCB manufacturing and test techniques for the entire converter
system. This level of manufacturing and inspection automation
is traditionally not possible for converter systems comprised
of semiconductor modules.
New developments in three areas enable the construction of
converters of this type: the topology arrangement, gate drive,
and dc-link capacitor voltage balancing. The first contribution is a novel way of visualizing and arranging the power
stage topology that allows for simplified mechanical layouts
while minimizing the commutation loop inductances [20]. This
topology “unwrapping” technique enables the separation of
a power stage into subcircuits where all non-zero current
commutation events are contained within the subcircuit. These
subcircuits can then be physically separated to address practical converter design issues.
The gate drive circuit requires a cost-effective isolation
scheme for the large number of semiconductor devices and
must be precisely synchronized to allow the use of seriesconnected devices. Typical methods for isolation use a costly
isolated power supply and fiber optic connection for each
device instance [21], [22]. Several methods are available
for driving series connected devices using gate side control
including synchronization [23], [24] and active voltage control
[21], [22], [25], but they are rather complex for large numbers
of devices, especially when each device requires individual optical isolation. A magnetically-coupled, current-sourced gatedrive system [26] is presented that significantly reduces the
cost and complexity of meeting both requirements.
Transformerless multilevel converter applications typically
require a voltage balancing scheme because the instantaneous
current distribution causes unequal charging and discharging among the dc-link capacitors. NPC, ANPC, NPP, and
2
capacitor-clamped topologies with four or more levels all have
a dc-link capacitor voltage imbalance problem due to unequal
current flows in the dc-link capacitors for all desired operating
points [7].
Balancing may be achieved by imposing a specific control
scheme on all power stages common to the dc-link; however, this requires complex space-vector modulation (SVM)
schemes or common-mode injection techniques, puts several
operational constraints on the common dc-link power stages
[27]–[35] and produces unwanted common-mode voltage
stresses on the motor [3] which is particularly undesirable for
motor retrofit applications where the motor insulation rating
with respect to ground may not be sufficient.
Several active balancing circuits and algorithms have been
proposed [28], [36]–[44]; however, none of the proposed
balancing circuits make use of the same topology used in
the converter power stage. An active balancing circuit and
algorithm is developed to transfer charge between all dc-link
capacitors and allow for a larger operational space for all
common dc-link power stages [45]. This circuit is identical
to the converter power stage, simplifying manufacturing, test,
and maintenance.
To demonstrate the proposed approach, a three-phase induction motor-drive application is studied. Experimental results
are presented for a 4.16 kV, 746 kW prototype in a back-toback configuration.
This paper is organized as follows: First, the concept
of unwrapping the power stage circuit and its mechanical
arrangement on a PCB is presented in Sec. II. The gatedrive circuit is presented in Sec. III, and dc-link capacitor
balancing in Sec. IV. Next, a three-phase induction motordrive application and its dc-link voltage imbalance signature
are presented in Sec. V. Implementation details of the fully
rated prototype are presented in Sec. VI. Finally, experimental
results are presented in Sec. VII.
II. P OWER S TAGE T OPOLOGIES AND C IRCUIT
U NWRAPPING FOR AN N-L EVEL M ULTILEVEL C ONVERTER
A key enabler for the medium-voltage use of discrete power
semiconductor devices soldered to a PCB is an exploitation
of the arrangement of the topology [46]. This topology “unwrapping” and mechanical arrangement scheme provides two
major advantages: it reduces commutation loop inductance,
and it can be exploited to create an active dc-link capacitor
balancing circuit using the same power bridge as discussed in
Sec. IV. The unwrapped arrangement is applicable to all NPC
topologies including classic NPC [4], ANPC [5], and NPP [6]
multilevel converter topologies.
The unwrapping scheme is presented first using the threelevel NPP bridge and then the five-level NPP bridge which is
the focus of the remainder of the paper. The three-level NPC
bridge is shown in the Appendix to demonstrate applicability
to both topologies.
A. Topology Unwrap for Three-Level NPP Converter
The three-level NPP bridge is illustrated in its usual
“wrapped” configuration in Fig. 1a and shown with commutation loop definitions. With this traditional depiction of the
topology, all switches and their corresponding freewheeling
diodes are grouped together in an antiparallel arrangement. A
single bridge can function as a bi-directional ac/dc or dc/ac
converter, therefore each dc and ac terminal can serve as an
input or output for the converter. The dc and ac connection
terminals are labeled in Fig. 1 as “DC” and “AC” respectively. The dc terminals contain a suffix that further identifies
the terminal level on the dc link.
The bridges in Fig. 1 are shown with one device for
each capacitor voltage the device must block during normal
converter operation. For example, the circuit branch connected
directly to the +1 capacitor node contains exactly two devices
because the branch will block exactly two capacitor voltages
when the converter output is driven to the -1 capacitor node.
It is possible to “unwrap” the circuit by grouping devices
into two subcircuits, with one carrying current into the dc-link
and one carrying current out of the dc-link. The output of the
two subcircuits are then connected together to create the output
terminal of a single-phase power stage. Fig. 1b illustrates
the single-phase, three-level NPP topology unwrapped into
two subcircuits shown with commutation loop definitions.
All circuit nodes are not preserved when the topology is
unwrapped such as the (QCA, QCB, DCA, DCB) node shown
in Fig. 1a. However, this does not change the switching
behavior because the stage does not require these nodes for
operation.
The bridge is operated to move the output node to any one of
three states: +1, 0, −1. Commutation events considered valid
are: moving in either direction between states −1 and 0, and
between states 0 and +1. From this analysis, one can see
that all non-zero current commutation events occur within a
single subcircuit. Moving between states −1 and +1 for both
current into and out of the dc-link are possible commutation
events that would not leave their respective subcircuits, but the
bridge is typically not operated this way in medium-voltage
converters to minimize the dv/dt stress in the system and is
therefore not illustrated in Fig. 1.
B. Reduced commutation inductance
The unwrapping technique allows for reduced commutation
inductance compared to the traditional antiparallel arrangement which is desirable to minimize the voltage overshoot on
the devices during turn-off events [47]. A power stage layout
for the antiparallel arrangement must consider commutation
loops with both switches and diodes for events with current
flowing into and out of the dc capacitors. In contrast, the
commutation loops in the unwrapped design contain only
switches or diodes, meaning each commutation loop contains
half as many devices. Typically each semiconductor die and
heat sink pair are the same size for either diodes or switches,
so half as many devices implies half the physical space. As
the commutation loop inductance is primarily a function of
the physical area of the loop, separating the loops translates
to a lower total inductance for each of the commutation paths.
The commutation loop inductances of the unwrapped mechanical arrangement can be minimized by properly arranging
the components within subcircuit 1 and subcircuit 2 independently, with outputs connected together to create a single
3
Heatsink Footprint
C
Heatsink Footprint
C
`
Q1
B
out of
dc link
Q2
Q1
B
Q2
A
2A
DC +1
D2
D1
D1
D2
0:+1 Commutation loop for
currents flowing into and out
of the dc link
QCA
QCB
DCA
DCB
0:+1 Commutation loop for
current into the dc link
D
DC +1
0:+1 Commutation loop for
current out of the dc link
out of
dc link
QCA
0:-1 Commutation loop for
currents flowing into and out
of the dc link
Q1
AC
QCB
DCA
DCB
DC 0
0:-1 Commutation loop for
current into the dc link
Q2
DC 0
AC
0:-1 Commutation loop for
current out of the dc link
out of
dc link
Q1
Q2
DC -1
D1
D1
D
D2
Sub-Circuit 1
(a) Classical antiparallel arrangement.
DC -1
D2
Sub-Circuit 2
(b) Unwrapped arrangement.
Fig. 1. Classic and unwrapped three-level NPP topology shown with commutation loop definitions and heat sink outlines. The unwrapped topology is
functionally identical but arranged into two subcircuits; subcircuit 1 conducts current into the dc link and subcircuit 2 conducts current out of the dc link.
Commutation paths in the unwrapped version stay within their respective subcircuits and do not cross between them for non-zero current events.
phase bridge. The adjacency of each commutation loop in the
unwrapped version ensures that the voltage between heat sinks
is equally distributed across the board, which is not true for
traditional ANPC or NPC layouts. This minimizes the distance
required between heat sinks to support the voltage isolation
requirement, further reducing the inductance. Minimizing the
inductance between the two subcircuit boards is not of great
importance because all non-zero current commutation events
will occur strictly within one of the two subcircuit boards.
When using PCB construction at the proposed voltages the
designer is limited to a layout with locally small voltage
differential around any PCB feature that crosses layers such as
through-hole pads or vias. If more than two layers were used,
the large creepage and clearance distances required to maintain
voltage isolation would make the system impractical. The main
voltage isolation method uses in-plane distance across the PCB
surface.
The reduction in commutation inductance can be approximated by calculating the loop area for the two layouts. The
devices in Fig. 1 are shown with their corresponding heat
sink outlines. The distance C between adjacent heat sinks in
a series connected string of devices is calculated based on
the amount of voltage isolation required between them. In a
series connected string of devices, each heat sink can only be
a maximum of a single device voltage rating away from each
other, so the device voltage rating defines this distance C.
Each dc link capacitor level −1, 0, +1 in Fig. 1 has a
corresponding circuit branch containing a row of heat sinks for
the entire series connected string of devices. The distance D
between any heat sink row and any of its directly neighboring
rows is determined by the required functional isolation for a
single dc link capacitor voltage.
All semiconductor devices require approximately the same
heat sink surface area to meet the cooling requirements
whether they are arranged classically or unwrapped. In Fig.
1b, each semiconductor device heat sink (IGBT or diode) has
width B and length A. In Fig. 1a, each heat sink has width
B but length 2A to cool both the IGBT and diode.
If no other geometric restrictions are assumed in the circuit
layouts, we can calculate the approximate commutation loop
area for both the classic arrangement Aclassic and the unwrapped arrangement Aunwrapped by assuming current flows
through the middle of the device as
Aclassic = (2B + C)(2A + D)
(1)
Aunwrapped = (2B + C)(A + D).
(2)
The mechanical dimensions A, B, C, and D are the same
across both the classic and unwrapped arrangements assuming
the same voltage rating and semiconductor cooling. Given that
these dimensions are all positive, it is possible to reduce the
commutation loop area and therefore the commutation loop
inductance with the topology unwrapping scheme presented
in this section.
Additionally, when the number of levels of the NPC or
ANPC toplogy in antiparallel configuration is increased beyond three, several of the connection paths must cross and
managing voltage isolation of these connection paths with a
two-layer bus structure becomes difficult due to the creepage
and clearance distance requirements. The unwrapped NPC
topology with more than three levels removes all connection
path crossings and enables a PCB layout with reasonable
spacing. This is not an issue with NPP.
C. Topology Unwrap for Five-Level NPP Converter
Fig. 2 illustrates the five-level NPP bridge shown in classical
antiparallel arrangement Fig. 2a and unwrapped Fig. 2b with
a single device rating per voltage level. This is the topology
chosen for implementation and it is the focus of the remainder
of this paper.
4
DC +2
AC
DC +2
AC
DC +1
DC +1
DC 0
DC 0
DC -1
DC -1
DC -2
DC -2
(a) Classical antiparallel arrangement.
(b) Unwrapped arrangement.
Fig. 2. Classic and unwrapped five-level NPP topology shown without commutation loops. The unwrapped version is functionally identical.
III. IGBT G ATE -D RIVE
A medium-voltage converter constructed as proposed requires the use of a gate-drive system that is low-cost, highly
synchronized, and capable of overdriving the gates.
Each switching device or device group requires an isolated
gate-drive. A large number of these gate drives may be
required depending on the individual device rating, number
of voltage levels in the power stage, and the overall voltage
rating of the system. Traditional isolated gate-drive systems
for series connected semiconductor modules make use of a
costly isolated power supply and fiber optic connection for
each device instance [48], driving the need for a low cost
alternative.
When using series connected devices, the gate-drive system
must be carefully designed to manage voltage imbalance
during turn-on and turn-off events. The system must be
tightly synchronized and overdrive the gates to account for
any mismatch in the physical characteristics of the power
semiconductors [49]. Methods for driving series connected
devices using gate side control include synchronization [23],
[24] and active voltage control [21], [22], [25] techniques.
These techniques are not well suited for this application due
to high cost and complexity.
A magnetically-coupled, current-sourced gate-drive system
[26] can be used to achieve all technical requirements while
minimizing cost and complexity, as illustrated in Fig. 3. The
gate-drive system for k devices in series is comprised of a
micro-controller unit (MCU) to create turn-on and turn-off
logic signals, a pulse amplifier circuit to create positive and
negative current pulses, a pulse transformer string, and the
pulse receivers that drive each gate.
A. Pulse Amplifier
The pulse amplifier level shifts, inverts, and buffers the
MCU gate signals so they can drive a MOSFET H-bridge that
creates current pulses. The pulse amplifier is a series of bipolar
junction transistor amplifier stages cascaded together as shown
in Fig. 4. The first stage of the pulse amplifier is a common
base stage shown in (a) of Fig. 4. This stage is driven by
MCU
Pulse
Amplifier
.
.
.
.
.
.
Pulse
Receiver 1
Device 1
Pulse
Receiver 2
Device 2
.
.
.
.
.
.
Pulse
Receiver k
Device k
Fig. 3. Magnetically coupled, current-sourced, gate-oxide insulated device
gate drive system for k devices in series commanded by a micro-controller
unit (MCU). The Pulse Amplifier is detailed in Fig. 4 and the Pulse Receiver
in Fig. 5.
a MCU digital output to level shift the voltage signals from
MCU voltage levels to H-bridge voltage levels. The second
stage in the pulse amplifier is a common-emitter amplifier
shown in (b) of Fig. 4. The common-emitter amplifier refers
the output voltage of the common-base amplifier to the opposite power rail. The third stage of the pulse amplifier is an
emitter-follower amplifier shown in (c) of Fig. 4. This stage is
used to reduce the effective gating resistance of the MOSFET
devices in the H-bridge to achieve adequate switching times
while minimizing switching loss in the H-bridge.
The MOSFET H-bridge is controlled to set up turn-on and
turn-off current pulses on a network of pulse transformers for
the power stage semiconductor devices. The primary windings
of each pulse transformer are wired in series to ensure that
the current pulses reflected to the secondary of each pulse
transformer are identical. This enables the series connected
devices within a device group to synchronously gate and
ensure each device will share voltage evenly during the turn-on
and turn-off events.
5
Logic Signal Reference Voltage
Amplifier Power Voltage +
H-Bridge Voltage +
MCU
Digital
Output
A
Pulse Transformer 1
.
.
Pulse Transformer 2
Pulse Transformer k
MCU
Digital
Output
B
H-Bridge Voltage (a)
(b)
(c)
Amplifier Power Voltage -
Fig. 4. Gate pulse amplifier circuit shown for a single device group. The pulse amplifier network processes signals generated from the MCU to create the
gate current pulses. This circuit forms the “Pulse Amplifier” shown in Fig. 3.
Qp
Qn
Device
Dz
Fig. 5. The pulse receiver network shown for a single gate-emitter instance
of the many pulse receivers in Fig. 3. This network receives the gate
current pulses from the pulse transformer system and sets up and latches
the appropriate turn-on or turn-off gate-emitter voltages.
B. Pulse Receiver
Each power stage semiconductor device or parallel device
group has an associated pulse receiver. The pulse receiver
receives the commanded current pulse, sets up the appropriate
gate voltage, and latches the commanded gate voltage of the
device, as illustrated in Fig. 5. The pulse receiver consists of
MOSFETs and zener diodes that form a synchronous rectifier.
This circuit rectifies a turn-on (positive) current pulse to
establish a positive gate voltage when a positive voltage is
applied to the pulse transformer secondary, and a negative
gate voltage for a negative current pulse. During a turn-on
current pulse, Qn is not conducting and Qp conducts until the
current pulse decays to zero. At this time, the gate voltage has
reached the appropriate turn-on level set by the bidirectional
zener diode Dz avalanche voltage. After the current pulse
decays to zero, Qp stops conducting and there is no longer
a path for current to flow into or out of the gate of the device,
therefore the gate is latched on. The process is similar but
opposite during a turn-off current pulse. Fig. 6 illustrates a
scope capture of the synchronized gate to emitter voltage of
two series connected IGBTs during a turn-on and turn-off
event along with the corresponding pulse amplifier MOSFET
H-bridge output voltage and current.
The latched gate voltage of the device falls over time due
to leakage current in the device gate-oxide layer and the
pulse receiver. The power semiconductor device gate must be
periodically refreshed on and off often enough to keep the gate
voltage from significantly deviating from the desired on-state
or off-state voltage. These refresh on and off current pulses
are of the same polarity as their corresponding turn-on and
turn-off pulses, but they can be shorter in duration.
To achieve a current-sourced gate-drive and reliably overdrive the devices, the pulse transformer turns ratio must be set
so that the back electromotive force reflected from the device
gates to the H-bridge is small compared to the H-bridge supply
voltage. Galvanic isolation between the pulse transformer
primary and secondary windings is achieved by using highvoltage silicon jacketed wire for the primary winding as shown
in Fig. 7.
IV. DC-L INK C APACITOR BALANCER T OPOLOGY AND
C ONTROL A LGORITHM
As discussed in the introduction, transformerless multilevel
converter applications typically require a voltage balancing
scheme because the current distribution causes unequal charging and discharging among the dc-link capacitors. This section
introduces a dedicated balancing circuit to maintain dc voltage
balancing, with a control algorithm that minimizes the need
for any drive-system level information.
A dedicated balancing circuit is usually undesirable because
of the additional complexity of a new circuit. However, the
unwrapped topology enables the balancing circuit to use the
same power circuit as the phase leg, simplifying the system
and reducing the number of distinct spare modules which must
be maintained by an end user.
This section will describe the construction of the balancing
circuit along with its modeling and control, while sizing
considerations are left to the next section.
10
0
IGBT1 GE Voltage
IGBT2 GE Voltage
H Bridge Voltage (V)
0.2
0.4
0.6
0.8
1
1.2
1.4
Time (µs)
1.6
30
25
20
15
10
5
0
−5
1.8
2
H Bridge Voltage
H Bridge Current
0.2
0.4
0.6
0.8
1
1.2
1.4
Time (µs)
1.6
1.8
2
0
−10
−20
2.2
30
25
20
15
10
5
0
−5
2.2
(a) Turn-on event waveforms.
H Bridge Voltage (V)
−10
IGBT1 GE Voltage
IGBT2 GE Voltage
10
0.2
0.4
0.6
0.8
1
Time (µs)
1.2
0
−5
−10
−15
−20
−25
−30
1.4
1.6
H Bridge Voltage
H Bridge Current
0.2
0.4
0.6
0.8
1
Time (µs)
1.2
1.4
0
−5
−10
−15
−20
−25
−30
H Bridge Current (A)
IGBT Gate Voltage (V)
20
H Bridge Current (A)
IGBT Gate Voltage (V)
6
1.6
(b) Turn-off event waveforms.
Fig. 6. Gate to emitter voltage waveforms of two series connected IGBTs along with the corresponding pulse amplifier H-bridge voltage and current waveforms
for a turn-on and turn-off event.
Charger Terminal
I reactor (t )
Discharger Terminal
DC +2
DC +1
DC 0
DC -1
DC -2
Fig. 8. Five-level NPP balancing circuit shown with balancing reactor.
Fig. 7. Pulse transformer primary winding shown with three secondary
windings.
A. Topology
A dc-link capacitor balancing circuit may be created for
an N -level converter by exploiting any unwrapped N -level
topology. If the outputs of subcircuit 1 and subcircuit 2 shown
in Fig. 1b are split and a reactor is inserted between the two
outputs, subcircuit 1 can be used to inject charge into all dclink capacitors that have low voltages and subcircuit 2 can be
used to withdraw charge from all dc-link capacitors that have
high voltages. For the five-level NPP topology the balancing
circuit with the balancing reactor is shown in Fig. 8.
B. Algorithm
A simple dc-link voltage balancing control algorithm is
designed such that all required feedback is calculated in analog
circuitry, and all required comparisons are presented to the
controller as digital signals. This simplifies running multiple
synchronized controllers for increased speed and reliability.
For the purposes of quantifying the control algorithm, it
is useful to depict the balancing circuit using a multi-pole,
ideal switch model as shown in Fig. 9. A dc bias current is
established in the balancing reactor which provides an energy
buffer used to shuttle charge between all dc-link capacitors in
both directions.
If the balancing reactor inductance is large enough, the
control can be greatly simplified by running the charging and
discharging control laws independently. A finite state machine
control law for balancing the dc-link of an N -level converter
is shown for both the charging and discharging subcircuits in
Fig. 10.
There are two nested control loops in each state machine.
The primary control loop regulates reactor current Ireactor to
a nominal value Inom within bands set by Imin and Imax .
The secondary loop uses this reactor current to inject and
7
State
Charger
N
Start
If (Ireactor>Inom)
State
Charger
N-1
If (d2VCN-2/dx2<0)
or
(Ireactor<Imax) or (Ireactor>Imin)
and
(previousState=N)
State
Charger
N-2
If (d2VCN-3/dx2<0)
or
(Ireactor<Imax) or (Ireactor>Imin)
and
(previousState=N-1)
.
.
.
State
Charger
2
If (d2VC1/dx2<0)
or
(Ireactor<Imax) or (Ireactor>Imin)
and
(previousState=3)
Start
If (d2VCN-2/dx2<0)
or
(Ireactor<Imax) or (Ireactor>Imin)
and
(previousState=N-2)
State
Discharger
1
If (Ireactor<Inom)
If (d2VCN-3/dx2<0)
or
(Ireactor<Imax) or (Ireactor>Imin)
and
(previousState=N-3)
If (d2VC1/dx2>0)
or
(Ireactor<Imax) or (Ireactor>Imin)
and
(previousState=1)
If (d2VC1/dx2<0)
or
(Ireactor<Imax) or (Ireactor>Imin)
and
(previousState=1)
If (d2VCN-3/dx2>0)
or
(Ireactor<Imax) or (Ireactor>Imin)
and
(previousState=N-3)
If (d2VCN-2/dx2>0)
or
(Ireactor<Imax) or (Ireactor>Imin)
and
(previousState=N-2)
If (Ireactor<Inom)
State
Charger
1
(a) Charger state machine.
State
Discharger
2
.
.
.
State
Discharger
N-2
State
Discharger
N-1
If (d2VC1/dx2>0)
or
(Ireactor<Imax) or (Ireactor>Imin)
(previousState=3)
If (d2VCN-3/dx2>0)
or
(Ireactor<Imax) or (Ireactor>Imin)
and
(previousState=N-1)
If (d2VCN-2/dx2>0)
or
(Ireactor<Imax) or (Ireactor>Imin)
and
(previousState=N)
If (Ireactor>Inom)
State
Discharger
N
(b) Discharger state machine.
Fig. 10. DC-link capacitor charger and discharger subcircuit control law state machines.
In this control scheme, a particular capacitor’s charge is
defined as balanced if its second difference equation with
respect to its two neighboring capacitors as given in (3) is zero.
When the discharger state machine considers a particular node,
current is withdrawn from the node until the second difference
is positive. Similarly, when the charger state machine considers
a particular node, current is injected into the node until the
second difference is negative. On an average basis, this control
scheme ensures that all capacitor voltages remain equal by
actively driving this second difference to zero. The total time
required to sweep through a complete state machine cycle
is proportional to the ratio of the average current deviation
divided by the Inom setpoint. When this ratio is low, the
state machine can cycle very quickly and cause unmanageable
switching losses in the devices. A wait state (not shown) is
inserted in each state machine to enforce a minimum total
cycle time. The wait states are configured to be freewheeling,
zero volt conditions on the reactor so that the energy stored
in the reactor remains constant when it is not required for
balancing.
I reactor (t )
L
NodeN-1
+
IN-1
VN-1
CN-1
-
.
.
.
Node3
C3

State Discharge 4
State Discharge 3

State Charge N
VC 3
Node2
State Charge 4
.
.
IC 3
State Discharge N
.
.
State Charge 3
State Discharge 2
State Charge 2
State Discharge 1
IC 2

C2
State Charge 1
VC 2

Node1
I C1
C1

VC1

Node0
V. C OMMON DC-L INK T HREE P HASE T OPOLOGY FOR
M OTOR D RIVE A PPLICATIONS
Fig. 9. Multi-pole, ideal switch model of the N -level balancing circuit.
withdrawal charge from a particular node to equalize all of the
dc-link capacitor voltages. In order to determine if a particular
node requires charging or discharging, the second difference
equation fN ode x of the voltages for nodes 1 through N − 2 is
calculated as follows:
fN ode 1 = VN ode0 − 2VN ode1 + VN ode2
fN ode 2 = VN ode1 − 2VN ode2 + VN ode3
fN ode N −2 = VN odeN −3 − 2VN odeN −2 + VN odeN −1
(3)
A. Schematic and Rating
A prototype motor-drive system was created by connecting
two, three-phase, five-level NPP bridges with a common dclink as illustrated in Fig. 11. The system is illustrated with a
single device’s voltage rating per dc-link level. These devices
represent a device group of series and parallel devices that
switch together. The voltage rating of the bridge can be
increased by two methods: adding series devices to each device
group to increase its rating, or by adding more voltage levels
to the converter while keeping each dc-link level constant.
8
Va
Vu
Vb
Vv
Vc
Vw
Fig. 11. Six, five-level NPP bridges connected with a common dc-link to form the power stages of a three-phase motor-drive. The bridges are shown with
one device per level to represent each switch group. The six ac terminals are labeled Va , Vb , Vc for the front-end, and Vu , Vv , Vw for the back-end.
B. Sizing of the Balancer Circuit
1) Current flow into the power bridges: During operation,
the front-end (line-side) and back-end (load-side) bridges will
draw current from the dc-link levels unevenly, both instantaneously and on average. The short term imbalance within
one power cycle is dealt with by using sufficient dc-link
capacitance to avoid significant voltage ripple at the power
frequency.
Even with such a design criterion, the average current drawn
from each capacitor level during one power cycle has a nonzero component. To analyze the sizing requirements for the
balancing circuit, consider the case of constant but different
operating points for the front- and back-ends. Under these
conditions, a dc current source is used to represent the average
current flow out of each level, as shown in Fig. 12.
First assume both front-end and back-end bridges have
balanced three-phase currents and modulation with front-end
frequency ωF E and back-end frequency ωBE , and use fivelevel, sine-triangle, in-phase disposition modulation schemes.
With these assumptions, the modulation references M for each
phase can be defined as
Ma (ωF E t) = mF E sin(ωF E t + θF E )
Mb (ωF E t) = mF E sin(ωF E t + θF E − 2π/3)
Mc (ωF E t) = mF E sin(ωF E t + θF E + 2π/3),
and back-end modulation references as
(4)
9
I FE
I FE
I FE
I FE
Level 4
Level 3
Level 1
Level 0
C4

VC 1
C3


VC 2
C2


VC 3
C1


VC 4

I BE
Level 4
I BE
Level 3
Linput_ reactor Rinput_reactor
Vsource
IAFE
VFE
Fig. 13. Positive sequence model of the front-end bridge and grid interface.
I BE
FE Vectors
Level 1
0.8
0.6
I BE
0.4
Level 0
Fig. 12.
sources.
Average current deviation model implemented using dc current
Imaginary (pu)
0.2
IFE
0
Vsource
XL input reactor * IFE
−0.2
VFE
−0.4
Rinput reactor*IFE
−0.6
Mu (ωBE t) = mBE sin(ωBE t + θBE )
Mv (ωBE t) = mBE sin(ωBE t + θBE − 2π/3)
(5)
Mw (ωBE t) = mBE sin(ωBE t + θBE + 2π/3),
−1
where the front- and back-end modulation depths are mF E
and mBE , and the front- and back-end modulation reference
angles are θF E and θBE .
Additionally, the instantaneous phase currents i can be
defined for the front-end as
ia (ωF E t) = IF E sin(ωF E t + θF E + φF E )
ib (ωF E t) = IF E sin(ωF E t + θF E + φF E − 2π/3)
(6)
ic (ωF E t) = IF E sin(ωF E t + θF E + φF E + 2π/3),
and for the back-end as
iu (ωBE t) = IBE sin(ωBE t + θBE + φBE )
iv (ωBE t) = IBE sin(ωBE t + θBE + φBE − 2π/3)
−0.8
(7)
iw (ωBE t) = IBE sin(ωBE t + θBE + φBE + 2π/3).
The front- and back-end peak current magnitudes are IF E
and IBE respectively, and the front- and back-end modulation
reference to current angles are φF E and φBE . These are the
currents directly out of the bridge and do not include any
effects from the filter.
Using the instantaneous phase currents (6) and (7) along
with the modulation references (4) and (5), we can determine
the instantaneous current flowing into each dc-link level from
both the front- and back- ends. Integrating these currents over
a cycle and summing the contributions of the three phases
yields the average currents for each dc level [50] as defined
in Fig. 12. For example, the front-end current into level 1
is IF ELevel1 . The results are shown in (8) - (17). The total
average current flow to each dc-link level is then the sum of
−0.5
0
0.5
Real (pu)
1
1.5
Fig. 14. Positive sequence vectors of the front-end bridge and grid interface
illustrated in Fig. 13
.
the front and back end contributions. Similar calculations can
be performed for converters with any number of levels. Note
that [50] contains a misprint for equations (10), (11), (14), and
(15) when modulation depth is 0 ≤ m ≤ 0.5. These equations
are shown here with the correct multiplier 3/2 for (10) & (11),
and −3/2 for (14) & (15).
2) Accounting for line filter effects: These equations (8)(17) describe dc current flows in terms of modulation and
angle of the bridge, but to study the converter it is necessary to
relate the modulation and current flow of the front- and backend bridge to the operating point at the converter terminals.
Although filter arrangements will vary on both the front-end
and back-end depending on the specific applications’ power
quality requirements, as a minimum, the front-end bridge must
interface to the grid through a filter reactor. This reactor with
its resistance is connected between the grid voltage VSource
and front-end bridge VF E for a positive-sequence mode as
illustrated in Fig. 13.
Using the quantities defined in Fig. 13, a vector diagram can
be constructed that defines the vector space as a function of the
input current magnitude and angle as shown in Fig.14. Using
this common technique, the operating point at the converter
terminals will yield the required data to calculate the average
current deviation of dc-link capacitors for different motordrive applications using (8)-(17). Other filter topologies can
be studied in a similar manner.
10
!

s 2

4mF E − 1
1
 3 I cos(φ ) · 2m π − 4m arcsin
−
FE
FE
FE
FE
IF ELevel4 = 4π
2mF E
m2F E


0
!

s 2

4mBE − 1
1
 3 I cos(φ ) · 2m π − 4m arcsin
−
BE
BE
BE
BE
IBELevel4 = 4π
2mBE
m2BE


0

!
s 2

4m
−
1
1
3

FE


IF E cos(φF E ) · − mF E π + 4mF E arcsin
+
2mF E
m2F E
IF ELevel3 = 2π

3

 mF E IF E cos(φF E )
2

!
s 2

4m
−
1
1
3

BE


IBE cos(φBE ) · − mBE π + 4mBE arcsin
+
2mBE
m2BE
IBELevel3 = 2π



 3 mBE IBE cos(φBE )
2
IF ELevel2 = 0
for 0.5 ≤ mF E ≤ 1,
(8)
for 0 ≤ mF E ≤ 0.5.
for 0.5 ≤ mBE ≤ 1,
(9)
for 0 ≤ mBE ≤ 0.5.
for 0.5 ≤ mF E ≤ 1,
(10)
for 0 ≤ mF E ≤ 0.5.
for 0.5 ≤ mBE ≤ 1,
(11)
for 0 ≤ mBE ≤ 0.5.
(12)
IBELevel2 = 0
(13)

s
!

4m2F E − 1
3
1


−
IF E cos(φF E ) · − mF E π + 4mF E arcsin
for 0.5 ≤ mF E ≤ 1,
+
2π
2mF E
m2F E
IF ELevel1 =
(14)


3

 − mF E IF E cos(φF E )
for 0 ≤ mF E ≤ 0.5.
2

s
!

4m2BE − 1
3
1


−
IBE cos(φBE ) · − mBE π + 4mBE arcsin
for 0.5 ≤ mBE ≤ 1,
+
2π
2mBE
m2BE
IBELevel1 =



 − 3 mBE IBE cos(φBE )
for 0 ≤ mBE ≤ 0.5.
2
(15)
!

s 2

4mF E − 1
1
 − 3 I cos(φ ) · 2m π − 4m arcsin
for 0.5 ≤ mF E ≤ 1,
−
FE
FE
FE
FE
(16)
IF ELevel0 =
4π
2mF E
m2F E


0
for 0 ≤ mF E ≤ 0.5.
!

s 2

4mBE − 1
1
 − 3 I cos(φ ) · 2m π − 4m arcsin
−
for 0.5 ≤ mBE ≤ 1,
BE
BE
BE
BE
IBELevel0 =
(17)
4π
2mBE
m2BE


0
for 0 ≤ mBE ≤ 0.5.
C. Induction motor-drive with constant torque voltage-current
profile
A typical motor-drive operating condition is now studied to
demonstrate the use of these calculations. For most industrial
motor-drive applications, it is desirable to hold the front-end
power factor at unity regardless of the back-end operating
points [51]. The most demanding application on the dc-link
voltage equalization is a constant torque application. The backend current is needed at 1 pu for all voltages, and the voltage
increases linearly with the back-end frequency, producing a
linear power profile [52].
The average current deviation for the constant torque motor
application was calculated using this method and is shown
in Fig. 15 in per-unit of the converter’s rated single phase,
positive sequence, ac root mean square (RMS) current. The
front-end power factor was held at unity at the converter
terminals assuming a filter as in Fig. 13, and real power flow
was determined by the control between the front-end and backend for a 746 kW, 4.16 kV motor-drive. The maximum average
current deviation of 0.42 pu occurs at a motor electrical
frequency of about 31.5 Hz.
The results illustrated in Fig.15 show that an average
current mismatch exists between the capacitors, and thus a
capacitor balancing scheme capable of balancing a dc-link
with at least 0.42 pu of current imbalance is required. For
the implementation here, a balancing circuit module was used
that is identical to the phase modules, with a rating of 1.0 pu.
11
0.5
and snubber networks will be discussed in Sec. VI-B2. Boardto-board power connectors are used along with a PCB backplane to network all common dc-link connections together for
all power stages within a system. All subcircuit components
responsible for conducting current flowing out of the dclink are grouped on one board and all subcircuit components
responsible for conducting current flowing into the dc-link
around grouped on another board, just as in the subcircuits
1 and 2 in Fig. 1b.
Capacitors 4 and 2
Capacitors 3 and 1
0.4
Average current deviation (pu)
0.3
0.2
0.1
0
−0.1
−0.2
A. Target Rating and Device Selection
−0.3
−0.4
−0.5
0
10
20
30
40
Back−end frequency (Hz)
50
60
Fig. 15. Average current deviation vs. Back-end frequency with Back-end
Modulation Depth = 1*(Back-end Frequency/60) and Back-end current = 1
pu. This figure illustrates the maximum current required for the balancer is
0.42 pu and occurs at just over half of rated speed.
This greatly simplifies design, manufacture, and repairs.
VI. I MPLEMENTATION
A prototype of the proposed converter concept was constructed using the five-level NPP topology as illustrated in
Fig. 11. The NPP topology variant was selected over the NPC
topology for three main reasons. Firstly, the NPP topology
inherently contains mechanical symmetry as each branch of
the circuit contains the same number of semiconductor devices. This mechanical symmetry translates to symmetry in the
commutation loops within the subcircuits, allowing common
snubber components to be used throughout the topology.
Secondly, the use of series connected devices inherent to
the NPP topology allows for lower switching losses compared
to the NPC topology [6].
Finally, semiconductor losses can be spread evenly in the
converter for low modulation depth, high current operating
points by taking advantage of redundant switch states using
space-vector modulation or common-mode injection techniques. This loss spreading is possible because each branch of
semiconductors conducts only if its output level is selected.
For a given modulation depth and current direction, losses
can be allocated to particular branches. This is in contrast to
the NPC topology, where certain devices must conduct for
multiple output voltages, limiting the ability to spread the
losses.
Each capacitor level was designed for a nominal voltage of
1600 V for a total dc-link voltage of 6400 V. This power stage
is appropriate for 4.16 kV motor-drive applications that are
prevalent in North and South America. An array of metallized
polypropylene film capacitors distributed throughout each
power board were used to establish the dc-link capacitance.
All required sharing-resistor networks and snubber networks
are easily implemented on the bottom of the board as surface
mount components. The requirements for the sharing resistor
The devices shown in schematics thus far each represent
a device group, a group of one or more semiconductors
operated as a single device. These groups have a voltage rating
equal to the sum of the series-connected device ratings and a
current rating equal to the sum of the parallel-connected device
ratings. Multiple device groups can then be arranged on a PCB
to achieve a medium-voltage power converter.
The base-plates of series-connected devices must be electrically isolated from each other because each operates at a
different power circuit voltage.
Devices can be effectively used in parallel by ensuring both
steady-state and dynamic current sharing [53]. Mounting parallel devices on a common heat sink provides thermal coupling
and encourages steady-state current sharing because commercially available discrete devices are designed with a negative
temperature coefficient that reduces the current through a
device with a higher junction temperature relative to cooler
devices in the parallel network. This feedback mechanism
minimizes current mismatch in the parallel device network
branches. To ensure dynamic current sharing, a geometrically
symmetrical layout of the parallel device network was used.
This symetrical layout is sufficient because the relatively high
inductance of the discrete device package coupled with the
high di/dt of medium-voltage converter commutation events
dominates the effective impedance of each device branch
within the parallel network.
Devices are available in the DO-247 and TO-247 packages
with ratings above 1200 V; however, these devices are only
available through a limited number of suppliers. The devices
chosen were 1200 V, TO-247 package IGBTs and 1200 V,
DO-247 package diodes because these device ratings are
standard in these packages and are offered by all of the major
discrete semiconductor manufacturers. In order to achieve the
appropriate voltage ratings with a 6400 V dc-link, two 1200
V devices in series were used per level. Four parallel devices
on a common heat sink were used to achieve the necessary
current rating for a 746 kW converter. Thus, in total each
device group contains eight discrete semiconductors operated
together. To produce the bridge shown in Fig. 2b requires 320
discrete devices.
B. PCB Arrangement for Medium Voltage
1) Voltage Isolation: One major design consideration is
providing appropriate voltage isolation between devices on
the PCB. One convenient way to do this is to assign each
device to its own heat sink and maintain proper creepage and
12
Fig. 16. Four parallel device PCB layout with lead forming to meet UL618005-1 creepage and clearance requirements. Note that the layout is shown
without the common heat sink to expose device pin layout details.
clearance spacing between different circuit potentials. Forcedair cooling schemes are compatible with this arrangement to
allow for different heat sink voltages while meeting device
thermal requirements. The power circuit layout was designed
using the distances defined in the UL61800-5-1 safety standard
Tables 9 and 10 [54], which is the most appropriate standard
for these voltages.
Fig. 16 illustrates a top down view of the layout of four
parallel TO-247 package IGBTs shown without the single
common heat sink. Lead forming was implemented to meet
the creepage and clearance distance requirements given in
UL61800-5-1 and to allow for a thermally optimal heat sink
design.
2) Series-Connected Power Semiconductor Devices: There
are four main device characteristics that will create voltage
imbalance associated with series-connected strings of devices:
leakage current, tail-charge, threshold voltage, and effective
input capacitance. Any mismatch in leakage current between
series-connected devices will cause the devices to not share
static blocking voltage equally in the device’s non-conducting
state. This particular mechanism for voltage imbalance is
easily addressed using a passive sharing-resistor network
connected across each semiconductor device group in the
series-connected string. An array of thick-film, 2512-package,
surface-mount sharing resistors per heat sink were implemented for the prototype. The sharing-resistor network bias
current was chosen to be ten times larger than the expected
mismatch in leakage current to ensure a voltage mismatch of
5% or less of the nominal static blocking voltage.
Any tail-charge mismatch (IGBT) or reverse-recovery
charge mismatch (diode) across series-connected devices that
clears during device turn-off events will cause an uneven
charging of the output capacitance of the devices and ultimately cause off-state voltage imbalance for the seriesconnected devices. Therefore a passive RC snubber is added
across each semiconductor device, with the capacitor sufficiently large so that a tolerable amount of voltage mismatch
is realized for the expected amount of charge mismatch.
However, large snubber capacitance increases power loss due
to dissipation of the energy stored in the capacitor during
each On/Off switching cycle. The snubber resistor is chosen
to minimize voltage overshoot during device turn-off by using
Fig. 17. Subcircuit 1 PCB shown with heat sinks.
an effective resistance value that is equal to the characteristic
impedance of the resonant tank formed between the commutation loop inductance and the parallel combination of the
device output capacitance and the snubber capacitance [47].
An array of 1812-package, surface-mount, ceramic capacitors
were used for the snubber capacitance and a series-network
of 2512-package, surface-mount, metal element type resistors
were added per heat sink for the snubber resistance to handle
the high pulsed power required.
Finally, any difference the series-connected IGBT threshold
voltage or effective input capacitance will cause the devices
to not share voltage during the initial turn-on and turn-off
edges. These differences are easily dealt with by overdriving
the devices as outlined in Sec. III. Voltage sharing during
these highly dynamic turn-on and turn-off edges is further
encouraged by the negative feedback from the collector to the
gate present in the IGBT due to the Miller capacitance [55].
The subcircuit 1 PCB with heat sinks is shown in Fig. 17;
subcircuit 2 is on a separate board.
VII. E XPERIMENTAL R ESULTS
A 746 kW, 4.16 kV prototype was constructed to demonstrate this converter scheme. Three input bridges labeled a, b, c
and three output bridges labeled u, v, w were each constructed
by connecting the outputs of subcircuit 1 and subcircuit 2
together with a wire and one balancing bridge was constructed
by connecting a 11 mH balancing reactor between the outputs
of subcircuit 1 and subcircuit 2. Three, 2 mH inductors were
placed between the outputs of each pair of input and output
modules to recirculate power from the back end to the front
end of the converter. The entire dc-link was fed from a 6400
V dc supply. A diagram of the dc fed test setup is shown in
Fig. 18.
The input modules’ modulation depth was held constant at
0.88 and output modules were controlled to circulate a 60 Hz,
1 pu (130 A) three-phase current with a constantly varying
back-end modulation reference to current angle φBE from 0
to 2π radians at a rate of 2π radians per hour. A 10 kHz, fourcarrier, sine-triangle, in-phase-disposition-modulation strategy
13
2mH
3000
300
1500
150
Va
Five-Level NPP Bridge
Five-Level NPP Bridge
Output Voltage (V)
2mH
Vu
Vb
Five-Level NPP Bridge
Five-Level NPP Bridge
Vv
Vc
Five-Level NPP Bridge
Five-Level NPP Bridge
Vw
0
0
−1500
−150
Output Voltage
Output Current
−3000
0.005
6400VDC
Output Current (A)
2mH
0.01
0.015
Time (µs)
0.02
0.025
−300
0.03
Fig. 20. Five-level NPP output voltage and current with a 6400 V total dc-link
voltage.
Balancing Reactor
Fig. 18. DC fed front-to-back test setup. The six bridges from Fig. 11
are connected to another bridge and balancing reactor to form a complete
motor-drive with balancing. To run the front-to-back test, the ac terminals
are connected with a reactive load, and the losses are fed from a dc source
connected to the dc bus.
0.05
Capacitors 4 and 2
Capacitors 3 and 1
0.04
Average current deviation (pu)
0.03
0.02
0.01
0
−0.01
−0.02
−0.03
−0.04
−0.05
0
1
2
3
4
Current angle (rad)
5
6
Fig. 19. Simulated average current deviation vs. current angle with a device
under test modulation depth of 0.88 and 2mH of inductance between each
phase module.
was implemented [56]. The capacitor balancing requirements
of this dc-fed front-to-back system topology for a constant
input bridge modulation depth of 0.88 as a function of the
current angle with respect to the input bridge modulation
reference were simulated and are shown in Fig. 19 to be always
less than 0.05 pu. The balancing module was configured to
regulate balancing reactor current to an Inom of 0.3077 pu
(40 A) with Imin of 0.1923 pu (25 A) and an Imax of 0.4231
pu (55 A). Plots of one phase current and one phase voltage
are shown in Fig. 20.
Series-connected device voltage sharing was measured and
verified during peak current switching events in the dc-fed
test configuration illustrated in Fig. 18. During device voltage
sharing verification, the bridges were operated to pass through
each of the five voltage levels. Plots of the voltage waveforms
for a series-connected IGBT pair in the string of IGBTs with
eight series-connected devices, and a diode pair in the string
of diodes with eight series-connected devices are shown in
Fig. 21.
The output voltages of the capacitor balancer at the charger
and discharger terminals are shown with respect to the midpoint voltage in Fig. 22 under the same operational conditions.
The difference between these voltages is the voltage applied
to the reactor and dictates the balancing reactor current shown
in the bottom plot. The spikes in the balancer voltage output
occur when the charging and discharging state machines cycle
through the voltage levels to provide active balancing. When
the system is in the wait state, the net reactor voltage is zero
and the current freewheels. In this case, the peak average
current deviation of 0.05 pu (Fig. 19) is much less than the
Inom set point of 0.3077 pu, so the balancing system spends
the majority of the sweep time in the wait state because little
capacitor voltage balancing is required.
VIII. C ONCLUSION
This paper presented a new philosophy for implementing
an IGBT-based, low-power, medium-voltage power converter
using discrete semiconductor devices and printed circuit board
technology. These ideas were demonstrated on a 4.16 kV, 746
kW prototype tested at rated current and voltage.
A power circuit topology unwrapping technique for N -level
NPC, ANPC, and NPP bridges was used to design a simple
mechanical arrangement of the devices on a PCB with very
low commutation inductance. This technique also allows the
same power stage to be used as a dc-link capacitor balancing
circuit for the N -level converter. The use of PCB technology
and a commonality across power stages and balancer circuit
allows extensive automated manufacturing, testing, and quality
control, along with minimal spare parts. The prototype was
14
900
900
IGBT1
IGBT2
700
700
600
600
500
400
300
200
500
400
300
200
100
100
0
0
−100
−100
−200
0
2
4
Diode1
Diode2
800
Device Voltage (V)
Device Voltage (V)
800
6
8
10
Time (µs)
12
14
16
18
20
(a) IGBT voltage waveforms.
−200
0
2
4
6
8
10
Time (µs)
12
14
16
18
20
(b) Diode voltage waveforms.
Fig. 21. Series connected IGBT collector-emitter voltage waveforms and series connected diode anode-cathode voltage waveforms during the bridge operation
through all five levels and back.
A PPENDIX
State Machine Voltage(V)
Capacitor Balancer State Machine Voltages
Discharger Output
Charger Output
2000
0
−2000
Balancer Current(A)
0
200
400
Time (µs)
Capacitor Balancer Reactor Current
600
A pair of traditional and unwrapped configurations are
shown for the single-phase, three-level NPC topology in Fig.
23. All circuit nodes are not preserved when the topology
is unwrapped such as the (Q1, Q2, D1, D2) node shown in
Fig. 23a. The unwrapped mechanical arrangement scheme is
theoretically applicable to all N -level NPC topologies.
R EFERENCES
30.5
30
29.5
29
28.5
28
0
200
400
Time (µs)
600
Fig. 22. Output voltages of the capacitor balancer at the charger and
discharger terminals are shown with respect to the midpoint voltage. The
difference between these voltages is the voltage across the balancing reactor,
which dictates the corresponding current shown in the bottom plot.
constructed using these layout and schematic techniques with
automated PCB assembly, which validates these ideas as useful
in practice.
A novel IGBT gate drive system was developed that is well
suited to gate large numbers of series-connected devices. A
capacitor balancing circuit was constructed that is identical to a
power stage. The balancer and its associated control algorithm
were studied in a motor-drive application through analysis,
simulation, and experiment. Both the gate drive and balancing
systems performed as expected during testing.
The development and validation of these ideas paves the
way for a new breed of transformerless and bi-directional multilevel converters that meet high power quality requirements
while minimizing dv/dt and common-mode voltage system
stresses.
[1] R. Campos, “Medium voltage drives intelligence database 2014,” IHS Research, Tech. Rep., 2014. [Online]. Available:
https://technology.ihs.com/
[2] J. Rodriguez, S. Bernet, P. K. Steimer, and I. E. Lizama, “A survey
on neutral-point-clamped inverters,” IEEE Trans. Ind. Electron., vol. 57,
no. 7, pp. 2219–2230, 2010.
[3] J. Rodriguez, J.-S. Lai, and F. Z. Peng, “Multilevel inverters: a survey
of topologies, controls, and applications,” IEEE Trans. Ind. Electron.,
vol. 49, no. 4, pp. 724–738, 2002.
[4] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped
PWM inverter,” IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518–523,
1981.
[5] T. Bruckner, S. Bernet, and H. Guldner, “The active NPC converter and
its loss-balancing control,” IEEE Trans. Ind. Electron., vol. 52, no. 3,
pp. 855–868, June 2005.
[6] V. Guennegues, B. Gollentz, F. Meibody-Tabar, S. Rael, and L. Leclere,
“A converter topology for high speed motor drive applications,” in Power
Electronics and Applications, 2009. EPE ’09. 13th European Conference
on, Sept 2009, pp. 1–8.
[7] J.-S. Lai and F. Z. Peng, “Multilevel converters-a new breed of power
converters,” IEEE Trans. Ind. Appl., vol. 32, no. 3, pp. 509–517, 1996.
[8] F. Z. Peng, “A generalized multilevel inverter topology with self voltage
balancing,” IEEE Trans. Ind. Appl., vol. 37, no. 2, pp. 611–618, Mar
2001.
[9] A. Lesnicar and R. Marquardt, “An innovative modular multilevel
converter topology suitable for a wide power range,” in Power Tech
Conference Proceedings, 2003 IEEE Bologna, vol. 3, June 2003, pp.
6–12.
[10] M. Glinka and R. Marquardt, “A new AC/AC multilevel
converter
family,”
IEEE
Trans.
Ind.
Electron.,
vol. 52, no. 3, pp. 662–669, 2005. [Online]. Available:
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1435677
[11] A. Nami, J. Liang, F. Dijkhuizen, and G. Demetriades,
“Modular multilevel converters for HVDC applications: Review
on converter cells and functionalities,” IEEE Trans. Power
Electron., vol. 30, no. 1, pp. 18–36, 2015. [Online]. Available:
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6824228
15
+1
Sub-Circuit 1
+
Vc
-
Q1
D1
DCP Q2
D2
0
+1
D2
DCN Q1
Q1
0
DCN
DCP
D1
Q2
Q2
Vout
D1
Q1
Vout
+
Vc
-
Sub-Circuit 2
Q2
D2
-1
-1
(a) Classical antiparallel arrangement.
D2
D1
(b) Unwrapped arrangement.
Fig. 23. Classic and unwrapped three-level NPC topology shown without commutation loops.
[12] M. Perez, S. Bernet, J. Rodriguez, S. Kouro, and R. Lizana,
“Circuit topologies, modeling, control schemes, and applications
of modular multilevel converters,” IEEE Trans. Power Electron.,
vol. 30, no. 1, pp. 4–17, 2015. [Online]. Available:
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6757004
[13] B. Riar and U. Madawala, “Decoupled control of modular multilevel
converters using voltage correcting modules,” IEEE Trans. Power Electron., vol. 30, no. 2, pp. 690–698, Feb 2015.
[14] R. Feldman, M. Tomasini, E. Amankwah, J. Clare, P. Wheeler,
D. Trainer, and R. Whitehouse, “A hybrid modular multilevel voltage
source converter for HVDC power transmission,” IEEE Trans. Ind. Appl.,
vol. 49, no. 4, pp. 1577–1588, July 2013.
[15] P. Hammond, “A new approach to enhance power quality for medium
voltage AC drives,” IEEE Trans. Ind. Appl., vol. 33, no. 1, pp. 202–208,
Jan 1997.
[16] T. Stockmeier, “From packaging to ”un”-packaging - trends in power
semiconductor modules,” in Power Semiconductor Devices and IC’s,
2008. ISPSD ’08. 20th International Symposium on, 2008, pp. 12–19.
[17] B. Le Gouic, A. Avron, W. Ding, and L. Cassarino, “Status of the power
electronics industry,” Yole Developpement, Tech. Rep., 2012.
[18] P. N. Oakes and R. N. Wilkes, “Semiconductor device,” US Patent
3,061,762, February 13, 1962.
[19] T. E. Hasty, “Method for encapsulating discrete semiconductor chips,”
US Patent 3 739 462, June 19, 1973.
[20] C. Chen, X. Pei, Y. Chen, and Y. Kang, “Investigation, evaluation,
and optimization of stray inductance in laminated busbar,” IEEE Trans.
Power Electron., vol. 29, no. 7, pp. 3679–3693, July 2014.
[21] P. Palmer and A. Githiari, “The series connection of IGBTs with
optimised voltage sharing in the switching transient,” in 26th Annual
IEEE Power Electronics Specialists Conference, PESC ’95, vol. 1, Jun
1995, pp. 44–49 vol.1.
[22] A. Consoli, S. Musumeci, G. Oriti, and A. Testa, “Active voltage
balancement of series connected IGBTs,” in Industry Applications
Conference, 1995. Thirtieth IAS Annual Meeting, IAS ’95., Conference
Record of the 1995 IEEE, vol. 3, Oct 1995, pp. 2752–2758 vol.3.
[23] B.-S. Seo, T.-K. Lee, and D. seok Hyun, “Synchronization on the points
of turn-off time of series-connected power semiconductor devices using
miller effect,” in Industrial Electronics, Control, Instrumentation, and
Automation, 1992. Power Electronics and Motion Control., Proceedings
of the 1992 International Conference on, Nov 1992, pp. 325–329 vol.1.
[24] C. Gerster, “Fast high-power/high-voltage switch using series-connected
IGBTs with active gate-controlled voltage-balancing,” in Applied Power
Electronics Conference and Exposition, 1994. APEC ’94. Conference
Proceedings 1994., Ninth Annual, Feb 1994, pp. 469–472 vol.1.
[25] C. Abbate, G. Busatto, and F. Iannuzzo, “High-voltage, highperformance switch using series-connected IGBTs,” IEEE Trans. Power
Electron., vol. 25, no. 9, pp. 2450–2459, Sept 2010.
[26] A. Permuy, N. Benavides, and L. Solomon, “Gate drive circuit and
associated method,” US Patent 8,471,604, June 25, 2013.
[27] G. Carrara, S. Gardella, M. Marchesoni, R. Salutari, and G. Sciutto,
[28]
[29]
[30]
[31]
[32]
[33]
[34]
[35]
[36]
[37]
[38]
[39]
[40]
[41]
[42]
“A new multilevel PWM method: a theoretical analysis,” IEEE Trans.
Power Electron., vol. 7, no. 3, pp. 497–505, 1992.
C. Newton and M. Sumner, “Novel technique for maintaining balanced
internal DC link voltages in diode clamped five-level inverters,” IEEE
Proceedings -Electric Power Applications Proceedings -Electric Power
Applications, vol. 146, no. 3, pp. 341–349, 1999.
M. Marchesoni and P. Tenca, “Diode-clamped multilevel converters:
a practicable way to balance DC-link voltages,” IEEE Trans. Ind.
Electron., vol. 49, no. 4, pp. 752–765, 2002.
K. Kaneko, J. Mitsuta, K. Matsuse, K. Sasagawa, Y. Abe, and L. Huang,
“Analysis of dynamic variation on a combined control strategy for a fivelevel double converter,” in Proc. IEEE 36th Power Electronics Specialists
Conf. PESC ’05, 2005, pp. 885–891.
A. Shukla, A. Ghosh, and A. Joshi, “Control schemes for DC capacitor
voltages equalization in diode-clamped multilevel inverter-based dstatcom,” IEEE Trans. Power Del., vol. 23, no. 2, pp. 1139–1149, 2008.
J. Qin and M. Saeedifard, “Predictive control of a modular multilevel
converter for a back-to-back HVDC system,” IEEE Trans. Power Del.,
vol. 27, no. 3, pp. 1538–1547, July 2012.
C. Townsend, T. Summers, J. Vodden, A. Watson, R. Betz, and J. Clare,
“Optimization of switching losses and capacitor voltage ripple using
model predictive control of a cascaded H-bridge multilevel statcom,”
IEEE Trans. Power Electron., vol. 28, no. 7, pp. 3077–3087, July 2013.
B. Riar, T. Geyer, and U. Madawala, “Model predictive direct current
control of modular multilevel converters: Modeling, analysis, and experimental evaluation,” IEEE Trans. Power Electron., vol. 30, no. 1, pp.
431–439, Jan 2015.
K. Wang, L. Xu, Z. Zheng, and Y. Li, “Capacitor voltage balancing of
a five-level ANPC converter using phase-shifted PWM,” IEEE Trans.
Power Electron., vol. 30, no. 3, pp. 1147–1156, March 2015.
N. S. Choi, J. G. Cho, and G. H. Cho, “A general circuit topology
of multilevel inverter,” in Proc. 2nd Annual IEEE Power Electronics
Specialists Conf. PESC ’91 Record, 1991, pp. 96–103.
K. Hasegawa and H. Akagi, “Voltage balancing of the four split DC
capacitors for a five-level diode-clamped PWM inverter with a frontend diode rectifier,” in Proc. Int. Power Electronics Conf. (IPEC), 2010,
pp. 734–739.
A. Shukla, A. Ghosh, and A. Joshi, “Flying-capacitor-based chopper
circuit for DC capacitor voltage balancing in diode-clamped multilevel
inverter,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2249–2261,
2010.
K. Hasegawa and H. Akagi, “A new DC-voltage-balancing circuit
including a single coupled inductor for a five-level diode-clamped PWM
inverter,” IEEE Trans. Ind. Appl., vol. 47, no. 2, pp. 841–852, 2011.
S. Srikanthan and M. K. Mishra, “DC capacitor voltage equalization
in neutral clamped inverters for DSTATCOM application,” IEEE Trans.
Ind. Electron., vol. 57, no. 8, pp. 2768–2775, 2010.
N. Hatti, Y. Kondo, and H. Akagi, “Five-level diode-clamped PWM
converters connected back-to-back for motor drives,” IEEE Trans. Ind.
Appl., vol. 44, no. 4, pp. 1268–1276, 2008.
K. Sano and H. Fujita, “Voltage-balancing circuit based on a resonant
16
[43]
[44]
[45]
[46]
[47]
[48]
[49]
[50]
[51]
[52]
[53]
[54]
[55]
[56]
switched-capacitor converter for multilevel inverters,” IEEE Trans. Ind.
Appl., vol. 44, no. 6, pp. 1768–1776, 2008.
Z. Shu, X. He, Z. Wang, D. Qiu, and Y. Jing, “Voltage balancing
approaches for diode-clamped multilevel converters using auxiliary
capacitor-based circuits,” IEEE Trans. Power Electron., vol. 28, no. 5,
pp. 2111–2124, May 2013.
D. Siemaszko, “Fast sorting method for balancing capacitor voltages in
modular multilevel converters,” IEEE Trans. Power Electron., vol. 30,
no. 1, pp. 463–470, Jan 2015.
A. Permuy and L. Solomon, “Capacitor balancing circuit and control
method for an electronic device such as a multilevel power inverter,”
US Patent Application 20 120 161 858, June 28, 2012.
A. Permuy and N. Benavides, “Mechanical arrangement of a multilevel
power converter circuit,” US Patent Application 20 120 163 057, June
28, 2012.
W. McMurray, “Optimum snubbers for power semiconductors,” IEEE
Trans. Ind. Appl., vol. IA-8, no. 5, pp. 593–600, Sept 1972.
S. Castagno, R. Curry, and E. Loree, “Analysis and
comparison of a fast turn-on series IGBT stack and highvoltage-rated commercial IGBTs,” IEEE Trans. Plasma Sci.,
vol. 34, no. 5, pp. 1692–1696, 2006. [Online]. Available:
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1710027
P. Palmer and A. Githiari, “The series connection of IGBTs with active
voltage sharing,” IEEE Trans. Power Electron., vol. 12, no. 4, pp. 637–
644, Jul 1997.
M. Saeedifard, R. Iravani, and J. Pou, “Analysis and control of DCcapacitor-voltage-drift phenomenon of a passive front-end five-level
converter,” IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 3255–3266,
2007.
T. Shimizu, T. Fujita, G. Kimura, and J. Hirose, “A unity power
factor PWM rectifier with DC ripple compensation,” IEEE Trans. Ind.
Electron., vol. 44, no. 4, pp. 447–455, Aug 1997.
A. Antonopoulos, L. Angquist, S. Norrga, K. Ilves, L. Harnefors, and
H.-P. Nee, “Modular multilevel converter AC motor drives with constant
torque from zero to nominal speed,” IEEE Trans. Ind. Appl., vol. 50,
no. 3, pp. 1982–1993, May 2014.
R. Letor, “Static and dynamic behavior of paralleled IGBTs,” IEEE
Trans. Ind. Appl., vol. 28, no. 2, pp. 395–402, Mar 1992.
UL 61800-5-1, Adjustable Speed Electrical Power Drive Systems - Part
5-1: Safety Requirements - Electrical, Thermal and Energy, UL Std.
V. Khanna, The insulated gate bipolar transistor: IGBT
theory and design, ser. IEEE Press Series on Microelectronic Systems.
IEEE Press, 2003. [Online]. Available:
http://books.google.com/books?id=BVxTAAAAMAAJ
D. Holmes, T. Lipo, and T. Lipo, Pulse width modulation for
power converters: principles and practice, ser. IEEE Press series
on power engineering. IEEE Press, 2003. [Online]. Available:
http://books.google.com/books?id=8LGi1AjSfpcC
Luke A. Solomon (M 08) is presently a Senior
Engineer for GE Power Conversion. He has over
ten years of experience focused in power electronics
design, real time control systems engineering and
power systems analysis. At GE Power Conversion,
Luke is serving as the lead engineer responsible
for all design, analysis, and hardware verification
aspects of a medium-voltage, IGBT-based, power
converter development project. These responsibilities include the management of a team of research
engineers performing engineering tasks ranging from
conceptual design of the power converter to the delivery of a complete
design and full-scale prototype unit to manufacturing. Dr. Solomon earned
his Ph.D. in Electrical Engineering from the University of Pittsburgh (2015),
MS in Electrical and Computer Engineering from the Georgia Institute of
Technology (2007) and BS in Electrical Engineering from the Pennsylvania
State University (2003).
Alfred Permuy started his career at the Centre
National de la Recherche Scientifique (CNRS) as
a computer scientist. In 1986 he joined Xerox in
Palo Alto, California as a Design Engineer. In 1988
he became Technical Director and then Managing
Director of Vectavib / Metravib RDS, an instrumentation company for the automotive, industry and defence sectors. In 1995, he joined Valeo as Technical
Director and Product Director of Electronic Group
Projects Division. In 1999, he moved to Saft Power
Systems as Technical Director and then Chief Operations Officer. In 2007, he joined Converteam as Chief Technology Officer.
Presently Alfred is the Chief Technology Officer of GE Power Conversion and
President and General Manager of GE-PC France. Alfred holds more than
60 patents in various technical fields including nano technologies, sensors,
vibration and noise control, electrical machines and electronics. Alfred earned
a Ph.D. in Solid State Physics from Ecole Normale Supérieure (Ulm) Paris
in 1985.
Nicholas D. Benavides (M 07) received BS degree from the University of Missouri-Rolla (now
Missouri University of Science and Technology)
in Rolla, MO in 2003 and MS and PhD degrees
in Electrical Engineering from the University of
Illinois at Urbana-Champaign, in 2004 and 2007,
respectively. He is currently a Senior Lead Engineer
with PC Krause and Associates where his primary
responsibilities include power electronic converter
design, modeling, and analysis for a variety of
customers in the mil/aero sector. Prior to joining
PC Krause and Associates, Dr. Benavides was with GE Power Conversion
(formerly Converteam) based in Pittsburgh, PA from 2007-2013. From 20072009, in the role of Senior Research and Development Engineer he was project
lead of development of a high-reliability, multi-megawatt inverter system for
naval propulsion. From 2010-2012, in the role of Chief Engineer-Technology,
he lead the research and development team developing commercial and
industrial products for the North America unit. Key projects of the team
included medium voltage inverters and utility-scale solar inverters (1-5 MW).
Most recently, in 2012-2013 he held the position of Executive-Engineering
responsible for engineering in the Power Conversion Services division.
Daniel F. Opila (M 08) received BS and MS degrees
from the Massachusetts Institute of Technology,
Cambridge, Massachusetts, in 2002 and 2003 respectively, and the Ph.D. degree from the University
of Michigan, Ann Arbor, Michigan, in 2010. He
is currently Assistant Professor of Electrical and
Computer Engineering at the United States Naval
Academy. Previously, he was a Senior Research
and Development Engineer at GE Power Conversion
in Pittsburgh, PA. Other past positions include a
Visiting Scholar at Ford Motor Company, a Senior
Engineer at Orbital Sciences Corporation, and a Mechanical Engineer at Bose
Corporation. He specializes in optimal control of energy systems, including
hybrid vehicles, naval power systems, power converters, and renewables.
17
Christopher J. Lee (M 08) received the B.S. degree
from the University of Pittsburgh, Pittsburgh, PA,
USA, in 2011. He is currently working toward a
M.S. degree in electrical engineering at the Georgia Institute of Technology, Atlanta, GA, USA.
He is currently a Lead Research and Development
Engineer with GE Power Conversion, Pittsburgh,
PA,USA. His primary technical focus and specialities are in medium-voltage power electronics design,
research and development, and validation of medium
voltage power converters. He has participated in
multiple power converter design teams for medium and low voltage inverters
for industrial, renewable energy and naval applications with a focus in
hardware design, analysis, and verification. He is currently participating on
cross functional team for concept through prototyping and full production
release for power converter projects with responsibilities in power electronics,
systems, test, and control.
Gregory F. Reed (M 85) is the Director of the
Electric Power Initiative in the Swanson School of
Engineering at the University of Pittsburgh, Associate Director of the Universitys Center for Energy,
and Associate Professor of Electric Power Engineering in the Swanson Schools Electrical & Computer
Engineering Department. He is also the Director
of the newly established Grid Technologies Collaborative of the DOE National Energy Technology
Laboratory’s Regional University Alliance; and an
inaugural member of the National Academies of
Science and Engineering’s Energy Ambassador Program. His research interests, teaching activities, and related pursuits include advanced electric power
and energy generation, transmission, and distribution system technologies;
power electronics and control technologies (FACTS, HVDC, and MVDC
systems); renewable energy systems and integration; smart grid technologies
and applications; and energy storage. Dr. Reed has over 27 years of combined
industry and academic experience in the electric power and energy sector,
including engineering, research & development, and executive management
positions throughout his career with the Consolidated Edison of New York,
ABB Inc., Mitsubishi Electric Corp., and DNV-KEMA. He is an active
member of the IEEE Power & Energy Society and the American Society
of Engineering Education. Dr. Reed earned his Ph.D, in electric power
engineering from the University of Pittsburgh (1997), M.Eng. from Rensselaer
Polytechnic Institute (1986), and B.S. from Gannon University (1985).