Carbon Nanotube Interconnects for IC Chips
by
MASSACHUS•-.I
INM ,
OF TECHNOLOGY
Hashina Parveen Anwar Ali
OCT 0 2 2006
Bachelor of Engineering (Electrical)
National University of Singapore, 2005
LIBRARIES
SUBMITTED TO THE DEPARTMENT OF MATERIALS SCIENCE AND
ENGINEERING IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE
DEGREE OF
MASTER OF ENGINEERING IN MATERIALS SCIENCE AND ENGINEERING
AT THE
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
September 2006
C 2006 Hashina Parveen Anwar Ali. All Rights Reserved
The author hereby grant to MIT permission to reproduce and to distribute publicly paper and
electronic copies of this thesis document in whole or in part in any medium or hereafter
created,
Signature of Author...................................................
Department of Materials Science and Engineering
August 8, 2006
Certified by .............................
.
•... ............................
Carl V. Thompson
Stavros Salapatas Professor of Materials Science and Engineering
Thesis Supervisor
Accepted by ...........................
.. ./
..............
..........
...
....
Samuel M. Allen
POSCO Professor of Physical Metallurgy
Chair, Departmental Committee on Graduate Students
ARCHVES
Carbon Nanotube Interconnects for IC chips
by
Hashina Parveen Anwar Ali
Submitted to the Department of Materials Science and Engineering
on August 8, 2006 in Partial Fulfillment of the
Requirements for the Degree of Master of Engineering in
Materials Science and Engineering
ABSTRACT
Carbon nanotubes (CNTs) have been investigated as candidate materials to replace or
augment the existing copper-based technologies as interconnects for Integrated Circuit (IC)
chips. Being ballistic conductors, CNTs are capable of carrying higher current densities of up
to 101oA/cm 2 and high thermal conductivity. This thesis examines the technological aspect of
carbon nanotubes - how these tubes can excel in place of copper in terms of their
performance and integration into the current commercial IC chip process. A detailed
literature review is covered, together with a performance analysis of the resistances between
copper and CNT interconnects. Further, a business model is proposed on the possibility of
introducing this technology into the mainstream IC industry.
Thesis Supervisor: Carl V. Thompson
Title: Stavros Salapatas Professor of Materials Science and Engineering
Acknowledgements
I cannot fully express my profound gratitude to several exceptional people who guided,
critiqued and encouraged me through the conception, development and conclusion of my
M.Eng thesis dissertation.
First and foremost, I thank my MIT professor, Stavros Salapatas Prof Carl. V. Thompson
for agreeing to be my supervisor for a forefront project scope and his superb guidance. An
understanding supervisor and firm one, he ensured that I went on with my project within the
boundaries set by him and helped me whenever I was faced with challenges.
My NTU facilitator Prof Zhang Qing has been a great help here in Singapore, keeping his
doors open for me to come in anytime and answered any doubts I have on carbon nanotubes.
The Nanotubes research group at MIT under Prof Thompson has been the team that guided
me through my research on carbon nanotubes. In particular, I sought the help of Gilbert
Nessim, who has provided me with his experience and expertise. Thanks a lot!
Last, but not the least, my family and friends who have supported and cheered me up to push
forward with enthusiasm and vigor to complete this M.Eng dissertation successfully.
Contents
ABSTRACT .............................................................................................................................
2
ACKNOWLEDGEMENTS ................................................................................................
3
CONTENTS .............................................................................................................................
4
LIST OF FIGURES ................................................................................................................
5
LIST OF TABLES ..................................................................................................................
5
ABBREVIATIONS ..................................................................................................................
8
CHAPTER 1
INTRODUCTION.......................................................................................
9
CHAPTER 2
FUNDAMENTALS ...........................................................
15
CURRENT TECHNOLOGY - COPPER DAMASCENE PROCESS .....................................
DESIGN CONSIDERATIONS INCOPPER INTERCONNECTS .........................................
LIMITATIONS OF COPPER INTERCONNECTS - NEED FOR A NEW SOLUTION ............
....
PROPOSED TECHNOLOGY - CARBON NANOTUBES..................................
..........
METHODS OF FABRICATING CNTS ...........................................
.......................
PROPERTIES OF CNTS THAT ENCOURAGE ITS USE AS POSSIBLE INTERCONNECTS .............
OTHER REMARKABLE PROPERTIES OF CNTS .......
...........................................
15
17
19
23
25
28
34
2.1
2.2
2.3
2.3
2.4
2.5
2.6
CHAPTER 3
CARBON NANOTUBES AS INTERCONNECTS.........................
............
36
3.1
FABRICATION OF CNT INTERCONNECTS ........................................................... 36
3.2
DESIGN CONSIDERATIONS FOR CNT INTERCONNECTS ...........................................
39
3.2.1
Research on SWNT bundles as Interconnects .......................................
.......... 39
3.2.2
3.2.3
Research on MWNTs as Interconnects ............................................
Patented Designs using CNTs.................................................
...........
44
47
3.3
RESISTANCE MODEL FOR CNTS VERSUS COPPER INTERCONNECTS .............................. 49
3.3.1
Assumptions - Interconnect Wire Design in IC chip ..........................................
. 50
3.3.2
3.3.3
Assumptions and Calculations for Copper Interconnects....................................... 51
Assumptions and Calculations for CNT Interconnects ......................................
. 53
CHAPTER 4
TECHNICAL ASSESSMENT OF CNTS AS INTERCONNECTS ............ 56
4.1
FABRICATION .............................................................
.............. ......................... 56
4.2
TREND IN THE RESISTANCE OF COPPER...................................................... 58
4.3
EFFECTS OF KEY PARAMETERS ON CNT PERFORMANCE .......................................... 59
4.3.1
Effect of packing distance on SWNT bundle...................................
.............. 60
4.3.2
4.4
4.4.1
4.4.2
4.5
4.5.1
4.5.2
4.5.3
4.6
Effect of Outer Diameter on Resistance of Single MWNTs...................................... 61
ANALYSIS ON THE MWNT MODELS .............................................
.................... 63
Comparison of Single MWNT models ..........................................
............. 63
Effect of MWNT rings on the MWNT bundle resistance............................................65
OVERALL RESISTANCE TRENDS - CNTS VERSUS COPPER INTERCONNECTS......
...... 66
Technology Node - 80nm ........................................
67
Technology N ode - 45nm ........................................................... .......................... 67
Technology Node - 14nm ........................................
68
RESULTS AND COMMENTS ........................................
CHAPTER 5
TECHNOLOGY ASSESSMENT OF CNTS AS INTERCONNECTS ........
68
70
5.1
5.2
T ECHNO LOGY SUPPLY C HAIN ................................. .................. ................................ 70
INTELLECTUAL PROPERTY ............................................................................................. 71
5.2.1
CNT patents in general ...................
.........
.................
72
5.2.2 Patents specific to CNT interconnects in IC chips ....................................... 74
5.3
TARGET W ORLD M ARKET ...................................
.....................
......... 76
5.3.1 Semiconductor M arket Trends .......................................................................... 76
5.3.2 Forw ard Looking Trends ............................................................ 78
5.3.3 Emerging Market - Nanotechnology ...........................
.
........................ 78
5.3.4 Opportunities for implementing Nanomaterials ..................... ...... ........... 80
5.3.5 Risks of implem enting N anomaterials ............................................................ 80
5.4
SOURCES OF FUNDING ..............................................
81
5.5
INVESTMENT COSTS ...................
.....................................
84
5.6
B USIN ESS PLAN ..............................................................
86
5.6.1 Success Factors ............
.....................................
86
5.6.2 Implementation ............
.....................................
88
5.7
FINANCIAL VIABILITY ........................................................................... 90
5.8
EXECUTION PLAN ...................................................
CHAPTER 6
CONCLUSION ................................................................................................
90
91
R EFEREN C ES ..............................................................................................................................
93
APPENDIX I
SCMOS LAYOUT RULES ....................................
95
APPENDIX 2
FLOWCHART OF INVENTION IN US PATENT 6,933,222................
97
List of Figures
Figure 1.1: The first Integrated Circuit (IC) - Kilby's invention (left), Noyce's invention (right) ....... 9
Figure 1.2: Cross-section of a typical IC Chip (MPU device) showing the hierarchical scaling of the
copper wires and vias (highlighted in light grey). [1] .........................
.................. 10
Figure 1.3: A futuristic picture of a CNT via replacing Copper. (a) A hole is made in the dielectric
above the metal layer to be contacted. (b) A catalyst particle is deposited or generated at the bottom of
the via from which the CNT can be grown (c) [2] .................... ...............................................
13
Figure 1.4: The current situation of CNTs in vias - cross-section SEM images of vias with CVDgrown MWNTs. The catalyst particles are based on Fe and the supporting metal layer is Ta. [5]...... 13
Figure 2.1: Illustration of the copper damascene process [4] .......................................... 16
Figure 2.2: Interconnect scaling scenarios for (a) fixed metal height and (b) fixed metal aspect ratio
[33]
...........................
.....................
...........................
18
Figure 2.3 Trend in Cu resistivity [1] ..............................................
........... 19
Figure 2.4: Dual Damascene Integration Concerns [33] ......................................
20
Figure 2.5: Maximum allowed RMS current densities for local vias under self-consistent Joule
heating and EM lifetim e constraints [32] ...................... ............ ..... .....................
... 22
Figure 2.6: Atomic configuration of (a) armchair (n, n), (b) zigzag (n, 0), and (c) general (inm,
n) CNTs.
...............................................................................
. . . . ....
23
Figure 2.7: Indexing scheme for a SWNT in terms of integer pair (m, n) .....................................
23
Figure
Figure
Figure
Figure
Figure
24
25
26
27
29
2.8 Density of States for a metallic and semiconducting tube ....................
......................
2.9: Carbon Arc experimental setup for CNT synthesis [8] ....................
.......................
2.10: Laser Vaporization Method [8] ........
........................................
2.11: CVD method schematically shown by Wagner et al [9] ......................................
2.12: Different properties of CNTs based on chirality [Courtesy of Prof Thompson] .............
Figure 2.13: Calculations on the packaging density of a dense (x = d) SWNT bundle [17] ............... 31
Figure 2.14: Number of conduction channels per graphene shell versus shell diameter for metallic and
semiconductor shells. The average number of conduction channels is also plotted assuming that
statistically one-third of the shells are metallic. [22] .................................................. 32
Figure 2.15: A graph of the thermal conductivities of iron, silver and diamond [24] ................... 34
Figure 2.16: Thermal Conductivity of (10,10) CNT as a function of temperature [11 ] ................... 34
Figure 3.1: Schematic of the Li group's Bottom up approach process [13] ..................
37
Figure 3.2: Schematic of the buried catalyst approach by the Nihel group[14] ................................. 37
Figure 3.3 Equivalent circuit model for an isolated SWNT, length less than the mean free path of
electrons, assum ing ideal contacts [15] ............................................................................................
40
Figure 3.4: Schematic of CNT-bundle interconnect. Elements labeled with numbers are the ones
characterizing the electrostatic coupling capacitance of the CNTs along the edges of the bundle. Each
circular cross-section CNT is shown along with the circumscribing square conductor. CED, and CEf are
the intrinsic plate capacitances. [39] ......... .............
.................................. 41
Figure 3.5: AC circuit model for interacting electrons in a carbon nanotube [15] ............................. 42
Figure 3.6: Inset: Latency versus interconnect length for minimum-sized copper wires implemented at
the 22nm node and bundles of SWNTs with electron mean-free paths of 0.1, 1 and 10Om, assuming
that SWNT resistance increases linearly with length. Main plot: Maximum performance enhancement
that can be achieved by using CNTs versus electron mean-free path in nanotubes for four various
technology nodes. [38] ................................................................................. 43
Figure 3.7: Maximum interconnect temperature rise for Cu interconnects and vias versus CNT bundle
vias integrated with Cu interconnects [17]. For CNT bundles, the shaded region shows the range
1750W/mK < Kth < 5800W/mK. Reference (substrate) temperature = 378K. [17] ..............
44
Figure 3.8: Factors influencing CNT resistivity: no. of shells and orientation of the graphene planes.
[5] .................
..................
.......... ............ .................................
45
Figure 3.9: Dependence of the total resistance of CNT vias on the number of CNTs [42] ........
. 46
Figure 3.10: XRD patterns of MWNTs/Co/Ti samples (a) Co(2.5nm)/Ti(6nm) (b) Co(lnm)/Ti(2nm).
Cross-sectional view of MWNTs/Co/Ti/Ta/Cu bottom layer structures (c) Co(2nm)/Ti(6nm) (d)
Co(Inm)/Ti(2nm) MWNTs with Co nanoclusters inside the ends of the nanoclusters inside the ends
of the nanotubes grew vertically on the Ti contact layers. [43] ...........................
47
Figure 3.11 Cross-sectional view of semiconductor device; CNTs in vias are labeled as 42 and Cu in
vias are labeled as 34 [24] ..................
............ ............ .. .........
............................................ 48
Figure 3.12 Sectional view of two stages of fabrication of CNT ICs using CNTs (labeled as 152) [25]
................................................................................................................................ ....... 49
Figure 3.13: Cross-section of Square Vias with design rule specifications (On left, CNT, right, Cu
via). The shaded area is to account for Cu barrier thickness ......................................
.......... 50
Figure 3.14: Cross-section of Circular Vias when manufactured (On left, CNT, right, Cu via) The
shaded area is to account for Cu barrier thickness ...................................
51
Figure 3.15: A one-tier metal layout view of a via between 2 metal layers. The dimensions given are
assumed for the resistance model ......................................................
51
Figure 4.1: Resistance of Copper (from 80nm to 45nm) (Sq: Square area, Cir: Circular area)........... 58
Figure 4.2: Resistance of Copper (from 45nm to 14nm) (Sq: Square area, Cir: Circular area)........... 59
Figure 4.3: Resistance of tube (RL) versus the Packing distance between 2 SWNTs
(Each SWNT: Diameter Inm and length of I tm) .................................................... ................... 60
Figure 4.4: Resistance of tube (RL) versus the Packing Distance between 2 MWNTs (Each MWNT:
Diameter 5nm, Diameter Ratio 0.35 and length of 1 tm) ..............................
61
Figure 4.5: Resistance of tube (R.) versus Outer MWNT Diameter with different Diameter Ratios of
0.35, 0.65 and 0.8. (Each MWNT: length of l tm and conductance of 2Go in each ring (General
model) ) ..............................
.........................................
62
Figure 4.6: Comparison of Single MWNT calculations, 80nm on left, 45nm on right...................... 63
Figure 4.7: Comparison of Single MWNT calculations for 14nm ..............................
64
Figure 4.8: Resistance of MWNT bundle versus number of rings in each MWNT at 14nm technology
node (Each MWNT: Diameter 5nm, Diameter ratio 0.35 and length of l• m) ................................... 65
Figure 4.9: Overall resistance trends for 80nm node (Left: for vias, Right: for long interconnects)... 67
Figure 4.10: Overall resistance trends for 45nm node (Left: for vias, Right: for long interconnects). 67
Figure 4.11: Overall resistance trends for 14nm node (Left: for vias, Right: for long interconnects). 68
Figure 5.1: A typical Silicon wafer manufacturing process chain .................................................. 70
Figure 5.2: US patents or published applications referring to carbon nanotubes in the patent abstract
(1999 - 2004) [23] ...................................
..
.................
........ . .................... 72
Figure 5.3: Carbon nanotube patents issued by US PTO, from 1999-2004 (the data was collected on
04/25/2005) [23] ................... .......... ...... ..................... ..................... ................................ 72
Figure 5.4 Sectional view of a semiconductor device that only uses CNTs (lines in diagram) from
Fujitsu Patent [24].............................. ......... ... ........................................... . ... ................. 75
Figure 5.5: W orldwide Semiconductor Trends [34] ....................
.... ................................
76
Figure 5.6: Worldwide Semiconductor Consumption highlighting the change in consumption from
majority N. America in 2000 to ROW in 2005. ROW includes Asia Pacific regions such as China,
Taiwan, Singapore, Korea etc [34] ........................................
................... 77
Figure 5.7: Global Nanoelectronics Market Forecast [36] .................................
79
Figure 5.8: Global Market and Forecast for Nanomaterials (SEMI 2005) [36] .................................. 79
Figure 5.9: Graphs showing rising costs of starting a fab [30] .............................
85
Figure 6.1 : Summary of the considerations for a successful IP business model ............................. 92
List of Tables
Table 1.1: MPU Interconnect Technology Requirements - Long-term years [1]............................ 12
Table 1.2: Comparison of different interconnect solutions [6] .................................
......
12
Table 2.1: Dielectric constants for several low-k materials.............................. 17
Table 2.2: MPU Interconnect Technology Requirements - Long-term years [1]............................ 21
Table 2.3: Most important properties of metallic carbon nanotubes .............
..................... 34
Table 2.4: Comparison of CNT with some of the toughest materials [10] ...................................... 35
Table 2.5: Quick Facts about Carbon Nanotubes [10] .................................................................
35
Table 3.1: Specifications for copper at different technology nodes [1] ................... ..................... 52
Table 4.1: Comparison of the fabrication process....................................
56
Table 4.2: Calculated values of a fixed diameter ratio of 0.35 to determine effect of outer diameter on
resistance for a single MWNT ............................
.................... 62
Table 4.3: The constants used to calculate the resistance of copper [1] ...................................... 66
Table
5.1:
Carbon
nanotube
patents
issued
by
US PTO,
from
1999-2004
(the data was collected on 25 April 2005) [23] ...................................................... 73
Table 5.2: List of possible competing patents with the intellectual property of having CNT vias...... 74
Abbreviations
CMP
CNT
CVD
EM
EUVL
HFCVD
IC
IMD
ITRS
MARCO
MPU
MTF
MWNT
OEM
PECVD
RC
SEM
SPM
SWNT
TSMC
-
Chemical Vapor Deposition
Carbon Nanotube
Chemical Vapor Deposition
Electromigration (Lifetime)
Extreme Ultra Violet Lithography
Hot Filament Chemical Vapor Deposition
Integrated Circuit
Inter-metal dielectric
International Technology Roadmap for Semiconductors
Microelectronics Advanced Research Corporation
Multiprocessor Unit
Median Time to Failure
Multi-wall Carbon Nanotube
Original Equipment Manufacturer
Plasma Enhanced Chemical Vapor Deposition
Resistance-Capacitance (in terms of time delay)
Scanned Electron Microscope
Scanning Probe Microscope
Single-wall Carbon Nanotube
Taiwan Semiconductor Manufacturing Corporation
Chapter I Introduction
The first integrated circuit (IC) developed by Jack Kilby of Texas Instruments and Robert
Noyce of Fairchild semiconductor in 1958 triggered the growth of semiconductor industries
that lead to the popularity of miniature devices for everyday use. Three general strategies
have guided these advances: i) scaling down minimum feature size, ii) increasing die size,
and iii) enhancing packing efficiency (i.e. increasing the number of transistors that can fit
into an IC). Mass production of integrated circuits, their reliability, low cost and ease of
adding complexity, prompted the use of standardized ICs. This resulted in the dominance of
IC chips in various applications ranging from computers to cellular phones to digital
microwave ovens.
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Robert Noyce was ingenious to consider depositing metal lines by direct vacuum evaporation
of aluminum [29] to link up key components on a silicon wafer thus the interconnect was
born. The function of an interconnect is to distribute clock and other signals and to provide
power and ground lines to the various circuits / system functions on a chip. The fundamental
characteristic of an interconnect is to meet the high-speed transmission needs of chips in
proportion to the scaling of feature sizes.
Currently in the industry, Copper is being used as interconnect material in the manufacture of
IC chips at the 0.13pm technology node. Figure 1.2 shows a cross-sectional view of a typical
IC chip where the light gray areas indicate the metallic wires. The bottommost layer consists
of various p-n junction transistor devices. The subsequent layers above hold the different
local (Metal 1), intermediate and global power lines and clock signals, connecting one device
to another. Each metal wire is surrounded by a dielectric (usually SiO 2 ), preventing short
circuits and minimizing interference between signals as much as possible. Vias are included
to provide connections of metallic wires between two different layers.
Passivation
Dielectric
Etch Stop Layer
• Dielectric Capping Layer
Global
Intermediate
Metal I
Pre-Metal Dielectric
Tungsten Contact Plug
,-
Metai 1 Pitch
Figure 1.2: Cross-section of a typical IC Chip (MPU device) showing the hierarchical scaling of the
copper wires and vias (highlighted in light grey). 11]
ICs have consistently migrated to smaller feature sizes over the years, allowing more
circuitry to be packed on each chip. As the feature size shrinks, the benefits multiply: both
the cost per unit and the switching power consumption go down, and the speed goes up.
While, scaling of interconnects serves to reduce cost, it increases latency (response time) in
absolute value and energy dissipation relative to that of transistors. These increases are due to
relatively larger average interconnect lengths (measured in gate pitches) and larger die sizes
for successive generations. Further, ICs with nanometer-scale devices do have their share of
problems, principal among them are leakage currents and electromigration.
As copper resistivity increases rapidly with decreasing linewidth, the reliability of
interconnects becomes an issue. As more and more transistors can be packed into a single IC
chip, the tiny copper interconnects are required to carry huge current densities over longer
distances in order for all the transistors to work to their full capacity. This results in longer
RC delays due to both line resistance and load capacitance.
For use in the future sub-50 nanometer generations, the limiting factors of the copper-based
interconnect schemes drive the need to invent new interconnect solutions. According to the
International Technology Roadmap for Semiconductors (ITRS), the continued down-scaling
of the features on semiconductor chips is expected to reach 14nm by 2020 [1]. By 2010, the
smallest wiring on the chip should be narrower than 50nm. The table below highlights this
trend predicted by ITRS [1] at certain nodes. With clock frequencies going into the gigahertz
(GHz) regime, the parasitic resistance, capacitance and inductance associated with these
wires will lead to performance bottlenecks related to properties of materials currently used.
Table 1.1: MPU Interconnect Technology Requirements- Long-term years [1]
Year of Production (estimated)
2005
2020
2010
Technology Node (nm)
80
45
14
Total Interconnect Length for 6
1019
2222
7143
metal layers (m/cm 2)
Max Current Density at 1050 C
8.91E+05
5.15E+06
2.74E+07
2
(A/cm )
Interconnect RC Delay for a 1mm
Cu metal wire (no scattering) (ps)
307
966
6207
Vias are the most common source of failures due to the occurrence of high current densities
and inhomogeneous current distributions that causes electron-induced material transport
(electromigration). In addition, processing difficulties in terms of etching ideal via sidewall
profiles and void-free filling of copper will be exacerbated with the decreasing linewidth.
The challenges and limitations of on-chip interconnects at the nanometer scale have led
researchers to seek innovative designs, circuit or interconnect optimization techniques and
material solutions. Solutions such as three-dimensional (3D) interconnects and optical
interconnects, have been proposed to provide alternatives to the metal / dielectric system and
solve the delay / power problems. Table
1.2 highlights their potential as possible
replacements.
Solution
Method
Advantages
Disadvantages
Table 1.2: Comparison of different interconnect solutions
Use Geometry
Use different physics
3D interconnects
Optical Interconnects
Creating a 3D height to
Using light as the main
the conventional flat
driving force instead of
multilayer IC chip,
electrons, with the help of
providing shorter
optical fibers, modulators
"vertical" paths for
and detectors.
connection
Reduces the number and
High propagation speeds
average length of global
Not Bandwidth Limited
wires
Provides chip-to-chip as
well as intra-chip
communication
Poor Thermal
management of internally
stacked active layers.
New system architecture
development required
Specialized components
such as
transmitter/receiver
circuits are needed
161
Radical Solutions
CNT Interconnects
Using CNTs as wires
instead of metallic
material, ballistic
conductors.
Very high current
carrying capability
High thermal
conductivity
Least disruptive of
options
Method of mass-scale
CNT growth with low
resistance contacts is still
unknown
None of these solutions are expected to be used universally over all IC product types as in the
case of Al/SiO 2 or Cu/low-k. This is due to the fact that not all of these alternatives are
suitable for mass production. Though some of them maybe technically feasible, they may not
be used for a number of reasons, both operational and economic. These technical and
economic limitations encourage exploitation of carbon nanotubes (CNTs) as interconnects.
Out of the three highlighted solutions, Carbon nanotubes (CNTs) are the closest possible
replacements to Copper with the ease of integration into current semiconductor processes and
alleviation of the problems experienced by copper, providing a substantially higher resistance
to electromigration and hence fewer failures [2].
CNTs are attractive as nanosize bricks for constructing devices by bottom-up fabrication.
They offer unique electrical properties such as the capacity to carry high current densities
exceeding 109A/cm 2 , ultrahigh thermal conductivity as high as that of diamond, and ballistic
transport along the tube [3]. They have therefore been suggested for use as one of the
possible future wiring materials to replace copper. Figures 1.3 and 1.4 give an illustrative
look at the possibility of CNTs as interconnects.
JOOnm
Figure 1.3: A futuristic picture of a CNT via
replacing Copper. (a) A hole is made in the
dielectric above the metal layer to be contacted. (b)
A catalyst particle is deposited or generated at the
bottom of the via from which the CNT can be
grown (c) 121
Figure 1.4: The current situation of CNTs in vias
- cross-section SEM images of vias with CVDgrown MWNTs. The catalyst particles are based
on Fe and the supporting metal layer is Ta. [51
This thesis highlights and quantifies the significant advantages of carbon nanotubes (CNTs)
over copper as interconnects in IC chips. A brief introduction of the current IC Copper
interconnects technology is provided before a summary of the basic characteristics of CNTs
are reviewed: the different types, their properties and methods of fabrication. Chapter 3 is
dedicated to the understanding of CNTs as interconnects and the design principles and
fabrication methods to demonstrate why CNTs are superior to copper in specific terms of
resistance (conductivity) in vias by providing a simple, but flexible model for calculating and
comparing of different CNT integration strategies versus evolved copper technologies. A
theoretical prediction of the effects of contacts to CNTs, and other performance parameters
are mentioned. Chapter 5 highlights the commercialization of this technology: the market
viability of CNT interconnects, in terms of registering a patent, adaptability of this
technology among market players and a possible business model for this concept.
Chapter 2 Fundamentals
2.1
Current Technology - Copper Damascene Process
The copper damascene process was introduced by IBM in 1997 to allow chip makers to use
copper wires, rather than traditional Aluminum interconnects to link transistors in chips [4].
At that time, the semiconductor industry was driven by the use of Aluminum (Al) as the main
power and clock signal carrying wires on IC chips.
Copper as a conducting material has significant advantages over aluminum. Copper has an
approximately 50% lower resistivity (Cu -1.75pm.cm versus Al - 3.3 pm.cm), higher
melting point (10830C versus 6600 C) and better electromigration resistance compared to
Aluminum. The median time to failure (MTF) of Cu can be two orders magnitude longer
than those of Al-alloys. Furthermore, copper has proven to handle higher current densities up
to 5x10 6 A/cm2 before the electromigration failure of movement of individual atoms through
a wire, caused by high electric currents, which creates voids and ultimately breaks the wires.
This is crucial as the feature sizes shrink through the years, packing in more transistors in one
IC chip.
There is just one problem with Cu. It is widely known that Cu rapidly diffuses into Silicon,
the substrate in which transistors are formed and creates mid-gap states that significantly
lowers the minority carrier lifetime and leads to leakage in diodes and bipolar transistors. Cu
also diffuses through SiO 2 and low-k dielectrics, and therefore requires complete
encapsulation in diffusion barriers. Additionally, there are no known dry etches for Cu,
which prevents fine-scale patterning using this standard technique. Eventually, researchers at
IBM found a way to overcome this last disadvantage - the damascene process.
Figure 2.1 shows the steps of the copper damascene process. It begins with the creation of a
pattern for wires or vias by patterned etching of the dielectric. Sometimes the dielectric (e.g.
silicon dioxide, SiO 2) is etched twice to form the overlapping pattern of wires and vias,
eliminating one metal deposition step and one polishing step. To overcome copper's
tendency to diffuse in silicon, a barrier layer is deposited followed by the seed layer to
encourage copper deposition. The metal is finally deposited and the excess is removed using
Chemical Mechanical Polishing (CMP). The process is repeated many times to form the
alternating layers of wires and vias which form the complete wiring system of an IC chip.
''
'
,Seed laver
trench
Figure 2.1: Illustration of the copper damascene process [4]
Silicon dioxide (SiO 2) is still widely used as the inter-layer insulator with copper. However,
in order to minimize the RC delay of IC chip, research efforts have focused on dielectrics
with low-k dielectric constants such as fluorine-doped or carbon-doped silicon dioxide.
Table 2.1 provides a list of different low-k materials considered for IC production.
Table 2.1: Dielectric constants for several low-k materials
Examples
Low-k Constant
Types
Oxide
Inorganic
Organic / Silicon
Organic
C-doped SiO2
Porous Silica
Polymer Foams
SiO2
Fluorinated Silicate Glass (FSG)
Hydrogen Silisequioxane (HSQ)
Benzocyclobutene (BCB)
FLARE m , SiLK'
Blk Diamond'T , HOSP I M
NanoglassTM
3.9
3.5 - 3.8
2.8 - 3.0
-2.7
2.7 - 2.8
2.5 - 3.0
1.8 - 2.5
Unsuccessful attempts to fabricate metal wires with low-k dielectrics have hindered their
introduction to the commercial IC chip fabrication. For this thesis, SiO 2 is retained as the
dominant interlayer dielectric used in IC chips.
2.2
Design considerations in Copper interconnects
A typical microprocessor design utilizes a hierarchical or "reverse scaling" metallization
scheme (Figure 1.1) where widely spaced "fat wires" are used on upper global interconnect
and power levels to minimize RC delay and voltage drop. Maintaining the power distribution
at a constant voltage through equipotential wires to all Vdd bias points requires increasingly
lower-resistance global wires as the operating voltage continues to scale and switching
frequencies increase.
Figure 2.2 shows the interconnect scaling scenario illustrating how sidewall capacitance can
be mitigated by reducing metal thickness, thereby avoiding any increase in crosstalk as
conductor spacing decreases. However, for this approach, the resistance and current density
in the wire increases with the square of the scaling factor, so RC delay and Joule heating
increase, the latter raising reliability concerns.
1
1I
C
i
(b) A,is
sc,
0.6
0..
0.6
0.6
Figure 2.2: Interconnect scaling scenarios for (a) fixed metal height and (b) fixed metal aspect ratio [331
Additional interconnect performance issues include crosstalk and noise, particularly for local
and intermediate wiring levels, power dissipation, and power distribution. As the transistor
operating voltage continues to scale downward, interconnect crosstalk becomes increasingly
important and noise levels must be reduced to avoid spurious transistor turn-on.
For copper, the resistance that occurs along a conducting metal interconnect is
R=p l ,
A
...
(2.1)
where p is the resistivity of copper at that technology node, I is the length of the interconnect
(or height of a via) and A is the cross-section of the interconnect.
As the lateral dimension of copper approaches the nanoscale regime, deviations of electric
resistivity are observed from that of the bulk Cu material (about 2.2pi -cm if one assumes no
scattering). Size effects play an important role as the lateral dimension of the wire is in the
range of the mean free path of the conduction electrons and below (about 40nm for Cu). For
copper, as the technology node decreases, its resistivity increases due to grain boundary and
scattering effects. Theoretical models such as Fuchs-Sondheimer model and the MayadasShatzkes Model have been done to calculate the resistivity of copper given the length and
width of a wire and the knowledge of its scattering properties and reflectivity coefficients
[20].
In the International Technology Roadmap of Semiconductors (ITRS) 2005, electron
scattering models in Cu have been used to predict the Cu resistivity as a function of line
width and aspect ratio. Figure 2.3 shows a significant contribution to the increase of
resistivity from both grain boundary and interface electron scattering.
40
a:
Linewidth (nm:
Figure 23 Trend in Cu resistivity [11]
2.3
Limitations of copper interconnects - need for a new solution
Copper metallization offers significant performance and improvements in reliability, but
presents numerous integration and reliability challenges. Copper, unlike aluminum, does not
have a self-passivation layer. Exposed copper surfaces will continue to oxidize, to high
resistance. Copper also does not react with silicon dioxide or most other dielectrics so it has
poor adhesion to them. Further, since copper readily diffuses into silicon and most
dielectrics, copper leads must be encapsulated with metallic (such as Ta, TaN) and dielectric
(such as SiN, SiC) diffusion barriers to prevent corrosion and electrical leakage between
adjacent metal leads. This film has much higher resistivity than copper (e.g. resistivity of Ta
= 13itl-cm), and about 10 - 20% of the wire width can be consumed by the barrier film.
Copper diffusion is greatly enhanced by electric fields imposed between adjacent leads
during device operation (- lxl 05 V/cm), and absolute barrier integrity is crucial to long term
device reliability.
CMP interface:
Met;
Void
adhe
Si Su ate
r
Via resistance: Cu
Oxide, etch residue
Cu Oxide: adhesion
Barrier Effectiveness:
Cu Diffusion through
weak spots, Cu buried
under barrier due to etch
Figure 2.4: Dual Damascene Integration Concerns [33]
Weak via: nitride
undercut
Figure 2.4 highlights some of the main concerns with the copper damascene process - voids,
barrier effectiveness, etch ratios and adhesion. With the continued scaling down of the
technology node, the cross-sectional dimensions of on-chip interconnects are of the order of
the mean free path of electrons in copper (40nm at room temperature).Copper interconnect
resistivity increases due to the increased scattering of electrons at the surface and grain
boundaries of copper atoms. As wire widths scale down, an electron will be subject to more
reflection at the surfaces, so the collisions with the surfaces will become a significant fraction
of the total number of collisions. In addition, grain boundaries in the polycrystalline films
may act like partially reflecting planes located perpendicular to the electric field, so they also
contribute to the resistivity increase. This is further aggravated by the presence of a highly
resistive barrier layer, playing a more significant role at smaller dimensions. The scaling of
IC technology also places higher current density demands on interconnects as shown on
Table 2.2.
Table 2.2: MPU Interconnect Technology Requirements - Long-term years [1]
Year of Production (estimated)
2005
2010
2020
Technology Node (nm)
80
45
14
Total Interconnect Length for 6
1019
2222
7143
metal layers (m/cm 2)
Max Current Density at 105 0C
8.91E+05
5.15E+06
2.74E+07
(A/cm 2)
Interconnect RC Delay for a 1mm
307
966
6207
Cu metal wire (no scattering) (ps)
Together these requirements cause a significant rise in interconnect temperatures, especially
global metal layers which are farthest away from the heat sink. These high temperatures
become a major concern for interconnect reliability as the median time to failure due to
electromigration depends exponentially on metal temperature. For contacts and local vias that
have the smallest cross-sectional dimensions among the on-chip interconnects, currentcarrying capability is a major concern.
The maximum allowable current density for interconnects is also dependent on the
electromigration (EM) lifetime, which is exponentially dependent on metal temperature.
Figure 2.5 shows that EM and thermal constraints make the current density requirements
unachievable beyond 45nm technology node [32].
x 10in
2.0
E 1.8
1.6
S1.4
c 1.2
0
E
E
10
0.8
0.6
0.4
0.2
S 10"
10.3
102
10 ",
100
Duty Ratio
Figure 2.5: Maximum allowed RMS current densities for local vias under self-consistent Joule heating
and EM lifetime constraints [321
While typical local interconnect delay is expected to decrease with decreasing feature size,
global interconnect delay increases. It is observed that in the older 1.Opm Al/SiO 2 technology
generation the transistor delay was -20ps and the RC delay of a Imm line was -l.0ps. In
contrast, in a projected 0.035tm Cu/low-k technology generation, the transistor delay would
be -1.0ps and the RC delay of a Imm line would be -250ps. Repeaters (inverters) are
inserted at regular intervals to drive signals faster to reduce RC delay at global scale, but
these repeaters can contribute significantly to total chip power dissipation, which is a critical
problem for high-performance IC chips. This dramatic reversal from performance limited by
transistor delay shows clearly the inadequacy of continuing to scale down the conventional
metal/dielectric system to meet future interconnect requirements. A natural progression to
22
overcome these limitation of copper interconnects is to consider carbon nanotubes (CNT) as
a feasible solution.
Proposed Technology - Carbon Nanotubes
2.3
Carbon nanotubes (CNTs) are tube-like structures that can be thought of as rolled up sheets
of graphene. The unit cells are hexagons, similar to that of graphite, where every carbon atom
is covalently bonded to three of its neighbors and the fourth electron is free to move over the
whole structure (delocalized sp 2 hybridization). Nanotubes can be fabricated in two basic
forms: either as single-wall cylinders (SWNT) or as wires that consist of a set of
concentrically arranged cylinders (MWNT).
(a)
(b)~
..
4c .
ic
.. ~
. . . .'
k-
'h~x2
<
~~
4
Figure 2.6: Atomic configuration of (a)
Figure 2.7: Indexing scheme for a SWNT in terms of
armchair (n, n), (b) zigzag (n, 0), and (c)
general (m,n) CNTs.
integer pair (m, n).
From the way the graphite sheet gets rolled up into a tube, Figure 2.6 shows three commonly
known CNTs. The indexing scheme shown in Figure 2.7 enables one to determine the type of
CNT considered in terms of integer pair (m,n) from the Bravais lattice vectors R=mal + na2
that spans the whole circumference of the tube. The (n,n) tubes have the "armchair" chains
and (n, 0) the "zigzag" chains. In between these two types, the tubes are generally known as
chiral tubes, (m,n).
The CNT's metallic or semiconducting properties depend on the chirality and diameter of the
tubes and the valleys and peaks of their valence and conduction bands with respect to the
Fermi Level. This is represented by the following equation
Ev =E(-,=o)=-- 3tao v- 2m
,
... (2.2)
where I ao I is the length of the carbon-carbon bonds, I t I is the Hamiltonian Matrix element
between neighboring carbon atoms and I D I is the shell diameter and v is an integer less than
m. If m is a multiple of 3, there will be a value of v where Ev = 0 corresponding to metallic
CNTs.
The study by Wilder et al. [7] showed that carbon nanotubes of type n-m=31, where I is zero
or any positive integer, are metallic. The fundamental gap (HOMO-LUMO) would therefore
be 0.0eV. These are mainly armchair and some zigzag tubes (about 1/3 of the total number of
tubes produced). Besides these, all other nanotubes behave as semi-conductors.
Metallic Nanotube (9,9)
f
0.1
0.1
C
t,1
Oc
1
0
Energy (eV)
-1
1
0
Energy (eV)
Figure 2.8 Density of States for a metallic and semiconducting tube
At the Fermi Energy level (the highest occupied energy level), the density of states is finite
for a metallic CNT (though very small), and zero for a semi-conducting CNT. As energy is
increased, sharp peaks in the density of states, called Van Hove singularities, appear at
specific energy levels.
2.4
Methods of fabricating CNTs
CNTs can be prepared using many techniques. The three widely used methods of fabricating
CNTs are as follow: the electric arc method, the laser vaporization of graphite, and the CVD
method of depositing catalyst and growing tubes out of it. [8]
Iijima discovered CNTs during an electric arc experiment in a gap between two graphite rods
in a non-atmospheric (vacuum) environment in 1991. A cylindrical chamber was filled with
flowing helium (He) at about 500 Torr. A voltage of 20-25V was applied across a gap of
Imm as shown in Figure 2.9. The arc generated a very high temperature of more than 3000TC
for vaporization of graphite into a plasma to form CNT bundles, fullerenes and amorphous
carbon which were deposited on the negative electrode.
Window
Figure 2.9: Carbon Arc experimental setup for CNT synthesis [8]
For the formation of isolated SWNTs, single metal catalysts such as cobalt, nickel or iron are
added before the process starts. Combinations of such catalysts Fe/Ni, Co/Ni and Co/Pt yield
ropes of SWNTs. For MWNT synthesis, no catalyst is needed.
As for the laser vaporization of graphite, a quartz tube is heated up to 1200 0 C (see Figure
2.10). A composite target of 1.2 atom % of Co-Ni catalyst mixed with 98.8% graphite is
irradiated with energetic laser pulses. The vaporized products are swept away by argon (Ar)
gas and condensed on a water-cooled Cu collector downstream.
More than 70% of the evaporated graphite is converted to ropes of SWNTs. The ropes have
diameters typically in the range of 10-20 nm, and each rope consists of a bundle of SWNTs
aligned along a common axis. The diameters of these SWNTs are peaked around 1.4 nm.
furmace
at 1200' Cesius
argor
noodymrum-ytrlnum-
auminum-garnmet
lser
Figure 2.10: Laser Vaporization Method 181
The distribution of nanotube diameter can be changed by adjusting the growth temperature,
the catalyst composition and other growth parameters.
The previous two methods produce CNTs at very high temperatures. This is not compatible
with typical IC chip interconnect fabrication processes where most temperature steps are
carried below 6000 C. In contrast, Chemical Vapor Deposition (CVD) can be used to
synthesize CNTs at relatively low temperatures.
The concept of CVD synthesis of wires was first introduced and explained in 1964 by
Wagner and Ellis [9] where silicon nanowires were grown on a silicon substrate. Using a
similar concept for carbon, a silicon substrate decorated with catalyst (Co, Ni or Fe) particles
is exposed to hydrocarbon (e.g., CH 4 , C 2H6 ) and H2 gases as shown in Figure 2.11.
Figure 2.11: CVD method schematically shown by Wagner et al 191
At a substrate temperature of about 7000 C and lower, carbon nanotubes grow from the
catalyst spots. The catalyst spots either remain at the bottom or the top tip of the tube during
the growth process. Large quantities of CNTs can be fabricated with a patterned array of
catalysts, ensuring a controlled growth process. These aspects of the vapor growth method
make it a favored synthesis technique among researchers and companies for many
applications, such as field-emitter arrays for flat panel displays.
2.5
Properties of CNTs that encourage its use as possible interconnects
Remarkable electrical properties can be seen from the structure of CNTs. The electrical
conduction of carbon nanotubes are widely varied from semiconductor to metal depending on
the chirality of the tube.
In 1998, Stephan Frank et al. experimented on the conductance of nanotubes. [12] Using a
scanning probe microscope (SPM), he carefully contacted nanotubes with a mercury surface.
His results revealed that the nanotube behaved as a ballistic conductor with quantum
behavior. The MWNT conductance jumped by increments of I Go as additional nanotubes
touched to the mercury surface. Go is defined as the quantum conductance of a typical D
electronic system, Go= 2e2/h. When calculated, it was found to be 1/12.9 k'
- 1.
The
coefficient of the quantum conductance was found to have some surprising integer and noninteger values, such as 0.5 Go. In the same paper, he was able to show that CNTs can reach
current densities greater than 107A/cm 2. This fundamentally proves that CNTs have
remarkable electrical properties, capable of replacing copper wires as interconnects.
CNTs are good conductors with long electron mean paths. For SWNTs, resistance is assumed
to be independent of length up to I gm, which defines the ballistic mean free path in a CNT
[5]. SWNTs' typical range of diameters is between 1-20nm.
When a graphite sheet is wrapped to form a SWNT (Figure 2.12), the momentum of the
electrons moving around the circumference of the tube is quantized. The result is either a
one-dimensional (1D) metal or semiconductor depending on how the allowed momentum
states compare with the preferred directions for conduction.
Metallic
Semiconducting
Figure 2.12: Different properties of CNTs based on chirality [Courtesy of Prof Thompson]
For the application of interconnects, metallic CNTs are preferred for its ballistic conduction
capabilities. Researchers who have been working on CNTs have found that a SWNT has four
ID channels in parallel due to spin degeneracy and the sub-lattice degeneracy of graphene
[21]. By the Landauer formula, the conductance is
,
G=
...(2.2)
where e is the electron charge, h is the Planck's constant, and T is the transmission
coefficient for electrons through the sample. The conductance of a ballistic SWNT with
perfect contacts (T= 1) is then
4e2
GQ = 4
R
h
-_
= 2Go = 155pS
h = 6.5kO
4e2
... (2.3)
The presence of scatterers that give a mean free path lo (typically 1gm) for backscattering
contribute an ohmic resistance to the tube of length I
RL
.
RL= 4ehI
2 10
... (2.4)
Included in the equation 2.4, are the terms of ballistic conductance and another of the length
dependence. For small lengths of less than 1gtm, the length dependence can be approximated
to that of ballistic conductance. However for longer lengths, this length dependence has to be
included to provide a realistic picture of conduction in CNTs.
Imperfect contacts will give rise to an additional contact resistance RCONTACT. Hence, the total
resistance of a CNT is
RCNT =RQ + RL + RCONrAC r
...
(2.5)
This basic equation (2.5) can be applied to both SWNTs and MWNTs.
A bundle of metallic SWNTs it can be taken as a bundle of conductive wires in the form of a
cable so that the its resistance drops by the number of identical SWNTs, nswNT
RSWAT bundle = RsW
.
...
(2.6)
SW'NT
The coupling between the adjacent SWNTs in a bundle is neglected. However, this is a
proper treatment as it has been shown that there exists a large tunneling resistance
(-2 - 140MO) between the CNTs forming a bundle. [17]
It is not realistic to grow a densely packed array of metallic SWNTs in a bundle since only a
third of tubes grown are truly metallic. One way of achieving so is to define a fraction of
CNTs that is metallic, e.g. fmeta•ic, so that this fraction and the packing density could be
independently varied.
Models have been developed to calculate conductance of a sparsely packed bundle of
SWNTs [17]. One such model is from Srivastava's paper, where they have managed to come
up with a theoretical model to pack SWNTs in a rectangular via [17]. As shown in Figure
2.9, each CNT is surrounded by six immediate neighbors, their centers uniformly separated
by a distance 'x'. The densely packed structure with 'x' ='d' (CNT diameter) will lead to the
best interconnect performance. In actual fabrication, not all the CNTs in a bundle are
metallic, x>d, and the diameters are not uniform. Non-metallic CNTs do not contribute to the
current and this is accounted for by considering the distance between the tubes, 'x' >'d'. nw
represents the number of CNTs in 1 row and nH represents the number of rows of CNTs.
W
nw =L
{
nc
nj= h
= nnn H -~
,=nRn
+L1
... (2.7)
if nH is even
nH -1
, if n, is odd
"
Figure 2.13: Calculations on the packaging density of a dense (x = d) SWNT bundle 1171
For a MWNT which has a structure consisting of several concentric shells, the charge carrier
transport along the tube axis is governed by a one-dimensional localized system, within a
characteristic length of about 1lm too [18]. The spacing between shells in a MWNT
corresponds to the Van der Waals distance between graphene layers in graphite,
approximately is 0.34nm [19].
Over the years, various researchers have been trying to understand the behavior of a MWNT.
It was originally thought that conductance in a MWNT occurs only at the outermost shell as
experimental results of MWNTs were seen to follow the 4e 2/h conductance that of a SWNT.
Later on, it was found that early experiments made contacts only to the outer shells and due
to weak inter-shell coupling, the inner shells had a small impact on overall conduction.
Recently, Li et al [19] have shown that with proper coupling of all the shells, every shell of
the MWNT, contributes to the saturation current to obtain a high current-carrying capacity,
resulting in a multi-channel electron transport.
In May 2006, Naeemi and Meindl came up with compact physical models to calculate the
conductivity of a multi-wall carbon nanotube interconnect [22]. Considering the band
structure of CNTs, the total number of channels for each shell can be written as
Nchan=/shell
=1
all subbandsexp
... (2.9)
E
E,, / kT) +1
all subbands
exl23ta
D
n 2
3
kTm
Looking at equation (2.9), the number of conducting channels in a shell is a function of
temperature and whether the shell is metallic or semiconducting. Increasing the temperature
is equivalent of increasing the diameter because the contribution of each subband is
determined by its distance to the Fermi level Ev normalized to the thermal energy KBT, where
Ev is inversely proportional to diameter.
SN'
"• ( ..
ii
:lnSticdu
kr hc:l
D4))
it'!
T
.
.
11N
Figure 2.14: Number of conduction channels per graphene shell versus shell diameter for metallic and
semiconductor shells. The average number of conduction channels is also plotted assuming that
statistically one-third of the shells are metallic. 122]
Assuming that the shells have random chiralities, statistically 1/3 of the shells are metallic
and rest are semiconducting. The authors went to derive the following equations (2.10 and
2.11) for the number of conducting channels based on the diameter of a MWNT [22].
Nchan = ZNchjo,,sIeII(D)
... (2.10)
all shells
and
Nea,, = I+
N
DmxDmm'
-a(Dax +Dmin )+ b
=
.. 2(,,,+[Dmax
I
-Dmin2
for Dm,
> 6nm
for Dx < 6nm
... (2.11)
where a = 0.0612nm-', b = 0.425, Dm,ax is the outer diameter, Dmi, is the diameter of the inner
most tube and 6 = 0.34nm is the interval between 2 MWNT rings. The conductance of a
MWNT is then calculated by multiplying the number of channels, Nchan with the quantum
conductance value Go. This equation is only valid for small voltages. This can hold for
interconnect applications where low-bias conductance is observed.
Carbon nanotubes are also stable at high temperatures. They are very stable in an Argon (Ar)
environment, and very resistant against strong acids. The thermal conductivity of carbon
nanotubes is dependent on the temperature and the large phonon mean free paths. As shown
in Figure 2.15, the thermal conductivity of '2 C (diamond) is about 30W/(cm.K). It is reported
that the thermal conductivities can go up to more than 300W/(cm.K) in an armchair CNT,
(10,10) [11].
4x10 4
!RON1 (Fe)
S3x10
SILVER (Ag)
DIAMOND
:NATURAL
ISOTOPE RATIO)
DIAMOND
(PURE '!C)
4
2x10
1x10 4
O wl0
0
.i 0 15 2.0 25 30
THERMAl. CONDUCTIVIT1'TY Wim
4
xA~
35
))T
0
100
200
[K]
300
400
Figure 2.15: A graph of the thermal
Figure 2.16: Thermal Conductivity of (10,10) CNT
conductivities of iron, silver and diamond 1241
as a function of temperature 11l]
Figure 2.16 shows the thermal conductivity of CNTs as a function of temperature, essential
in the application of CNTs in IC chips where IC chips are subjected to operating
temperatures over 1000 C. Thus, CNTs which are a material of such very high thermal
conductivity can be used as a material of the thermal conductors whereby heat generated in
the semiconductor elements such as the transistors might be more efficiently dissipated.
These remarkable electrical and thermal properties make CNTs strong contenders to replace
Cu interconnects. Table 2.3 summarizes the main advantages of metallic CNTs.
Table 2.3: Most important properties of metallic carbon nanotubes
Electron Transport
Maximum Current Density
2.6
Ballistic, no scattering
101oAcm -2 (experimentally)
Quantized Resistance
6.45k0
Diameter
Length
Thermal Conductivity
1 - 100nm (SWNT/MWNT)
Up to mm scale
Up to 2000 W/mK
Piezoelectric strain (Al/1)
0.11% at 1V
Other Remarkable Properties of CNTs
Carbon in the form of diamonds has a Young modulus of 1050 - 1200GPa. Since CNTs are
mainly made up from the same elemental material, they are predicted to have of a similar
Young Modulus range. When SWNT properties were studied, it was found that the bonds
between the carbon atoms are very strong and stiff Table 2.4 shows that the Young's moduli,
tensile strength and density of carbon nanotubes are a lot higher than commonly used
materials.
Table 2.4: Comparison of CNT with some of the toughest materials [10]
I)ensity (g/cm 3)
Tensile Strength (GPa)
MaterialI
Young's modulus (GPa)
150
1054
Single wall nanotube
150
1200
Multi wall nanotube
208
Steel
1.25
0.005
Epoxy
0.008
0.6
Wood
One of the more fascinating potential applications is to use carbon nanotubes as electron field
emitters for flat panel displays. CNTs have the excellent material properties of a large aspect
ratio (>1000), atomically sharp tips, high temperature and chemical stability and high
electrical and thermal conductivity, required to be effective field emitters. Below is a
summary of properties of carbon nanotubes.
Table 2.5: Quick Facts about Carbon Nanotubes [101
Equilibrium Structure
Average Diameter of SWNTs
Carbon Bond Length (Line 4)
C-C Tight Bonding Overlap Energy
1.2-1.4 nm
1.42 A
- 2.5 eV
Lattice: Bundles of Ropes of Nanotubes: Triangular
Lattice(2D)
Lattice Constant
17 A
Lattice Parameter:
16.78 A
(10, 10) Armchair
16.52 A
(17, 0) Zigzag
16.52A
(12, 6) Chiral
Density:
(10, 10) Armchair
(17, 0) Zigzag
(12, 6) Chiral
Interlayer Spacing:
(n, n) Armchair
(n, 0) Zigzag
(2n, n) Chiral
1.33 g/cm 3
1.34 g/cm3
1.40 g/cm 3
3.38 A
3.41 A
3.39 A
Optical Properties
Fundamental Gap:
For (n, m); n-m is divisible by 3 [Metallic]
For (n, m); n-m is not divisible by 3 [SemiConducting]
0 eV
-0.5 eV
Electrical Transport
Conductance Quantization
Resistivity
Maximum Current Density
n x (12.9 kl)-1
10-4 f)ecm
1013 A/m2
Thermal Transport
Thermal Conductivity(RT)
Phonon Mean Free Path
Relaxation Time
- 2000 W/m*K
- 100 nm
~ 10-11 s
Elastic Behavior
Young's Modulus (SWNT)
Young's Modulus (MWNT)
Maximum Tensile Strength
-~ 1 TPa
1.28 TPa
-30 GPa
Chapter 3 Carbon Nanotubes as Interconnects
The ability of CNTs to carry high current densities with a fixed resistance over several
micrometers makes them attractive for on-chip interconnects in microelectronics. However,
the most critical components are the vertical interconnects (vias) between the metal layers.
Higher contact resistances at the boundaries between the vias and the lower metal layer
together with the narrowing of the vias at the base contacts leads to an enhanced risk of local
heating and electromigration.
In this chapter, a detailed analysis of CNT interconnect performance compared to copper
interconnects in vias is done to highlight its strong points. Later on, a theoretical study on
other performance aspects of CNTs as vias will be examined.
3.1
Fabrication of CNT Interconnects
Currently in research, there are two different approaches in growing bundles of (mainly
MWNT) nanotubes as interconnects using the CVD method.
Li et al [13] proposed the "bottom-up" approach. The CNT is grown on a metal 1 layer
before the deposition of the inter-metal dielectric (IMD). Lithographically defined Nickel
spots act as catalyst particles, from which carbon fibers are grown by plasma enhanced
chemical vapor deposition (PECVD) at temperatures below 700TC. During the growth
process, the fibers need to be as straight as possible to ensure ballistic conduction.
Subsequently, SiO 2 is deposited and the wafer is planarized using chemical mechanical
polishing (CMP). The last step also opens the nanotube ends for contact with the second
metallic layer. A very high resistance of about 600k() per CNT has been evaluated with this
approach, which may be attributed to the imperfect structure of PECVD grown MWNTs. The
approach is suited for single-MWNT filling because high-density growth could not be
demonstrated.
PECVDI
Catalyst
Patterning
mli
Metal
Deposition
Top Metal Layer
Deposition
TEOS CVD
TS
CM
I
II
Figure 3.1: Schematic of the Li group's Bottom up approach process 1131
An alternate approach is the "buried catalyst" method. The vias are etched down to the Metal
1 layer and the CNTs are grown in these vias. This has been the focus of two research
groups, Nihel et al [14] of Fujitsu Ltd and Kreupl et al [5] of Infineon Technologies.
Ti
0
.-Co
-(Ti
-Ii
T
-41]
*'I":
I
Cu
II
Figure 3.2: Schematic of the buried catalyst approach by the Nihel group[14]
Nihel et al deposited on top of a Cu layer (300nm); a Ti contact layer (50nm), a Ni (or Co,
Fe) catalyst layer (10nm) and a SiO 2 dielectric layer (350nm). After the deposition of SiO 2
layer, via holes were patterned using conventional g-line lithography and anisotropic dry
etching with fluorine-based gases. CNT-bundles of 1000 MWNTs were grown selectively in
via holes by using hot-filament CVD (HFCVD). The figure suggests that the Ti and catalyst
layers are deposited after oxide deposition and patterning. The resulting MWNTs have outer
diameters of about 10Onm with well-graphitized graphene sheets using Ni and Co catalysts on
Ti contact layers. Gas sources were a mixture of C2 H2, Ar and H2. The CVD chamber
pressure was set at IkPa. The substrate temperature during growth was 5400 C. The CNTs
were cut mechanically by CMP with diamond slurry. Finally, the upper Ti contact layer
(50nm) and a Cu layer (300nm) were connected to the CNT vias. A resistance of-134ko per
MWNT has been achieved partly due to the high quality nanotubes grown by HFCVD.
Krepul et al [5] developed a similar buried catalyst approach. However, by performing a pure
CVD approach to produce high quality tubes, they succeeded in lowering the via resistance
to about 10kU per MWNT. In order to manage the via etch stop on the 2nm catalyst layer, a
catalyst multilayer stack has been developed, which allows proper landing on a catalyst layer
with reliable growth of MWNTs. Krepul's catalyst layer consists of a triple stack (3nm Fe,
5nm Ta) deposited on Metal 1 prior to the deposition of 150-200nm SiO 2 . Electron beam
lithography in combination with a hard mask technique was used to define the 20nm vias.
The MWNTs were grown by CVD at 450 - 7000 C. It was found that the quality and yield of
the CNT-vias rise with growth temperature. The top MWNTs are then encapsulated with a
thin SiO 2 layer either by using spin-on glass or through a PECVD deposition process. CMP
was then performed to expose the end of the MWNTs. This step prevents metallic whisker
formation during the top contact preparation, which may affect the resistance measurements.
Annealing steps in a reducing atmosphere lowers the resistance further. This is due to
improvements of the bottom and top contacts.
3.2
Design Considerations for CNT interconnects
3.2.1
Research on SWNT bundles as Interconnects
This section highlights key analyses of research groups who strongly believe that SWNTs, in
particular SWNT bundles will become possible replacements to copper for interconnects in
the near future.
A single-walled CNT (SWNT) is very close to an ideal quantum wire in which electrons can
move in one dimension only. The phase space for scattering in nanotubes is therefore very
limited; electrons can be scattered only backwards. The mean-free path in a high-quality
nanotube therefore is in micrometer range.
Burke et al proposed a SWNT theoretical model to quantify the electric properties of SWNTs
using Liittinger liquid theory [15]. The DC circuit model for a one-channel quantum wire of
non-interacting electrons is well known from the Landauer-Biittiker formalism of conduction
in quantum systems. In AC, a CNT is believed to be equivalent to a transmission line with a
distributed "quantum" capacitance and kinetic inductance per unit length. The presence of
electron-electron interactions can be included as electrostatic capacitance and magnetic
inductance is included (Figure 3.3).
RF;2
Lcjr
Driver
R=!2
LCNT
4CC
4CQ
C=
CE
I
Load
Figure 3.3 Equivalent circuit model for an isolated SWNT, length less than the mean free path of
electrons, assuming ideal contacts 1151
Neglecting electron spin and sublattice degeneracy, the dc conductance of an ideal (ballistic)
e
quantum wire is independent of length and is equal to -, where h is the Planck constant and
h
e is the electron charge. The current carriers in a nanotube occupy the one-dimensional
conduction bands with very low density of states, and hence the kinetic energy stored in
current is so large that it results in a very large kinetic inductance per unit length [15].
1K
2e
2e2v
...(3.1)
where vf is the Fermi velocity of CNTs, 8 x 105m/s. The kinetic inductance per unit length of
CNTs is therefore around 16nH/lm, more than four orders of magnitude larger than its
magnetic counterpart oflM = lpH /pm.
Srivastava et al simulated the electrostatic capacitance of a typical SWNT bundle in a square
conductor [39]. It was shown that the electrostatic capacitance of a SWNT bundle
interconnect is mainly from the CNTs lying at the edges of the bundle that are capacitively
coupled with the adjacent interconnects as well as the substrate. Figure 3.4 provides an
insight to the calculations made.
C.
C II
2
C=
CC
C'f
44r
=
2
1
5;
(11)
CE
4
M
97
(4
I nrr
•
Jl
11
Substrate
1
4
Figure 3.4: Schematic of CNT-bundle interconnect. Elements labeled with numbers are the ones
characterizing the electrostatic coupling capacitance of the CNTs along the edges of the bundle. Each
circular cross-section CNT is shown along with the circumscribing square conductor. CEn and CEf are the
intrinsic plate capacitances. [39]
To add electric charge to a quantum wire, one must add electrons to available states above
the Fermi level (Pauli Exclusion Principle); hence there is a quantum capacitance of
CQ =(
2e 2
... (3.2)
vhY-
in series with the electrostatic capacitance of CE ,50aF1/1m
[15]. The quantum
capacitance of a CNT is 100aF/pm, and is of the same order of magnitude as its electrostatic
counterpart.
As shown in Figure 3.5, electron spin and sublattice degeneracy result in four parallel
channels through which three spin modes and one charge mode can travel [15].
~~~~lr
'i
Spin
Spin up
Spin down b -
Figure 3.5: AC circuit model for interacting electrons in a carbon nanotube [15]
The wave propagation speed for the charge mode is
v=
F4
1
+ 4C o
7 - 1CE
... (3.3)
Due to large values of contact resistance and characteristic impedance of a single nanotube,
connecting nanotubes in parallel lowers the overall resistance and inductance, making a
bundle suitable for interconnect applications. Furthermore, since the coupling between
nanotubes within a bundle is weak [39], good contacts to most nanotubes within each bundle
are needed so that most nanotubes contribute to conduction.
Naeemi et al considered various scenarios of effect of latency on CNTs, including the latency
of SWNT bundles and copper interconnects implemented at 22nm node versus interconnect
length for Lo= 0.1rpm, 1pm and 10pm [38]. From Figure 3.6, it was shown that nanotube
bundles can outperform copper wires unless they have very short mean-free paths (- 0.1 pm).
I_____~_________·_____________________~~_
L.-
$S
_·___
4CNTBandlaML4-O0 5fl
S.CapperlInteroesa
--•CNBundleals.
I=mI
,,--•C.Lr
undkIrO•
/
3
E[
SI
-
n5
0
1
10
Electron Mean Free Path in SWCNs, L (pnm)
Figure 3.6: Inset: Latency versus interconnect length for minimum-sized copper wires implemented at
the 22nm node and bundles of SWNTs with electron mean-free paths of 0.1, 1 and 10imn, assuming that
SWNT resistance increases linearly with length. Main plot: Maximum performance enhancement that
can be achieved by using CNTs versus electron mean-free path in nanotubes for four various technology
nodes. [38].
At nanometer scale dimensions, high copper resistivity and current densities result in higher
self-heating of copper interconnects. The metal temperature (Tm) rises significantly above the
junction temperature especially at the topmost interconnect layers even though copper has a
high thermal conductivity Kth, Cu of 385W/mK. Together with the use of low-k dielectrics of
low thermal conductivities (Kth,
ILD
< 0.4W/mK), heat conduction from the interconnect
layers to the heat sink becomes difficult. All these factors affect the electromigration lifetime
of copper interconnects.
It is predicted based on experimentation that the thermal conductivity of a SWNT bundle,
Kth. SWNT is in the range of 1750-5800 W/mK at room temperature [40]. This high value of
Kth, SWNT is in the direction along the length of the nanotubes since thermal conductivity in
CNT bundles is anisotropic [41]. Figure 3.7 shows that even when CNT bundles are used
only as vias integrated with copper interconnects, maximum interconnect temperature is
much smaller.
6500
-n300
Fr
CNT-bundle vias
S100
22
X
2
32
45
Technology node (nm)
Figure 3.7: Maximum interconnect temperature rise for Cu interconnects and vias versus CNT bundle
vias integrated with Cu interconnects [17]. For CNT bundles, the shaded region shows the range
1750W/mK < Kth < 5800W/mK. Reference (substrate) temperature = 378K. [17]
Over the past few years, these researchers have accurately modeled conduction with SWNTs
but at present, no CVD process has been presented for the creation of bundles of SWNTs in
vias. Though theoretically SWNTs have proven to have the advantage of copper, it remains
to be seen whether SWNTs can be implemented realistically in a commercial process.
3.2.2
Research on MWNTs as Interconnects
As highlighted in Section 3.1, unlike the SWNT researchers, groups from Fujitsu and
Infineon have grown an array of MWNTs in a single metallic layer vias surrounded by SiO 2
dielectric. Through experimental procedure and characterization, researchers infer back to
understand possible reasons of MWNT behavior in vias.
PECVD is most encouraged to be used for its low temperature procedure. The ion
bombardment during PECVD encourages the breaking up of the catalyst layer into particle
sizes. Careful material and interface design in combination with low temperature budget and
time dependent diffusion phenomena, needs to be taken into account to guarantee CNT
growth.
The quality of nanotubes determines the conductivity of the tube and affects its performance.
This depends on the number of shells, their parallelism with the CNT axis and possible
defects [37].
Further, the quality and yield of the CNTs rises with growth temperatures.
CNTs grown by PECVD method at temperatures below 6500 C deviate from the perfect
structure. This is highlighted from the resistivity of the CNT tubes.
IV = 11
C
IC
C
Figure 3.8: Factors influencing CNT resistivity: no. of shells and orientation of the graphene planes. 151
As shown in Figure 3.8, ballistic transport can only occur when a1 = 0. The carriers have to
hop from shell to shell which reduces conductivity tremendously because the conductivity
along the c-axis (shell to shell) is a factor 1000 smaller than in-shell conductivity [5].
Ballistic transport can only be expected with well-aligned shells. For a given diameter, the
conductivity increases with the number of participating shells. Thus, the diameter ratio
should be as low as possible.
Forming low resistance ohmic contacts between CNTs and metal electrodes is important to
ensure good conduction. The CNTs' ends are covered with a titanium electrode and titanium
carbide (TiC) ohmic contacts are formed by annealing [14]. Nihel et al used Nickel/Titanium
double layer electrode for the growth of MWNTs. The Nickel spot size controls the diameter
of the tubes grown. It was found that without the presence of Titanium, the resistance of the
CNT tubes was in the MO range. With the introduction of Titanium, it reduced to the kO
range. A final proposed design came about for a via using a combination of cobalt (catalyst
for CNTs), Titanium (for ohmic contact), Tantalum (barrier layer to copper) layers to reduce
the via resistance as much as possible [42]. The two options are compared in Figure 3.9.
C'NT density i CN'ls/cni2
I
1Il!
1"1
103
I
via dialnicter: 2 ill
]4
"'NiUi.
1I 14
141'
10
0
140
1.16
numlnbller of
(C'N'I in vius
Figure 3.9: Dependence of the total resistance of CNT vias on the number of CNTs 1421
The thicknesses of these layers play a part in the lowering of the resistance. Nihel et al
established this in a later paper, by adjusting the thickness of the ohmic Titanium layer. The
X-ray diffraction (XRD) analysis showed that the peak TiC (111) which is formed when
good ohmic contact occurs only exists in the 6nm Titanium layer compared to the 2nm layer.
This indicates that TiC (111) at the interface is essential to good ohmic contact between most
of an MWNT's inner shells and titanium contact layer. With the 2nm layer, the presence of
46
TiO 2 and Co (002) near the surface discouraged the growth of TiC, resulting in higher
resistance contacts.
(a)Ca'? .1i.ir1u "mI
(bi Cull
mu'a~i(2
M71
S..Ti(..l..
0I
1
20 25
1.deg
10
5
10
15
25
20(depJ
•0
30
Mc)
runedo
MWNT
ret
MWNM
condutafl
MwNT
resltaace
iI
T
35
i CTI
TIC
L bo***!**J
T"rc,
bertone
wir
Figure 3.10: XRD patterns of MWNTs/Co/Ti samples (a) Co(2.5nm)/Ti(6nm) (b) Co(lnm)/Ti(2nm).
Cross-sectional view of MWNTs/Co/Ti/Ta/Cu bottom layer structures (c) Co(2nm)/Ti(6nm) (d)
Co(lnm)/Ti(2nm) MWNTs with Co nanoclusters inside the ends of the nanoclusters inside the ends of the
nanotubes grew vertically on the Ti contact layers. [431
Although, researchers are improving in their methods of growing MWNTs in a bundle, little
understanding has gone into the theoretical analysis of these tubes. Theorists are still trying
to understand how a MWNT works - whether conduction occurs only along the outer shell or
that all the shells of a MWNT can conduct. It was only recently in 2006 that a theoretical
analysis was done by Naeemi, to provide a more substantial stand that MWNTs can take over
copper too [22]. The analysis of its model has been covered in the Chapter 2.5 equations 2.10
to 2.12. With improvements in the fabrication process and the theoretical analysis, MWNTs
have a better chance for possible integration into the IC semiconductor process.
3.2.3 PatentedDesigns using CNTs
From a random patent search at the US government website, one key patent that highlighted
the CNT technology was found - US 6,800,886 by Fujitsu Limited, issued on Oct 5, 2004
47
[24]. CNTs, well-known for their high thermal conductivity of 30W/cm.K (as high as pure
12C),
can act as effective heat radiators in an IC chip over copper with the increasing number
of insulator layers in high output power devices. An example of this possible application is
shown in Figure 3.11.
20a
22a
20b
22b
26b
Figure 3.11 Cross-sectional view of semiconductor device; CNTs in vias are labeled as 42 and Cu in vias
are labeled as 34 [24]
In the patent, the authors were non-specific into the CVD methods of growing the tubes, the
type of tubes grown (whether single or multi-walled) and catalysts used for growth. The
group showed foresight in their vision of CNTs as they highlighted many possible CNT
placement strategies for IC chips, whether in the vias, directly from the substrate to surface
and even as horizontal CNT tubes.
Recently, Dublin et al in Intel had a bigger picture in mind by combining the advantages of
3D-interconnection and CNTs to create 3D CNT-integrated circuits (Figure 3.12). Appendix
2 shows a flow diagram for embodiments of methods for fabricating carbon nanotube
48
integrated circuits - a multi-layer dielectric structure filled with CNTs. Dublin et al believe
that going into 3D CNT-integrated circuits is the only way of making a scalable commercial
production using CNTs not only as interconnects but also as part of the FETs through the
controlled doping of semiconducting tubes. They argue that it will only be a matter of time
before this becomes reality.
16
Figure 3.12 Sectional view of two stages of fabrication of CNT ICs using CNTs (labeled as 152) [125]
3.3
Resistance Model for CNTs versus Copper Interconnects
From the literature survey on CNTs in interconnects, it has been shown that CNTs, both
SWNTs and MWNTs can perform much better than copper in terms of its capability to
handle high current densities. In this section, analyses of the resistance of interconnects are
presented, to discuss whether CNTs can provide a better alternative to Copper when the
industry scales down the technology node from 80 to 14nm. Two areas of local interconnects
are explored - the vias and the long wires. Vias are known to be the first sources of failure
when electromigration failure in copper wires occurs. An understanding of how to counter
this problem with CNTs will be helpful. For long interconnects, CNTs' ability to carry high
current densities can be exploited if its resistance is close to or lower than that of copper. The
CNT types considered are a SWNT bundle, a single big MWNT in the via, and a MWNT
bundle. Before proceeding to the model results, the assumptions and calculations made in the
design of model are explained.
3.3.1
Assumptions - Interconnect Wire Design in IC chip
In the semiconductor industry, the IC designers follow a set of design rules to optimize the
performance of IC chips for a specific function at a particular technology node. Each foundry
has its own specific preferences in accordance to their manufacturing capabilities, but in
general, there is a set of guidelines called SCMOS Design Rules that fundamentally holds for
all chips.
For this model analysis, a general set of rules will be assumed to predict the most likely
situation for a via. Taking Xas the typical technological dimension, the following dimensions
were taken to simulate a typical via and metal wire connection [See Appendix 1 for Design
Rules from mosis.org].
Although the design rules show that vias are square in shape, when processed through
lithography and etching, the edges become curved leading to circular vias rather than the
square vias originally laid out. For accurate analysis, both shapes are considered for this
model.
I
2j
0
I
01
21
Figure 3.13: Cross-section of Square Vias with design rule specifications (On left, CNT, right, Cu via).
The shaded area is to account for Cu barrier thickness
Figure 3.14: Cross-section of Circular Vias when manufactured (On left, CNT, right, Cu via) The shaded
area is to account for Cu barrier thickness
Via
Via Height
Metal 1
Figure 3.15: A one-tier metal layout view of a via between 2 metal layers. The dimensions given are
assumed for the resistance model.
The heights of vias in various technology nodes are assumed to be of a particular height in
various papers on the study of CNTs in vias [13-19]. The heights of CNT-filled vias tend to
go Ilm or below for various circular diameters of vias from 20nm to 250nm. For this
resistance model, a range of lengths is considered. For vias, the lengths range from 0.1 to
1Am and for the long horizontal interconnects from 1 to 10Im.
3.3.2 Assumptions and Calculationsfor Copper Interconnects
It is assumed that the copper wires are ideal and free of voids that might cause failure much
more easily. Copper wires need diffusive barriers around the circumference of the wire to
prevent copper diffusing into silicon or dielectric. For the model, this thickness is defined by
the ITRS and also scales down with the technology node as shown in Table 3.1.
Technology Node
Table 3.1: Specifications for copper at different technology nodes 1I
80nm
45nm
14nm
Metal 1 wiring pitch (nm)
Metal 1 A/R (for Cu)
Cu resistivity for Metal 1(110 -cm)
include scattering & barrier
Cladding thickness (nm)
180
1.7
3.15
90
1.8
4.08
28
2
8.19
6.5
3.3
1.1
Due to the barrier layer, the actual area that contains copper is smaller than that of the
interconnect specifications in the design rule. The predicted ideal copper resistance is based
on the assumption that the material undergoes the following physical changes such as
catastrophic failure due to electromigration, or additional resistance contributed by grain
boundary scattering, sidewall roughness scattering and voids through its resistivity.
Copper's resistance occurs along a conducting wire is
R = pl
A
,
... (3.4)
where p is the resistivity of copper at that technology node, I is the height of interconnect
and A is the cross-section of interconnect.
Ideally, one has to include the resistance of the Ta diffusive barrier to the total resistance.
From section 2.3, the Ta film has much higher resistivity than copper of 13ug).cm, and about
15% of the interconnect area is consumed by this film. The ITRS roadmap has included the
barrier resistivity in its calculations of copper resistivity at each technology node.
3.3.3
Assumptions and Calculationsfor CNT Interconnects
The electronic properties of perfect multi-walled carbon nanotubes (MWNTs) are rather
similar to those of perfect SWNTs, because the coupling between the ring layers is weak in
MWNTs. Thus, electronic transport in metallic SWNTs and MWNTs occur ballistically
(without scattering) over long nanotube lengths (for length <= lAm), enabling them to carry
high currents with essentially no heating.
For simplicity of the model, the tubes are assumed to be manufactured perfectly and free of
impurities. The conductance values calculated are applicable to room temperature conditions
of 300K. As explained in the previous chapter, low-resistance contacts between CNTs and
metal electrodes are important for exploiting the excellent features of CNTs. One good
example is by covering CNTs' ends with titanium electrodes which become titanium carbide
(TiC) through annealing [14]. Thus, the resistance calculated in the model is the ohmic
resistance, RE of the line containing either 1 big MWNT or bundles of SWNTs or MWNTs
using equation 3.5. The idealized quantum resistance is accounted for in the ohmic
resistance, RL.
RL =
... (3.5)
Since different manufacturers use different catalyst for growth of CNTs, resulting in varied
resistance measurements, the contact resistance RCONTACT is neglected in this model.
A bundle of SWNTs can be taken to be a bundle of conductive wires traveling through a
cable, where the resistance drops by the number of identical SWNTs, nSWNT,
RSWT brund - RCAT
C
RL
RL
nSWNT
nSWNT
...
(3.6)
The coupling between the adjacent SWNTs of a bundle is neglected. However, this is a
proper treatment as it has been shown that there exists a large tunneling resistance (-2 140MO) between the CNTs forming a bundle. [17]
A question occurs as to how well one can pack a bundle of SWNTs. Ideally, one can assume
that by calculating the area of a typical SWNT of a certain diameter, you can calculate the
number of tubes, nswNT by dividing the area of a via over the area of SWNTs. Practically,
while growing the tubes in a via, one cannot pack the SWNTs so densely. For this model,
Srivastava's model of packing SWNTs / MWNTs in a bundle [17] is considered. (See
equations 2.7 and 2.8). For a circular via, a percentage of the tubes is estimated, accounting
for the percentage coverage of area of the CNTs to that of a square via.
For MWNTs, this model is approached in two ways since they are more likely to be all
metallic tubes than semiconducting ones. One approach is to consider one single big MWNT
in a via [19]. Another approach is to model a MWNT bundle in an interconnect such as via as
grown by many research groups [13, 14].
For a MWNT with an outer diameter, DMa, and innermost diameter. DMii, the diameter ratio
of a MWNT is defined as
Diameter Ratio =
DMin
DMax
...
(3.7)
This ratio varies in different MWNTs and values between 0.35 and 0.8 have been observed
[19]. The number of walls in a MWNT, Nwalls is defined as
Nwaiis
DMax - D
M in
...
(3.8)
2*8
where 6 = 0.34nm, the distance between the 2 rings of MWNT.
For each of the analysis, two calculations were made to determine the accuracy of the
calculated conductance to experimental data by
1) Considering each shell as a SWNT with a conductance of
G =4e'
...
(3.9)
and calculating the total conductance as G* * Nwalls,
2) Using the equations obtained by Naeemi and Meindl (see Equations 2.10 to 2.12)
to determine the number of channels. The equations are repeated here for reference.
N = 1+
[Dm 2 Dmm
a(Dma +Dmin)+bI
+I
D
-Dmin-)(2
Nchan =
Ncan
= 2 1 + Dmx -min
for Dmx < 6nm
for Dm. >6nm
...
(3.10)
,
where a = 0.0612nni', b = 0.425, Dmax is the outer diameter, Dmin is the diameter of the inner
most tube and 6 = 0.34nm is the interval between 2 MWNT rings.
The total conductance is calculated as G = G* x Ncha,, =
NLec"a
h 10
To determine the resistance of a MWNT bundle, the reciprocal of conductance is considered.
To calculate the packing density of MWNTs in the bundle, the same approach as that for the
SWNT bundles was taken for a fair comparison of results.
Chapter 4 Technical Assessment of CNTs as Interconnects
4.1
Fabrication
Table 4.1 summarizes the key process steps required to create a via using copper and CNTs.
Table 4.1: Comparison of the fabrication process
Copper Damascene Process
CNT Process
Barrier Layer
Ta Layer
Copper Seed Layer
Ti Layer
Copper Deposition
Co Layer
CNTs (by PECVD)
Ti Layer
At first look, the fabrication of CNT vias seems more complicated than the copper
damascene process with the addition of 3 catalyst layers before a low temperature plasmaenhanced CVD (PECVD) process is performed to grow CNT tubes. The additional layers are
necessary to ensure good electrical contact of CNTs to the silicon substrate before growth of
tubes.
The thickness of the catalyst layer affects how well the CNTs are connected to the underlying
layer. There are some studies that indicate that the reaction of titanium and carbon to form
titanium carbide (TiC) encourages a good Schottky contact compared to the use of nickel.
Usually a catalyst layer is deposited over the area where the tubes are grown, not as
individual dots as ideally desired. Thus, the placement of CNTs on the catalyst layer cannot
be controlled to facilitate the densely packed structures.
Through observation of pictures of CNTs being grown in vias such as the one in Figure 1.4,
one notices that CNTs are capable of twists and bends during the growth process. It is quite
hard to maintain straight tubes unless external methods are employed. Some methods
suggested are the use of porous alumina in which tubes are grown and use of electric fields to
guide tubes to erect upright (like magnetism).
Even if grown upright for SWNTs, there has not been a proven way to determine how many
tubes are metallic out of the tubes grown in a via. Currently, it is approximately estimated
that a third of the CNTs are metallic. This shows a weakness in having a repeatable process
to produce CNT vias. Individual characterization of a via has to be done to ensure conduction
is maintained in all vias.
There is also an issue of carbon contamination during the CMP process required to trim
CNTs for each metal layer. Thus, compared to copper, the overall fabrication process will
cost more due to the introduction of PECVD as the main process step, controlled process
growth of CNTs and ensuring as minimal contamination as possible for high yields.
For long horizontal interconnects, the challenge is to grow these tubes horizontally as most
research groups have not shown experimental evidence of this possibility at this point in
time. One suggestion is to apply the microfluidic channel method to flow CNTs (under a
horizontal electric bias field) to the spot desired and connect them together. This ensures
straight CNTs during placement horizontally.
Despite these disadvantages, the performance of these tubes compared to copper vias in
subsequent sections will show its strong advantage over copper with the help of the
resistance model explained in Section 3.3.
4.2
Trend in the resistance of copper
Figures 4.1 and 4.2 depict the trend in the resistance of copper scaling down from 80nm to
14nm. The resistance is calculated using values quoted from the International Technology
Roadmap for Semiconductors (ITRS) [1] and including the effects of scattering and existence
of a barrier layer.
Resistance of Copper (from 80 to 45nm)
ov
7060E
M
506
I--Cu (Sq) (80)
- - - - Cu (Cir) (80)
i.......
Cu (Sq)(45)
- .....Cu
45nm
.
Circular
/
(Cir) (45)'
.
.I "
-S"a..
..
.
SSquare
E 40
S3020 -
."
•
.
80nm
10,
0*
0
2
4
6
Lengthlum
8
10
12
Figure 4.1: Resistance of Copper (from 80nm to 45nm) (Sq: Square area, Cir: Circular area)
In general, since the circular area is lower than that of the square area of an interconnect; its
resistance value is much higher. From 80nm to 45nm, there is an increase of a factor of 4 in
the calculated resistance due to the smaller area and higher resistivity. The same trend is
observed from 45 to 14nm.
Resistance of Copper (from 45nm to 14nm)
1800----
-----Cu (Sq) (45)
Cu (Cir) (45)
1-
1600
1200
E
------------
-
4nm
Cu (Cir) (14)
800
4000
............
0
2
45nm
----..
4
6
8
10
12
Lengthlum
Figure 4.2: Resistance of Copper (from 45nm to 14nm) (Sq: Square area, Cir: Circular area)
4.3
Effects of key parameters on CNT Performance
Both SWNTs and MWNTs have unique characteristics that affect the resistance of the
nanotubes. The parameters considered for SWNT bundles are each tube's diameter and
packing density distance between tubes. For MWNTs, the tube diameter, the ratio between
the outer and inner diameters and the packing density distance between tubes (for MWNT
bundles only). For the following graphs, the general research community's perception of how
SWNT and MWNT resistances are calculated is applied. The consideration of the Naeemi
model for MWNT will be analyzed in a later section. The length of the CNTs is fixed to
1l m.
4.3.1
Effect ofpacking distance on SWNT bundle
Effect of packing distance on SWNT bundles
1800 1600 -
,1400 01200 -
80nm
-45nm
...
14nm
,
-
14nm
,
,
S1000 a
800 -
600
-
400
-
S.
200 -
0-
LOa
•
•Onm
.=•
•=,=='
*45nm
=
J
i
0
2
-
4 disft n 6nrn
1 ckAina
8
10
Figure 43: Resistance of tube (RL) versus the Packing distance between 2 SWNTs
(Each SWNT: Diameter Inm and length of lpm)
As shown in Figure 4.3, the resistance of the interconnect increases when the packing
distance increases for the same technology node. When the packing distance becomes longer,
a lower number of tubes can be used in a fixed interconnect area, reducing the number of
conductive shells required to improve on its conductance performance.
From Srivastava's model for calculating packing density in a bundle, there is an inverse
relationship between the number of CNTs at each side of a rectangular cross-section (nw and
nH) and its packing distance, x.
nw =[ w
,
nH=
j
...
(4.1)
These two variables are multiplied to give the total number of tubes, ncNT in a bundle. The
resistance is then calculated as follows:
RSWNT bundle
R=
a
nCNT
RRLx.
RL
...
2
(4.2)
nWnH
Equation 4.2 shows a parabolic trend of resistance with increasing packing distance. This is
evident in the resulting graph. As one goes down the technology node, the resistance
increases due to the smaller area of interconnect being covered which allows for a lower
number of conducting tubes.
A similar trend was seen to determine the effect of packing distance for a MWNT bundle as
shown in Figure 4.4.
Effect of Packing Density Distance on Resistance of
MWNT bundles
1-'
450- 400 - ....... 14nm
E 350
S300 c 250 -
----
45nm
"
1n4nm -4
a
.J 200 -
15045nm80nm
80nm
10050n
4
5
R
7
Packing Distance / nm
8
9
10
Figure 4.4: Resistance of tube (RL) versus the Packing Distance between 2 MWNTs
(Each MWNT: Diameter 5nm, Diameter Ratio 0.35 and length of 1ptm)
4.3.2
Effect of Outer Diameter on Resistance of Single MWNTs
When considering the properties of one MWNT, for the same diameter ratio in Figure 4.5,
the resistance of the tube decreases. For this study, a general model that each ring in a
MWNT has a conductance of 2Go was adopted. With the knowledge that the distance
between rings is 0.34nm; at a fixed diameter ratio, more rings are introduced into one tube,
resulting in more channels of conduction.
Effect of Diameter Ratio and Outer Diameter of MWNTs on Resistance
35UU
3000
E
2500
2000
u
S1500
1 1000
500
0
0
20
40
60
80
100
Diameter/nm
Figure 4.5: Resistance of tube (RL) versus Outer MWNT Diameter with different Diameter Ratios of 0.35,
0.65 and 0.8. (Each MWNT: length of ltpm and conductance of 2Go in each ring (General model) )
Table 4.2 shows the resistance trend when the outer diameter is doubled for a fixed diameter
ratio of 0.35. It is seen that the number of walls available for conduction doubles resulting in
the drop of resistances.
Table 4.2: Calculated values of a fixed diameter ratio of 0.35 to determine effect of outer diameter on
resistance for a single MWNT
Outer Diameter (nm)
Inner Diameter (nm)
No. of walls
Resistance (0)
10
3.5
10
646
20
7
20
323
40
14
39
166
80
28
77
83.9
As the diameter ratio increases, the resistance increases substantially. With higher diameter
ratios, there are less conduction rings available between the inner and outer diameter. This
results in a lower conduction of the MWNT.
Analysis on the MWNT models
4.4
The goal of this part of the analysis is to compare the differences of MWNT models between
the general perception of considering each MWNT ring as a separate SWNT of conductance
of 2Go and Naeemi model of the number of conduction channels available in a MWNT. They
were compared in two separate instances:
1) Considering an interconnect being occupied by a single big MWNT
2) A bundle of MWNTs occupying an interconnect
The following sections provide an overall trend of the two models and possible conclusions
resulting from it. Please take note that the area of the via or interconnect scales with the
technology node.
Comparison of Single MWNT models
4.4.1
Comparison ofSingle MWNT calculations (45nm, long wires)
long wires)
Comparison of Single MWNT calculations (80nm,
... . .. ...
..
.. . .....
450
W
800
r (General)
400
700
600
I
200-
j9500
250
200 -
General
S400
. 1501001
eemi
200
Nae
d· el
100
0
2
4
6
Lengh (urnm)
8
10
12
0
0
2
4
6
8
10
12
Length (um)
Figure 4.6: Comparison of Single MWNT calculations, 80nm on left, 45nm on right
At the technology nodes of 80nm and 45nm, as shown in Figure 4.6, the Naeemi model
predicts to be the better alternative, providing a lower resistance than that of the general case.
An interesting observation was made at the 14nm technology node in Figure 4.7. The general
model of a single MWNT gave a lower resistance than that of the Naeemi model.
Comparison of Single MWNT calculations (14nm, long wires)
----
3500-
3000-
Single MWNT (General)
- Single MWNT (Model)
.
2000-
i
1500-
Naeemi
-
MNndpl
2500-
10005000o
0
2
4
6
8
10
12
Length (urn)
Figure 4.7: Comparison of Single MWNT calculations for 14nm
Looking at Naeemi model for outer diameters greater than 6nm,
(0.0306(Dmx +Dmi,)+0.425) forDmx >6nm
Na,, = 1+ Dma -Dm
Nca,, oc [No of walls
x
(0.0306(Dmr
+Dmin)+0.425)]
... (4.3)
the number of conduction channels is determined by two factors. One is the number of walls
in a MWNT ring and another is the sum of the outer and inner diameters. For technology
nodes between 80 and 45nm, the diameters considered are quite large such that the number of
conduction channels available becomes multiples of 3 and 4 due to the second term. Thus,
the resistance of the Naeemi model is much lower than general case.
However, at 14nm, due to the small diameters considered, the number of conduction
channels from the Naeemi model becomes comparable or even lower than the general case.
That's the result of the reversal of the resistance of the graphs.
When compared with MWNT and SWNT bundles, the single MWNT models lose out as
their resistances are of a much higher value (twice as much as copper resistance at 14nm).
Since this model only calculates the resistance of the tube, RL, it does not seem feasible to
consider this as a possible alternative to copper. However, at a small enough node, a single
MWNT resistance will be comparable to that of a MWNT bundle, resulting in a convergence
of the two models.
4.4.2 Effect of MWNT rings on the MWNT bundle resistance
A study was conducted to see the trend of resistance when the number of rings increases for
each MWNT at 14nm technology node. A single shell CNT of diameter of Inm was
considered as the starting point. Knowing that the interval between 2 rings is 0.34nm, a shell
is added to each CNT. The resistance of the interconnect as a MWNT bundle is then
calculated. This process is repeated for subsequent rings. The packing distance calculated
between 2 MWNTs is equivalent of a MWNT diameter + Inm. Both General and Naeemi
models are considered to see a comparison between the two models.
Effect of MWNT rings in a bundle
...
300-
-
-
.. ...... ..........
. ...
General
- Naeemi Model
-
Min at
-
3 rings
250E
0 200-
1005000
1
2
3
4
5
6
Number of rings in each MWNT
7
8
9
Figure 4.8: Resistance of MWNT bundle versus number of rings in each MWNT at 14nm technology
node (Each MWNT: Diameter 5nm, Diameter ratio 0.35 and length of 1pm)
It is found that there is minimum point of 3 rings at 14nm for both models. For different
technology nodes, the minimum point shifts between 2 and 5 rings due to the area of
interconnect and packing density changing with the technology node. This shows the
possibility of modeling a MWNT bundle containing MWNTs of the same diameter and of a
certain packing density.
4.5
Overall Resistance trends - CNTs versus copper interconnects
To understand the performance of the different CNTs versus copper interconnects, analyses
were done to calculate the resistance values of SWNTs and MWNTs at different technology
nodes - 80nm, 45nm and 14nm. The parameters for copper were obtained from the ITRS
report on Interconnects [1].
Table 43: The constants used to calculate the resistance of co per [1l
p/pl.cm
A/cm
80nm
3.15
1.69x 10- o
45nm
4.08
14nm
8.19
5.46x 10-
5.23x10 -"
For the figures generated below, a few key parameters were set to provide a fair comparison
between the SWNT bundle, the MWNT bundle and copper. These values were chosen based
on the commonly used values in research papers and analysis from the previous sections
above. Each SWNT in a SWNT bundle has a diameter of Inm and has a packing density
distance of 2nm. This is close to the ideal packing density for bundles. Each MWNT in a
MWNT bundle has a diameter of 5nm, diameter ratio of 0.35 and packing density distance of
6nm. The General model is only considered for the calculation. As shown in section 4.4, in
most cases, the general model predicts a lower resistance than Naeemi model [22].
Technology Node - 8Onm
4.5.1
Resistance trends in 80nm node vias (bundles)
2.5 i.
Resistance Trends
in80nm long Interconnects
.
251
2-
20
15WNT
150
,undle
undle
10
05i
50
0.2
0.4
0.6
0.8
1
0
1.2
0
Length (urn)
5
4
2
10
8
12
Length (urn)
Figure 4.9: Overall resistance trends for 80nm node (Left: for vias, Right: for long interconnects)
It is known that copper resistance is much lower than that of CNT bundles at the 80nm
technology node for both vias and long interconnects. The MWNT bundle provides a slightly
lower resistance than that of the SWNT bundle. This is confirmed in Figure 4.9.
4.5.2 Technology Node - 45nm
Resistance Trends in45nm long interconnects
801
Coppe
70 -Copper
S---MWNT
WNT
A bundle
MWNT bundle
'i
"
40,
20100
0
2
4
6
8
10
12
Length
(um)
Figure 4.10: Overall resistance trends for 45nm node (Left: for vias, Right: for long interconnects)
As shown in Figure 4.10, both SWNT and MWNT bundles have much lower resistances than
copper in vias and over longer distances. Out of the two CNT bundles, the MWNT bundles
give a lower resistance. The comparison is so close that any one of the system can provide
the interconnect solution at 45nm.
4.5.3
Technology Node - 14nm
Resistance Trends in 14nm long interconnects
1800 1600
1400
1200
MWN
bundl,
1000
800
I
400
200
0
0
2
4
6
8
10
12
Length (um)
Figure 4.11: Overall resistance trends for 14nm node (Left: for vias, Right: for long interconnects)
SWNT bundles win with the lowest resistance. Figure 4.11 shows a distinct SWNT bundle
advantage over MWNT bundles and Copper, having a resistance half of that of Copper.
Although MWNT bundles are easier to grow with higher probability of metallic tubes, more
effort should be taken on SWNTs instead of MWNTs to be considered for technology nodes
14nm and below.
4.6
Results and Comments
To obtain the lowest resistance possible in the resistance of the tube to beat copper, the
following observations are made:
*
The SWNT diameter should be as small as possible
*
A small packing density distance for SWNT and MWNT bundles is needed
*
A large outer diameter of MWNT is needed
D
* A low diameter ratio for MWNTs of ( DM" =0.35) is needed
D Max
*
Single MWNTs are not a good alternative up to 14nm
*
MWNT bundles provide the lowest resistance at the 45 nm technology node
*
SWNT bundles provide the lowest resistance at the 14 nm technology node
The same resistance trends are observed for both short vias and long interconnects. A fallacy
of this comparison is that when the diameter of the CNTs are varied and compared again,
different outcomes are obtained. The challenge is to optimize the diameter size of CNTs that
can be practically grown and meet or outperform the resistance of copper. You should again
note that the contact resistance has not been considered, and that this is especially important
for the via calculation.
This is a first attempt in creating a model to calculate the resistance of a via or wire. Some
assumptions such as how the CNTs are packed in a bundle are taken to simplify the
calculations. Assumptions such as the electron mean free path (scattering length) of a
MWNT is assumed to be equal to that of a SWNT (1 tm) and it is assumed that there is
negligible coupling between adjacent SWNTs in a bundle. All of these assumptions require
further investigation for a clearer picture.
This model can be further improved by including other parameters such as other resistances
involved for CNTs such as quantum and contact resistances, latency, current densities and
thermal conductivity.
Chapter 5 Technology Assessment of CNTs as Interconnects
From earlier chapters, CNTs have proven themselves to be potential replacements for copper
in IC chips in terms of its electrical, thermal and reliability capabilities. To understand how
this technology can be integrated into the real processing world, let's begin with the supply
chain.
5.1
Technology Supply Chain
Si Wafers with
Electronic circuits
Si Wafers
74
A
IC Chips
OEM
MOO
Commercial
Products
MON.
TI
GUI PrScess
Figure 5.1: A typical Silicon wafer manufacturing process chain
The IC chip manufacturing process begins with unprocessed Si wafers brought into a
manufacturing or original equipment manufacturer (OEM) plant. Through the various steps
of deposition, lithography and etching of the wafer, thousands of microelectronic circuits are
created according to the design specifications for that component. The wafer is then broken
down to smaller pieces and packaged into IC chips before integrating them into commercial
products such as telecommunication equipment, laptops and consumer electronics.
CNT interconnect technology will enter the processing stage during the creation of the
integrated circuit chips in the wafer. Initially, the introduction of a new process technology
will bring about adjustments to the current system and even possibility a whole new setup to
accommodate its presence while maintaining process control of devices manufactured from
this chain. In the long run, the significant value of this technology is seen at the end of the
process chain of the finished IC chips in terms of performance and capabilities in various
devices.
Investors might think that implementing CNTs into IC chips might result in high start-up
costs and that low profit margin benefits will only trickle down from high profit sales from
IC chips. Through the introduction of CNTs; its significant advantages of high current
densities and better electrical conductivity over copper as technology nodes shrink down in
size allows for higher processing speed and high computing performance, the investment is
of long term and allows one to command a high price for the new process technology.
The following sections will highlight this point through the analyses of the current
intellectual property scene for CNTs and the feasibility of starting a company incorporating
CNTs in IC chips.
5.2
Intellectual Property
With nanotechnology in question, one of the keys to the protection of a useful, moneymaking idea is to identify the possibility of patenting this technology so that one becomes the
first owner of this technology.
5.2.1
CNT patents in general
Single-walled carbon nanotubes were discovered in 1991 by Sumio Iijima of Japan, a
researcher for the Japanese computer giant, NEC Corporation. Since then, any company that
wants to manufacture or sell carbon nanotubes must first negotiate a license on NEC's two
seminal patents before it pursues its own inventions.
IBM holds an early and fundamental patent on single-wall carbon nanotubes - US Patent No
5,424,054. This is the first patent for growing CNTs in a controlled manner using the CVD
method of cobalt catalyst and carbon vapor. Since then, the number of US patents granted
relating to carbon nanotubes is considerable, but the number of patent applications received
UK
by US PTO from 1999-2004 is far greater. This suggests that there could be increased
activity in the carbon nanotube patent area in the next few years. At the beginning of this
year alone, there are over 300 patents (both issued and applied). About half of the patents
issued are from the US alone, but there is a growing interest in the East Asian countries of
Korea and Japan.
Taiwan UK
70.
..
ta.h....
....
:·
.
:
*
*
.
..
r
4%
Taiwan
4%
Japa 7%
149
USA
49%
i>...:.
:•
W
•
•
W..
:•
i:<
i O,•;..
l•.
Ki
26%
Figure 5.2: US patents or published applications
referring to carbon nanotubes in the patent
abstract (1999 - 2004) [231
Figure 53: Carbon nanotube patents issued by US
PTO, from 1999-2004 (the data was collected on
04/25/2005) [231
Most of the current CNT patents come from big industry players and research institutes who
believe that there is a possible future with CNTs, mainly from the microelectronics industry.
Since patent databases do not always reveal the current ownership of patents or disclose
assignees, this is not a true reflection of a company or institution's dominant position.
Table 5.1: Carbon nanotube patents issued by US PTO, from 1999-2004
(the data was collected on 25 April 2005) 231
Samsung Electronics and Samsung
SDI Co., Ltd.
Korea
23
Rice University
Hyperion Catalysis International,
Inc.
The United States of America
University of Kentucky Research
USA
USA
14
10
USA
9
NEC Corp. and Research Institute,
Inc.
Iljin Nanotech CO., Ltd.
Japan
Korea
7
6
Battelle Memorial Institute
The Regents of the University of
USA
USA
5
4
Japan
UK
USA
4
4
4
Foundation
Industrial Technology Research
Institute
California
Agency of Industrial Science and
Technology
Hitachi, Ltd.
LG Electronics, Inc
Stanford University
There currently exists a nanotube patent thicket. Most of the claims are often broad,
overlapping and conflicting in the hopes of capturing any possible benefits. This means that
researchers in hope of developing new technology on CNTs such as the CNT interconnect
technology must first negotiate licenses from multiple patent owners.
5.2.2
Patents specific to CNT interconnects in IC chips
As highlighted in section 3.2.3, Fujitsu and IBM have applied for patents that cover use of
CNTs as interconnects for specific applications such as efficient heat conductors in IC chips
and 3D-CNT integrated circuits.
Table 5.2 highlights a list of possible competing patents with intellectual property relating to
CNT vias. With many other patents specializing in the process or placement of CNTs, it will
be hard to establish a particular patent in the CNT interconnect technology unless we become
as creative as Intel in coming up with alternative solutions to IC technology.
Table 5.2: List of possible competing patents with the intellectual property of having CNT vias
Patent Title
In-situ nano-interconnected circuit devices
and method for making the same (Agere
systems)
Article comprising vertically nanointerconnected circuit device and method for
making the same (Agere systems)
Amorphous carbon insulation and carbon
nanotube wires (Intel)
Catalytic Growth of Single-Wall Carbon
Nanotubes from Metal Particles (CNI)
Method of Forming Composite Arrays of
Single-wall Carbon Nanotubes and
Compositions Thereof (CNI)
Method for forming composites of sub-arrays
of single-wall carbon nanotubes (CNI)
Patent No
Date
US 6,297,063
October 2, 2001
US 6,383,923
May 7, 2002
US 6,730,972
May 4, 2004
US 6,692,717
February 17, 2004
US 6,939,525
September 6, 2005
US 6,986,876
January 17, 2006
One potential area is improvements or variations on a part in the Fujitsu's patent. As shown
in Figure 5.4 below, Fujitsu proposed the integration of horizontal CNTs with the help of
insulation layers (labeled 84a and b) to facilitate the conduction of tubes from vertical to
horizontal CNTs. Insulator layers such as SiO 2 are poor conductors of electricity; limiting
the overall conductance of the circuit.
Figure 5.4 Sectional view of a semiconductor device that only uses CNTs (lines in diagram) from Fujitsu
Patent [24]
A possible proposal is replacing metallic layers for the insulated ones such as titanium or
palladium to ensure almost ideal conduction can take place. An alternative could be to open
up the CNT tubes, similar to that of creating holes for endohedral fullerenes (inserting atoms
into fullerenes to change its properties) to encourage chemical bonding between a horizontal
and vertical tube at specific location, making CNT networks of tubes rather than individual
cylinders.
With such differentiation, it would be then possible to establish a unique patent for
commercialization. Thus, one answer to a potential business strategy is an Intellectual
Property (IP model). To analyze this option, one has to establish the potential of
nanomaterials in a market place.
5.3
Target World Market
5.3.1
Semiconductor Market Trends
The current outlook for the semiconductor industry is positive for this year and 2007. There
is a significant regional shift occurring in the semiconductor industry. According to senior
market analyst, Lara Chamness at SEMI, the semiconductor equipment and materials
suppliers enabled the electronics end market to reach US$1,340 billion even though the
equipment and materials market was only about US$64 billion by the end of 2005. It was
also a record year for device revenues (US$228 billion) and unit shipments (455 billion). For
the years to come, the projections for semiconductor growth in 2006 range from 3% to 20%,
with forecasts for 2007 ranging from 5% to almost 20% growth. Figure 5.5 illustrates this,
showing a positive sign to pursue investing into semiconductor industry.
I
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120 -
$0.60
s
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rja·- -·-
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$0.50
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SActual Bilings (left scale)
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Jan..ar 2006
a
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m Urits (left scae)
$0.30
2
$0.20
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u
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ASP (rigt scale)
IIIII
Figure 5.5: Worldwide Semiconductor Trends [341
.
:
I
Unlike the past in which the IC industry depended just on one major application (the personal
computer) to drive super normal growth, currently the IC industry is maturing with a wide
range of fast-growing products such as Flash Memory and Special Purpose Logic/MPR
(Industrial/other, Automotive, Consumer, Telecom, Computer Applications). In each case,
these ICs are widely used in some of the fastest growing end-use applications including
laptops and cell phones and especially consumer electronics systems (Source: IC Insights).
With consumers' high price sensitivity, the industry is motivated to drive down the price of
chips to the low cost regions through chip manufacturers and their suppliers.
Worldwide chip consumption by trends supports this assertion where consumption is the area
where chips are first shipped to-not their final end market destination. In terms of IC sales
(Figure 5.6), the market controlled by ROW countries is increasing due to growing number
of foundries setting up in these countries.
2000
2005
N.America
America
31%
ROW
46%
Ja
2:
u,,v
,w
21%
Europe
17%
I
Jdl3
I
19%
Figure 5.6: Worldwide Semiconductor Consumption highlighting the change in consumption from
majority N. America in 2000 to ROW in 2005. ROW includes Asia Pacific regions such as China,
Taiwan, Singapore, Korea etc [34]
5.3.2
Forward Looking Trends
According to a SEMI consensus equipment forecast, Japan is expected to remain the largest
semiconductor equipment purchasing region for the next three years. By the end of 2006,
there will be 9% growth overall, with stronger growth forecasted for China and Rest of
World. This growth continues positively in 2007 and 2008.
Despite growing revenues for chips, the percentage of money spent on equipment per device
revenue is forecasted to remain a relatively flat 15% over the next few years. This lower
capital spending as a percent of sales is an indication of a maturing industry and perhaps may
even lead to smoother cycles.
It is also believed that the lower spending will ultimately lead to stable and even increasing
average selling prices (ASPs). This is because of the supply-side implication new equipment
has-new equipment means more capacity is available, increasing supply. In situations
where there is more supply, ASPs tend to decline.
5.3.3
Emerging Market - Nanotechnology
With the shrinking technology nodes, microelectronics is slowly becoming nanoelectronics.
The global demand for nanoelectronic tools and equipment are forecasted to surpass the
US$3 billion mark by 2010. Thus, there is a push from the semiconductor industry for some
form of nanotechnology commercialization to take place soon. It is expected that this could
happen in the near-term. In displays, there are talks of using CNTs in field emission displays
and backlight units. Alternative memory storages are considered in semiconductors with the
help of quantum dots and using MEMS or even NEMS to shrink functional devices into the
micro or nanoscale. Additional uses of nanomaterials in electronics include heat sinks and
anti-static packaging. Figures 5.7 and 5.8 are graphs from Nano Markets and SEMI,
predicting the trend of nanomaterials in the future, showing signs of high profits ahead.
Global Nanoelectronics Market Forecast
I
$120
$100
E $80
0
u,
$60
$40
$20
$0
2007
2011
2015
Figure 5.7: Global Nanoelectronics Market Forecast 1361
$1250
4t!Ir
Sl000
I
t71C
E
$750
ssoo
1XK,
·
S3
S$246
05250
$161
s•
so
n
-"
204
2005
2006
Actual
Estimate
F~recast
SEvohltuwrw
y E Revolutlrnryr
2007
Extltder kens
2008
11%
$%
IS'
n
2009
2010
*"v•r
Figure 5.8: Global Market and Forecast for Nanomaterials (SEMI 2005) 1361
These graphs highlight a question - how will a nanomaterial like CNT fare in the
microelectronics market?
5.3.4
Opportunities for implementing Nanomaterials
To solve many of the materials challenges facing the electronics industry today, the answers
lie with nano science and technology. Some of the solutions are currently investigated in
research. With tiny scales to consider, the challenge is to maintain reproducibility and control
in the manufacture of nanomaterials to obtain standards in a commercial process.
One of the big advantages is that technology from other industries is being leveraged in the
development of new or revolutionary materials. From the understanding of CNTs from the
physicists, engineers have been coming up with applications to embrace this newfound
material and enhance its superior properties.
Through the adoption of revolutionary nanoelectronic equipment, demand is created for new
materials, yet eliminates demand for others. Examples of revolutionary tools include nano
imprint lithography, EUVL, organic vapor phase deposition and certain nano positioning or
atomic manipulation platforms. With specific uses in nanomaterials, when companies invest
in such equipment, they hope to earn profits and eventually switch to that technology. Thus,
materials will have much higher intellectual property value in the near future, through new
applications and the value of materials will increase in the next 5 years.
5.3.5
Risks of implementing Nanomaterials
Significant investments are required to create niche markets where new materials are
developed and integrated into manufacturing processes. It would be great if an application
using nanoelectronic material takes off and earns profit. However, the probability of this
happening is small. As such, it is difficult to capture a large enough market share to make
returns on investment in a short period of time.
Intense price pressure of the market prices versus that of the new material, lag time between
product development and production cycles, and unique requirements associated with
electronics applications are causing suppliers to question the possibility of such a business.
Further, there is insufficient environmental, health and safety information available for new
materials and compounds that will be introduced into the commercial production plants,
endangering the lives exposed to the materials.
In the short term, the opportunities for nanomaterials are outside of the electronics industries
in areas such as beauty products and biomedical sciences. With further research and
development on the use of such nanoelectronic materials in the semiconductor industry, it
will be a matter of time before large scale integration of CNT technology into IC chip
fabrication can be seen.
5.4
Sources of Funding
To start any business, capital is required to fund through the first few months (or years)
before making profit. Possible sources can be either from owners' personal funds, family or
friends or if one is fortunate, from a venture capitalist that sees potential in the business.
Below are some sources of funding in particular to the IC microelectronics industry, where
the government, certain organizations and even universities can provide the startup capital.
The first source of immediate funds can come by obtaining funds from the government. If a
government body sees potential in the project, they will be most willing to chip in the
required funds over a period of time to work on the research and development of this newfrontier technology. Recently in the news (April 12, 2006), a nanotechnology company
specializing in applications for carbon nanotubes, Nanosys Inc. received government contract
awards totaling US $4.6 million dollars to continue its research on nanotechnology [26].
Since the nanotechnology being dealt with is carbon nanotubes for interconnect applications
in IC chips, the closest source of government funds that can be considered is the
Microelectronics Advanced Research Corporation (MARCO) [27]. Out of its different focus
concentrations in the microelectronics industry, they realize the immediate need for research
on interconnects leading to the creation of the Focus Center Research Programme (FCRP) for
interconnects. One can just apply for funds online defining the purpose, length of funds
required and the amount needed for the project. Most of the projects are university or
research institute collaborated projects and if necessary tie-ups with expertise can be
arranged. The only disadvantage is that one has to contend with MARCO retaining
ownership of all IP. Thus, obtaining funds from a government source would be a better
choice.
More than S$15 billion dollars in venture capital funds are managed out of Singapore. A cofinancing equity scheme from the Economic Development Board (EDB) for seedstage or
startup companies (Startup Enterprise Development Scheme) is available for companies who
wish to start out in the semiconductor field. Conditions are mainly to set up a business in
Singapore with incentives of lower startup costs, tax reductions and government support for
any successful venture made.
If one is still in university, another way to gain starting funds is by tapping into university
research funds. Most innovative ideas come from doing research in a particular field during
our graduate studies. If it has the potential to become a successful profitable business, why
not work on it at the university level with the support of professors and internal funding.
There are avenues of even patenting the invention or technology. The MIT patent office is
one good example of this approach, encouraging future entrepreneurs among its students. On
November 4, 2005, Arrowhead Research Corporation has decided to fund Dr. Jie Liu of
Duke University with more than US$680,000 to continue his research on CNT interconnects
over the next 2 years, realizing its strong potential in the IC industry [28].
If the target OEMs are keen on developing this technology, possible tie-ups of the startup
company can be made with the OEMs. There are companies that spend millions working on
improving the current technology or working on future possible technologies like "IBM bets
on nanotech for faster PCs" on March 24, 2006, Fujitsu's commercialization plans for CNT
heat-sinks on December 5, 2005 and Samsung joining the IBM, Infineon and Chartered
Alliance to work on 65nm process technology for 300mm (12") wafers [44]. Using the
advantage of a potential high value CNT interconnect technology, it is possible to arrange a
partnership deal with the OEMs.
5.5
Investment Costs
As challenges tied to the industry's move towards ever-smaller dimensions have intensified,
governments in Asia, the U.S. and Europe have moved vigorously to coordinate and fund
research in both product and process technologies. The scale of these efforts is
unprecedented.
For a new manufacturing process such as growing CNTs in vias instead of copper
interconnects, an initial thought is why not start up a new plant like of Intel Corp. and
Advanced Micro Devices Inc. (AMD) that will prove a repeatable mass fabrication process
of IC chips with CNT vias. New fabrication facilities (fabs) mean more new business for
equipment and materials companies in the future. While this is generally true, it does
however beg the vital questions of what how you want to structure the new fab, where to
build it and when do you want to do so.
Intel, for instance, announced in July that it would spend US$3 billion to build a new fab in
Arizona and Advanced Micro Devices (AMD) is investing US$2.5 billion in a new fab in
Germany. That kind of price tag can make a decision whether to build a new fab a make-orbreak choice.
Invetment (Costsfor Fab Startup
Rising Cost of Fabs inEach Successive
Technology Generation
71R
S3.):,a
7__
S!~'t'V
SS_'.CrJO.-
_l.oW
. .
$.•000
110;1?!
$6
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.)411
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1
0
00
035
025
r
il
01
0m3
0
0.13
009
Ini
j~
~Mi91\
SY~J:'i:~a3Z:IuL:
Figure 5.9: Graphs showing rising costs of starting a fab [30]
Seeing from Figure 5.9, the costs of starting up a fab runs up to US$3.5 billion for 90nm
transistor linewidth plant. It is not feasible to start a business with most of the capital money
put into a fab and run a risk of having unutilized infrastructure if the CNT process is not
sustainable in a long run. A relatively, new technology proven by research in laboratories
does need time for some fine tuning and improvements in the mass production of CNTs in
multiple vias in a IC chip. What other options are there?
This has led many companies to move on to a "fabless" business model - producing
integrated circuits under contract for firms that work exclusively in device design. Foundries
provide relatively low-cost products for "fabless" companies that need high-performance
fabrication but are unable or unwilling to invest the $2 billion-plus it now takes to build a
new plant. Examples of companies that go fabless are that of LSI and communications
chipmakers, Qualcomm Corp. and Broadcom Corporation.
It is a decision that carries significant risk management challenges, such as balancing savings
on workers' compensation and property coverage costs against increased worries about
85
business continuity and supply-chain management. Another area of concern for companies is
the choice of contract manufacturers resulting in an issue of protection of their intellectual
property in a business where billions of dollars in sales may hinge on a new chip design.
Selling the IP of this technology to an OEM is another option. This might bring in the quick
bucks to the inventor and gain 2 - 3% commission from the sales. Having spent so many
time and effort in coming up with this technology that will see into the next revolution after
the introduction of copper, it would be great if a share partnership deal can be established
between the new business venture and the OEM. The new business venture will have the
technological expertise to work on this technology and make further improvements and the
OEM has the capital and market share advantage to push for better performing chips for
higher profits - a win-win situation.
5.6
Business Plan
It is essential to have a plan that sets out the future strategy and financial development of a
business covering a period of several years - a business plan.
5.6.1
Success Factors
it A predictable niche market
Nt Enabling Technology
*
Practical and reliable process
*
Acceptable risks and rich rewards
where the ticks represent what this technology can achieve at current stage
The use of CNTs as interconnects for IC chips technology is a new concept (owned by
Fujitsu) that has been proven by researchers in OEMs and universities. It has shown a sign of
being a more commercially viable solution compared to 3D interconnects and optical
interconnects where substantial changes to the process systems to accommodate these
technologies.
3D interconnects require new methods of stacking layer over layer of interconnects to
shorten distances between different modules. Optical interconnects require new modules to
provide the light source, modulators, detectors in between the electrical signals.
However, carbon nanotubes can, in principle, be fabricated consistently with the required
properties (e.g. MWNT bundles) for the required application of CNTs as interconnects, using
techniques that are compatible with current IC manufacturing processes and equipment
models. The starting point is in its use in vias to see to its significant possibility of integration
into the silicon IC chip processing. If successful, a monolithic integration of CNTs as
interconnect wires may be seen in the near future.
The niche market is the big semiconductor IC chip industry in particular high performance
memory chips and processors that require continuous improvements in technology to head
for packing in more modules and faster speeds. It is believed that CNTs can provide the
solution in the future when technology nodes shrink to 35nm and lower, when copper starts
to fail due to electromigration.
The challenge is providing a commercially viable process to produce CNTs on IC chips.
CNT interconnects in research labs only prove the concept for 1 layer of metal. There is no
guarantee that previously grown CNTs will not be affected by subsequent metal layers where
CNTs have to be grown in the vias too. Accidental growths of CNTs on metal contacts or
other areas of the wafer is possible if the Si wafer is not kept free of catalysts other than the
vias, resulting in possibly lower yields. There is also a possibility of carbon contamination
into the process during chemical wafer polishing (CMP) of the tubes. Such problems are
being looked at by companies and targeted to provide a viable solution as soon as possible.
Besides that crucial issue, the risks are acceptable to a potential investor and rewards are
high.
5.6.2 Implementation
it Identify product or TECHNOLOGY
t List Interested Parties
it Perform Cost Benefit Analysis
Since ours is not a product-oriented business, the technology in question is CNT
interconnects. It is a new, enabling technology, hoping to catch a slice of the big
semiconductor chip market. With the technology in hand, a patent can be claimed to establish
its capability, gain advantage over competitors.
The key interested parties that a new IP oriented business would like to target are the
Original Equipment Manufacturers (OEMs). It is these people who are going to be targeting
their chip designs based on the properties of this technology and implemented either through
88
their own manufacturing facilities or to outside foundries like Taiwan Semiconductor
Manufacturing Corporation (TSMC) or Chartered Semiconductor to do the work for them.
By convincing one of these companies of the IP's potential, a potential tie-up can be
established and other OEMs and manufacturers are encouraged to follow suit, following the
model of copper interconnects' introduction to the IC chip industry.
A key step is to perform a cost benefit analysis of our technology in comparison with the
alternative of investing same money in a bank and gaining interest or going into another
venture that can gain reasonable profit. Financial viability can not be established due to
reasons given in the next section but ideally this business venture should give a 10X value
added to the capital placed in the beginning. This is not just the monetary gain but significant
gains in its performance, reliability and yield compared to other competitors.
An alternative way is to come up with a process step that can integrate the grown of CNTs
into the commercial IC chip fabrication process. Since a low temperature CVD process needs
to be carried out to grow CNTs in vias and interconnects, a new fabrication step of PECVD
process with the introduction of carbon-based gases can be introduced. By calculating the
start-up and maintenance costs of introducing this step into the current IC fabrication process,
an outlook of whether it is feasible to have this option in the hindsight of better
electromigration resistance at smaller technology nodes will be known.
5.7
Financial Viability
CNT design maturity is not yet sufficiently advanced to allow an accurate assessment of
costs. There are many variables to be considered in the manufacture of IC chips. The cost of
each processing step to the creation of CNTs has to be individually accounted for such as
deposition steps of the catalyst layers, material cost and specialized equipment cost. Further,
there are also overall costs of running the manufacture process such as capital expenditure,
labor cost and R&D recovery. Therefore, let the unit cost of a possible IC chip be "Y".
This enabling CNT interconnect technology is intended to produce superior microchip with
10X increase in capabilities. This allows production of non-competing new generation
products and allows freedom to determine the sale price. Under such circumstances,
particularly in a demanding market; the margins are substantially high to overcome the unit
cost of production "Y".
5.8
Execution Plan
1.
2.
3.
4.
5.
6.
7.
Conduct Patent Search and establish viability
Engage a patent lawyer and register patent
Work out a business plan - cost/benefit analysis
Approach OEMs that are keen on CNT technology
Convince OEM on process reliability and practical manufacturing
Cut a deal - Up front fixed fee plus royalty per piece
Continue to work on enhancement
Chapter 6 Conclusion
This thesis provides insight into the properties of CNTs and how they can be incorporated
into ICs as interconnects to meet the need for replacing copper interconnects in the near
future. As the technology node shrinks from 80nm to 14nm (and below), the electrical
properties of ballistic conduction, ability to handle high current densities (up to 101oA/cm2 )
and high thermal conductivity make CNTs far superior to copper.
The resistance model gave a key insight into the understanding of conduction of the various
combinations of CNTs - SWNT bundles, a single MWNT, and MWNT bundles rating their
performance over copper. From the final analysis, SWNT bundles provide the best solution
overall to replace copper for vias and interconnects at 14nm, though MWNT bundles are
easier to manufacture and have a higher probability to be metallic in nature. However, the
calculated resistances are found to be substantially high when contact resistances, making
CNTs' introduction difficult unless fabrication methods can be improved. The most probable
reason for the introduction of CNTs is more to its ability to support high current densities
(>10 7A/cm 2) at lower technology nodes compared to copper at the cost of high resistances.
In the commercial arena, there is a strong eagerness to breach the boundaries of technology
to meet consumer expectation. With the advent of decreasing linewidth dimensions and
demand for improvements in memory power and processing speeds, CNTs in interconnects
provide the first step in making this a reality for future applications where CNTs provide
enabling technology that provide tremendous value. Continuous process improvement is
required to ensure its sustainability. In collaboration with Original Equipment Manufacturers
91
(OEMs), an IP business model is recommended to bring this idea to the big market. Being the
first of its kind to be implemented in IC chips, there is a freedom to fix the margin at which
profit can be earned as a high value enhanced product, offsetting off increased re-tooling or
manufacturing costs.
A futuristic, ideal interconnect system in an IC chip would be a total CNT system where
openings in CNTs are created to join one CNT to another, forming a network such that no
metallic wires are required. Despite their remarkable properties, it remains to be seen
whether CNTs can capture the industry and make it out in a strong way.
Successful Technology
Carbon Nanotubes Interconnects
Time Horizon
5 - 10 years
Probability of Success
Medium to High
Risk / Reward
Medium risk
Very High Reward
Potential User
OEMs like Intel, Fujitsu, and Infineon i
Figure 6.1: Summary of the considerations for a successful IP business model
References
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[2] Graham et al., "How do carbon nanotubes fit into the semiconductor roadmap?" Appl.
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[3] Wei, B.Q., Vajtai, R., Ajayan, P.M., "Reliability and current carrying capacity of carbon
nanotubes", Appl. Phys Letters, 79, No.8, 1172, (2001).
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[5] Kreupl, F., Graham, P. et al., "Carbon Nanotubes for Interconnect Applications," Infineon
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Analysis in the Nanometer Era: Cu and Beyond," Proceedings of the 2 2 nd Advanced
Metallization Conference, Colorado Springs, CO, September 27-29, 2005.
[7] Wilder, J.W.G., Venema, L.C., Rinzler, A.G., Smalley, R.E., Dekker, C., Nature 391,
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[8] Dresselhauss M.S., Dresselhauss, G., Avouris, Ph. (eds.), "Carbon nanotubes: synthesis,
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[10] Applied Nanotechnologies Inc.'s webpage on carbon nanotube properties
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[14] Nihei, Mizuhisa, Horibe, Masahiro Kawabata, Akio and Awano, Yuji, "Simultaneous
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Candidates for Short Local Interconnects", IEEE Electron Dev. Letters, 26, 544, (2005).
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IEEE InternationalElectron Devices Meeting, (2005).
[18] Hamada, Yoshihiro, Negishi, Hideki, Akita, Seiji, and Nakayama, Yoshikazu,
"Electrical Properties of Connected Multiwall Carbon Nanotubes". Jap. Jour. Of Applied
Phys. 44, No. 4A, pp. 1629-1632 (2005).
[19] Li, H.J., Lu, W.G., Li, J.J., Bai, X.D. and Gu, C.Z., "Multichannel Ballistic Transport in
Multiwall Carbon Nanotubes", PhysicalReview Letters, 95, 086601, (2005).
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[22] Naeemi, A., and Meindl, J., "Compact Physical Models for Multiwall Carbon-Nanotube
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[24] US Patent 6,800,886 B2 *10/2004 Awano
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Phys. Rev. Lett., 85, 5186-5189, (2005).
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for VLSI applications", IEEE/ACM International Conference on Computer-Aided Design,
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[42] Nihel et al, "Electrical Properties of Carbon Nanotube Bundles for Future Via
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[43] Nihel et al, "Low-resistance multi-walled carbon nanotube vias with parallel channel
conduction of inner shells [IC interconnect applications]", Proc. of the IEEE, Interconnect
Technology conference, 234-236, (2005).
[44] Electronic News, "Samsung Joins IBM, Infineon, Chartered Alliance", March 5, 2004.
Appendix 1 SCMOS Layout Rules
website
the
from
taken
are
pages
following
The
to
is
available
which
http://www.mosis.org/Technical/Designrules/scmos/scmos-main.html,
the public.
To interpret the rules, take the technology node as X,
For example, the exact size of via = 2x2 is equivalent to taking it as a square area with 2X on
each side. For the resistance model, the SCMOS specifications are considered.
For more specific rules related to IC fab, please contact the fab directly.
For Via
Vias must be drawn orthogonal to the grid of the layout. Non-Manhattan vias are not
allowed.
n--I---
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8.1
Exact size
2x2
n/a
n/a
2x2
2x2
3x3
8.2
Minimum vial spacing
3
n/a
n/a
3
3
3
8.3
Minimum overlap by metall
1
n/a
n/a
1
1
1
8.4
Minimum spacing to contact
for technology codes mapped
to processes that do not allow 2
stacked vias (SCNA, SCNE,
SCN3M, SCN3MLC)
n/a
n/a
2
2
n/a
n/a
2
2
n/a
8.5
Minimum spacing to poly or
active edge for technology
codes mapped to processes
that do not allow stacked vias
(NOTE: list is not same as
for 8.4)
Is
.A-W
e
_ _
Active
.5
Active
For Metal 1
r"YllrrrCY*~r~··-wU1
~I·I---·--~--·---·
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-- ·
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3
3
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2
3
3
Minimum overlap of any contact
1
1
1
Minimum spacing when either metal line is wider than 4
10 lambda
6
6
Active
7.3
7.1
.2
~
Appendix 2 Flowchart of invention in US Patent 6,933,222
Provide a base substrate upon which the carbon nanotube integrated circuits
ar7 to be fabricated
Deposit a first dielectric layer or plurality of dieleclric layers onto the substrate
Provide one or more first vias in the first dielectric layer into which a first conductive
layer is deposited
Deposit a second dielectric layer onto the first conductive and dielectric layers
Pattern the second dielectric layer with small diameter vias of various or equal sizes
extending to and exposing the first conductive layer, followed by the patterning of larger
diameter vias interconnected with one or more of the smaller diameter vias
-
-
--
I`---~I
Provide the exposed first conductive layer at the base of the small vias with a catalyst
....
Grow/deposit a carbon nanotube in each via or via stack on the catalyst material in vertical
alignment with the openings formed by the second vias in the second dielectric layer
Provide the third dielectric layer onto the second dielectric layer and the embedded carbon
nanotube with one or more fourth vias into which a second conductive layer is deposited
~~~~
_ ____~__~_______~__~
Build up additional layers upon the conductive and
fourth dielectric layers for form additional carbon
nanotube integrated circuits followed by a passivation
layer on the final dielectricoconductive layer
Deposit a passivation layer
onto the second conductive
and fourth dielectric layers