Using CDC2509A/2510A PLL
with Spread Spectrum
Clocking (SSC)
Application
Note
December 1998
Mixed Signal Linear Products
SCAA039
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Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Adjusting the Phase Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Important SSC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 SSC System Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.1 Clock Synthesizer SSC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.2 Clock Synthesizer Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3 PLL Input Clock Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.4 PLL Clock Avcc Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5 PLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.6 PLL Tracking Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Measurement Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
List of Figures
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
CDC2509A Phase Error vs. CL (FBOUT CL = 0 pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
CDC2509A Phase Error vs. CL (FBOUT CL = Output CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CDC2509A Tracking Skew (linear triangle, 30 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
CDC2509A Tracking Skew (linear triangle, 50 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CDC2510 Driven by Vendor A Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CDC2510 Tracking Skew Driven by Vendor A Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CDC2510A Driven by Vendor A Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CDC2510A Tracking Skew Driven by Vendor A Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CDC2510 Driven by Vendor B Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical AVCC Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PLL Slow Down after CLK Pin is Held Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PLL Start Up after CLK Stream is Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)
iii
Figures
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iv
SCAA039
Using CDC2509A/2510A PLL with Spread Spectrum Clocking
(SSC)
ABSTRACT
This application note describes the CDC2509A/2510A[1] phase-lock loop clock
drivers and their use with spread spectrum clocking system. This application note
gives SSC system performance measurements and parameter measurement
instructions.
1 Introduction
With the introduction of CDC2509A/2510A[1], TI supports the use of spread
spectrum clocking (SSC) of registered SDRAM DIMMs. The major difference
between the A version and the non-A version of CDC2509/10 is the increased
PLL loop bandwidth in the A version. While the non-A version has a loop
bandwidth in the range of 400 kHz, the CDC2509A/2510As loop bandwidth is
about 1.5 MHz. This increase is necessary to follow the modulation of the spread
spectrum input clock signal. This application note describes the practical effects,
careabouts, and measurement techniques involved in designing a clock system
based on the CDC2509A/2510A.
1
Adjusting the Phase Error
2 Adjusting the Phase Error
Static phase error is the average phase error of the device excluding jitter. The
typical static phase error of the CDC2509A/2510A is about –550 ps at 100 MHz
and an equal lumped loading of 30 pF at all outputs, including FBOUT. The minus
sign reflects that the output transition of the PLL occurs before the clock input
transition, i.e., there is a phase lead of the PLL outputs versus the PLL clock input.
There are four major factors that influence the static phase error:
1. The input edge rate at the clock input of the CDC2509A/2510A
2. The skew seen on the outputs due to their capacitive loading
3. The capacitive loading of the feedback output
4. The delay introduced by the electrical length of the connection between the
FBOUT and the FBIN pin
The first one is of least significance, nevertheless it should be mentioned here.
The real input threshold of the device differs slightly from the 1.5 V measurement
reference point specified in the datasheet. Maintaining all other conditions
identical, a CDC2509A/2510A application using a 1.1 ns/V input rise time will
show about 50 ps less phase lead than the same system fed by a 0.5 ns/V clock
input.
CDC2509A
PHASE ERROR
vs
LOAD CAPACITANCE
700
600
500
Phase Error – ps
Output Skew
400
300
200
100
Avg Phase Error
0
–100
0
5
10
15
20
25
30
35
40
45
CL – Load Capacitance – pF
Figure 1. CDC2509A Phase Error vs. CL (FBOUT CL = 0 pF)
2
SCAA039
Adjusting the Phase Error
Capacitive loading of the outputs influences phase error indirectly to a larger
extent. Of most importance is the ratio of capacitive load on the outputs versus
the load of the FBOUT pin. Figure 1 shows the static phase error of the PLL seen
at the outputs with the FBOUT with the load always near 0 pF. The feedback trace
is just a straight line between pin 12 and 13, about 0.2 inch in length. The
increasing capacitive load of the PLL outputs slows down the edge rate,
introducing a skew resulting in a phase lag. Phase error of the FBOUT pin
remains constantly close to zero.
In a practical system design, output loading is always a combination of
transmission lines having a distributed capacitive load and SDRAM clock input
capacitance seen as a lumped capacitive load. Output load should be kept even
among the outputs, otherwise output pin-to-pin skew will increase beyond
specification. If vias are needed on the PCB to route top level signals into inner
layers and back, they should be placed close to the PLL outputs and the SDRAM
inputs and equally among the outputs. It is useful to simulate the PLL output load
seen in the system by using the CDC2509A/2510A IBIS model[2]. Care must be
taken not to increase the total capacitive load beyond the 40 pF to 45 pF range.
When beyond this range, the output transition of the PLL will be slowed down
such that it no longer reaches the VOL and VOH level at 100-MHz switching rate.
CDC2509A
PHASE ERROR
vs
LOAD CAPACITANCE
200
100
Phase Error – ps
0
–100
–200
–300
–400
–500
–600
0
5
10
15
20
25
30
35
40
45
CL – Load Capacitance – pF
Figure 2. CDC2509A Phase Error vs. CL (FBOUT CL = Output CL)
Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)
3
Important SSC Parameters
The capacitive loading of the feedback pin is the best way to fine tune the static
phase error of the PLL. Figure 2 shows the static phase error versus lumped
capacitive load at the FBOUT pin. Again, a short connection between pin 12 and
13 was used. A higher capacitive load leads to a more negative phase error, i.e.,
more phase lead. It is important to keep the lumped capacitive load of the FBOUT
below the 40 pF to 45 pF range, to ensure valid VOL/VOH levels at high
frequencies. Also, the transmission line load of the feedback trace slows down
the FBOUT transitions. When applying a lumped capacitive load to the feedback
path, it should be placed near the FBIN pin, as the lumped load looks like a short
to the FBOUT pin and will generate reflections that can be forwarded to the FBIN
pin if the lumped load is not placed close to the FBIN.
Finally, the electrical trace length of the feedback path is the coarse adjust of the
phase error. For calculations, the electrical length of the traces from the PLL
outputs to the SDRAMs versus the electrical length along the feedback trace
determine the amount of phase lead or lag. Increasing the output-to-SDRAM
length increases the phase error in the positive direction towards phase lag;
increasing the feedback trace length decreases the phase error towards phase
lead. The phase error is always measured from the rising clock input to the rising
PLL output.
3 Important SSC Parameters
•
•
•
Modulation scheme
Modulation depth
Modulation frequency
The two most common modulation schemes are linear triangle modulation and
the nonlinear modulation scheme patented by Lexmark International Inc[3],
commonly known as the Hershey Kiss scheme.
As described in Intel’s application note[4], the Hershey Kiss modulation scheme
gains better EMI reduction than the linear triangle scheme. In terms of loop
frequency bandwidth, Hershey Kiss requires a higher bandwidth of the memory
PLL than the linear triangle modulation.
Modulation depth is the amount of frequency modulation applied to the clock
carrier. Current synthesizers use 0.5%–0.75% downspread modulation.
Downspread means that a clock carrier of 100 MHz is modulated down to
99.5 MHz–99.25 MHz. The modulation depth does not include the output jitter of
the synthesizer, thus a frequency versus time plot of a 0.5% downspread signal
may look like a 0.75% down, 0.2% upspread, signal due to the inherent output
jitter of the device.
Modulation frequency is the repetition rate of the modulation scheme applied to
the clock carrier signal. The typical modulation frequency used is 33 kHz. A higher
modulation frequency requires increasing the loop bandwidth of the driven PLL.
4
SCAA039
SSC System Performance
4 SSC System Performance
While reducing system EMI, SSC introduces a new set of parameters that need
to be considered in SSC clock system design. These parameters are not related
to the SSC clock synthesizer, the driven PLL, and the system layout alone, but
rather are influenced by the combination of all three. Here are the most important
parameters:
• Clock synthesizer SSC parameters
• Clock synthesizer output jitter
• PLL clock input signal integrity
• PLL clock Avcc noise
• PLL loop bandwidth
• PLL tracking skew
Clock Synthesizer SSC Parameters
4.1
Vendors use different SSC modulation schemes, modulation depth, and
frequencies. Although all these devices comply with the Intel PC100
specification, it does not necessarily mean the total system performance is still
according to the specification. System radiated EMI significantly depends on PC
Board layout signal routing, as well as GND/VCC plane layout. It is possible that
some systems may not need SSC clocking to meet federal EMI specification,
while some may require linear modulated SSC and some may require nonlinear
modulated SSC.
CDC2509A
TRACKING SKEW AND INPUT FREQUENCY
vs
TIME
1000
100.5
1.0% Downspread
0.4% Upspread
33 KHz Linear Triangle Modulation
800
Clk Input SSC On
600
400
99.5
Clk Input SSC Off
200
Track Skew SSC On and SSC Off
99
Input Frequency – MHz
Tracking Skew – ps
100
0
–200
98.5
0
5
10
15
20
25
30
35
t – Time – µs
Figure 3. CDC2509A Tracking Skew (linear triangle, 30 kHz)
Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)
5
SSC System Performance
CDC2509A
TRACKING SKEW AND INPUT FREQUENCY
vs
TIME
0.8% Downspread
0.3% Upspread
50 KHz Linear Triangle Modulation
800
100.5
Clk Input SSC On
Tracking Skew – ps
100
600
Clk Input SSC Off
400
99.5
Track Skew SSC On and SSC Off
200
99
0
–200
98.5
0
5
10
15
20
25
30
t – Time – µS
Figure 4. CDC2509A Tracking Skew (linear triangle, 50 kHz)
Figure 3 and Figure 4 show the output waveform, modulated versus not
modulated, of a waveform generator fed to CDC2509A in a lab setup. The input
clock signal with SSC turned off is a straight 100-MHz signal with the inherent
generator jitter modulated on top. With SSC on, a linear triangle modulated
100-MHz square wave is fed into the CDC2509A PLL. Modulation width is 1%
down and 0.4% up, Figure 3 shows 33-kHz modulation; Figure 4 shows 50-kHz
modulation. This is exceeding the current maximum modulation depth and
frequency of the CK100 synthesizers. The bottom two graphs of Figure 3 and
Figure 4 show the normalized tracking skew of the PLL. There is no noteworthy
difference in tracking skew between SSC on or off and 50 kHz versus 33 kHz. The
CDC2509A/2510A PLL has enough bandwidth to cope with the modulation depth
and frequency exceeding those of current CK100 synthesizers.
6
SCAA039
f – Input Frequency – MHz
1000
SSC System Performance
CDC2510
FREQUENCY
vs
TIME
102
101.5
2510 FBOUT
2510 CLK
f – Frequency – MHz
101
100.5
100
99.5
99
98.5
98
Jitter:
Peak-TO-Peak
clk input:
fbout:
97.5
Cycle-TO-Cycle
306 ps
147 ps
245 ps
85 ps
97
0
5
10
15
20
25
30
35
t – Time – µs
Figure 5. CDC2510 Driven by Vendor A Synthesizer
CDC2510
TRACKING SKEW
vs
TIME
400
300
Tracking Skew – ps
200
100
0
–100
–200
–300
–400
0
5
10
15
20
25
30
35
t – Time – µs
Figure 6. CDC2510 Tracking Skew Driven by Vendor A Synthesizer
Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)
7
SSC System Performance
CDC2510
FREQUENCY
vs
TIME
102
101.5
2510 CLK and 2510 FBOUT
101
f – Frequency – MHz
100.5
100
99.5
99
98.5
98
Jitter:
97.5
Peak-TO-Peak
CLK input:
FBOUT:
Cycle-TO-Cycle
295 ps
308 ps
237 ps
117 ps
97
0
5
10
15
20
25
30
35
t – Time – µs
Figure 7. CDC2510A Driven by Vendor A Synthesizer
CDC2510A
TRACKING SKEW
vs
TIME
400
300
Tracking Skew – ps
200
100
0
–100
–200
–300
–400
0
5
10
15
20
25
30
35
t – Time – µs
Figure 8. CDC2510A Tracking Skew Driven by Vendor A Synthesizer
8
SCAA039
SSC System Performance
CDC2510
FREQUENCY
vs
TIME
102
101.5
2510
FBOUT
101
2510
CLK
f – Frequency – MHz
100.5
100
99.5
99
98.5
98
Jitter:
97.5
Peak-TO-Peak
CLK input:
FBOUT:
Cycle-TO-Cycle
448 ps
150 ps
370 ps
79 ps
97
0
5
10
15
20
25
30
35
t – Time – µs
Figure 9. CDC2510 Driven by Vendor B Synthesizer
4.2
Clock Synthesizer Output Jitter
Figure 5 and Figure 9 show the clock output jitter of two CK100 vendors. Vendor
A uses linear triangle modulation while vendor B uses the nonlinear Hershey Kiss
scheme. The output jitter of device B is 50% higher than the jitter of device A. A
PLL fed by this signal is supposed to act as a low pass filter, thus filtering the jitter
presented at its clock input to a lower value at its output. Higher loop bandwidth
PLLs have a higher –3 dB low-pass filter cutoff frequency, being less efficient in
filtering clock synthesizer output jitter.
4.3
PLL Input Clock Signal Integrity
With higher loop bandwidth, the PLL gets more susceptible to clock input signal
integrity. Flat spots in the threshold region may result in an increased jitter due
to false triggering of the input phase detector circuit. The system designer should
verify input transition signal integrity and eventually improve the signal by
implementing proper termination.
Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)
9
SSC System Performance
4.4
PLL Clock Avcc Noise
Figure 10. Typical AVCC Noise
Proper decoupling of AVCC noise is mandatory if increased jitter is to be avoided.
Figure 10 shows a typical AVCC noise plot measured directly at the PLL. While
the AVCC noise generated by the PLL can be easily decoupled, the challenge is
to decouple outside noise from the SDRAMs and the system back into the
AVCC/AGND system of the PLL. For further details, please refer to the CDC2509
application report[5].
4.5
PLL Loop Bandwidth
The CDC2509A/2510A has a higher PLL loop bandwith than the non-A version.
A PLL that is not able to track SSC due to its low loop bandwidth has a higher
tracking skew. Figure 5 shows the non-A version of the CDC2510 effectively
filtering the clock output jitter of the synthesizer from 306 ps to 147 ps. However,
the tracking skew shown in Figure 6 is ±300 ps. Figure 8 shows the tracking skew
of the CDC2510A PLL fed by exactly the same input clock signal. Here, tracking
skew caused by input modulation is no longer visible. The dominant factor is the
jitter of the CDC2510A PLL, resulting in a peak tracking skew of ±210 ps.
10
SCAA039
SSC System Performance
PLL Tracking Skew
Apart from cycle-cycle jitter, tracking skew is an important measure of system
performance. A high tracking skew is caused by a mismatch of the SSC
modulation parameters used by the clock synthesizer and the loop bandwidth of
the receiving PLL. It is measured as the dynamic phase delta between the clock
input and the PLL output on a cycle-by-cycle basis. Normalized tracking skew is
calculated by subtracting the static phase error of the PLL from the dynamic
(cycle-by-cycle) phase error. Tracking skew is mixed with jitter of the synthesizer
output that could not be filtered by the PLL loop filter and the inherent PLL jitter.
It cannot be measured separately. Refer to Section 5 for measurement details.
CDC2510A
FREQUENCY
vs
CLOCK STOP TIME
120
100
f – Frequency – MHz
4.6
80
Unit #5
Unit #1
Unit #3
Unit #4
Unit #2
60
40
20
0
0
5
10
15
20
25
30
35
t – Time – µs
Figure 11. PLL Slow Down after CLK Pin is Held Low
Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)
11
SSC System Performance
CDC2510A
FREQUENCY
vs
CLOCK START TIME
120
f – Frequency – MHz
100
80
60
40
20
0
0
5
10
15
20
25
30
35
40
t – Time – µs
Figure 12. PLL Start Up after CLK Stream is Started
As described in the CDC2509A/2510A datasheet, the outputs of the PLL can be
switched off to a static low state while the PLL and the FBOUT are still running.
Of course, this requires a constant stream of input clocks to maintain the PLL in
a locked mode. As soon as the outputs are enabled again, the CDC2509A/2510A
are back in their standard mode of operation.
Shutting down the AVCC to GND puts the device into a PLL-bypass mode. Here,
the outputs, if enabled, follow the clock input like a buffer. After reapplying the
AVCC, the PLL first needs to operate for the specified stabilization time before
jitter and phase error are within specification.
A third option exists by switching off the input clock for a certain period of time.
In this case, the PLL loses its lock condition and lowers its frequency to a certain
minimum in the range of a few megacycles. Figure 11 illustrates this process
takes a couple of microseconds. A similar process starts as soon as the clock
signal is reapplied to the PLL (see Figure 12). Both, the shutdown and the
wake-up time vary among the process lots. These parameters are not ensured
and caution should be taken in calculating shutdown and wake-up times, if
needed in the system application at all.
12
SCAA039
SSC System Performance
5 Measurement Techniques
There are several ways of measuring the parameters described in this application
note in a system. Data acquisition equipment commonly used are:
• Digital sampling scopes (DSOs) using infinite persistence mode
• Real time scopes
• Digital time scopes
For a rough system check on jitter and phase error, an infinite persistence scope
is sufficient. Recording the clock input and PLL output signals for a while comes
up with two bands of traces on the scope screen. The width of the band describes
the maximum and minimum phase seen on the clock input and output signals.
This method is not suitable to measure accurate phase error, tracking skew, or
cycle-to-cycle jitter, as there is no information about which input trace belongs to
what output trace.
Using a real time scope, cycle to cycle as well as channel to channel information
is stored in the real time scope’s memory. Post-processing software exists to
calculate cycle-to-cycle jitter, peak-to-peak jitter, and phase error[6]. The only
drawback is the trade-off between sampling rate and channel memory of a real
time scope. To analyses SSC parameters, channel memory needs to be deep
enough to record at least 1.5 periods of SSC modulation at a sufficient sampling
rate (>2Gs/sec).
Finally, a unique version of scope, called digital time scope[7], is a common
instrument to measure dynamic PLL parameters. The principle of operation is like
a very precise, very fast stop watch. The watch is triggered (armed) by one
channel (in this case the clock input) and stopped by a transition of the second
channel (the PLL output). This way, dynamic phase error can be measured by
taking enough shots of the stop watch. The average result is equal to the static
phase error of the PLL. For further details, please refer to the equipment
manufacturers datasheets.
6 Summary
Although the low loop bandwidth PLL of the CDC2509/2510 non-A version was
able to follow the SSC waveforms shown in this document, it is highly
recommended that the high bandwidth version CDC2509A/2510A be used if SSC
clocking is being used. Process variations of both the synthesizer, and the PLL
can cause the non-A version to lose lock , resulting in excessive tracking skew.
Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)
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References
References
1. CDC2509A/2510A datasheet SCAS603, April 1998
2. CDC2509A/2510A IBIS model is available from Texas Instruments
3. K.B. Hardin, et al., Spread Spectrum Clock generation and Associated
Method, US Patent 5,488,627, Jan 30, 1996
4. M.Zhang, Intel Corporation, Notes on SSC and Its Timing Impacts Rev 1.0,
Feb 98
5. Application Note, High Speed Clock Distribution Design Techniques for
CDC509/0, Texas Instruments, March 1998
6. M1 system, using the HP 54720D Real Time Scope, Amherst Systems
Associates, Amherst MA, USA
7. Wavecrest DTS systems, Wavecrest Corporation, Edina, Minnesota, USA
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SCAA039