Toward the End of the MOSFET Roadmap: Investigating Fundamental Transport Limits and Device Architecture Alternatives by Anthony Joseph Lochtefeld Bachelor of Science in Electrical Engineering Ohio Northern University, May 1990 Master of Science in Electrical Engineering Purdue University, August 1996 Submitted to the Department of Electrical Engineering and Computer Science in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science at the Massachusetts Institute of Technology May 2001 ©Massachusetts Institute of Technology, 2001. All Rights Reserved. A u th o r ............ . . ... .... . . .... . ........ e n. Departmen olfrical Engineefing and Computer Science May 15, 2001 Certified by ......................................... Dimitri A. Antoniadis Professor of Electrical Engineering -fTl9sis Supervisor ......... Accepted by ................... .ASSOCUSE s JUL . 1200 LIBRARIES Arth rC. Smith rofessor of Electrical Engineering Graduate Officer ARKER Toward the End of the MOSFET Roadmap: Investigating Fundamental Transport Limits and Device Architecture Alternatives by Anthony J. Lochtefeld Submitted to the Department of Electrical Engineering and Computer Science on May 15, 2001, in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science Abstract MOSFET scaling and performance has progressed rapidly in recent years, with physical gate lengths for electrostatically sound devices reaching 30 nm or below: near the prospective scaling limits for traditional bulk MOSFETs. This work investigates several key issues for this "end of roadmap" regime. Focus is on understanding the limitations to carrier velocity in MOSFET inversion layers as channel lengths are scaled well below 100 nm, and on relaxing these limits through architectural alternatives to bulk MOSFETs. It has been proposed that drain current is ultimately limited by the rate at which carriers can be thermally injected from the source into the channel. In this work it is shown that commonly used techniques for experimentally determining carrier velocity are insufficient to determine how close modem MOSFETs operate to this ballistic or "thermal limit". A new technique is proposed, and applied to two advanced industry technologies with deep-sub-100-nm channel lengths. It is shown that a IV NMOS technology with Leff < 50 nm operates at no more than -40% of the limiting thermal velocity. Furthermore, no indication is found that continued scaling is bringing us closer to the thermal velocity limit. Via simulation, the relationship between mobility and scaling is investigated for bulk silicon NMOSFETs and FDSOI (Fully-Depleted Silicon-On-Insulator) alternatives, focusing on the 50 and 25 nm Leff generations. Scaling of bulk MOSFETs well below 100 nm Leff requires heavy channel doping, leading to degraded low-field mobility. Provided that the gate workfunction is used to determined the threshold voltage, FDSOI devices do not suffer from this trade-off, by virtue of the fact that their channel can be undoped. It is shown that single-gate FDSOI is, accordingly, an attractive alternative down to 50 nm Leff. For deeper scaling, double-gate FDSOI should have approximately a 3X mobility advantage over bulk NMOS. With careful determination of channel length, inversion-layer charge, and series resistance, it is possible to study experimentally the relation between channel length and mobility in deep-sub100-nm MOSFETs. With the aid of inverse modeling techniques, evidence is found that in the very shortest modern MOSFETs, mobility is less then would be expected from "universal" mobility, and independent of transverse field. This may be indicative of a transition in the dominant scattering mechanism, from surface- to Coulomb- scattering. 3 The relevance of low-field mobility to the performance of deep-sub-100-nm MOSFETs is not well understood. In this work this relationship is studied experimentally: mobility (with low lateral electric field) is modified by externally applying uniaxial stress to NMOS devices, and the corresponding shift in carrier velocity (with high lateral field) is measured. The dependence of velocity on mobility is found to be significant, and is found to correspond well with the predictions of energy-balance modeling. Given their promise for scalability without mobility degradation, the design space for FDSOI MOSFETs merits detailed study. Via 2D simulation, scalability and drive current are investigated for three basic FDSOI alternatives: single-gate, and double-gate either with symmetrical workfunction mid-gap gates or asymmetrical workfunction n+p+ gates. For the single-gate device, it is shown that scaling below Leff = 35 nm may not be achievable for practical silicon film thickness, unless Ioff requirements are relaxed. For double-gate devices we have shown that hypothetical mid-gap top- and bottom- gates are superior to n+/p+ poly gates, for both scalability and drive current. Realization of the ideal double-gate device structure involves three major technical challenges: formation of gates above and below a thin single-crystalline silicon layer, achievement of fine alignment between top- and bottom-gates, and achieving low source/drain resistance for the thin silicon film. These issues are addressed in this work through demonstration of three primary technologies: wafer bonding with pre-patterned features, interferometric alignment, and selective epitaxy for raised source/drains. Thesis Supervisor: Dimitri A. Antoniadis Title: Professor of Electrical Engineering 4 Acknowledgments Many individuals have supported me, both professionally and personally, throughout the course of this work. I would like to thank Professor Dimitri Antoniadis for years of guidance and patience, and for allowing me considerable freedom in pursuing this research. His technical direction and vision have made this work possible. I would also like to thank, especially, professors Hank Smith, Jim Chung, Eugene Fitzgerald, Anantha Chandrakasan, and Judy Hoyt for guidance in various stages of this work, and professors Smith and Hoyt for serving as readers of this thesis. I would also like to thank my former advisor, Professor Michael Melloch at Purdue University, for the opportunity to work in his group and my introduction to this field. The exchange of knowledge and perspectives with members of my research group has been invaluable. I am thankful to have had the chance to work with Isabel Yang, Melanie Sherony, Zachery Lee, Mark Armstrong, Andy Wei, and Keith Jackson, all of whom now have a "Dr." before their name. And many others: Andrew Ritenour, Siva Narendra, Hasan Nayfeh, Ihsan Djomehri, Jim Fiorenza, Isaac Lauer, Ilia Sokolinski, Corina Tanasa, Dr. Jong-Ho Lee, Dr. Duheon Song, and Dr. Hitoshi Wakabayashi. Collaboration with members of other research groups at MIT has been important as well. In particular I would like to thank Dr. Thomas Langdo, Mitchell Meinhold, and Dr. Maya Farhoud. Thanks as well to Euclid Moon, Dr. David Pflug, Dr. Juan Ferrara, Dr. Matthew Currie, and Dr. Lalitha Parameswaran. Many thanks to the research, support and administrative staff at the Microsystems Technology Laboratory and the Nanostructures Laboratory. Among many names I would like especially to mention Bernard Alamariu, Paul Tierney, Patricia Burkhardt, James Carter, Dan Adams, and Wayne Price. Many others as well: Dr. Vicky Diadiuk, Joe Walsh, Barry Farnsworth, Paudely Zamora, Kurt Broderick, Paul Mcgrath, Ron Stoute, Joe DiMaria, Dennis Sullivan, Brian Foley, Jim Daley, Deb Hodges-Pabon, Christina Gordy, and Mark Mondol. And more. And at Lincoln Laboratory: special thanks to Andy Loomis; thanks also to Jim Reynolds, Jim Burns, and Skip Hoyt. Beyond the research, life here has been enriched by the people, friends in the lab, office, and pub. Andy, Andy, and Andy. Mark, Fletch, Tom, and Isaac. It's been some trip, hasn't it? And beyond MIT, I think of a few special people who have given me support through these long years. Old friends and new, you know who you are. And Brenda, who has kept me going through the end of all this. And finally my family, and most of all my parents. 5 6 Contents 1 Introduction 1.1 Background ................................................. Velocity and Scaling in MOSFETs: the Roadmap Perspective ......... Velocity and Scaling in MOSFETs: Device Physics Perspective ....... Goals of This Work .......................................... 1.2 Outline ....................................................... 21 21 22 24 25 26 28 2 Experimental Determination of Carrier Velocity in Deeply Scaled NMOS 28 2.1 Introduction ................................................. 29 2.2 The Thermal Injection Limit ..................................... 2.3 Investigation of Velocity Measurement Techniques by Simulation .......... 31 32 Carrier Velocity from Saturated Transconductance .................. Carrier Velocity from Drain Current and Short-Device CV............ 34 35 Simulation Results: Comparison of Techniques..................... 39 2.4 Experimental Results .......................................... 39 Technology Parameters ....................................... 43 M easurements .............................................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 How Close? . . 46 ----.................................. Dependence of veff on Vdd 2.5 Further Investigation of the Inversion-Charge Relationship Between Long and 47 Short Devices .............................................. 51 Conclusion .................................................. 2.6 3 Mobility and Scaling I: Universal Mobility in Bulk and FDSOI MOSFETs 3.1 Introduction ................................................. Universal Mobility .......................................... 3.2 Mobility and Scaling in Bulk MOSFETs ............................ Bulk MOSFET Scaling ....................................... Transverse Field Determination ................................. M obility versus Generation .................................... 3.3 Mobility and Scaling in FDSOI MOSFETs........................... 3.4 Results ....................................................... 3.5 Conclusion .................................................. 7 52 52 52 53 53 58 60 60 62 64 4 Mobility and Scaling II: Channel Length Dependence in Super-Halo NMOS 4.1 Introduction ................................................. Scattering Mechanisms in Deeply Scaled Bulk MOSFETs ............. 4.2 On Experimental Determination of Low-Field Mobility. .......................... 4.3 Experimental Results: Long Channel Mobility ........ 65 65 66 67 .70 .70 71 .75 .75 .78 79 80 Mobility versus Vgs .......................... 4.4 4.5 4.6 Mobility versus Effective Transverse Field ......... Experimental Results: Mobility versus Channel Length. Effective Mobility versus Channel Length at Constant Effective Mobility versus Channel Length at Constant Effective Mobility versus Channel Length at Constant Technology B ................................ Investigation of Sources of Error................... Effects of Error in Rsd and Leff Estimates .......... Results for Longer Channels..................... C onclusion ................................... Gate Bias ... Overdrive ... Effective Field .... .... .... . . . . . . . . . .. . ... ..... .... .81 81 83 .83 5 Electron Velocity Dependence on Mobility in Deep-sub-100-nm bulk NMOS 5.1 Introduction ................................................. 5.2 Experiment ...................................... M obility with Uniaxial Stress ....................... 5.3 Velocity versus M obility .......................... On Sources of Error in RR Estimation................. Series Resistance Effects .......................... Drain Bias for Low-Field Measurements .............. 5.4 Energy Balance M odeling ........................... 5.5 On Energy- and Momentum- Relaxation Interdependence Conclusion ...................................... 85 85 .86 86 89 .91 91 93 .94 95 .96 6 FDSOI Design-Space 6.1 Introduction .............. Methodology ............ 6.2 Single Gate Scaling Results. . 6.3 Double Gate Scaling Results. DG Alternatives ......... Simulation Results ....... 6.4 Relaxing Ioff Criteria ....... 6.5 Energy Balance Simulation of Ion 6.6 Conclusion ............... 97 .. 97 7 Double-Gate Fabrication Technology 7.1 Introduction ...... 7.2 Formation of Gates 7.3 Alignment of Gates 7.4 Reduction of S/D Parasitic Resistance. . Raised Source and Drain Process . .. 113 .113 .113 .116 .116 .119 . 97 .. 99 .101 .101 .103 .108 .110 .112 8 7.5 C onclusion ................................................... 121 8 Conclusion 8.1 Summary of Results........................................... Experimental Results ........................................ Simulation Results .......................................... 8.2 Future Work................... .... .......................... Experimental Analysis of Deep-Sub-100-nm Devices ............... Fabrication ............................................... 122 122 122 122 123 123 125 A Simulation Techniques 134 9 10 List of Figures Figure 1.1: Effective electron velocity veff required to meet 1999 ITRS Roadmap targets (NMOS). Unscaled T0 X: > 1.5 nm. Unscaled Vt: 0.25 V. Vt values used (Table 1.1) correspond to short-channel devices in each technology, so are well below roadmap guide23 line of 0.4 V . .......................................................................................................... Figure 1.2: Potential profile and electric fields in a bulk NMOSFET channel, for Vgs = Vds = Vdd. For acceptably low DIBL (Drain Induced Barrier Lowering) IEy must be sig. 25 nificantly greater than Ex . ........................................................................................ Figure 1.3: FDSOI M OSFET Architectures .............................................................. 26 Figure 2.1: Carrier velocity considered at source-to-channel barrier. Unless transport is ballistic, average carrier velocity (veff) at the source-to-channel barrier must be less than the thermal injection velocity vO. For deep-sub-100-nm devices conduction-band peak is typically within several nm of source-channel transition (x=0, defined as the point where source doping falls to 2x10 19 cm- 3 [19]). Note that simulations for bulk MOSFETs indicate a conduction-band peak much less pronounced than shown in this schematic30 Figure 2.2: Illustration of relationship between carrier velocity and inversion-charge density along MOSFET channel. Since there is no single ve for the channel, different extraction techniques for ve can give significantly different answers.................................30 Figure 2.3: Monte-Carlo simulation results: electron velocity as a function of position in an ultra-scaled bulk NMOS channel. T0 X phys=1.5 nm. Vgs=Vds = 1V. Courtesy of D. 1 F ran k (IB M )....................................................................................................................3 Figure 2.4: NMOSFET simulation structure (Avant! MEDICI TM [13]). Mobility models used in this chapter: (a) for low Ex, concentration-dependent pt; (b) for EY, Si-Si0 2 universal g assumed, with coefficients from [13]; (c) for high Ex, either a Caughey-Thomas relationship [64] for DD simulations, or an electron-temperature dependent model as described in Appendix 1 for EB simulations. For DD simulations, electron saturation ve- 11 locity vsat = 1.3x 10 7 cm/s. For EB simulations, energy relaxation time t vsat=1x10 7 = 0.1 ps, and cm/s. From simulation, T0 xelec was assessed from the slope of the dQi/dVgs curve for mid-channel for a long-channel device at Vds=O; slope was taken at Vgs=Vdd- Classical distribution was assumed for inversion layer electrons for all simulations. Leff is determined by the 2x10 19 cm- 3 S/D doping points. Fermi-Dirac statistics. External lumped resistance of 90 Q2pm per side, to give total Rsd = 220 Qtm........................32 Figure 2.5: EB simulation results for the device of Figure 2.4. Investigating components of transconductance as a function of position in channel. (Avant! MEDICI TM). ........ 33 Figure 2.6: Example of Qi(xo) determination. Capacitance is measured on large device. For large device, overlap C is inconsequential, so area under curve corresponds to inversion layer charge. Integration limit is adjusted by AVt (= DIBL + Vt-rolloff - IonRs) as determined from the target short device. Qi(xo) = (Qio+AQi) / (W*L). NMOS. ....... 35 Figure 2.7: EB simulation for the device of Figure 2.4: area between curves gives which corresponds to Qi as determined in Eqn. (2.9). ............................................... Qcgs, 36 Figure 2.8: DD simulation results (solid): output characteristics for the device of Figure 2.4, matching saturated gm and Ion of experimental technology A (discussed in Section 2 .4 ). ................................................................................................................................ 37 Figure 2.9: Simulation results: conduction-band and carrier velocity vs. position for bulk super-halo device of Figure 2.4. Velocities at five marked points along the channel correspond to values given by different MOSFET carrier velocity extraction techniques (Table 2.1). Solid symbols are corrected for S/D series resistance, open symbols are uncorrected. Vt, Txelec, Rsd, and Ion approximately match the "Technology A" under in- vestigation. DIBL here is 66 mV/V. (a) DD model: vsat = 1.3x107 cm/s (b) EB model: = 0 . I s.........................................................................................................................3 8 Figure 2.10: Monte-Carlo results: output characteristics and electron inversion-layer velocity, for a 25 nm Leff NMOSFET design presented in [2]. Courtesy of D. Frank (IBM). Inversion-layer distribution is classical. Our estimates of vid and vgm shown are approxim ate v alues. ................................................................................................................... 40 Figure 2.11: Example output characteristics for NMOS devices from two technologies under investigation. DIBL is similar for both devices shown, 60-70 mV/V.............42 Figure 2.12: Measured Vt and DIBL for technology A. Results shown are for same set of devices used for inverse-modeling determination of Rsd and Leff. Leff corresponds to the points where S/D doping falls to 2x10 19 cm-3 [19]. DIBL is via Eqn. (2.10). ........ 42 12 Figure 2.13: Experimental results: carrier velocity by four techniques vs. DIBL, for technology A. Solid symbols are corrected for S/D series resistance, open symbols are uncorrected. The implicit variable in the x-axis is gate length.....................................44 Figure 2.14: Experimental results: carrier velocity by four techniques, for technology B. Solid symbols are corrected for S/D series resistance, open symbols are uncorrected. .45 Figure 2.15: Experimental results: effective electron velocity measured from vidiDIBL=100 mV/V in all cases. For technologies A and B, as a function of Vdd. ..... 47 Figure 2.16: EB simulation result for the device of Figure 2.4: Incremental gate capacitance vs. channel position, with Vgs = Vds = IV. Compared with and without lumped external resistance, to long channel value C'iong-inv (Vds = 0). x0 , indicated above, is position of Ec-peak from simulation at Vgs=Vds=lV. (Determined from a lateral cut through the device, at approximately the inversion layer depth)...............................49 Figure 2.17: EB simulation result for the device of Figure 2.4: Inversion layer charge vs. channel position for first half of channel. Vds=1V. Upper-right insert shows size of corrections made to long-channel Qj to obtain Qi(xo) via Eqn. (2.6). Short-channel correc50 tion increases, and Rsource correction decreases, Qi(xo). .......................................... Figure 2.18: Illustration of three methods of determining conduction-band potential with position: top two are weighted averages of electron potential, to the depth specified. Bottom is simple 1-D cut along the length of the device, at 0.4 nm. DD simulation, for structure of Figure 2.4; only first half of channel is shown...............................................51 Figure 3.1: Measured NMOS effective mobility for FDSOI and bulk MOSFETs. From [37]. The deviation for Eeff < 0.6 MV/cm is likely due to overestimation of Qj that can occur unless Vgs >> Vds [38] when measuring via the split-CV method [52]. Vds =50 mV. 54 Modern bulk MOSFETs operate at Eeff > 1 MV/cm ................................................. Figure 3.2: Simulation structures for NMOS bulk doping alternatives investigated. Junctions are spatially abrupt. For (a) 09 = 4.19 V (for n+ Si). For (b) c9 = 4.19 V and <Db = 5.25 V (for p+ Si). For Nb and Tstep values by scaling node, see Figures 3.4 - 3.6. 54 Source and drain are n+. ............................................................................................. Figure 3.3: Results for uniform-doped bulk NMOSFET: shown are 2D simulation data points for Vt vs. Nb, from which Nb values meeting criteria (2) are interpolated. (Avant! M ED IC I TM )..................................................................................................................56 Figure 3.4: 2D simulation results for uniform-doped bulk NMOSFET: doping level (Nb) 13 correlated with Leff, across four generations. Requisite doping levels to meet two separate criteria are show n. ............................................................................................ 57 Figure 3.5: Results for perfect step-doped bulk NMOSFET: shown are 2D simulation data points for Vt vs. step depth, from which Tstep values meeting criteria (2) are interpolated. (Avant! M ED ICI TM )..................................................................................... 57 Figure 3.6: 2D simulation results for perfect step-doped bulk NMOSFET: step depth (Tstep) correlated with Leff, across four generations. Tstep required for meeting two separate criteria are show n. ............................................................................................ 58 Figure 3.7: 2D simulation results: maximum effective field Eeff along NMOSFET channel for two bulk doping alternatives, with n+ poly gates, using Eqn. (3.4). Shown vs. scaling across four generations. Devices are in saturation (Vds = Vds = Vdd)- Qi/q = C' ,(Vdd-Vt)/q = 1x10 13 cm-3 was used for all generations. Also shown is dashed line for Eeif = Qj / 2 Fsi. This corresponds to zero channel charge and no built-in potential between top and bottom contacts (Qb =0, (bi = 0), which is the situation for SG- and DGFDSOI devices with mid-gap workfunction gates......................................................59 Figure 3.8: Calculated universal-curve mobilities for two bulk NMOSFET doping alternatives, correlated with scaling. Values are plotted using Eqn. (3.2) with Eeff values from Figure 3.7. For Eqn. (3.2), go = 670 cm2/Vs, Eo= 0.67 MV/cm, n = 1.6, all according to [31]. Included is dashed line corresponding to the limit of Qb = 0 and cDbi = 0, applicable to SG- and DG- FDSOI devices with mid-gap workfunction gates. ......................... 61 Figure 3.9: Universal effective NMOSFET mobility (for low lateral field) from Eqn. (3.2), with regions of operation delineated for four different bulk and FDSOI device architectures. For each device architecture, the range of Eeff corresponds to: 0.8x10 13 < Qi/q < 1.2x1013 cm- 3 . In the case of DG-Dmg, Qj is the sum of inversion charge in both inversion layers, except for special case noted in (b). For DG-Dmg and SG-mg, since Qb = 0 Eqn. (3.3) was used to estimate Eeif, independent of channel length. For bulk architectures, peak Eeff along channel was determined via 2D simulation, as Esurf - Qi/2cs. ........................................................................................................................................ 63 Figure 4.1: Universal vs. bulk-limited mobility as a function of channel doping. NMOS Universal mobility is from Eqn (3.2) using coefficients from [31], and is based on Ni = 1x1013 cm-3 . Calculation of Eeff is one-dimensional from Eqn. (3.3): lateral charge sharing effects are ignored. Bulk-limited mobility is for electrons in p-region. ............. 67 Figure 4.2: Simulation results: comparison of mid-channel Qi-Vgs relationship in short vs. long NMOS devices, with TOxelec = 1.9 nm and uniform channel doping: Na = 1.25x10 18 cm-3 for short devices and 0.6x10 18 cm- 3 for long. Abrupt junctions are 21 nm 14 deep. DIBL > 300 mV/V for 35 nm device, 100 mV/V for 50 nm device, and < 10 mV/ 70 V for the 500 nm device. ............................................................................................. Figure 4.3: (a) Gate leakage current I9 for technology A, with effect on source and drain currents. (b) Correction to allow Id determination for mobility measurements..........72 Figure 4.4: Measured effective mobility vs. Vgs for technologies A and B...............73 Figure 4.5: Two experimental methods of Eeff determination....................................73 Figure 4.6: Measured effective mobility compared for two methods of Eeif determination. Technology B. Qj and Qb are from split-CV meas. [52]. Toxelec = OX /C' gsd(Vgs) -...7 Figure 4.7: Measured effective mobilities for technologies A and B, plotted along with universal curve mobilities. For measured data, Eeff is determined via Eqn. (4.8).........75 Figure 4.8: Measured Iteff vs. Leff for different gate biasing. Technology A. Toxelec=2.4 76 nm . DIBL at Leff = 45 nm = 120 mV/V...................................................................... Figure 4.9: Intrinsic drain-to-source bias in (= Vds - IdRs) channel for pgff measurements 77 of Figure 4.8. Applied Vds is 50 mV. ...................................................................... Figure 4.10: Measured dependence of short-device pgef extraction on applied Vds, for a 77 . ................................................................................................. range of Leff. Vgs = Figure 4.11: Measured Reff vs. Leff for different gate overdrive. Technology A. Applied 78 V gs is indicated in inset............................................................................................. Figure 4.12: Range of Qj corresponding to Figure 4.11. ........................................... 79 Figure 4.13: Measured pge vs. Leff for different Eeff. Technology A. Eeif is determined 80 via Eqn. (4.8). Applied Vgs is indicated in inset........................................................ Figure 4.14: Effects of error in Leff estimation, +/- 5nm. Actual estimated AL is 65 nm. 82 (a) assumes AL = 60 nm. (b) assumes AL = 70 nm. ................................................ Figure 4.15: Effects of error in S/D series resistance estimation, +/- 10%. Actual estimated Rsd is 190 Qpm. (a) assumes Rsd = 209 2gm. (b) assumes Rsd = 171 2gm..82 15 Figure 4.16: Measured pge vs. Leff for different gate biasing. Technology A. T0 "elec=2.4 83 nm. Results for points of Leff < 150 nm same as in Figure 4.8. .............................. Figure 5.1: Schematic illustration of strain experiment............................................87 Figure 5.2: Experimental results: normalized mobility shift in long and short (Leff = 10 gm, -45 nm) devices vs. uniaxial strain. Each point represents a fractional shift relative to unstrained value (which is represented by *). ........................................................ 88 Figure 5.3: Experimental results: normalized velocity shift (near the source) in short (Leff -45 nm) device vs. uniaxial strain. Each point represents a fractional shift relative to unstrained value (which is represented by *). .............................................................. 89 Figure 5.4: Experimental results: 6 ve extracted by two methods, versus long-device kteff. Mobilities are measured at (VgsVds) = (IV, 50 mV). Velocity viad is measured at (Vgs,Vds) = (IV, IV). Velocity vgmi is from peak saturated intrinsic transconductance, measured at Vds= 1V; the peak occurs for Vgs somewhat less than 1V. For this data 6 ve / pgeff = 0.31 when using vgmi, and 0.30 for Vidi. Each point represents a fractional shift relative to unstrained value (which is represented by *) ........................................... 90 Figure 5.5: Experimental results: 8ve extracted by two methods, versus short-device pg9ff. Gate and drain biases are as described for Figure 5.4. For this data, the ratio Rg = 6 ve / 4Peff = 0.48 when using vgmi, and 0.46 for vidi. Each point represents a fractional shift relative to unstrained value (which is represented by *). .................................. 91 Figure 5.6: Resistance test structure setup. Current was forced through terminals 1-4, and the corresponding voltage drop measured between terminals 2 and 3. Test structure resistance Rt was measured for strain = 0, 0.04, and 0.08%. Rt V3 -V2 / 114 .-........ -93 Figure 6.1: Scaling simulations for SG-CDmg device. (Avant! TMA Medici [13]). Driftdiffusion with Lombardi mobility model. No gate depletion. S/D are n+ 1.5x1020 cm~3 , abrupt junctions. Na = 1x1015 cm~3 in channel. In (a) and (b) each point corresponds to a set of IV transfer characteristics from device with specified Tsi, from which DIBL (according to Eqn. 2.10) and Ioff were extracted. Tox and Vdd from Table 6.1...............100 Figure 6.2: Interpolated results from Figure 6.1: Tsi required per scaling node of Table 6.1. TX and Vdd vary with Lcff according to Table 6.1...............................................101 Figure 6.3: Alternative double-gate FDSOI structures.................................................102 16 Figure 6.4: Ratio in inversion charge in DG-n+p+ vs. DG- 4 mg MOS, according to longchannel charge-sheet m odel..........................................................................................102 Figure 6.5: Scaling simulations for DG-n+p+ device. Model and doping specifications from Figure 6.1 apply. Tox and Vdd from Table 6.1...................................................103 Figure 6.6: Scaling simulations for DG-mg device. Model and doping specifications from Figure 6.1 apply. Tox and Vdd from Table 6.1...................................................104 Figure 6.7: Interpolated results from Figure 6.5-6.6: Tsi required to meet short-channel criteria for each scaling node of Table 6.1. Tox and Vdd vary with Leff according to Table 104 6 .1 . ............................................................................................................................... Figure 6.8: Simulation results: DIBL and Vt-rolloff for DG structures. Vt-rolloff = Vt(long-device) - Vt(short device), where Vt is linear extracted at Vds=50 mV. Tsi values used are from Figure 6.7, meeting the Ioff requirement. Other parameters as per Table 105 6.1. D IB L is via Eqn. (2.10). ....................................................................................... Figure 6.9: DG-n+p+ long-channel Vt: dependency on Tsi and Tbox, with corresponding range of DG-Img long-channel Vt indicated, upper right. Analytical are ID Laplace solutions (appropriate in the limit of zero channel depletion charge) for Qi/q=1 x 1011 cm-3 . 10 6 ...................................................................................................................................... Figure 6.10: Simulation results: effect of lateral S/D doping gradient on Tsi required to meet Ioff! 1x10- 8 A/gm. Shown versus scaling nodes of Table 6.1. Simulation grid spacing is 0.6 nm at transitions from S/D to channel. Tox and Vdd vary with Leff according to 10 7 T ab le 6 .1. ..................................................................................................................... Figure 6.11: SG-Dmg MOSFET, interpolated results from Figure 6.1: Tsi required per scaling node of Table 6.1. Tox and Vdd vary with Leff according to Table 6.1. .......... 108 Figure 6.12: DG-n+p+ MOSFET, interpolated results from Figure 6.5: Tsi required per scaling node of Table 6.1. Tox and Vdd vary with Leff according to Table 6.1...........109 Figure 6.13: DG-dmg MOSFET, interpolated results from Figure 6.6: Tsi required per scaling node of Table 6.1. Tox and Vdd vary with Leff according to Table 6.1. .......... 109 Figure 6.14: Energy balance simulation results for Ion and Ioff for the three FDSOI architectures. For solid symbols, lumped resistances were added to the source and drain (80 Qgm per side). Total Rsd for solid symbols is 190-200 Qitm; for open symbols, 30-40 17 Qsm. Tsi values chosen to meet Ioff criterion(Figure 6.2-6.7); other parameters are for the 50 nm node in Table 6.1. rw=0. 15 ps, Lombardi mobility model. .............................. 110 Figure 7.1: Three fundamental structural possibilities for DG-FDSOI MOSFETs; illustration from [77 ]............................................................................................................114 Figure 7.2: Illustration of the SOIAS flip-and-bond process, applied to double-gate MOSFET fabrication . ............................................................................................................ 115 Figure 7.3: Illustration of the IBBI alignment scheme, applied to double-gate fabrication via X -ray lithography. .................................................................................................. 117 Figure 7.4: Test double-gate structures fabricated via pre-patterned flip-and-bond, with IB B I alignment. ............................................................................................................ 117 Figure 7.5: Sacrificial SiNX spacer / selective epitaxial raised S/D process. (a) Gate stack is etched using LTO (low-temperature oxide) hard-mask, followed by re-ox (not shown) and S/D arsenic implants. (b) LTO liner and SiNx LPCVD deposition (13 and 90 nm respectively), followed by anisotropic spacer RIE etch in NF 3 :0 2 , stopping on LTO liner. (c) Pre-epitaxial wet clean (H2 0 2 :H 2 SO 4 followed by HF). (d) Selective removal of SiNx spacers in H 3PO 4 , followed immediately by UHVCVD selective growth..........118 Figure 7.6: Selective epitaxial raised S/D results, shown for a bulk MOSFET. Epitaxial layer is 75 nm thick. The 13 nm LTO liner between epi and n+ poly is not visible here, but its presence can be inferred from the lack of epi-growth on the n+ poly side-wall. (SEM im age taken at 10000O X , uncoated)...................................................................119 Figure 7.7: XTEM images. (a) Faceting at Si / LTO interface, with 750C UHVCVD growth via SiH 2 Cl 2 /H2 - (b) Faceting suppressed, w/ 750C growth via SiH 2 Cl 2 /H2 /PH 3 ...................................................................................................................................... 1 20 Figure 8.1: Illustration of alternative method for 9gef determination in short NMOS devices, adapted from [93]. For given Lmask, mobility is found from dRtot / dLmask. Inversion charge density Qj is determined from long-device CV integration, corrected for short device according to Eqn. (4.6). Results are extremely sensitive to the polynomial fit (here, to degree 3) to the data, suggests that more points are required for reliable results. Techn ology A . .............................................................................................................. 124 18 List of Tables Table 1.1: 1999 ITRS Roadmap Parameters ............................................................. 23 Table 2.1: Summary of the Carrier Velocity Techniques Investigated........................36 Table 2.2: Parameters for NMOS Technologies Investigated .................................. 41 Table 2.3: Comparison of carrier velocity, ballistic efficiency, and transmission coefficients. Experimental results for technologies A and B, plus Monte-Carlo results for 25 nm from [2]. 0 = veff/vo = T/(2-T). vo values estimated from [18] as 1.6, 1.7, and 1.9x10 7 cm! s, respectively, moving from right to left in the table. veff = vidi at DIBL = 100 mV/V. For Monte-Carlo device, Qj(xO) was estimated from (FOx / Toxelec)(V gs-Vt). As this method of charge determination was different from the capacitive techniques used for technologies A and B, some uncertainty was introduced in the comparison, reflected in that range of values 46 for M C results. .................................................................................................................. Table 3.1: Design N ode Param eters ........................................................................... 55 Table 6.1: FDSOI Design Node Parameters .............................................................. 98 Table 6.2: Normalized Transconductance for Three FDSOI Architectures; Leff = 50 nm 11 1 .......................................................................................................................................... 19 20 Chapter 1 Introduction 1.1 Background For several decades silicon bulk MOSFET microprocessor scaling and performance has progressed exponentially: transistor gate density and microprocessor speed have doubled approximately every 18 months [1]. This progress has been made possible by enormous advances in all areas of semiconductor device fabrication: lithography, thin-film growth and deposition, reactive ion etching, channel implant engineering, as well as device contact, interconnect and packaging technologies. For digital logic applications silicon CMOS has long outperformed alternatives, particularly for mass-market applications like desktop and portable computing, where power consumption and heat dissipation must be limited. Many past predictions of a slowdown or end to this era of rapid progress have been based on over-conservative assumptions regarding one or another of these fabrication technologies. However, in recent years research MOSFET devices have been fabricated which may be approaching more fundamental limits: it has been projected that both band-to-band and gate-oxide tunneling will prevent channel length scaling below -20 nm [2]. Electrostatically sound devices with gate lengths reaching down to 25-30 nm [3][4] have been recently demonstrated. Although industry projections, as found in the 1999 International Technology Roadmap for Semiconductors (ITRS) [1], suggest devices of 21 these dimensions will not be in production until 2011-13, we appear to be approaching the "end of roadmap" regime. This work focuses on understanding the limitations to carrier velocity in MOSFET inversion layers as channel lengths are scaled well below 100 nm, and on relaxing these limits through architectural alternatives to bulk MOSFETs. Velocity and Scaling in MOSFETs: the Roadmap Perspective For a given gate capacitance and gate overdrive, drain current corresponds directly to carrier velocity at the source-side of a MOSFET channel. From the 1999 ITRS, which presents estimated targets for many aspects of device fabrication that will be required to continue the trend of exponential performance increase, target carrier velocities can be derived. Figure 1.1 represents effective carrier velocity veff for an "on" device (Vgs = Vds = Vdd), as required for NMOS, derived from roadmap targets for Tox and Vdd via the fol- lowing relationship, as in [5]: veff = =on Ion (1.1) i Cox(Vdd - Vt) Where Qj is inversion layer charge, C'ox is the normalized gate-oxide capacitance, Vdd is power-supply voltage, and Vt threshold voltage. Relevant roadmap parameters are listed in Table 1.1. The roadmap gives a range of values for Tox and Vdd for each generation; the thicker values were chosen for Tox for this this comparison. For Vdd low values, corresponding to low-power, were chosen. Effect of unscaled threshold voltage, unscaledgate oxide thickness The 1999 ITRS roadmap does not list Vt per generation, instead giving Vt = 0.4 V (for long-channel devices) as a guideline. This is a reflection of the fact that without innova- tive techniques to manage static power dissipation, Vt cannot be scaled concomitantly with Vdd while simultaneously maintaining acceptable Ioff. As is evident in Figure 1.1, unscaled Vt places high demands upon carrier velocity for the shorter roadmap generations. 22 0 Vt, Tox scaled U Unscaled Vt A Unscaled To 0 0 Unscaled Vt, Tox 1-2 E 10 4- - _6 6 0 01 100 70 180 130 ITRS Node (nm) Figure 1. 1: Effective electron velocity veff required to meet 1999 ITRS Roadmap targets (NMOS). Unscaled T0 x: > 1.5 nm. Unscaled Vt: 0.25 V. Vt values used (Table 1.1) correspond to short-channel devices in each technology, so are well below roadmap guideline of 0.4 V. TABLE 1.1 1999 ITRS ROADMAP PARAMETERS YEAR 1999 2002 2005 2008 NODE (nm) 180 130 100 70 NMOS Ion (pA/pm) 750 750 750 750 Lgate (nm) 140 85 65 45 Vdd (V) 1.5 1.2 0.9 0.6 Toxelectrical (nm) 2.5 1.9 1.5 1.2 Vt (V) 0.25 0.25 0.2 0.2 In addition, the SiO 2 gate insulator can be scaled only so far before leakage current due to tunneling becomes unmanageable. Predicted limits range from 2 nm (for equivalent electrical thickness in inversion Toelec, which includes gate-poly depletion and non-zero inversion layer depth) to 1 nm (physical thickness) [6][7][8]. If an acceptable high-k gate dielectric process cannot be developed, the most aggressive roadmap targets for To, elec 23 may not be practical. For Figure 1.1, to demonstrate the additional demands that unscaled T0 Xelec will place upon carrier velocity, a limiting minimum thickness of 1.5 nm was chosen. Alternately, achieving high carrier velocity in deeply scaled MOSFETs can relax other challenging roadmap targets. Velocity and Scaling in MOSFETs: Device Physics Perspective To understand what may happen to carrier velocity with continued device scaling, we must consider two perspectives on limits to carrier velocity: The "tyranny of universal mobility" Figure 1.2 illustrates MOSFET fields and potentials. Vdd is not expected to scale proportionally to channel length, so that lateral electric field IEx| will increase for shorter devices: this would tend to improve veff with scaling. However, for electrostatic integrity the gate bias must have much more control over the potential at the source-side of the channel than drain bias; otherwise the device cannot be turned off fully via zero gate bias. This requires JEyJ >> ExJ near the source for a device in saturation (gate and drain bias high), where EY is transverse electric field. High Ey leads to degraded carrier mobility: it is well known that MOSFET effective mobility peff has a universal relationship with Ey, decreasing as EY increases [9]. Because of this "tyranny of universal mobility" (geff degraded by scaling) in bulk MOSFETs it is not clear whether further scaling will improve, or degrade, veff. This is difficult to predict theoretically, since traditional device analysis based on the Drift-diffusion (DD) or energy balance (EB) approaches may not be physically justifiable in this "end of roadmap" regime, primarily because EX and potential can change significantly over one carrier scattering length [10]. The ballistic or "thermal limit" It has been suggested that advanced MOSFET devices may in fact be approaching the fundamental limit of ballistic transport [11][12] (zero scattering events for electrons), where veff reaches its maximum possible value, determined by the thermal velocity of carriers 24 Vgs V Vds -Ex EX V S, ~0S Vd X SLCH Figure 1.2: Potential profile and electric fields in a bulk NMOSFET channel, for Vgs = Vds = Vdd. For acceptably low DIBL (Drain Induced Barrier Lowering) IEy must be significantly greater than IEJI. entering the channel from the source [14]. In this case DD and EB approaches are clearly inappropriate. Goals of This Work The two primary goals of this work are: (1) To further the experimental understanding of the behavior of veff and peff in deeplyscaled bulk MOSFET channels. To this end, we investigate NMOS devices from two advanced deep-sub-100-nm CMOS technologies. (2) To examine both design-space and fabrication technology for alternative MOSFET architectures that have the potential for scaling without high transverse electric fields: single and double-gate Fully Depleted Silicon-on-Insulator (FDSOI) MOSFETs (Figure 1.3) may allow scaling without a mobility penalty. 25 Double Gate Single Gate LG I I Top Gate Si02 LG I II T4= Si Channel Si02 Bottom Gate Figure 1.3: FDSOI MOSFET Architectures 1.2 Outline In Chapter 2, we investigate experimentally (and with the aid of 2D simulation) electron velocity in advanced NMOSFETs to see how near they operate to the thermal limit. In Chapter 3, we investigate via 2D simulation the relationship between scaling and lowfield mobility for bulk NMOSFETs as well as for FDSOI alternatives. In Chapter 4, we explore experimentally the effect of scaling on mobility in bulk NMOSFETs, to see if the universal relationship of 9ef with EY holds in heavily doped deep-sub100-nm channels. In Chapter 5, we explore experimentally the relation of low-field mobility to the carrier velocity of NMOSFETs in saturation: mobility change is induced via mechanical strain, and the corresponding mobility and velocity shifts are correlated. In Chapter 6, we explore via 2D simulation the design-space for single- and double-gate FDSOI MOSFETs, focusing primarily on scalability and transport. 26 In Chapter 7, we investigate two novel fabrication technologies which may make deeplyscaled FDSOI MOSFETs feasible: gate alignment via Interferometric Broad-Band Imaging (IBBI) and selective epitaxial raised source and drains. Chapter 8 summarizes results and suggests future work. 27 Chapter 2 Experimental Determination of Carrier Velocity in Deeply Scaled NMOS 2.1 Introduction Continued success in scaling bulk MOSFETs has brought increasing focus on fundamental performance limits. It has been proposed that drain current is ultimately limited by the rate at which carriers can be thermally injected from the source into the channel [12]. In this chapter we show that commonly used techniques for experimentally determining carrier velocity are insufficient to determine how close modem MOSFETs operate to the ballistic or "thermal limit". We propose a new technique, and apply it to two advanced industry technologies with deep-sub-100-nm channel lengths. We show that an advanced 1V NMOS technology with Leff < 50 nm operates at no more than -40% of the limiting thermal velocity. Furthermore, we find no indication that continued scaling is bringing us closer to the thermal velocity limit. 28 2.2 The Thermal Injection Limit It has been shown that electrons in a MOSFET channel can exceed significantly the saturation velocity for isotropic field regions vsat (~1x10 7 cm/s) [15][17]. The ultimate limit to performance is, rather, thought to be the thermal injection velocity vo (1.2-2x,0 7 cm/s) from the source accumulation layer into the channel [14][18]. Applying the formalism of 1-flux scattering theory [14] this can be stated as: Ion / W = vo Qi(xo) T/(2-T) (2.1) where Ion is the saturated drain current and Qi(xo) is the areal inversion layer density at the conduction-band peak (with Vgs=Vds=Vdd) at the source-side of the channel. The effec- tive carrier velocity at xO is: veff = v 0 T/(2-T) (2.2) T is the transmission coefficient at x0 . T=1 (and veff = v0 ) represents the thermal limit: transport is fully ballistic, and there is no backscattering of carriers to the source. This viewpoint is illustrated in Figure 2.1. As a measure of how close to the thermal limit a device operates, it is conceptually useful to define a thermal or ballistic efficiency $ veff/vo = T/(2-T) 1: (2.3) To estimate T and $, veff must be determined experimentally (vo can be estimated theoretically [18]). The point xo, where Eqs. (2.1-2.3) are evaluated, is identified with the conduction-band peak (where transport is purely diffusive) because v0 is the limit of diffusive velocity only: moving toward the drain carriers are accelerated (to well beyond v0 eventually) as Q1 decreases, regardless of P. This is illustrated schematically in Figure 2.2. Monte-Carlo simulation results emphasize this point, showing that carrier velocity increases dramatically along the MOSFET channel (Figure 2.3). This demonstrates the necessity of determining veff as close to x. as possible, if the goal is to assess how near to the thermal limit a modern MOSFET operates. The answer to this question has important ramifications: large $ for a modern "standard" MOSFET would suggest only minor drivecurrent benefit could be expected from continued scaling, or from technology alternatives for mobility improvement (e.g. strained-Si or undoped thin-film SOI). 29 EC I I I 0 0 LCH -- , -- X Figure 2.1: Carrier velocity considered at source-to-channel barrier. Unless transport is ballistic, average carrier velocity (veff) at the source-to-channel barrier must be less than the thermal injection velocity v0 For deep-sub-100nm devices conduction-band peak is typically within several nm of source-channel transition (x=O, defined as the point where source doping falls to 2x10 19 cm- 3 [19]). Note that simulations for bulk MOSFETs indicate a conduction-band peak much less pronounced than shown in this schematic. Vs VD VG -1 1 Q! C) IdIW = QiVe 0 LCH = constant in x x Figure 2.2: Illustration of relationship between carrier velocity and inversion-charge density along MOSFET channel. Since there is no single ve for the channel, different extraction techniques for ve can give significantly different answers. 30 Leff 3 E 00 2 0 , 0 5 10 15 20 25 Channel Position (nm) Figure 2.3: Monte-Carlo simulation results: electron velocity as a function of position in an ultra-scaled bulk NMOS channel. Toxphys=1.5 nm. Vgs=Vds ~ 1V. Courtesy of D. Frank (IBM). 2.3 Investigation of Velocity Measurement Techniques by Simulation We explore the physical significance of several experimental carrier velocity extraction approaches via 2-dimensional drift-diffusion (DD) and energy balance (EB) simulations (Appendix 1). The goal is to find a technique which measures velocity near the conduction-band peak. We use a "super-halo" MOSFET structure (Figure 2.4) with effective channel length (Left) of 50 nm, where Left is defined as in [19], by the points at which the source/drain doping fall to 2x10 19 cm- 3 . Note that the metallurgical junction distance is much less in this case, 36 nm. The highly non-uniform doping profile is used in advanced bulk MOSFETs to provide some degree of immunity to short channel effects, reducing short-channel threshold voltage rolloff [20]. The structure was designed to match closely 31 measured characteristics (Vt, T0 X, DIBL, Leff, gm) of the experimental technologies investigated below (technology A, Section 2.4). Gate elec TT0oxe 2.4 Leff =50 nm Source -E0 Drain n-type - 3x1O1 9 1x10 19 p-type y 1x10 18 Figure 2.4: NMOSFET simulation structure (Avant! MEDICI TM [13]). Mobility models used in this chapter: (a) for low Ex, concentration-dependent g; (b) for EY, Si-SiO 2 universal p assumed, with coefficients from [13]; (c) for high Ex, either a Caughey-Thomas relationship [64] for DD simulations, or an electron-temperature dependent model as described in Appendix 1 for EB simulations. For DD simulations, electron saturation velocity vyt = 1.3x 107 cm/s. For EB simulations, energy relaxation time TW = 0.1 ps, and vsat=lxlO cm/s. . From simulation, Toxelec was assessed from the slope of the dQi/dVgs curve for mid-channel for a long-channel device at Vds=O; slope was taken at Vgs=VddClassical distribution was assumed for inversion layer electrons for all simulations. Leff is determined by the 2x10 19 cm-3 S/D doping points. Fermi-Dirac statistics. External lumped resistance of 90 ipm per side, to give total Rsd = 220 Qgm. Carrier Velocity from Saturated Transconductance Effective carrier velocity can be measured from extrinsic or intrinsic saturated transconductance gm and gmi [15]: vgm = gm / WC'0 X (2.4) vgmi = gnm / WC',x (2.5) 32 C'10 is the gate oxide capacitance per unit area in inversion. gmi is saturated transconductance corrected for source/drain parasitic resistance (Rsd) as in [16]. As carrier velocity is inherently an intrinsic quantity, vgmi should be a more accurate reflection. Nonetheless vgm is a useful estimate when Rsd is not known. According to [21] vgmi is related to carrier velocity ve at the point in the channel where ave/aVgs= 0; EB simulations show that this occurs 10-30 nm beyond the source for a 100 nm device. Repeating the simulations in [21] for deep-sub-100-nm devices, we find that this distance (relative to channel length) becomes more significant, occurring at a point almost 45% across the channel. This is shown in Figure 2.5. Note also that aQ/ aVgs at this point so far into the channel can not be approximated by C'x. Thus, as devices are more deeply scaled, vgm and vgmi become less appropriate as a measure of velocity at the conductionband peak (x = xO). Simulated results of this approach are compared with other approaches, below. e o Sgs 0 10 30 20 40 50 Channel Position (nm) Figure 2.5: EB simulation results for the device of Figure 2.4. Investigating components ). of transconductance as a function of position in channel. (Avant! MEDICI 33 Carrier Velocity from Drain Current and Long-Device CV Conceptually, a more straightforward way to extract veff is to directly measure Io. WQi(xo). Determining Qi(xo) in deeply scaled devices is problematic due to uncertainties in channel length, large (relative) overlap and fringing capacitances, and non-uniform charge distribution along the channel. However, in strong inversion and in the gradual channel approximation (IEy >> JExJ, which is true for electrostatically-sound bulk MOSFETs), Qi(xo) in a short channel should correspond closely to the long-channel inversion layer charge Qo=fOCgsd Vds=O, where C'gsd is the gate-to-source/drain (tied) capacitance, normalized to unit area. This assumption is examined further in Section 2.5. Accordingly we let: Qi(xo)(short-chan.) = fVgs*Cgsd Vds=O (long-chan.) (2.6) where Vgs* = Vgs + AVgs with AVgs accounting for differences between long and short devices. The most important component in AVgs is AVt due to DIBL and thresholdvoltage rolloff. Adjustment due to AVt is illustrated in Figure 2.6. The expression for effective velocity as extracted from Ion becomes: vid = Ion / WQi(xo)(short-chan.) =Ion / (WfOtygs+A> C'gsd (long-chan.)) (2.7) A second component in AVgs is due to voltage drop on the source resistance, IonRsAdding this correction to the upper integration limit in Eqn. (2.7) gives the expression used for "intrinsic" effective velocity, vidi: vidi = Ion / /(W (W C1 Vgs + AVt-IRs) C gsd (long-chan.)) js+ (2.8) The extraction techniques for vid and vidi were developed for this work. Simulated results of this approach are compared with other approaches, below. Carrier Velocity from Drain Current and Short-Device CV In [22] a carrier velocity extraction technique is presented, which we denote vid2: Vid2 I vgs C'gs (vds=vdd)) C'gs is the capacitance (per unit area) measured from the short device. 34 (2.9) The method W=L=10gm Vds = 0 AVt gs 1.5 - S 1.0 QiO AQi 0.5 0 0.5 0 1.0 Gate Voltage (V) Figure 2.6: Example of Qi(xo) determination. Capacitance is measured on large device. For large device, overlap C is inconsequential, so area under curve corresponds to inversion layer charge. Integration limit is adjusted by AVt (= DIBL + Vt-rolloff - IonRs) as determined from the target short device. Qi(xo) = (Qio+AQi) / (W*L). NMOS. requires no Rsd correction, as the Qi obtained from integrating C'gs in saturation is intrinsic. In addition, no correction is required for short-channel effects (as with vid and vidi) since IV and CV are measured in the same device. From a practical standpoint, this technique is difficult to apply accurately because knowledge of Left is required to normalize Cgs to unit area. In addition, for a short device fringing capacitances are a much larger relative contribution to Cg, requiring more correction. From a device theory standpoint, since Cgs is measured in saturation, integrating gives a value of Qi which is an average along the channel Since this is much less than Qi at xO (the (Figure 2.7). conduction-band peak), vid2 will be much higher than veff at xO. Simulation Results: Comparison of Techniques Simulation allows investigation of quantities unobtainable by experimental methods, such as potential, and carrier velocity and density, as functions of position along the channel. 35 - I 2 E 0 Vd,=lV V ,=OV CO. Vds=Vgs=lV 1 / x Qlong-channel 1r I(Vds=O) 0 10 50 40 30 20 Channel Position (nm) Figure 2.7: EB simulation for the device of Figure 2.4: area between curves gives Qcgs, which corresponds to Qj as determined in Eqn. (2.9). Name Ref. Measurement Vgm gm / WC'%x [15] Vgmi gmi / WC'ex [15] Vid2 Ion / W vS C vt [22] VdsVdd U d~d Vid Ion/ WJ(Vgs+ Avt)ctgsd f0 Vidi Ion/ W(Vgs + AVt - Ion Rs) Eqn. (2.7) I Eqn. (2.8) 0 TABLE 2.1: Summary of the carrier velocity techniques investigated. 36 Using our 50 nm super-halo simulation structure, velocity values corresponding to five extraction methods (summarized in Table 2.1) are extracted from the simulated output characteristics (DD example is shown in Figure 2.8). For vgm and vgmi, C'0 x was determined from the slope of the dQi/dVgs curve, taken at mid-channel for a long-channel device at Vds=O, Vgs=Vdd. These values are plotted on the simulated carrier velocity profile along the channel, as shown in Figure 2.9. Note that results are relatively insensitive to model chosen: DD model produces very similar velocity profile for first 15 nm of chanSaturated extrinsic transconductance gm for both models are matched nel as EB model. approximately to an experimental device from technology A (described in Section 2.4) with approximately equal DIBL. For DD model this matching is achieved through adjusting electron saturation velocity vsat; calibration of EB model is through adjusting energy For both DD and EB models "universal curve" mobility is used (see relaxation time tc. Section 3.1). The simulated conduction-band depicted is a cut at 0.4 nm below the SiSi0 2 interface, which is the depth of the inversion-layer centroid at the source end of the channel. 0.8 o 0 o Tech. A, measured DD simulation 0.6 E -E * S0. * 0.2 0 e 0 0.2 0.4 0.6 0.8 1.0 Vds (V) Figure 2.8: DD simulation results (solid): output characteristics for the device of Figure 2.4, matching saturated gm and Ion of experimental technology A (discussed in Section 2.4). 37 Ec-peak (x=xo) (a) Vds=Vgs=1V 0 3 .Vid -0.2 AVidi 2 -0.4 SVid2 1 -0.6 0 0 10 20 30 40 5( Channel Position (nm) (b) Ec-peak I Vds=Vgs=lV I 0 3 -Vid -0.2 AVidi 0 vgm N- - -0.4 2 -.1i 0 Vg~. -id 1 -0.6 0 10 20 30 40 Jo 50 Channel Position (nm) Figure 2.9: Simulation results: conduction-band and carrier velocity vs. position for bulk superhalo device of Figure 2.4. Velocities at five marked points along the channel correspond to values given by different MOSFET carrier velocity extraction techniques (Table 2.1). Solid symbols are corrected for S/D series resistance, open symbols are uncorrected. Vth, TOXelec, Rsd, and Ion approximately match the "Technology A" under investigation. DIBL here is 66 mV/V. (a) DD model: vsat= 1.3x10 7 cm/s (b) EB model:T,=0.1 ps. 38 These results show clearly that the extraction methods developed for this work (vid, vidi) correspond to inversion-layer velocities closer to xo than the methods from the literature (Vgm, vgmi, vid2). Using any of the latter methods will significantly overestimate ballistic efficiency 1. However, vid and vidi also correspond to points in the channel somewhat beyond xo. We must interpret, then, the subsequent experimental results (based on vigd) as putting a reasonable upper bound on veff, and therefore 1, for the technologies investi- gated. Carrier velocity ve(x) was extracted from simulation by taking Ion / WQi(x). In the case of EB simulations, this leads to some overestimation at the drain end, where the inversion layer is found to "spread out" deep below the surface. Since the integration depth was fixed (at 5 nm) for the purpose of extracting Qi(x) from the simulation, the deep tail of the charge distribution was missed at the drain end. Velocity extraction near the scaling limit Extending this investigation closer to the projected limit of MOSFET scaling requires Monte-Carlo simulation. Figure 2.10 shows results for the simulated 25 nm super-halo device presented in [2]. S/D series resistance of the simulated device is not known accu- rately; with the available data only an approximate comparison of vid vs. vgm is possible. For vid in this figure, Qi(xo) was estimated from C'0 x(Vgs-Vt) since CV data was not available. Furthermore, in this case gm is not a differential quantity but a difference: gm = AIon / AVgs for one Vgs step. The results support our contention that vic is more suited than vgm for measuring velocity near xo. 2.4 Experimental Results Technology Parameters We measure vid and vidi (and compare with transconductance methods) for NMOS devices from two advanced CMOS technologies, referred to in this work as technologies 39 1.0 VgS=1.1I V- . 0.9 V S0.5 0.7 V- 0.5 V 0 0.4 0.8 1. Vds (V) Leff 0 3 -0.4 < CD g -i 2 (D WI 04 x 0 -0.8 1 C 3 C,, -1.2 0 0 5 10 15 20 25 Channel Position (nm) Figure 2.10: Monte-Carlo results: output characteristics and electron inversion-layer velocity, for a 25 nm Leff NMOSFET design presented in [2]. Courtesy of D. Frank (IBM). Inversion-layer distribution is classical. Our estimates of vid and vgm shown are approximate values. 40 "A" and "B" (Table 2.2)*. Figure 2.11 gives example output characteristics. Figure 2.12 gives Vt for the shorter devices of technology A. Corresponding information for technology B is available in [24]. In Chapters 3 and 5 the more scaled technology A will be examined in greater detail. Toxelec was determined experimentally from Fox / C'gsd (with Vgs=Vdd) measured in a large (L/W = 10/10 pm) device. Regarding the range of source- drain parasitic series resistance (Rsd) presented in Table 2.2: for both technologies, the low estimate is determined from inverse modeling [25][53]. However, at the time of the investigation summarized in this chapter, only data from the shift and ratio technique [23] for was available for technology B. This higher estimate (270 i- m) was used for the subsequent analysis. The inverse-modeled result for "A" (190 i- tm) was considered to be preliminary, and somewhat low compared to the best reported results in the literature. For this reason a more conservative estimate of 220 0-pm was used here. The use of these estimates, that are likely high (by 30 9-gm for both technologies), introduces negligible error for the relative comparisons between measured velocity for "A" vs. "B" to be shown below. For absolute values of vidi for comparing to the thermal limit, the final values (Table 2.3) presented are small overestimates (1.0-1.5%). TABLE 2.2 PARAMETERS FOR NMOS TECHNOLOGIES INVESTIGATED *INDICATES RSD VALUE USED IN THIS CHAPTER tINDICATES VALUE USED IN SUBSEQUENT CHAPTERS Technology T elec Vt (Vds= Nominal 50mV linear extracted, long chan) Vdd Rsd Leff for DIBL < 130 mVN A 2.4 nm 0.3 V 1.0 V 1 9 0 t- 2 2 0 * -40 nm B 4.3 nm 0.35 V 1.8 V 2 40t-2 7 0 * -65 nm 92-gr * These devices were obtained courtesy of industrial partners. 41 Technology A Technology B I 1.2 I Vgs = 1.5 V 00000000C 0000 000000 E 0.8 Vgs = 1.8 V 000000000000000000 - 00 00*00000*00000 000000* 0000 E 0 00 4-0 C CD 0000000000000000000000 0.4 . 00000000000000000000 oO ,%0*** 0 00**0 0 00 00000000*** 00 C 0 00 0 00 0 0 0 0.5 V-^- ^^ ^^0~ 0 00000000000000000OOOOC 0 0.6 V 0---------0 000000000o00000000000000 *00000 C: 00 0 0 0 0.5 1.0 1.5/0 0.5 1.0 1.5 Drain Voltage (V) Figure 2.11: Example output characteristics for NMOS devices from two technologies under investigation. DIBL is similar for both devices shown, 60-70 mV/V. 40C I E 0 _0 .c 300 - 300 200- 200u 10 F- 100 ~~_~ ----- OF H/ -100OF -200 Leff = 3 5 nm - -- 0 3 - 0 A Vds = 50 mV Lin. Ext. 0 Vds = 50 mV, Icc = 1e-7W/L A LVs = 1V mV, Icc = 1e-7W/L A 100 500 Log Effective Channel Length (nm) Figure 2.12: Measured Vt and DIBL for technology A. Results shown are for same set of devices used for inverse-modeling determination of Rsd and Leff. Leff corresponds to the points where S/D doping falls to 2x10 19 cm-3 [19]. DIBL is via Eqn. (2.10). 42 Measurements To determine experimentally Qi(xo) we integrate C'gsd obtained from a large (10x device, and make adjustments according to Eqn. (2.6). im) An example measured CV for technology A is shown in Figure 2.6. For AVt determination, rolloff was defined as the difference between linearly extracted threshold voltages (50 mV Vds): compared for the long (L=10 pim) device versus each short device characterized. DIBL was defined as: AVt V t(Vd AVS = Vdd) - t(VdS, = 0.2) (2.10) (Vdd - 0.2) where Vt is determined for a constant current of le-7(W/L) A. C'ox for vgm and vgmi was determined experimentally from Eox/C'gsd (Vgs=Vdd)- The dependence of Rsd on gate bias is not taken into account; modest inaccuracies in Rsd do not significantly affect the results. Experimental results for technology A (Figure 2.13) corroborate the simulation results, showing relative differences between vid, vidi, vgm, and vgmi of the same order as shown in Figure 2.9. It is important to compare velocities of different technologies at equal DIBL (regardless of measurement technique), because for a given technology carrier velocity increases as electrostatic integrity decreases [26]. Similar results were found for the longer-channel technology B but with moderately less spread among the values (Figure 2.14). That this difference is most pronounced at shorter channel lengths (either within one technology, or moving from "B" to "A") suggests that with deeper scaling, effective velocity extraction via an Ion / WQi(xo) method such as Vid or Vidi is increasingly necessary How Close? The thermal injection velocity is a function of channel doping and inversion layer density [18], increasing with both. Our estimates for vo are taken from [18]. A more detailed treatment would take into account the non-uniform doping profile and 2D effects at xo, as well as the non-parabolicity of the bands. However, the approximate values used are sufficient in the context of setting a reasonable upper-bound estimate on P. 43 Using Technology A 1.0 . .gm E OVgm A vidi 0 8 Q0.6 .P 0 C 00 A AA A,- ,& - - - - - - - - - A AAIL 2 jU Veff 00 0.4 Vgs=Vds=1 V 0 100 50 150 Drain Induced Barrier Lowering (mVN) Figure 2.13: Experimental results: carrier velocity by four techniques vs. DIBL, for technology A. Solid symbols are corrected for S/D series resistance, open symbols are uncorrected. The implicit variable in the x-axis is gate length. vo=1.7x10 7 cm/s for technology A, and taking veff = vidi from Figure 2.13, we find that for maximum acceptable DIBL (100 mV/V) $ = veff/vo = 0.39 corresponding to an upper bound on T of 0.56. Table 2.3 summarizes experimental results for technologies A and B, as well as for 25 nm (Leff) Monte Carlo simulation results from [2]. Although caution must be taken drawing general conclusions from comparisons of different technologies (and Monte-Carlo simulations as well) the results suggest that 1 is not increasing as we scale to shorter generations. The significant (15%) decrease in veff from "B" to "A" may result partly from lower mobility, due both to heavier channel doping and thinner gate oxides. In [27] a mobility difference of -15% was shown between 3.2- and 1.5-nm physical T0 X: thicknesses very close to our estimates for "B" and "A" respectively. In addition, for this work devices are tested at the technology's nominal Vdd; this means that Vds / Leff (at DIBL=100 mV/V) is moderately higher for "B". For a more "fair" 44 Technology B 1.0 - Vgmi O Vgm E AVidi 0 AVid - 0.8 0 4tt 0 W C A AA 0 X 0 0.6 QA A 0 A A A A > QD 0 0.4Vgs=VdSl .8V 100 50 150 Drain Induced Barrier Lowering (mVN) Figure 2.14: Experimental results: carrier velocity by four techniques, for technology B. Solid symbols are corrected for S/D series resistance, open symbols are uncorrected. comparison we compare also for constant overdrive (for technology A: Vdd [=Vgs=Vds] =1V; for B: Vdd=1. 6 5 V), which determines the transverse field. Comparison at constant DIBL (100 mV/V) determines the lateral field. For these conditions we find the decrease from "B" to "A" is essentially the same: 14%. Current drive corresponds directly to carrier velocity; with continued scaling (to 25 nm) NMOS current drive does not appear to be significantly above 40% of the thermally limited value. These results for technology B (P = 0.47) are consistent with results reported for an Lgate = 130 nm technology in [29], where f was estimated at 0.45 by comparing Ion (measured) with Ion (ballistic-limit from simulation). However, the authors of [29] have reported P as high as 0.55 for devices of similar dimensions at DIBL ~ 100 mV/V [30]. Results in [29] were not given for a specified DIBL. 45 25 nm M.C. Tech. A Tech. B Veff (cm/s) 6.7-7.6x10 6 6.6x10 6 7.7x10 6 0 0.35-0.40 0.39 0.47 T 0.52-0.57 0.56 0.64 -o*-- Decreasing Leff, Tox Increasing v0 TABLE 2.3: Comparison of carrier velocity, ballistic efficiency, and transmission coefficients. Experimental results for technologies A and B, plus Monte-Carlo results for 25 nm from [2]. @= veff/vo = T/(2-T). vo values estimated from [18] as 1.6, 1.7, and 1.9x10 7 cm/s, respectively, moving from right to left in the table. veff = vidi at DIBL = 100 mV/V. For Monte-Carlo device, Qi(xo) was estimated from (sex / Toxelec)(Vgs-Vt). As this method of charge determination was different from the capacitive techniques used for technologies A and B, some uncertainty was introduced in the comparison, reflected in that range of values for MC results. Dependence of veff on Vdd In order to separate effects of Leff scaling from the corresponding changes in lateral electric field, the above experiments were repeated for different Vdd (=Vgs = Vds). Figure 2.15 summarizes the results. It is significant to note that, beyond the lowest Vdd node, for each technology there is relatively little increase in carrier velocity with increasing drain bias. One possible explanation is the "tyranny of universal mobility" touched on in Chapter 1. From the standpoint of carrier velocity, there are competing trends corresponding to increasing Vdd: decreasing mobility (because of increasing transverse field EY due to increasing Vgs) versus increasing lateral field EX. Another explanation is offered by the scattering theory approach to estimating MOSFET drain current [14]. As noted in Section 2.2, scattering theory relates Ion to vo by Eqs. (2.1-2.3): Ion = W v0 Qi(xo) @ (2.11) Scattering theory makes the further assumption that for modem short devices at high drain bias, to first order 1 is determined only by the backscattering of carriers within a distance 46 ( of the source, determined by Ec(C) - Ec(peak) = -KT. In this view, for a MOSFET in strong inversion and with high drain bias, ( and hence I0. is only weakly dependent upon lateral field and drain bias [28]. E 1.0 NMOS - Technology B C 0.8 r- 0 0) 0.6 Technology A 0 0.4 III 0.5 1.0 1.5 2.0 Vdd = Vgs = Vds(V) Figure 2.15: Experimental results: effective electron velocity measured from vidi. DIBL=100 mV/V in all cases. For technologies A and B, as a function of Vdd. Although it would seem of interest to try to separate the Ex and EY dependencies of veff by examining veff as a function of Vds at fixed Vgs, this approach would be limited by the fact that lateral field should not increase significantly for Vds > Vgs -Vt. 2.5 Further Investigation of the Inversion-Charge Relationship Between Long and Short Devices Through simulation we further explore the physical significance of our value of Qj(x 0 ), the estimated inversion-layer charge at the conduction-band peak for a short device. In our velocity extraction methods we compensate for short-channel effects and series resistance; nevertheless it may not be appropriate to use long-channel low-Vds CV to estimate 47 short-channel high-Vds Qi, for two reasons. First, 2D effects significantly modify the electric field configuration. Second, 2D doping profiles can be significantly different due to the use of halo doping. If this is not physically justifiable, the importance of our methods of velocity extraction (vid, vidi) rests only on the fact that they give estimates of velocity closer to the conduction-band peak than other methods. First we look at long- vs. short- channel capacitance, in Figure 2.16. We compare (a) simulated long-channel capacitance (C'long-inv = dQi/dVgs at mid-channel of a long device with zero Vds) with (b) simulated short-channel incremental capacitance C'short-inv(x) = dQi(x) /dVgs (at the operating bias point, i.e. with Ion current flowing). For the short device, the structure of Figure 2.4 is used; the long device has super-halo doping identical to that of the short device near the source and drain, but with the channel more lightly doped far from the source and drain. We see that even at x=0, C'short-inv (dashed line) does not match the long-channel value. However, given the basic relation for inversionlayer charge in a MOSFET: Q (x) = C'ox[Vgs -Vt - (Ds(x)] (2.12) (where Os is surface potential) the incremental capacitance along the channel will be dQi(x) = O dVgs ds(x) (2.13) dVgs At the source end of the channel, dcDs/dVgs depends upon the potential drop across the source resistance. This suggests that nonzero source resistance may be why C'short-inv(x=o) < C'i ong-in,. Re-doing the simulation with no lumped resistors to account for extended source/drain regions reduces the total simulated Rsd down to about 40 igm, and we get the solid line in Figure 2.16. As would be expected in the gradual channel approximation, the gate capacitance at the source end of a short device approaches the long-channel gate capacitance value. This suggests that there is in fact a physical basis for our estimation of Qi(xo) for the short device from capacitance measurements of the long device. Nonetheless, when in simulation we determine Qi(xo) according to Eqn. (2.6) we do not in fact get a value that corresponds to x=x0 (the simulated conduction-band peak). This is 48 X0 midchannel C'long-inv C\1 El IL dQi = C'rt-n dVgs (short channel Rsd = 220 Qiprm) .0--..i dVgS (short channel Rsd = 40 2tm) 0 20 10 0 Channel Position (nm) Figure 2.16: EB simulation result for the device of Figure 2.4: Incremental gate capacitance vs. channel position, with Vgs = Vds = 1V. Compared with and without lumped external resistance, to long channel value C'iong-inv (Vds = 0). xo, indicated above, is position of Ec-peak from simulation at Vgs=Vds=lV. (Determined from a lateral cut through the device, at approximately the inversion layer depth). seen in Figure 2.17. The dashed line is Qi(xo) derived from simulated CV measurements of a long channel (10 gm) device at zero Vds, then adjusted for short-channel effects and series resistance via Eqn. (2.6). The solid lines are Qi(x) determined, from simulation, as a function of channel position in a short (Leff = 50 nm) device. It is not apparent from this figure that Qi(xo) via Eqn. (2.6) corresponds to any special point near the source. However, the picture is complicated by the "extra" carriers that can be thought of as "spilling over" from the heavily doped source region, present even when Vgs =0. In this case we have: Qi(xo)=fsdQI/dVgs where Qivo is the channel charge at x. when Vgs=O. + Qivo (2.14) Note that xO is defined as the position of the conduction-band peak with Vgs =Vds=Vdd: when Vgs = 0, the conduction-band peak 49 is further into the channel. Thus when the device is off (Vgs = 0) the charge at the conduction-band peak will be less than Qiv,0 . x0| * midchannel 2 Adjustments: VgSlV C~~~j~ __ A Rsource COl 1. C7, Qixo) by Eqn. (2.6) a0 20 10 0 Channel Position (nm) Figure 2.17: EB simulation result for the device of Figure 2.4: Inversion layer charge vs. channel position for first half of channel. Vds=lV. Upper-right insert shows size of corrections made to long-channel Qi to obtain Qj(xO) via Eqn. (2.6). Short-channel correction increases, and Rsource correction decreases, Qj(xO). Relevance to determinationof P The presense of these "extra" carriers, not induced by the gate, make our experimental method of determining Qj(xO) via Eqn. (2.6) an underestimation of the actual inversioncharge at xO. This is the reason that our extracted velocity vid is an over-estimate of velocity at xO, as seen in Figure 2.9. If taken literally, the results of Figure 2.9 and 2.17 suggest the experimental viad could overestimate the true value of velocity at the conduction-band peak by - 70%. This means that the actual ballistic efficiency of technology A may only be approximately 25% versus the experimental value of 39%. However, EB simulations, with classical vertical distribution of inversion charge, are inadequate to accurately make this assessment. To further demonstrate one aspect of the 50 ' 5 nm 2.5 nm Vds=Vgs=1 V Integration Depth w 1-D cut approx. at min. inversion centroid depth (method used in this study) 20 10 0 Channel Position (nm) Illustration of three methods of determining conduction-band potential with Figure 2.18: position: top two are weighted averages of electron potential, to the depth specified. Bottom is simple 1-D cut along the length of the device, at 0.4 nm. DD simulation, for structure of Figure 2.4; only first half of channel is shown. problem: Figure 2.18 demonstrates the uncertainty in determination of xo. Since inversion charge varies strongly with position at the beginning of the channel (according to our simulation results) differences of a few nm in xo will affect critically the actual value of $, since D oc1/ Qi(xo) from Eqs. (2.1-2.3). 2.6 Conclusion We have demonstrated a technique for measuring effective carrier velocity near the source-side of the MOSFET channel, which is more appropriate than existing techniques for the purpose of determining how close modem technologies are to the thermal (ballistic) limit. With this we have shown that a deeply-scaled (Leff < 50 nm) IV NMOS technology operates, at most, at 40% of the limiting thermal velocity. Based on our analysis of two sub-100 nm experimental technologies plus Monte-Carlo simulations near the bulk scaling limit, we conclude that continued bulk NMOS scaling should not bring us closer to the limit of source-to-channel carrier injection. 51 Chapter 3 Mobility and Scaling I: Universal Mobility in Bulk and FDSOI MOSFETs 3.1 Introduction We investigate via simulation the relationship between mobility and scaling for bulk NMOSFETs and FDSOI (Fully-Depleted Silicon-On-Insulator) alternatives, focusing on the 50 and 25 nm Leff generations. Scaling of bulk MOSFETs well below 100 nm Leff requires heavy channel doping, leading to degraded low-field mobility. Provided that the gate workfunction is used to determined the threshold voltage, FDSOI devices do not suffer from this trade-off, by virtue of the fact that their channel can be undoped. We show that single-gate FDSOI is, accordingly, an attractive alternative down to 50 nm Leff. For deeper scaling, double-gate FDSOI should have approximately a 3X mobility advantage over bulk NMOS. Universal Mobility In deriving analytical expressions for MOSFET drain current, it is convenient to define an "effective" mobility as a weighted average through the inversion layer: 52 1- fo i gn(y)dy eff = .(3.1) fo n(y) where yj is inversion-layer thickness and go is low-field mobility: that is, with lateral electric field EX << Esat (electric field for velocity saturation in an isotropic field region). In bulk-Si and SOI MOSFETs egf behaves according to a "universal" relationship depending only on Eeff, the effective or average transverse field seen by carriers in the inversion layer [9][31][37]: - Eeff = (3.2) 0 Eeff (1Qi+ Qb) (33) Esi where po, Eo, v and q are fitting parameters which depend on carrier type. ("Low-field" in this context refers to lateral, not transverse, electric field). 1 = 1/2 for electrons. Qj and Qb are the inversion and channel depletion region charge areal densities, respectively. Figure 3.1 illustrates with experimental results from [37]. Note that Eqn. (3.3) applies to FDSOI only in the case of Vgb = 0. Typically for channel doping heavier than 2-3 x 1018 cm-3 , Qb becomes the dominant contribution to Ecif. Although lateral electric fields in a modem MOSFET are far in excess of Esat, theoretical [32][14] and experimental work [33][34], as well as our own work in Chapter 5, suggests that carrier velocity (and hence drive current) will still depend strongly on gef in the sub100 nm regime. 3.2 Mobility and Scaling in Bulk MOSFETs Bulk MOSFET Scaling To maintain electrostatic integrity while shrinking channel length, depletion depth W must be reduced [35]. We investigate two basic strategies for controlling W in bulk MOSFETs 53 700 -- o-- 600 - s1=53 nm tsi=60 nm E 500 a. nm Stsi90 - 400 300 200 V 100 V,0V ' 0 -0.2 0 0,2 0.4 0.6 0.8 1.2 1 Effective Electric Field (MV/cm) Figure 3.1: Measured NMOS effective mobility for FDSOI and bulk MOSFETs. From [37]. The deviation for Eeff < 0.6 MV/cm is likely due to overestimation of Qj that can occur unless Vgs >> Vds [38] when measuring via the split-CV method [52]. Vds = 50 mV. Modem bulk MOSFETs operate at Eeff > 1 MV/cm. Tstep xi I ON. I PP_ I I Gate:(g - LeI Ge SI Gate:(Dg I 1I. 15 nm (b) Step-doped (a): Uniform-doped Figure 3.2: Simulation structures for NMOS bulk doping alternatives investigated. Junctions are spatially abrupt. For (a) ( = 4.19 V (for n+ Si). For (b) Dg = 4.19 V and (Db = 5.25 V (for p+ Si). For Nb and Tstep values by scaling node, see Figures 3.4 - 3.6. Source and drain are n+. 54 (Figure 3.2) via 2D Drift-diffusion simulations, for four design nodes of decreasing Left. Table 3.1 lists key technology parameters scaled concomitantly with Left; numbers are based approximately on ITRS technology nodes [1], with Vdd chosen for Qi/q = 1x10 13 cm-2 at Vt=0.2 V. It is necessary to estimate from simulation (with classical distribution of electrons in the inversion layer, and no gate depletion) the relation between physical and electrical gate oxide thicknesses Toxphys and Toxelec. T0 elec was taken as the slope of the simulated dQi/dVgs curve, extracted at mid-channel of a long-channel device, at Vds=O and Vgs=Vdd- It is found that across all four scaling nodes, for bulk MOSFETs the correction is in the range of 0.8 - 1.2 nm, consistent with 1-D solutions from [36]. Accordingly, the physical Tox in simulation is 0.1 nm less than the values shown in Table 3.1. When assessing scalability, for all device architectures treated in this study we adopt two criteria, to ensure electrostatic integrity and acceptable loft: (1) DIBL 100 mV/V and (2) Vt (Vds = Vdd) > 0.2 V. In [20] it is suggested that Vt = 0.2 V is the limiting "worst case" value--including worst DIBL and rolloff effects for the shortest device in a technology-for MOSFETs with channel lengths below 100 nm. TABLE 3.1 DESIGN NODE PARAMETERS Approximate ITRS Year Leff (nm) Toxelec (nm) S/D extension Xi (nm) Vdd (V) 2000-1 2002 2005 2008 70 50 35 2.5 1.9 1.5 25 1.2 48 34 26 21 1.35 1.1 0.9 0.75 Uniform channel doping For bulk MOSFETs with uniformly doped channels, depletion depth W is scaled by increasing channel doping Nb. Figure 3.3 shows the effect of varying channel doping on high-Vds Vt for the four scaling nodes of Table 1.1. Interpolating between simulation points to find Nb required for Vt = 0.2V (and doing likewise to find points of DIBL = 100 mV/V) results in Figure 3.4. A sharp increase in Nb is indicated for scaling to 25 nm Left. 55 Note that for the uniform-doped device criterion (2) is more stringent (requiring heavier channel doping) except for the shortest node. 0. 14, 0.3- Lef (nrr 'u 0 50 35 25 0.2 CO, ~0 0.11 0' 18 18.5 19 Log 10 (Nb) cm-3 Figure 3.3: Results for uniform-doped bulk NMOSFET: shown are 2D simulation data points for V vs. Nb, from which Nb values meeting criteria (2) are interpolated. (Avant! MEDICI TNI) Perfect step-doping A hypothetical alternative is the perfect step-doped bulk MOSFET (also known as the ground-plane MOSFET [39]), where Nb = 0 down to depth Tstep, and is arbitrarily high beyond. In this case W is simply Tstep- In practice this could be approximated by epitaxial growth of a lightly doped layer on a heavily doped substrate, or super-steep retrograde doping. Vt is highly sensitive to Tstep, as shown in Figure 3.5. Interpolating values from Figure 3.5 gives the step depth required to meet scaling criterion (2) which for the step doped device is much more stringent than criterion (1), as shown in Figure 3.6. 56 10 Criteria: c.0 C o DIBL = 100 mVN 7.5 e Vt (drain hi) = 0.2 V E 3C? 51 C To 0) 2.51 0 D 0 30 70 60 50 40 Effective Channel Length (nm) Figure 3.4: 2D simulation results for uniform-doped bulk NMOSFET: doping level (Nb) correlated with Leff, across four generations. Requisite doping levels to meet two separate criteria are shown. 0.4 0.3 II 0.2 70 0.1 Leff (nn ): 0 10 35 50 2 ' 20 15 ' 25 ' 30 35 Tstep (nm) Figure 3.5: Results for perfect step-doped bulk NMOSFET: shown are 2D simulation data points for Vt vs. step depth, from which Tstep values meeting criteria (2) are interpolated. (Avant! MIEDICI TM) 57 I 60- I I 1 1 50 60 70 Criteria: 0 DIBL = 100 mVN 50 - * Vt (drain hi) = 0.2 V E 40-- 0- 30CD o 2 0 -............. .4-4 30 40 Effective Channel Length (nm) Figure 3.6: 2D simulation results for perfect step-doped bulk NMOSFET: step depth (Tstep) correlated with Leff, across four generations. Tstep required for meeting two separate criteria are shown. Transverse Field Determination Eqn. (3.3) will overestimate the Qb contribution to of Eeff for short MOSFETs, due to the omission of lateral charge-sharing effect between the channel and source/drain. However, our simulations indicate that the contribution due to Qj does not change appreciably when 2D effects are taken into account. Therefore, for short bulk-Si devices Eeif can be obtained from: Eeff = Esurface - Qi/2Esi (3.4) where Esurface is the simulated maximum transverse field in the channel, at the SiO 2 /Si interface, and Qj is approximated as C'ox(Vdd -Vt), where Vt is the high-Vds value. The high Eeff that results from scaling is shown in Figure 3.7; note the reduction for the stepdope device at equivalent scaling node. For the step-dope device, high Eeif is not due to high Qb but rather to the large built-in potential (CDbi) between the n+ gate and the p+ doping at depth Tstep (NMOS case). Reducing Tstep to meet scalability criteria results in 58 1.8 Bulk, Uniform-Doped 1.6 . -9 * Bulk, Step-Doped 1.4- W (D > E 1.2 1 CZ > 0 .8 -- - - - - - - - - - - - - 0 0.6- - - -- Limit for Ob =0, (Ibi = 0 30 20 40 50 60 70 Effective Channel Length (nm) Figure 3.7: 2D simulation results: maximum effective field Eeif along NMOSFET channel for two bulk doping alternatives, with n+ poly gates, using Eqn. (3.4). Shown vs. scaling across four generations. Devices are in saturation (Vds = Vds = Vdd)- Qi/q = C'ox(Vdd-Vt)/q = 1x10 13 cm- 3 was used for all generations. Also shown is dashed line for Eeif = Qj / 2Esi. This corresponds to zero channel charge and no built-in potential between top and bottom contacts (Qb= 0, Obi = 0), which is the situation for SG- and DGFDSOI devices with mid-gap workfunction gates. increased built-in transverse field. This can be understood qualitatively from the relation for effective transverse field for a long-channel step-doped device: assuming Vgs=O and zero channel depletion charge, EOxT0 x + EsiTsi = Fbi where EOX and Esi are the transverse fields in the oxide and silicon. Since Fsi/EOx ~ 3 and since EOXEOX = EsiEsi at the Si-SiC 2 interface to conserve electric flux density, we have Esi = Dbi / (3TOx + Tsi) = (bi / Teq as the contribution from (bi to the transverse field. Therefore instead of Eqn. (3.3), we have: Eeff = TAQ+ Esi 59 TDbi Teq (3.5) Together these two doping alternatives--uniform and step--correspond to the limits of Eeff for bulk devices of a given generation: for the same Q results for halo and/or retrograde profiles can be expected to fall in-between. Mobility versus Generation Figure 3.8 gives the corresponding universal curve mobilities via Eqn. (3.2): significant mobility degradation occurs near the projected bulk-Si scaling limit (-20 nm [2]). However, using the universal mobility relationship appropriate for the Si0 2 -Si interface to illustrate bulk scaling trends may not be appropriate. Experiments have shown that nitrided gate oxides improve NMOS gerf at high Eeff [40][41]. This results in a significant improvement for deeply scaled bulk NMOSFETs (see Figure 4.7). Conversely, for the high dopings required for extremely scaled bulk MOSFETs, it has been projected that Coulomb scattering may dominate [42]. In Chapter 4 we explore experimental evidence for this. We must conclude that assumptions regarding peff in deep-sub-100-nm bulk MOSFETs are speculative. This is especially true if we assume that to reach roadmap targets for T0 Xelec < 1.5 nm, an alternative high-k gate dielectric material will be required (Section 1.1). Considering the difficulty in demonstrating alternative dielectrics with interface quality on Si comparable to the Si-SiO 2 system, it may well be that assuming nonnitrided Si0 2 -Si universal curve mobility is not, in fact, pessimistic for bulk MOSFETs. In light of these observations we consider this a reasonable choice for demonstrating the relation between mobility and scaling. 3.3 Mobility and Scaling in FDSOI MOSFETs In fully depleted SOI devices (Figure 1.3) short-channel effects are suppressed by limiting silicon and oxide film thicknesses. The deleterious effect of drain bias on source-side channel potential is limited by device geometry, so that the requirement of Ey >>IEx (Section 1.1) is relaxed; FDSOI devices thus do not suffer from the "tyranny of universal mobility." If alternative gate material processes can be developed such that 60 Limit for Qb = 0, (Dbi = 0 300-----------------------------------C,) E O 0 2 200- 100-- 0 Bulk, Uniform-Doped * Bulk, Step-Doped .> W 0 30 40 50 60 70 Effective Channel Length (nm) Calculated universal-curve mobilities for two bulk NMOSFET doping Figure 3.8: alternatives, correlated with scaling. Values are plotted using Eqn. (3.2) with Eeif values from Figure 3.7. For Eqn. (3.2), go = 670 cm 2 /Vs, Eo= 0.67 MV/cm, v = 1.6, all according to [31]. Included is dashed line corresponding to the limit of Qb = 0 and Obi = 0, applicable to SG- and DG- FDSOI devices with mid-gap workfunction gates. gate work-functions alone set an acceptable threshold voltage, Qb can be essentially zero, and Beff and gf are decoupled from device scaling. Figures 3.7 and 3.8 include Eeif and peff corresponding to the limit of Qb=0 and Obi =0, illustrating this potential benefit of FDSOI. However, the simplest FDSOI implementation, Single-Gate with mid-gap gate (SG-mg) may not scale beyond -35 nm (for Tsi > 5 nm) because of fringing fields in the buried oxide (Section 6.2; also [43][39]). Double-Gate MOSFETs, either with symmetrical-workfunction mid-gap gates (DG-(cmg) or with asymmetrical n+/p+ gates (DG-n+p+), do not suffer from this problem [39]; even so it has been suggested that DG MOSFETs may not scale far beyond bulk [2]. Scalability considerations aside, we find that SG and DG MOSFETs still have a significant advantage over bulk, a significantly reduced effective transverse field. For SG-mg, with Qb<<Qi Eqn. (3.3) reduces to Eeff Q/ 2Esi. For DG-Dmg Eiff is further reduced by half, if 61 Qj is = interpreted as the sum of inversion layers at both gate interfaces: Eeff = Qj / 4Esi- This points to an important difference between transport in DG-mg versus DG-n+p+ devices. Since the latter has a single inversion layer (at the n+ interface for NMOS), Eeif will be twice as high when compared with a DG-Img device with the same total Qj, resulting in a much-reduced pgJf. We accordingly find that DG-n+p+ effective mobility is 30-40% reduced versus the DGDmg device, across all four generations investigated. For ultra-thin SOI films, it may be questioned whether the bulk universal mobility applies: mobility may be degraded by the presence of a second scattering interface near the inversion layer. Recent experimental results [44] show that this is a concern when Tsi << 10 nm. For the case of Qi/q= 1x10 13 cm- 3 , degradation for a 9.4 nm film (compared to a control device with 54 nm Tsi) appears to be less than 5%. However, this increases to -10% degradation for Tsi = 5.2 nm. 3.4 Results We illustrate the trends discussed above for the Leff = 50 and 25 nm generations, respectively, in Figure 3.9. In Figure 3.9a, for each of the discussed device architectures a region of operation is plotted against the universal mobility curve, for the Leff = 50 nm node. For determining Eeff, a range of Qj is used: high and low values of Eeff correspond to Vdd chosen for higher-performance vs. low-power operation. For Leff = 50 nm, SG- Dmg is a viable option, offering a 35-50% mobility advantage over bulk designed for the same length, depending on the bulk doping profile, and the operating Qj. The advantage for DG-mg (when operated at the same total inversion-layer density as bulk) is higher, greater than 2X. Moving to the Leff = 25 nm generation (Figure 3.9b) the advantage for DG-mg over bulk increases to 2.6-3.5X, again depending upon both the bulk doping profile and Qj. Recent research has suggested that the mobility advantage of thin FDSOI MOSFETs may be counteracted by a decrease of gate capacitance (-12%, due to looser confinement of 62 (a) 50 nmn Leff (b) 25 nm Leff DG-Img DG-(mg CD cmJ E 0 0 SG-4mg .5 DG-(mg* UD 0 0 0 4- 0 SD DG: SG: SD: UD: 0 UD SD SOl Double Gate SOI Single Gate Bulk Step-Doped Bulk Uniform- 0.5 1.0 1.5 * double Q,5 0 0.5 0 , 1.0 1.5 Effective Transverse Field (MV/cm) Figure 3.9: Universal effective NMOSFET mobility (for low lateral field) from Eqn. (3.2), with regions of operation delineated for four different bulk and FDSOI device architectures. For each device architecture, the range of Eeff corresponds to: 0.8x10 13 < Qi/q < 1.2x10 13 cm- 3 . In the case of DG-Dmg, Qi is the sum of inversion charge in both inversion layers, except for special case noted in (b). For DG-Dmg and SG-Dmg, since Qb = 0 Eqn. (3.3) was used to estimate Eeff, independent of channel length. For bulk architectures, peak Eeff along channel was determined via 2D simulation, as Esurf Qj/2Es. the inversion layer), leading to little net gain in current drive [44]. However, the magnitude of the mobility advantage indicated in our study suggests significant gains in current drive may in fact be possible for FDSOI MOSFETs, particularly as Leff approaches 25 nm. This depends critically upon the relation between low-field mobility pLeff and carrier velocity at high lateral fields, in deep-sub-100-nm MOSFETs. relation is explored in Chapter 5. 63 This 3.5 Conclusion The most significant benefit of SG- and DG-FDSOI over bulk may be the ability to maintain high mobilities with deep scaling. However, to fully realize this benefit it is essential to use gates with near-mid-gap workfunctions. SG-mg, despite a poorer prospective scaling limit compared to bulk, has superior transport properties at the 50 nm Leff generation. Furthermore DG-Dmg has a very significant mobility advantage over bulk near the prospective bulk scaling limit of 20 nm. 64 Chapter 4 Mobility and Scaling II: Channel Length Dependence in Super-Halo NMOS 4.1 Introduction In Chapter 3 we examined via simulation the interrelation between scaling and universal low-field mobility for bulk and FDSOI MOSFETs. Measurements of mobility in deeply scaled MOSFETs are difficult, because of sensitivity of extraction techniques to uncertainty in channel length, inversion-layer charge, and series resistance. In this chapter we study experimentally the relation between channel-length and mobility in NMOS devices in a deep-sub-100-nm CMOS technology. This is made possible by careful determination of key parameters by inverse modeling and other techniques. We find evidence that in the very shortest modem MOSFETs, mobility is less than would be expected from "universal" mobility, and independent of transverse field. This may be indicative of a transition in the dominant scattering mechanism, from surface- to Coulomb- scattering. 65 Scattering Mechanisms in Deeply Scaled Bulk MOSFETs Considering a wide range of temperature and transverse field conditions, the dominant scattering mechanisms for carriers in MOSFET inversion layers are Coulomb, phonon, and surface-roughness scattering [45][46][47]; we can therefore approximate by Matthiesson's rule [48]: 1 p _ 1 + Pcoulomb 1 tphonon 1 + (4.1) 9sr As discussed in Chapter 3, modem MOSFETs operate with effective transverse field Eeff on the order of 1 MV /cm and inversion layer density Ni on the order of 1x1013 cm-2 . In this regime at room temperature the "universal" mobility behavior (Section 3.1) is thought to be surface-roughness dominated [49]. 2.4x10 18 Even for uniform channel dopings as high as cm-3 , gff for long-channel NMOS at high Ni and Eeff appears to be independent of doping, suggesting 9sr «< gcoulomb [49]. From Figure 4.1 we can see why this can be expected to remain true, even for much higher channel dopings. As doping is increased the corresponding Eeff is increased, increasing surface-roughness scattering and decreasing 9sr and g. Making the assumption that pcoulomb = 9bulk (minority carrier value) we find that universal mobility (and thus presumably psr) is less than peoulomb for Ni up to Ix 1019 cm-3 and beyond. For deeply-scaled MOSFETs this may not be the case. The electric-field configuration is dominated by 2D lateral charge-sharing effects: much of the channel depletion charge Qb is imaged in the source and drain depletion regions instead of in the gate. This means that in short channels, for high channel doping density Nb, Eeff is significantly less than for a long device with the same Nb. In this case it may no longer be true that gsr << lcoulombAdvanced modem MOSFETs have highly non-uniform "super-halo" dopings to suppress threshold-voltage rolloff. Doping is highly peaked at the source and drain ends of the channel, so that as channel length decreases Nb increases. In light of the 2D consider- ations mentioned above, it is possible therefore that Coulomb scattering will become dominant in deep-sub-100-nm devices, in which case p would be less than the psr-determined 66 800. Long-channel limit 600Bulk Limited 400- Universal E 0 200 - 1017 1018 1019 Nb (cm-3) Figure 4.1: Universal vs. bulk-limited mobility as a function of channel doping. NMOS Universal mobility is from Eqn (3.2) using coefficients from [31], and is based on Ni = lx1013 cm-3 . Calculation of Eeff is one-dimensional from Eqn. (3.3): lateral charge sharing effects are ignored. Bulk-limited mobility is for electrons in p-region. universal-curve mobility at the corresponding Eeff. Examination of this issue, through measurement of the peff-Leff relationship under different conditions, is the primary goal of this chapter. 4.2 On Experimental Determination of Low-Field Mobility Drain current for a bulk MOSFET can be approximated by [50]: Id = peffC'O [(Vgs - - 2 V t)Vds - Vds (4.2) where Lef is as defined in Eqn. (3.1). Eqn. (4.2) is valid for Vds << (Vsb + (Ds) where Vsb is substrate bias and (s = 2 0F [51]. For Vds << Vgs, this reduces to: 67 Id = peffC'x Using the approximation Qi (4.3) (Vgs-vt)Vds ~ C'ox(Vgs-Vt), which is accurate in strong-inversion, effective mobility can be determined according to: IdLeff (44) V*dsWQi where Qi is the loW-Vds inversion charge areal density, assumed uniform throughout the channel. V*ds (= Vds - Id Rsd) is the effective or intrinsic drain bias, reduced from the applied value because of source/drain parasitic resistance Rsd. For a long-channel device, where uncertainty in Left is negligible and channel series resistance (Rch) is much larger than Rsd, it is straightforward to evaluate Eqn. (4.4). For accurate determination of inversion charge, CV measurements are preferred [52]: Qi= (1/W Leff ) Cs s (4.5) For advanced bulk MOSFETs with highly non-uniform lateral channel doping profiles, accurate determination of Rsd and Leff is difficult [23]. In a short device, because Rsd may be of the same order as Rch, there may be a significant drop of potential across the source and drain resistance, so that V*ds may be much less than the applied value. In addition, as mentioned in Section 2.3, determining Qi in a short device is difficult, primarily because of uncertainty in Left. Without accurate Left and Rsd determination, Eqs. (4.4-4.5) (which together have an Left2 dependency), are essentially useless. For our subsequent investigation in Section 4.4 we rely on novel inverse modeling techniques* [25][53] to determine Leff and Rsd; effects of error in these estimates are carefully considered. In order to reduce the dependency of Eqs. (4.4-4.5) from Leff2 to Left, we use a relation similar to Eqn. (2.6) to determine short-device Qi from long-device CV measurements: Qi (short-chan.)=(1 / W Left JgrS*Cgsd IVds=O (long-chan.) * Inverse modeling results in this and subsequent chapters are from the work of Ihsan Djomehri. 68 (4.6) where Vgs* = Vgs + AVgs with AVgs accounting for differences between long and short devices, and also for the potential drop across the source resistance. AVgs = Vt(long-chan) Vt(short-chan) - IdRs; for this purpose Vt is the linear-extracted value (Vds=50 mV) Furthermore, for Vds << Vgs, Qi is not a strong function of position along the channel, so there is no x dependency in Eqn. (4.6). Leff in Eqn. (4.6) is for the long-channel device, so it does not introduce significant uncertainty. Verification of Equation (4.6)for short channels As discussed in Section 2.5 (there, for the case of high-Vds), it may be asked whether long- and short- device Qi can be so simply related. Eqn. (4.6) assumes the strong 2D field effects in short devices will not modify the inversion-charge density, except through modulation of Vt. Based on our 2D simulation results, for low-Vds this appears to a wellfounded assumption, even for devices that are too short to be electrostatically sound. We compare NMOS devices with uniformly-doped channels, comparing mid-channel Qi vs. Vgs for short (50 nm) vs. long (500 nm) channels at same Tox and junction depth (Figure 4.2). The simulation structure is as shown in Figure 3.2a. Doping is adjusted to approximately match threshold voltages for the 50 and 500 nm device (in effect, this is what halo doping does in real devices: Nb rises with scaling, to maintain approximately constant Vt). The near-identical Vgs vs. Qi characteristics suggests the approach of Eqn. (4.6) is valid. However, in real devices at the shortest channel lengths Vt rolls off and DIBL >> 100 mV/V despite high doping. This is the case in technology A (as shown in Figure 2.12) which will be studied via Eqs. (4.4-4.6) in Section 4.4. To see what to expect for the very shortest experimental devices, in Figure 4.2 a 35 nm device is also simulated: Vt is lower but the slope dQi /dVgs remains the same. Therefore as assumed by Eqn. (4.6) a Vt-shift is the only correction required to make Qi for the 35 nm device correspond to the long-channel value. 69 1012 1 8 -----. E 6Leff = 3 5 nm 0 -- Short Channels Long Channel 44Leff= 5 0nm 2 0 0 Leff= 0.2 0.4 0.6 5 00 0.8 - nm 1 vgs (V) Figure 4.2: Simulation results: comparison of mid-channel Qi-Vgs relationship in short vs. long NMOS devices, with T0 'elec= 1.9 nm and uniform channel doping: Na = 1.25x1018 cm-3 for short devices and 0.6x1018 cm-3 for long. Abrupt junctions are 21 nm deep. DIBL > 300 mV/V for 35 nm device, 100 mV/V for 50 nm device, and < 10 mV/V for the 500 nm device 4.3 Experimental Results: Long Channel Mobility We examine the long-channel universal mobility behavior in large (lOxlO gm) NMOS devices from technologies A and B from Chapter 2 (see Figure 2.11-2.12 for specifications). Mobility versus Vgs For technology A, Toxphys is estimated at -1.5 nm. For large devices, this results in significant gate-to-drain and gate-to-source leakage (Ig) for Vgs > 0.5 V, as seen in Figure 4.3a. To correct Id for this effect, so that it is useful for mobility determination via Eqn. (4.4), we make the assumption that half of the gate leakage current goes to the drain, and half to the source. The results of applying this correction can be seen in Figure 4.3b: with corrected -Is and 'd overlaid, a slight divergence is only apparent for Vgs ~ 1.5V. Substrate 70 current was measured, and found to be negligible for the whole range of Vgs. For subsequent measurements of large devices in technology A, the drain current is corrected in this manner. Technology B does not show significant gate leakage. Applying Eqs. (4.4-4.5) with Vds=50 mV, results for "A" and "B" are compared in Figure 4.4. Note that using Vds > 10 mV can result in significant error in mobility extraction unless Vgs >> Vds [38], due to overestimation of channel charge by Eqn. (4.5). However, in this study we are interested in mobility for Vgs = Vdd, so this error can be neglected. Mobility versus Effective Transverse Field Experimental results reported in the literature typically use Eqn. (3.3) to determine Eeff, the effective or average transverse field seen by electrons in the inversion layer. Channel depletion charge Qb in this case is determined by: V (4.7) Qb= fy'Cg Vds=O where Cgb is gate-to-body capacitance, and Vfb is the flat-band voltage [52]. In practice Vfb may be determined from simulation. Due to lateral charge-sharing effects in short channels Eqn. (4.7) is only valid for long channels. We examine an alternative experimental method for Eeff determination that is applicable to both long and short devices. Assuming that for NMOSFETs with n+ poly gates there is only a small step (at high Vgs and low Vds) between the source and channel potentials, we determine Eeif by: E S eff = 3Telec _ (4.8) 2s where Qj is a function of Vgs, determined via Eqn. (4.5). Toxelec is also a function of Vgs, measured from Eox/C'gsd(Vgs). Comparing Eeff determined by Eqs. (3.3) and (4.7) with the method of Eqn. (4.8), we see in Figure 4.5 that except for low-Vgs (where it is no longer valid to neglect the source-to-channel contact potential) the measured results are almost identical for long-channel devices (technology B). plot of universal mobility for technology B (Figure 4.6). 71 This result is reflected in the (a) x 10- W% Tech A 5 Vds = 50 mV Leff= 10 m 4 3 -is . s ,'/ S 2 . -- -~'' - -- 1 / ' 0 IL -6.5 0 0.5 1 1.5 1 1.5 vgs (V) x 10 (b) -5 2 ~.,I 2- K- -Is+Ig/2 = Id + I92 1.510.51- -8. 5 0 0.5 vgs (V) Figure 4.3: (a) Gate leakage current I9 for technology A, with effect on source and drain currents. (b) Correction to allow Id determination for mobility measurements. 72 Vt 400 - E"" I~ 300 . (n09000 00 0 >l Tech. A C E B "0 0000Tech. 00 200- 0 .0 0 100og 0' Vds =50 mV VtLfflm 060~Lef = 10 pM 0 0 0.5 1 1.5 2 2.5 Vgs (V) Figure 4.4: Measured effective mobility vs. Vgs for technologies A and B. 1.2 (Qb+Q I i2)!, 1 - -- Vgs / 3 TOxelec -Q 2Es E 0.80.6LU. 0.2- = 50 mV ''Vds Leff = 10 pm 0 0.5 1 1.5 Vgs (V) Figure 4.5: Two experimental methods of Eeff determination. 73 2 2.5 500 Vds = 50 mV ' 400- . Leff = 10 p 300- E 2- 200100- Eeff= (Qb + Q/ 2) /Es - 1 8.2 - 0.4 - Eeff = Vgs/ 3Toxec -Qi 1 0.6 - 0.8 1 2Es 1 1.2 Eeff (MV/cm) Figure 4.6: Measured effective mobility compared for two methods of Eeff determination. Technology B. Qj and Qb are from split-CV measurements [52]. TXelec = OI C'gsd(Vgs). Applying this method as well to technology A, the combined results are presented in Figure 4.7. Also shown is the universal mobility curve for the Si0 2 gate dielectric, from [31], and an alternate universal mobility curve fitted to results of technology A. This fit matches experimental mobility with mobility extracted from simulation (using inversemodeled doping profiles) according to Eqn. (4.4); fitting is for a long-channel device at low Vds. The experimental technologies have nitrided gate oxides, so are expected to be superior to Si-Si0 2 universal mobility for high Eeff. Significantly, for high Eeff the mobility in "A" is in fact not inferior to "B", contrary to speculation made in Section 2.4 to account for the poorer electron velocity in saturation. This apparent contraction is further motivation to investigate mobility behavior in short devices, and is resolved in this chapter. 74 500, 500 3Universal 400 Cl) (calibrated to "A") 0000000 300 0 000 0 0 E 0 200 0 Tech. A Tech. B 100- Vds = 50 mV Universal Leff = 10 jim 0' 0.4 0.6 0.8 1 1.2 Eeff (MV/cm) Figure 4.7: Measured effective mobilities for technologies A and B, plotted along with universal curve mobilities. For measured data, Eeff is determined via Eqn. (4.8). 4.4 Experimental Results: Mobility versus Channel Length Effective Mobility versus Channel Length at Constant Gate Bias We apply Eqs. (4.4, 4.6) to measure the pe vs. Leff relationship for technology A. For mobility measurements we use the inverse-modeled set of devices (same wafer and die) from which the parameters Rsd = 190 Qipm and AL = 65 nm were determined. In Figure 4.8, results are shown versus channel length, at two gate biases. Our Rsd estimate may be considered on the low end, compared to other reported experimental estimates [54][55]. However, if we assume a higher value in Eqs. (4.4, 4.6) we no longer see the expected result of geff converging toward the long-channel (10 jim) value as Leff is increased: for example, assuming Rsd = 220 ipm there is significant "overshoot": peif at 100 nm is approximately 10% higher than the long-channel peff. 75 In the absence of any physical explanation for why this would occur, we consider the convergence seen in Figure 4.8 as some confirmation of the inverse-modeled Rsd. Figure 4.8 shows that 9ef at the shortest channel length (35 nm) is almost independent of gate bias and hence transverse field Eeff, suggesting that the universal behavior of Ieff with Eeff has been lifted. It appears that psr is not the limiting component of gep for the shortest devices. This will be explored fur- ther, below. 300- -etf-ongchan (Vgs = 1V) Vgs = 1 .0V 250- E 1.5V C>--Vs= 200- F eff-Iong.chan (Vgs = 1.5 ) 150- 1001 40 - 60 Vds = 50 mV 80 - 100 Effective Channel Length (nm) Figure 4.8: Measured peff vs. Leff for different gate biasing. Technology A. Toxelec=2.4 nm. DIBL at Leff = 45nm = 120 mVIV. On V*ds as a source of error Since V*ds is sensitive to Id, it is not constant across the range of Leff and Vgs investigated, but varies by about a factor of two, as shown in Figure 4.9. For high Eeff and for long channels the dependence of pgef on V*ds should not be significant, but for shorter channels this is unclear. In Figure 4.10 we explore this dependency, comparing peff measured at Vds = 20 mV and 50 mV (a range on the order of the range of V*ds in our eff vs. Leff experiment). We find that the error introduced is less than 0.3% for the range of Leff investigated. 76 40 VgS= 1.0v 30- E 20F- V gs =1.5V Wo 10 Tech. A C' 40 80 60 100 Effective Channel Length (nm) Figure 4.9: Intrinsic drain-to-source bias in (= Vds - IdRs) channel for pe measurements of Figure 4.8. Applied Vds is 50 mV. 1. 0 6 51 1 1 Tech. A 1.061E 0 S 1.055F a) 1.051.00* E 1.045- C). (, 1.041.0c, ' 1%J 5 50 100 150 Effective Channel Length (nm) Figure 4.10: Measured dependence of short-device peff extraction on applied Vds, for a range of Leff. Vgs = IV- 77 Effective Mobility versus Channel Length at Constant Overdrive In order to explore the geff-Leff relationship for several values of constant inversion charge Qj, we measure geff via Eqs. (4.4, 4.6) at three gate overdrives Vod=Vgs-Vt (where Vt is the linear-extracted value at Vds= 5 0 mV). This is shown in Figure 4.11. Although constant overdrive does not correspond exactly to constant Qj, in fact it provides a very good estimate, as can be seen from Figure 4.12, which gives the Qi/q (as determined from long channel CV measurements, interpreted for short-channels according to Eqn. (4.6). 300 - ' 'od (V) = 0.8 1.0 250- 200- Leff (nm~ E 1.451.3 -.. tml.2 150 Vs = 50 mV 100 40 09 60 80 100 Effective Channel Length (nm) Figure 4.11: Measured geff vs. Leff for different gate overdrive. Technology A. Applied Vgs is indicated in inset. Effective mobility at short channels appears to be independent not only of gate bias but of inversion-charge density as well. This would not be expected in the presense of a strong screening effect (invesion-charge screening of ionized channel impurities), which has been invoked in interpreting MOSFET peff data at lower transverse fields [56] [57]. However, for firmer conclusions as to the relevance of carrier screening in deep-sub-100-nm devices, it will be necessary to look at a technology with stronger halos and/or shorter 78 012 12 1.2 10 81 C 1.0 8-Vod(V)= 0.8 0 p __r 0 0 6 -- Tech. A VdS = 50 mV 4 40 60 80 1 100 Effective Channel Length (nm) Figure 4.12: Range of Qj corresponding to Figure 4.11. channel lengths: it is possible that for a shorter device peff would "cross over" and in fact be higher for higher inversion layer density, as would be expected if (1) Coulomb scattering is dominant and (2) strong Coulomb screening exists (see Figure 4.15, below). Effective Mobility versus Channel Length at Constant Effective Field Using Eqn. (4.4) for determination of Eeff, mobility measured for two constants Eeff is shown in Figure 4.13. This clearly demonstrates the disappearance of universal mobility behavior at short channels. This behavior, as well as the trend of Jeff degradation (up to about 30% for the lower Eeff value) are interpreted as evidence that with deep-sub-100-nm scaling, with heavy halo doping, the dominant scattering mechanism changes: pcoulomb < psr However, another scattering mechanism has been proposed for deep-sub-100-nm NMOSFETs: electron mobility may suffer from long-range Coulomb interactions, not with ionized channel impurities but rather with electrons in the heavily doped source/drain and gate regions [58]. In this case the heavy channel doping due to halos might not in fact be the cause of the observed geff degradation. This is a very significant point, for consid- 79 eration of alternative device architectures as discussed in Chapter 3: if such long-range Coulomb interactions are dominant, undoped channels will not be a significant benefit. 300 - - III- 0 e0ff-ong chan (Eeff = 0.8 - - _ MV/cm) Eeff (MV/cm) = 0.8 =1.1 250 W eff-long-chan c E 200 4 (Eeff= 1.1 MV/cm) Lef (nm 1.5 - 1.401.2 100 Vds = 50 mV 40 0.9 60 80 100 Effective Channel Length (nm) Figure 4.13: Measured gf vs. Leff for different Eeff. Technology A. Eeif is determined via Eqn. (4.8). Applied Vgs is indicated in inset. For Iteff at constant Vgs (Figure 4.8) we observe close convergence to the long-channel mobility limits with increasing Leff, this is not the case at constant Eeff. This suggests our method of estimating Eeff for short channels (Eqn. 4.8) needs refinement; ignoring the step in potential between source and channel may be introducing significant error. In addition, we are ignoring any dependence of Rsd on gate bias. Technology B The behavior of technology B with channel-length scaling is not as well understood at this point, in part because the corresponding inverse modeling results are not as refined. Very preliminary results suggest that with Leff scaling there is a decrease of dependence of peff on Eeff--as observed with technology A, but significantly less pronounced. Regarding the 80 work of Chapter 2, it tentatively appears that at the short channels for which velocity was compared ("A" to "B"), Iteff degradation for technology B is much less significant than for technology A. Further investigation is warranted. In Section 2.4 a 14% decrease in electron velocity in saturation was shown for technology A relative to technology B, comparing at constant Qj and DIBL. For the same gate bias conditions, and making the simplifying assumption of no Jteff degradation at shorter channel lengths in technology B, the corresponding mobility degradation moving from "B" to "A" is approximately 25%. 4.5 Investigation of Sources of Error The results of gef versus channel length presented in this chapter must be considered preliminary, for two primary reasons: sensitivity of experimental peff to error in Rsd and Leff estimations, and irregularities in results at longer channel lengths. Effects of Error in Rsd and Leff Estimates Figure 4.14 demonstrates that error in the Leff used for Eqn. (4.4) affects significantly the degree of degradation seen at the shortest channel, but does not affect the general form of the gef - Leff relationship: the high- and low- Eeif data still converges, and g independent of Eeff at the shortest channel length. remains However, in Figure 4.15 we see that using incorrect Rsd in Eqs. (4.4,4.6) leads to more significant error. If we are overestimating Rsd, then the observed convergence at low Leff could be merely an artifact of the measurement technique. We think this unlikely: as mentioned the estimate for Rsd is already considered on the low end. Underestimation is more likely: in this case the high- and low- Eeif lines cross over, as would be the case if carrier screening were a significant effect. To be more confident of the Rsd and Leff numbers from inverse modeling, the mobility model used must be further refined: our inverse modeling up to the time of this work assumed universal mobility (fitted to technology A for high Eeff [as in Figure 4.7]) for all 81 channel lengths. The results presented in this chapter suggest that this assumption is invalid. (a) Underestimating Leff 3jUU Eeff(M V/cm) (b) Overestimating Leff 300 0.8 1.1 - - - - - - 0 250 E 200 - - - U Long Channel Limits - 150 --- - 250 . ...... .. .. .. .. 200 1501Vds= 100 Tech. A 50 mV 60 40 80 40 100 60 80 100 Effective Channel Length (nm) Figure 4.14: Effects of error in Leff estimation, i-/- 5nm. Actual estimated AL is 65 nm. (a) assumes AL = 60 nm. (b) assumes AL = 70 nm. (a) Underestimating Rsd 3uuTeMV/c-)O. - - -- (b) Overestimating Rsd - (0 250- E 0 200- - - - - - - - - - 200 - Long Channel Limits 150 - Tech. A Vds= 50 mV 40 - - - %f)0 1501 100 ......... 250- 60 80 100' 100 40 60 80 100 Effective Channel Length (nm) Figure 4.15: Effects of error in S/D series resistance estimation, +/- 10%. Actual estimated Rsd is 190 Q-gm. (a) assumes Rsd = 209 9i-gm. 82 (b) assumes Rsd: = 171 nm. Results for Longer Channels At medium channel lengths, measured Reff values depart from the long-channel (L = 10 gm) values by up to -10%, as shown in Figure 4.16. In light of this, the assumption that AL and Rsd are constant across a broad range of channel lengths must be questioned. Alternately, it is possible that isolation-induced compressive stress is degrading mobility in some devices, if it can be assumed that this effect varies with differing L/W ratios. Further investigation is necessary to understand this issue. 300 _eff-Io'ng chan (Vg _ = 1V) -- - 25---- 1.OV Vg eff-Iong han (Vg = 1.5V) 0 150 -- 100 100 200 300 400 Effective Channel Length (nm) Figure 4.16: Measured oyff vs. Leff for different gate biasing. Technology A. Txeelec=2.4 nm. Results for points of Leff < 150 nm same as in Figure 4.8. 4.6 Conclusion We have shown that mobility in the shortest NMOSFETs from a deep-sub-100-nm technology does not behave according to a traditional universal relationship with Eeff. We interpret this as evidence that Coulomb scattering (perhaps from ionized channel impurities, but possibly from electrons in the source, drain and gate) is limiting the mobility. However, it is crucial to have an Rsd estimate that is accurate to within a few percent, to 83 make firm conclusions about mobility behavior at these channel lengths. In addition it would be valuable to repeat these observations in another technology with shorter Leff. 84 Chapter 5 Electron Velocity Dependence on Mobility in Deep-sub-100-nm bulk NMOS 5.1 Introduction In Chapters 3 and 4 we have shown mobility degradation with scaling in deep-sub-100-nm bulk NMOS devices, and have suggested architectural alternatives (FDSOI-MOS) for improved mobility. However, the relevance of low-field mobility to the performance of deep-sub-100-nm MOSFETs is not well understood. In this chapter we investigate experimentally, for electrons in short (45 nm) NMOS devices, the relation between mobility at low lateral electric fields (peff) and velocity in the MOSFET saturation regime (veff), where peak lateral fields in the channel are high. Mobility is modified by externally applying uniaxial stress to devices. The corresponding shifts in electron velocity are found to be significant, and are accounted for in energy balance modeling. Understanding the geff-veff relationship is essential for interpreting trends of velocity with scaling observed in Chapter 2. Previous experimental investigations [33][34][59] of the geff-veff (or gewf-gm) relationship have employed alternative NMOS structures with lightly-doped channels and gate oxides 85 in the 4-6 nm (physical) range; the observed geff dependencies may not apply to deepsub-100-nm NMOS devices. We know of no such investigations performed on devices that are "well-tempered" for channel lengths well below 100 nm. 5.2 Experiment Mobility with Uniaxial Stress We investigate NMOS transistors in the 1V CMOS technology A, with Leff for electrostatically sound devices (DIBL <= 120 mV/V) down to -45 nm (see Figure 2.112.12). Using a four-point bending apparatus, schematically illustrated in Figure 5.1, compressive and tensile uniaxial stress parallel to the direction of electron transport is applied to a silicon strip containing several processed die. Surface strains of up to 0.12% are achieved, as estimated from the sample thickness T and radius of curvature R according to the relation: strain = T/2R. This method allows electrical characterization of the same set of devices with and without strain, reducing sources of experimental error. Fractional change in low-field effective mobility (6 eff Age/ eff) corresponding to the induced strain is measured in long (10 gm) and short (45 nm) devices, as shown in Figure 5.2. With Vds low, for linear-region operation, and for Vgs = Vdd, effective mobility is determined from Eqn. (4.4): IdLeff geff = V*dsWQi (5.1) where V*ds (= Vds - Id Rsd) is the intrinsic drain bias. As in Chapter 4, inversion charge density Qi is determined from measurements of capacitance of the long device, but adjusted for the short device via Eqn. (4.6). This long-channel capacitance was measured without strain. Since Vth shifts with strain E, it is necessary to add an additional term AVt- Vt(E=0) - Vt(E#0) to the integration limit in Eqn. (4.6). This approach assumes that introducing strain does not change the shape of the CV characteristic, but only causes a shift. Experiment indicates that this assumption introduces an error of less than 0.1%. 86 Some of the problems associated with mobility measurement in short devices--difficulty in accurately determining Leff and Qi--are not a significant problem for this experiment, because only the ratio of strained to unstrained mobility is required. By measuring geffstrained/geff-unstrained the uncertainties in Leff and O tt 1. t 0 mint tt tt Qi cancel t out. t It ett t t t t t I-V, C-V wi a V TC ~w Figure 5.1: Schematic illustration of strain experiment. This "cancellation of uncertainties" does not apply to the drain-bias term. For short channels and low Vds, channel resistance (Rch) is of the same order as Rsd. Because of this the use of V*ds instead of Vds is found to be critical in the determination of 8peff (short device): the large relative contribution of Rsd to total series resistance means that AV*ds with strain is significant (AV*ds = Vds - AMdRsd)- Effect of uncertaintiesin Rsd on 8geff measurement For our analysis we assume that Rsd does not change with strain; this is not strictly true, because of the piezoresistance effect in the source/drain. Note that: 89ef / Id0 V*dsE IdFV*dso d 87 - 1 (5.2) +10 Vgs = 1V I I I Vds = 50 mV S+5- 10 pmr U)Leff 4-- 0 Leff 00 45 nm 00 -5 -0.05 Tech. A I 0 I +0.05 +0.1 % Uniaxial Strain Figure 5.2: Experimental results: normalized mobility shift in long and short (Leff = 10 gm, -45 nm) devices vs. uniaxial strain. Each point represents a fractional shift relative to unstrained value (which is represented by *). where I', V*dsE are values with strain, and Id, V*dsO unstrained. From this it can be seen that the piezoresistance effect on Rsd may lead to an overestimation of 89eff For example, with tensile strain the piezoresistance effect will increase Id' and decrease VdSE, so that the 8ggff measured is larger than the "intrinsic" value. The effects of this will be discussed further in Section 5.3. The determination of ggff in short devices is also sensitive to misestimation of the nominal (unstrained) value of Rsd; this too will be discussed in Section 5.3. Determination of pg9ff in the long channel device is not significantly affected by this. This sensitivity to Rsd is evident in the greater scatter among data points for 8geff-short: for each measurement at a new strain value, the probe-tip-to-pad contact resistance varies, changing slightly the total S/D series resistance. This is also why the straight-line fit to the data does not pass through (0,0) for the short devices. 88 On long- versus short- channel behavior The difference between 6 peff-long and kteff-short--a 40% reduction of dependence on strain for geff in the short devices--may be indicative of a transition in the dominant scattering mechanism with device scaling, as discussed in Chapter 4. peff-ong is limited by interface scattering (Section 4.1). However, for deep-sub-100-nm channels alternate scattering mechanisms may dominate (Section 4.4). If this is in fact the case, a different dependence of gerf on strain is possible. Vgs = 1V 2 . 1 Vds=1V 10- 0 o -1 -2 ,* * *- Tech. A -0.05 0 0.05 0.1 0.15 % Uniaxial Strain Figure 5.3: Experimental results: normalized velocity shift (near the source) in short (Leff -45 nm) device vs. uniaxial strain. Each point represents a fractional shift relative to unstrained value (which is represented by *). Velocity versus Mobility For this work, velocity is extracted via two methods described in Chapter 2: either ve = vgmi from peak intrinsic saturated transconductance (Eqn. 2.5), or ve = viad from saturated drain current (Eqn. 2.8). Figure 5.3 gives the fractional change in short-device electron velocity (ve - Ave/ve), plotted versus strain; here ve=vidi. As with short-device gf, measurements are sensitive to probe-tip-to-pad contact resistance variation. In Figure 5.4 89 short-device 8 ve is correlated with long-device 6 igff. (Note that ve, vgr and vidi always refer in this chapter to velocity in the short devices). The measured 8ve dependence on strain is essentially the same by either method, appearing to be independent of velocity extraction method. A least-squares linear fit gives 5ve/geff= 0.3. S C,, a!) CD 0 I I I . +2 +4. 00 -C I Vds = 1V Vgmni" +20 Cl) _ 0 -2 - Vidi 0 > Tech. A -5 0 +5 +10 % Mobility Shift, Long Device Figure 5.4: Experimental results: 8 ve extracted by two methods, versus long-device 8 9eff. Mobilities are measured at (Vgs,Vds) = (IV, 50 mV). Velocity vidi is measured at (Vgs,Vds) = (IV, lV). Velocity vgm is from peak saturated intrinsic transconductance, measured at Vds= lV; the peak occurs for Vgs somewhat less than IV. For this data 6ve / 8 peff = 0.31 when using vgn, and 0.30 for vidi. Each point represents a fractional shift relative to unstrained value (which is represented by *) It is more relevant to examine the relation between velocity shift and short-device mobility shift (Figure 5.5) so that mobility and velocity are measured in the same device. Again the results do not depend strongly on the velocity extraction method employed. This smaller mobility shift for short devices, noted previously, translates to a 55% larger value of 8ve/pg9ff than seen in Figure 5.4. Clearly, for understanding transport in deepsub-100-nm MOS devices, it is not valid to infer short-device mobility behavior from 90 measurements of long devices from the same technology. We denote the ratio 8 ve/sgeff (with both values from the short devices) as RVp, and interpret it as a measure of the dependence of source-end electron velocity in the MOSFET saturation regime on lowfield mobility. From Figure 5.5, Rv9 = 0.46-0.48. CD 0 +4 +2 C.) CD V +2 0 0 -0 -2 0 4-** e O* -2 , Vidi -4 -4 -2 0 +2 +4 % Mobility Shift, Short Devices Figure 5.5: Experimental results: 6 ve extracted by two methods, versus short-device 6 pgff. Gate and drain biases are as described for Figure 5.4. For this data, the ratio Rvg = 6 ve / peff = 0.48 when using vgmi, and 0.46 for vidi. Each point represents a fractional shift relative to unstrained value (which is represented by *). 5.3 On Sources of Error in R jt Estimation Series Resistance Effects As mentioned, neglecting the piezoresistance effect in the source and drain may lead to an overestimate of 89eff, producing an artificially low result for Rvg. To assess the signifi- cance of this effect, we measure a square resistance test structure for this technology (technology A): an n-well in a p-type substrate, with doping in the low-10 91 17 cm-3 range, to a depth of 1.5 gm. The test configuration is illustrated in Figure 5.6. We find that test- structure resistance Rt varies linearly with applied strain E. This is characterized by a gaugefactor: G = (ARt/Rt) IE For our test structure G = 50. To estimate from this result how Rsd is changing with strain, we make use of two observations: (1) from inverse modeling results for technology A we find that polysilicon resistivity contributes approximately 40% of the total Rsd, and (2) the piezoresistance effect decreases with increasing doping, by a factor of 2 for an increase of Nd from low-10 17 to mid-10 1 9 cm- 3 [61]. This latter doping level is more appropriate for the source and drain of the real MOSFET. We define an effective gauge factor Geff (ARsd/Rsd) /E which takes these two corrections into account: Geff = (G/ 2 )* 40% = 10. For our maximum tensile strain of 0.12% this means that Rsd may decrease by 1.2%. This means that we are underestimating V*ds (= Vds - Id Rsd) at strain by up to 1.2%, since Vds = 2 *IdRsd (from Figure 4.9) for these bias conditions. This is very significant, given that the maximum measured shift in peff-short in Section 5.2 was 5%. To recalculate Rv taking S/D piezoresistance into account, in Eqn. (5.1) to calculate peff we let: V*ds = Vds - Id Rsdo (1- GeffE) where Rsdo is unstrained S/D series resistance. For velocity calculation, in Eqn. (2.8) we replace the integration limit IdRs with IdRs(1-GeffE). Re-solving, we find Rv is signifi- cantly increased: from 0.47 to 0.59. In addition we check the sensitivity of our measurement of Ryg to an misestimation of the unstrained valued Rsd by 10%: with all parameters extracted assuming Rsd = 190Qpm * 1.1, we find that Ryg is 0.42-0.43: approximately 10% reduced. As we found previously in Chapter 4, it is essential to have an accurate Rad estimate for determination of shortdevice transport quantities. This sensitivity of Ry, to Rsd is mainly through the 8peff measurement: this is evident from the fact that, making the same assumption of Rsd = 190Qgm * 1.1 we find that 8ve shifts by only about 1% (an increase). 92 Axis of stress V2 V3 44 114 200 gm 114 Figure 5.6: Resistance test structure setup. Current was forced through terminals 1-4, Test strucand the corresponding voltage drop measured between terminals 2 and 3. ture resistance Rt was measured for strain = 0, 0.04, and 0.08%. Rt V3 -V 2 / 114- Drain Bias for Low-Field Measurements For all mobility measurements in this chapter, Vds=50 mV. To verify that this in fact corresponds to low-field conditions (i.e. far from velocity saturation) for a 45 nm MOSFET, we estimate the corresponding intrinsic value V*ds from Figure 4.9 as approximately 25 mV. Making the simple approximation that (for Vds << Vgs-Vt) lateral field Ex~ V*dsLeff, we find EX = 5.6 KV/cm. We evaluate this via the Caughey-Thomas expression [64]: (EX) = F i0 1+ (5.3) ( vsat 7 If we estimate go = peff = 250 cm 2 /Vs (from Figure 4.8) and vsat = 1xi0 cm/s, then we find g(Ey) / go = 0.99. This suggests a sufficiently low applied Vds was used. This is further supported by Monte-Carlo simulations of the drift-velocity / electric field relation 3 17 in doped bulk silicon [65], where for bulk doping density Nb = 4x10 cm- velocity- 93 saturation effects do not begin to appear until Ex = 7 KV/cm. For Nb = 4x10 18 cm- 3 , this critical EX value increases to - 15 KV/cm. These simulations, however, were performed for the <111> crystallographic direction. 5.4 Energy Balance Modeling We find that drift-diffusion (DD) simulations severely under-predict RW. However, closer agreement is found in earlier theoretical work with energy transport models [32], with a value of RVg = 0.5 predicted at the 50-nm channel length node, compared to our experimental value (with S/D piezoresistance corrections) of RV = 0.6. We explore this further with energy balance (EB) modeling of a realistic simulated super-halo NMOSFET with 2D doping profiles carefully designed to match measured subthreshold characteristics (DIBL, subthreshold slope, Ioff) of the short (45 nm) devices. To model drain current, a "universal" 9gef vs. Eeff relation is used [9][31], but modified to fit our measured values of peff-ong (as described in Section 4.3). The EB model requires specification of an energy relaxation time (Tw) characterizing the decay of carriers with kinetic energy values out of equilibrium with the semiconductor lattice: this cannot be measured directly, and must be determined from theoretical calculations or from calibrating simulations to experimental results. With our calibrated universal mobility, and with r, = 0.11 ps and an electron saturation velocity vsat = 8.3x10 6 cm/s, we match closely the unstrained Iof vs. Ion characteristic of NMOS devices over a broad range of gate-length in the experimental technology A. This value of vsat agrees with experimental values found for silicon inversion layers in long-channel devices [62]. To simulate the introduction of strain, we use a simple multiplier to increase Reff by 10% for all Eeff. This assumes that both t, and vsat are independent of strain; for vsat this is supported by theoretical studies [63]. The resulting shift in Ion (2.7%) corresponds directly to carrier velocity shift: simulated Rv = 8Ion/keff = 0.27. However, it has been pointed out that tw may not be independent of strain: experimental results for Si/SiGe strained-silicon NMOSFETs have been successfully modeled by assuming Tw and geff 94 have approximately equivalent fractional change with strain [34]. Monte Carlo calculations in [63] support this assumption of t,-increase with strain. Assuming 8'r = 8 geff (where 8, = ATw/Tw), we find by simulation Rv = 0.55, much closer to the experimental value. On Energy- and Momentum- Relaxation Interdependence In [66] an expression is derived relating t, with Tm (momentum relaxation time) where p = qTm/m* (m* = effective mass). Starting with expressions for conservation of electrons, momentum, and energy as derived from the Boltzmann transport equation, if (1) steadystate homogeneous conditions exist, (2) the Caughey-Thomas expression relates chordal electron p. to lateral field Ex, and (3) the electron diffusivity is only weakly dependent upon electron temperature Te (as suggested by Monte Carlo and experimental techniques, summarized in [67]), then the following relation holds: T 3kBTO 110 2 q 1 V2 1+(To/Te) (5.4) sat where To is the lattice temperature. In this case, since IoocTm, tw = A tm where the proportionality constant A depends only upon Te. This suggests a physical basis for letting 8T, = 8pef with strain. This simple picture is complicated by the fact that Te will increase with TW: as Te increases A increases. This suggests 8Tw could be greater than peff, unless Te is significantly higher than To at the channel location where electron velocity is extracted. The above derivation makes no assumptions regarding the dominant scattering mechanism. However, Monte-Carlo simulations for bulk silicon (for the <111> direction) do not suggest Tw and Tm are so strongly interrelated, for the case of heavy Nb. For 104 EX < 105 V/cm, almost no dependence of Tw on Nb is indicated [65]. < This is in apparent contradiction with the above conclusion. The quantity 'r, may have different physical interpretation depending upon the implementation of different models. 95 5.5 Conclusion By corroborating measured velocity and mobility dependence on strain, we have demonstrated experimentally for the first time the importance of low-field effective inversion-layer mobility in deep-sub-100-nm bulk NMOS. Crucial to this work is the determination of mobility shift directly from the shortest device, for which accurate estimates of Rsd are essential. Energy balance models are found to agree with the observed behavior, when it is assumed energy relaxation time shifts with strain. The experimental value Ry, ~ 0.6 suggest that the 14% velocity degradation seen in Chapter 2 (moving from technology B to the shorter technology A [Section 2.4]) should correspond to a 24% mobility degradation. This agrees well with the results of Section 4.4, where a mobility decrease of up to 25% was estimated moving from "B" to "A". 96 Chapter 6 FDSOI Design-Space 6.1 Introduction In Chapter 3 it was shown that FDSOI (Fully-Depleted Silicon-On-Insulator) MOSFETs with mid-gap workfunction gates should have a significant mobility advantage over bulk, in the deep-sub-100-nm regime. In this chapter we examine via 2D simulation the design-space for three basic FDSOI alternatives: single-gate (SG), and double-gate (DG) either with symmetrical workfunction mid-gap gates (DG-CDmg) or asymmetrical workfunction n+p+ gates (DG-n+p+). We focus primarily on scalability and drive current. Methodology Investigations have shown that DG FDSOI MOSFETs may ultimately scale to -10 nm channel length [68] [69]. In this chapter we focus on nearer-term possibilities, consider- ing scaling constraints and performance for the same four design nodes (based approximately on the 1999 ITRS) discussed in Chapter 3, with Leff from 25 to 70 nm (Table 6.1). As we will show, for this regime it is not required to scale silicon film thickness (Tsi) for FDSOI below 5 nm for most cases. For Tsi > 5 nm, quantum-mechanical effects on threshold voltage are not significant [39], suggesting that a classical distribution of inver- 97 sion-layer electrons is still an appropriate approximation. This allows use of a 2D coupled Poisson's / drift-diffusion solver [13] for investigating the sub-threshold region of device operation, to determine scalability and threshold-voltage control. For Tsi < 5 nm, Vt depends critically upon film thickness due to quantum effects [39]; even slight variations could make such ultra-thin films impractical. For modeling saturated drive-current (Ion) we use an energy balance model; the physical justification for this is not clear for deepsub-100-nm devices. However, as noted in Section 5.4, when model parameters are set with proper care the EB model gives realistic results, for Left down to at least 40 nm. TABLE 6.1 FDSOI DESIGN NODE PARAMETERS Approximate ITRS Year Lef (nm) T xphyst Vdd loff (nm) (V) (A/gm) 2000-1 2002 2005 2008 70 50 35 25 2.4 1.8 1.4 1.1 1.35 1x10- 8 1.1 0.9 0.75 1x10- 8 1x10~8 1x10-8 tTOXelec is 0.1-0.2 nm greater than TOxPhys To retain the mobility advantage discussed in Chapter 3, all films are assumed intrinsically doped: threshold voltage Vt is determined by the gate workfunctions and device geometry. High mobility is an additional reason for considering only films with Tsi > 5 nm: thinner films may have degraded mobility due to the proximity of a second scattering interface near the inversion layer [44]. Gate oxide thickness considerationsfor FDSOI In Chapter 3 (Figure 3.7) it was shown that, for inversion-layer areal density Qi/q= 1x10 1 3 cm-2 an FDSOI device with mid-gap gate will operate with effective transverse field Eeff = 0.75 MV/cm, while for a bulk MOSFET Eeff will be approximately 35% to almost 100% higher, depending upon the scaling node. From these numbers, we can infer from 1-D coupled Poisson-Schroedinger solutions in [36] that Tinv (inversion layer centroid depth) in an FDSOI device will be -1.0 nm deeper compared to a heavily-doped bulk device at 98 the same scaling node. This translates to a difference in T0 xelec of -0.3 nm. Because of this it may not seem appropriate to use the same roadmap for TOelec for FDSOI. However, if the lower limit to To, is direct tunneling leakage, FDSOI may permit thinner physical To, by virtue of its substantially reduced transverse surface electric field. Unfortunately, direct tunneling has no simple dependence on VgS or Eeff [72], so it is difficult to evaluate this benefit here. For our analysis in this chapter, we assume the same TOXphys, per generation, as was used for bulk-device simulation in Chapter 3. Solving Poisson's equation assuming a classical distribution for the electron inversion layer results in a very modest increase in Tinv with reduced channel doping and Eeff: TeX lec for FDSOI in our simulations is 0.1-0.2 nm larger than TOxphys (no gate-depletion effects), and up to 0.1 nm larger than Toxelec for the simulated bulk devices of Chapter 3. 6.2 Single Gate Scaling Results Single-gate FDSOI scalability has been examined in [39] with a similar approach (2D Poisson/drift-diffusion solver, and a classical distribution of electrons): Vt-rolloff (with Vds=Vdd) was examined versus Leff for various Tsi and Tox combinations. We take an approach more suited for comparison to roadmap nodes: several parameters (Leff, T0 X, Vdd) are scaled together. For each scaling node we vary Tsi to meet two criteria. As in Section 3.2 we require DIBL ; 100 mV/V. Regarding the second criterion: in Section 3.2 scaling was examined for two structures with similar subthreshold-slope (S) characteristics; a minimum-worst-case-Vt requirement was enough to insure that a device could be sufficiently turned off. However, S can vary widely between SG and DG structures: a maximum-I0 ff requirement (1x 108 A/pm) is more suitable here. In Figure 6.1 we see the effect of varying Tsi on DIBL and Iof for the four scaling nodes. Each point represents a simulated structure from which DIBL and Ioff were extracted. Solid lines represent the fit to this data, from which the critical Tsi was interpolated. The results are shown in summa- 99 requirements below Leff = 35 nm will require Toxelec < rized in Figure 6.2. Meeting I 1.3 nm and/or Tsi < Snm. Gate:G =4.6 V x TL y Tbox = 100 nm Lef 15 nm (b) lof vs. Tsi (a) DIBL vs. Tsi 2001 Leff (nm): Leff (nm): 150- 25 35 25 35 50 70 ,-7 E 50 70 100- S-8 -J M - -- - - -- - - - -- - - -9 501F Vds=Vdd; Vgs=0 -1 II 0 10 20 0 10 20 Silicon Film Thickness (nm) Figure 6.1: Scaling simulations for SG-mg device. (Avant! TMA Medici [13]). Drift3 20 diffusion with Lombardi mobility model. No gate depletion. S/D are n+ 1.5x10 cm , abrupt junctions. Na = 1x10 15 cm-3 in channel. In (a) and (b) each point corresponds to a set of IV transfer characteristics from device with specified Tsi, from which DJIBL (according to Eqn. 2.10) and Ioff were extracted. Tox and Vdd from Table 6.1. On choice of D For both DG- and SG-(mg structures, we choose a gate workfunction (4.6 V) -100 mV below mid-gap, in order to give an appropriate long-channel Vt (300-350 mV, for SG-Gmg and DG-qmg at all four scaling nodes; see [73] for a discussion of optimal Vt). This is expected to result in a PMOS Vt that is too negative, which can be corrected by counter- 100 20 Criteria: o DIBL = 100 mVN C 15 C/ U,CD l off = 1x10~8 A/pm 10- E C 0 5 SG-CDmg 0 30 40 50 60 70 Effective Channel Length (nm) Figure 6.2: Interpolated results from Figure 6.1: Tsi required per scaling node of Table 6.1. To, and Vdd vary with Leff according to Table 6.1. doping of the channel, if mobility in the PMOS device is not considered as critical as in NMOS. Alternatively, there has been some progress in modifying the workfunction for a mid-gap material by controlling deposition parameters [74]: one gate material could have cDg optimized for both N- and PMOS. Our choice of 09=4.6 V corresponds to Schottky barrier measurements of tantalum [71]. SG FDSOI MOSFETs have been fabricated successfully with Ta gates, but with Vt -100 mV lower than expected for both N- and PMOS; the authors attribute this to surface state charge [70]. 6.3 Double Gate Scaling Results DG Alternatives The two alternatives for DG FDSOI design are illustrated schematically in Figure 6.3. Symmetrical DG-Dmg has two inversion layers and DG-n+p+ one. In the long-channel limit Qj for the two cases can be simply related if it is assumed that the inversion charge is a 2D sheet at the Si-SiO 2 interface. In this case the silicon film can be treated as a dielec- 101 tric layer, and the capacitor model shown is appropriate. The corresponding ratio of charge between DG-n+p+ and DG-CDmg is shown in Figure 6.4 for a range of Tsi and Tox. For thin silicon films this charge-sheet assumption is not appropriate, in which case the Qj relationship must be found from a Poisson solution (or coupled Poisson-Schroedinger solution, for very thin films). In addition, 2D effects at short channels significantly modify Qj for a DG-n+p+ device, so that no simple relationship exists between Qj in the two alternative architectures. In this case Figure 6.4 is only illustrative of qualitative trends. FSzED 77~ T T (a) DG-CDmg (b) DG-n+p+ Figure 6.3: Alternative double-gate FDSOI structures. E 0 CL 1 0.9 Increasing Tox 0.8 0 ........ 0.7 0.6 Al. 50 -O Te= 1.0 - 2.5 nm 5 10 15 20 Silicon Film Thickness (nm) Figure 6.4: Ratio in inversion charge in DG-n+p+ vs. DG-(Dmg MOS, according to longchannel charge-sheet model. 102 Leff 15 nm (a) DIBL vs. Tsi (b) lof vs. Tsi -6 200 Leff (nm): Leff (nm): 25 150 5 50 100 - - - - - - - - 70 - - - - - - - 25 35 50 70 E -7- - - - - -8 - -- 50- - - 70 - - - - - - - - - - - - - 9. Vds=Vdd; Vgs=O n 0 - 20 40 1n1 60 0 10 20 30 Silicon Film Thickness (nm) Figure 6.5: Scaling simulations for DG-n+p+ device. Model and doping specifications from Figure 6.1 apply. To, and Vdd from Table 6.1. Simulation Results As with the single-gate device, we vary Tsi and interpolate between DIBL and Iof results from many simulated structures (Figures 6.5 - 6.6) to find the critical Tsi to meet the two short-channel criteria. Results are summarized in Figure 6.7. As we find consistently for FDSOI, the IOf criterion is the more difficult to meet. In [8] it is pointed out that the DG-n+p+ should have better electrostatic confinement and hence relaxed Tsi requirements. From our simulations, this is true if we only consider the DIBL criterion. Considering as well maintaining Ioff : 1 x10~8 A/gm, DG-n+p+ actually requires thinner Tsi. In this sense DG-CDmg scalability is found to be superior. 103 Le)G = 4.6 V ',Ieff T"; - - D -4-(b) loft vs. Tsi (a) DIBL vs. Tsi 200 Leff (nm): Leff (nm): 150 E 35 50 70 - - - - 7- -- E 1001- 0 35 7 -- 25 - -8 m _j -- 50 25 -9 ' ' ' ) ' 40 20 -10- 20 10 0 60 30 Silicon Film Thickness (nm) Figure 6.6: Scaling simulations for DG-(Dmg device. Model and doping specifications from Figure 6.1 apply. To, and Vdd from Table 6.1. I 50 a I I 50 60 Criteria: C 40 A O DIBL = 100 mVN = 1x10-8 A/pm AO If 0 C: 30 DG- +p+ C. E 20 C 10 0 0) '0 30 40 70 Effective Channel Length (nm) Figure 6.7: Interpolated results from Figure 6.5-6.6: Tsi required to meet short-channel criteria for each scaling node of Table 6.1. To, and Vdd vary with Leff according to Table 6.1. 104 For these device architectures, DIBL and Vt-rolloff behaviors are decoupled: large DIBL does not fully correlate with large Vt-rolloff, and vice versa. This can be seen in Figure 6.8, where the DIBL and rolloff components are separated for both architectures. (In this context, Vt-rolloff is the lowering of low-Vds threshold voltage by 2D effects; high Vds effects are captured in the DIBL metric). (a) DG-n+p+ E 80 0 Vt-rolloff C3 DIBL 60- 0 El 60- Vt-rolloff DIBL 40- 40- E 20- 0 (b) DG-(mg 80 30 40 50 60 70 0 20- 0 30 40 50 60 70 Effective Channel Length (nm) Figure 6.8: Simulation results: DIBL and Vt-rolloff for DG structures. Vt-rolloff = 5 Vt(long-device) - Vt(short device), where Vt is linear extracted at Vds= 0 mV. Tsi values used are from Figure 6.7, meeting the Ioff requirement. Other parameters as per Table 6.1. DIBL is via Eqn. (2.10). On threshold voltage dependencies in DG-n+p+ versus DG-(mg We can understand the much-greater Vt-rolloff behavior of the DG-n+p+ device by investigating further the long-channel Vt dependencies. From both simulation and analytical results presented in Figure 6.9 it is clear that the bottom-gate proximity has a strong influence on Vt. Threshold voltage is decreased dramatically as distance to the p+ bottom-gate is increased, either by thickening the bottom-gate oxide (Tbox) or increasing Tsi. Considering the situation in 1-D, the proximity of the p+ gate tends to lower potential cD(y) in the silicon film, and consequently (Ds at the top Si-SiO 2 interface as well. This in turn requires 105 a higher Vgate to raise (IS to the point of inverting the surface: raising Vt. This bottom-gate influence is more pronounced as Tj and T,, are thinned. For the case of short-channel devices, it is conceptually useful to consider the channel (in sub-threshold, with no inversion layer) as a 2D-box where 1(x,y) is set only by the four boundary conditions: source, drain, gate and bottom-gate. As the ratio Tsi / Leff becomes larger, the boundary conditions at the ends of the box (the source and drain) increase in influence over c1(x,y) and hence Fs, This means that gate control over cIS is decreased relatively; this affects the bottom-gate much more, because of its greater distance to the top interface. Vt-rolloff in a DG-n+p+ device can thus be thought of as the bottom-gate progressively, with decreasing L, losing influence on Is and hence Vt TOXphys= 1.5 nm 0 0.3- Tbox = S 1.5 nm 0 > _ l 3 >, .ft Simulated Analytical >0 3nm 3 Z (p = 0.2- 0) 6 nm 0.1. 0 5 10 15 20 25 Silicon Film Thickness (nm) Figure 6.9: DG-n+p+ long-channel Vt: dependency on Tsi and Tbox, with corresponding range of DG-(mg long-channel Vt indicated, upper right. Analytical are ID Laplace solutions (appropriate in the limit of zero channel depletion charge) for Qi/q=1x1O 11 cm-3 Conversely, our simulations show that Vt in a long-channel DG-(mg device is nearly independent of Tsi and Tbox, as also indicated in Figure 6.9. The bottom-gate does not signifi- 106 cantly influence Vt, so the decrease of bottom-gate influence with scaling does not result in a significant lowering of threshold voltage. Importance of lateral SID profiles The simulation structures for the scaling studies in Sections 6.2 - 6.3 have abrupt doping transitions from source/drain to channel. In order to understand the importance of the lateral S/D gradient, the simulations in Figure 6.6 (b) are repeated with Gaussian profiles. The Gaussian characteristic length a,, corresponds loosely to the lateral rolloff in nm/ decade-of-doping. As cy is varied, effective and physical gate lengths are kept fixed (with Leff determined by the points at which the S/D doping fall to 2x10 the metallurgical junction length decreases with increasing a,. 19 cm-3 ). Only We focus on the Ieff crite- rion only, since for all architectures investigated in this chapter it is the more stringent. The results are summarized in Figure 6.10. We see that for a DG-CDmg device their is no significant deleterious effect on scalability for ax 5 4 nm. This is similar to results reported in [2] for a simulated bulk super-halo NMOSFET designed for Leff =25 nm. 25 E 20CD, 5 15. E 10 C: Q Abrupt A ax=2nm . * o0* 9o 30 40 50 ax=4nm Tax=8nm 60 70 Effective Channel Length (nm) Figure 6.10: Simulation results: effect of lateral S/D doping gradient on Tsi required to meet Ioff 1 x 10-8 A/pim. Shown versus scaling nodes of Table 6.1. Simulation grid spacing is 0.6 nm at transitions from S/D to channel. To, and Vdd vary with Leff according to Table 6.1. 107 6.4 Relaxing Ioff Criteria In this section we consider the consequences of relaxing off-current constraints for future scaling generations, for both SG- and DG-MOSFET architectures. Innovative techniques to manage static power dissipation may permit off>> 1x10-8 A/gm for the fastest devices of a technology generation. This is considered for SG-Dmg devices in Figure 6.11; mod- erately larger values of DIBL (120 mV/V) are allowed as well. We see that this substantially relaxes constraints on Tsi. However, for 1x10- 6 < Ioff < 1x10 channel length) DIBL becomes the limiting criterion. 7 A/gm (depending on Significantly, if Ioff = 1x10~7 A/gm is permissible, SG-(mg devices can scale to 25 nm for Tsi > 5nm: this is near the prospective bulk scaling limit [2]. Figures 6.12 and 6.13 repeat this analysis for DG-n+p+ and DG-Dmg devices. 20 Criteria: 0 DIBL = 120 mVN Wc15 - 0 'off, A4"m ~1X1 a) 0-7 0' -c 10-8 ' 10- E 50 0 io 30 40 50 60 70 Effective Channel Length (nm) Figure 6.11: SG-@mg MOSFET, interpolated results from Figure 6.1: Tsi required per scaling node of Table 6.1. T0 , and Vdd vary with Leff according to Table 6.1. 108 6( I 50, * C,) C Criteria: o DIBL = 120 mVN Ioff, A/m 40- -o- 30- E 0 1x10-7 o' 2010F 30 40 50 60 70 Effective Channel Length (nm) Figure 6.12: DG-n+p+ MOSFET, interpolated results from Figure 6.5: Tsi required per scaling node of Table 6.1. To, and Vdd vary with Leff according to Table 6.1. 6( 'I C 50. Criteria: o DIBL = 120 mVN * CLL CD lof, A/Lm E 4030- E C 0 1 X10-7 20- '. -x0-8X1 -~~ ...... 10- 0) 2) 30 40 50 60 70 Effective Channel Length (nm) Figure 6.13: DG-CDmg MOSFET, interpolated results from Figure 6.6: Tsi required per scaling node of Table 6.1. To, and Vdd vary with Leff according to Table 6.1. 109 6.5 Energy Balance Simulation of Io As noted in Section 5.4, EB simulations have been found to match well the experimental Ion/loff characteristics for a family of bulk devices with Leff down to -45 nm. For this reason we choose here to focus on the Leff= 50 nm scaling node of Table 6.1, for our use of EB simulations to compare saturated drive current for the three FDSOI architectures studied in this chapter. Using the Tsi values found from Figures 6.2 and 6.7 to meet Ioff = 1xi 0-8 A/gm, we find Ion using the Lombardi mobility model [75]. In [76] it was shown that the Lombardi model closely approximates universal mobility behavior for the case of low channel doping. Energy relaxation time tw was 0.15 ps. This is reasonable from the perspective of Eqn. (5.4), assuming vsat=9x10 6 cm/s and go of 300-350 cm 2/Vs as determined from Figure 3.9 for SG with Qi/q = 1x10 13 cm-3 or DG with Qi/q = 2x10 (reasonable values assuming Vdd and Tox chosen from Table 6.1). 13 cm-3 The results are shown in Figure 6.14. The EB model gives moderately larger values for Ioff, depending on the -7. R. Leff = 50 nm Vds=Vgs=Vdd E -6 0 0 0 E 0 E 0 -8 CM loff from DD model 0 0 SG-Dmg E -8 Tsi DG-Dmg :Tsi 7.5 nm 18.5 nm A DG-n+p+: T,,= 11.5 nm '0 0.5 1 1.5 2 2.5 Ion (MA/9) Figure 6.14: Energy balance simulation results for Ion and Ioff for the three FDSOI architectures. For solid symbols, lumped resistances were added to the source and drain (80 Qgm per side). Total Rsd for solid symbols is 190-200 Qgm; for open symbols, 30-40 Qpm. Tsi values chosen to meet Ioff criterion(Figure 6.2-6.7); other parameters are for the 50 nm node in Table 6.1. r,=0.15 ps, Lombardi mobility model. 110 device architecture. We see that as expected, for the case of low source/drain resistance (Rsd) the Ion for DG-(cmg is approximately twice that of SG-(cmg. DG-n+p+ falls in between. The total gate capacitance is significantly different for each architecture; from the simple model of Figure 6.3 we can see that Csg < Cdg-n+p+ < Cdg-cDmg- We can normalize for this difference, by comparing carrier velocity as determined from gm / WC'oX (Eqn. 2.4) where gm is the peak saturated transconductance. Cox is determined in simulation from the maximum slope of the dQi/dVgs curve (taken for a short device with Vds=O, extracted from mid-channel; the validity of this approach for a short device was demonstrated in Section 4.2). The results are given in Table 6.2; the lower velocity of DG-n+p+ can be attributed to lower mobility with higher Eeff, in turn due to the fact it has inversion charge density Qj higher than the SG device, and higher than the Qj per channel for the DG-dmg device. Note that the degradation of Ion and gm / WC'x due to Rsd appears to be greatest for the DG-Dmg device: with higher current the potential drop across Rsd is larger, so the intrinsic Vds is degraded further. TABLE 6.2 NORMALIZED TRANSCONDUCTANCE FOR THREE FDSOI ARCHITECTURES; LEFF = 50 NM gm/WC'ox (cm/s) ipm Rsd=190-200 gm/WC'ox (cm/s) Rsd= 3Q- 4 0 Qgm SG-Dmg 8.6x10 6 9.9x10 6 DG-n+p+ 6.7x10 6 8.3x10 6 DG-Dmg 7.9x10 6 10.1x10 6 111 6.6 Conclusion We have explored the design-space for the three basic FDSOI NMOS architectures, which were shown in Chapter 3 to have the potential for significant mobility advantage to bulk at deeply scaled channel lengths. For the single-gate device, it has been shown that scaling below Leff = 35 nm may not be achievable for practical silicon film thickness, unless Ioff requirements are relaxed. For double-gate devices we have shown that hypothetical midgap top- and bottom- gates are superior to n+/p+ poly gates, in terms of both scalability and drive current. 112 Chapter 7 Double-Gate Fabrication Technology 7.1 Introduction Realization of the ideal double-gate device structure involves three major technical challenges: formation of gates above and below a thin single-crystalline silicon layer, achievement of fine alignment between top- and bottom-gates, and achieving low source/drain resistance for the thin silicon film. We address these issues through integration of three primary technologies: wafer bonding with pre-patterned features, interferometric alignment, and selective epitaxy for raised source/drains. 7.2 Formation of Gates Three basic DG fabrication approaches are illustrated schematically in Figure 7.1. Approaches (b) and (c) place extremely stringent demands upon minimum lithographically-defined feature size (Lmin), and hence may not be practical for fully-depleted double-gate devices [8]. From Figure 6.7 we can see that for the 50 nm channel-length generation, Tsi < 20 nm (given Toxelec = 2 nm). For (b) and (c) Ti is defined by lithogra- phy and etch: Tsi=Lmin. This is approximately four times smaller than the Lmi. required 113 for a bulk MOSFET at the same Leff generation (Lgate = 70-80 nm, assuming 10-15 nm gate-to-S/D overlap per side). Although there are various approaches for laterally shrinking features beyond the limits of the photolithography technology (e.g. resist-ashing [78], or trench-narrowing via spacer formation [79]), barring a fundamental breakthrough these do not solve the problem because they do not reduce the variation AL .n- Typically the required tolerance has been +/- 10% [80]; this is also the ITRS requirement through 2014 [1]. Lithography sufficient for bulk at Leff = 50 nm may have Lgate ~ 80 nm and thus ALmn on the order of +/- 8 nm. For (b) and (c) this translates to equivalent ATsi: from Figure 6.6b, it is apparent this at this would result in totally unacceptable 10: in the worst8 case about 20X the nominal value of 1x10- A/gm. z rrent-Carry ng tiZ Plane x Y z urrent- Y X ying oBottom Bott Gater X Icon Wafer (a) Illcon (b) G RMcon Wafer Water (c) Figure 7.1: Three fundamental structural possibilities for DG-FDSOI MOSFETs; illustration from [77]. Option (a), the planar geometry, appears more feasible: technologies for defining vertical dimensions (implantation, diffusion, epitaxy) can be very finely controlled. Planar double-gate devices have been fabricated by pre-patterned bonding [81][82]. We have developed a variation based on the SOIAS process (Silicon-On-Insulator-with-ActiveSubstrate) [83]. This process is illustrated in Figure 7.2; further details of the SOIAS process can be found in [84]. The CMP planarization technology required for pre-patterned bonding is described in [82]. 114 0 -t 0 Grow bottom-gate oxide on SIMOX Pattern bottom-gates . SIMOX Buried Oxide Etch SIMOX wafer and buried oxide Polysilicon Bottom-gate Oxide Silicon 0 Cn, 0 l. LTO Oxide Bonded Interface (a) (c) Deposit LTO and planarize Flip and bond to handle wafer Front-End SOI Process 0 0 LTO CD LTO Oxide Handle Wafer 0 Bonded Interface 0 (d) Cr CD (b) 7.3 Alignment of Gates Several schemes for self-alignment of gates have been proposed [85] and demonstrated [77][86], but have not been shown to be practical for deeply scaled devices with thin Tsi. Models predict that the tolerance in aligning top and bottom gates has to be within Lgate/4 in order to avoid performance deterioration due to bottom-gate overlap capacitance [87]. In order to meet this challenge we apply the IBBI (Interferometric Broad Band Imaging) alignment technique* [88]. A pattern of interference fringes is formed by diffraction from a grating on the mask and a complementary grating on the substrate: the technique relies on the extreme sensitivity of this pattern to the relative position of mask to substrate, to achieve detectivity of sub-nanometer misalignment. We integrate this with proximity Xray lithography: the configuration of X-ray mask and pattern is shown schematically in Figure 7.3. Fabricated test devices, involving pre-patterned bonding for bottom-gates and IBBI alignment of top- to bottom-gates, is shown in Figure 7.4. We have obtained alignment detectivity on the order of several nanometers. However, final alignment results are equally a function of precise pattern placement in the fabrication of top and bottom X-ray masks. We are now developing a process to obtain this precision through close proximity X-ray mask replication. Patterns from the top-gate mask are transferred directly to the bottom-gate mask, eliminating errors in gate-to-gate relative placement due to e-beam field-stitching and other sources. 7.4 Reduction of S/D Parasitic Resistance Silicidation of thin-film SOI devices for low parasitic series resistance Rsd is difficult for Tsi << 50 nm. It is crucial that the silicide does not completely consume the silicon film, in order to maintain a large silicide/silicon interface area [89][55]. This is necessary for traditional silicides with relatively high silicide-to-silicon barrier height Db. One possible solution is to use alternative silicides with Db << Eg/ 2 (where Eg is the Si bandgap). In [90] this was done for Schottky S/D PMOS with PtSi and NMOS with ErSi; consumption * This work was performed in collaboration with Mitch Meinhold and Euclid Moon. 116 X-ray Flux IBBI Signal X-ray Mask Resist / Hardmask --- Poly-Si (Top gate material) Channel Buried gate & Alignment marks Van _Si Si0 2 Si Wafer Figure 7.3: Illustration of the IBBI alignment scheme, applied to double-gate fabrication via X-ray lithography. DG-test devices Figure 7.4: Test double-gate structures fabricated via pre-patterned flip-and-bond, with IBBI alignment. 117 of the entire Si film did not lead to unacceptable Rsd. However, since CDbn = Eg - CDbp two silicides are required for low barriers for CMOS. An alternative approach is to increase the thickness of the S/D regions via selective epitaxial growth of silicon. This has been previously demonstrated in single-gate FDSOI devices fabricated with a traditional silicon nitride (SiNx) spacer process [91]. Epitaxial selectivity to SiNx is more difficult to achieve than to Si0 2 [92]; in [91] this is achieved by introducing HCl during growth, which etches polysilicon nuclei as they form on the SiNx. LTO LTO Si0 SiO 2 2 (a) (b) LTO Lateral overgrowth Si-epitaxy 2 SiO 2 (c) (d) Si0 Figure 7.5: Sacrificial SiNx spacer / selective epitaxial raised S/D process. (a) Gate stack is etched using LTO (low-temperature oxide) hard-mask, followed by re-ox (not shown) and S/D arsenic implants. (b) LTO liner and SiNx LPCVD deposition (13 and 90 nm respectively), followed by anisotropic spacer RIE etch in NF 3 :0 2 , stopping on LTO liner. (c) Pre-epitaxial wet clean (H2 0 2 :H 2 SO 4 followed by HF). (d) Selective removal of SiN, spacers in H3PO 4 , followed immediately by UHVCVD selective growth. 118 Raised Source and Drain Process We have developed a selective-epitaxial raised-S/D process (with sacrificial SiNx spacer) which does not require SiNx selectivity*. Figure 7.5 outlines this process. Epitaxial growth is in a vertical-flow hot-wall UHVCVD reactor with SiH 2 Cl 2/H 2/PH 3 , at 750C. Growth is preceded by an H2 desorb step at 850C. Figure 7.6 shows the results of this process: high-quality S/D regions are formed, to be followed by silicidation. Figure 7.6: Selective epitaxial raised S/D results, shown for a bulk MOSFET. Epitaxial layer is 75 nm thick. The 13 nm LTO liner between epi and n+ poly is not visible here, but its presence can be inferred from the lack of epi-growth on the n+ poly side-wall. (SEM image taken at 100000X, uncoated). Facetingat epitaxy/insulatorinterface A significant problem encountered in the development of this process was the formation of facets at the epitaxy-SiO 2 boundary. This phenomenon is well-known in selective epitaxy [92]. For the process of Figure 7.5 faceting was found to prevent lateral overgrowth * This work was performed in collaboration with Tom Langdo. 119 (a) Si Epi Gate S'02 Si Substrate 50 nmn (b) Figure 7.7: XTEM images. (a) Faceting at Si / LTO interface, with 750C UHVCVD growth via SiH 2 C2/H2. (b) Faceting suppressed, with 750C growth via SiH 2 C12 /H2/ PH 3 - 120 of the LTO liner, leaving the Si film thin at the liner edge: this could be consumed entirely by silicidation, leading to high series resistance. We found faceting could be entirely suppressed by the introduction of moderate amounts of phosphorus in-situ doping (Na ~ 1x10 18 cm-3 ) during the growth process, via PH 3 . Figure 7.7 demonstrates this with an LTO spacers on bulk substrates. The n-doping introduced into the source and drain by this process is low compared to CMOS S/D doping levels: it is not an impediment in forming S/D regions for PMOS devices. 7.5 Conclusion We have demonstrated the key process modules required to build a deeply-scaled doublegate MOSFET: bottom-gate formation via pre-patterned planarization and bonding, direct alignment of top and bottom gates via IBBI, and epitaxial raised source and drain for reducing parasitic resistance associated with very thin-film FDSOI devices. Technical issues still remain in the integration of these models, but there appear to be no fundamental roadblocks to this approach. 121 Chapter 8 Conclusion 8.1 Summary of Results Experimental Results Our study of transport in deep-sub-100-nm NMOS technologies yielded several new observations, which together may be key to understanding drive-current performance trends as bulk MOSFET scaling is continued. In Chapter 2 it was shown that NMOS devices from an advanced CMOS technology operate well below the thermal or ballistic limit of source-to-channel carrier injection, and that continued scaling may actually be decreasing both the ballistic efficiency and the carrier velocity. Degradation of electron low-field mobility with channel length scaling, observed in Chapter 4, is a possible explanation for this. For this explanation to be tenable, velocity in deep-sub-100-nm MOSFETs in saturation must have a strong dependence on low-field mobility: this was demonstrated via the strain measurements of Chapter 5. Simulation Results Whereas the experimental work of Chapter 4 linked the mobility degradation in short Sibulk MOSFETs to a transition in the dominant scattering mechanism, in Chapter 3 via 2D 122 simulations it was demonstrated that even without this transition, future Si-bulk MOSFET scaling is expected to lead to significant mobility degradation. Single- or double-gate Fully-Depleted (FD)SOI MOSFETs, if manufacturable with mid-gap workfunction gates, should not suffer from this drawback. In Chapter 6 it was further shown that, from a scalability standpoint, mid-gap workfunction gates could be a significant enabler for FDSOI MOSFETs, allowing single-gate devices to scale down to 25-35 nm channel lengths with appropriate threshold voltage, and double-gate devices to scale with relaxed silicon film thickness requirements. Changing MOSFET architecture from Si-bulk to FDSOI is one viable route to improving mobility and velocity while maintaining scalability. On the need for enhanced carriervelocity The NMOS carrier velocities measured in Chapter 2 are sufficient to meet the roadmap targets for future generations (Figure 1.1) only if aggressive Toxelec scaling is possible and Vt requirements are relaxed. Whether or not these targets are met, velocity enhancement leads to better performance or equivalent performance at lower power, and may open applications to Si-based MOSFETs that are currently dominated by more expensive III-V devices. 8.2 Future Work Experimental Analysis of Deep-Sub-100-nm Devices As discussed throughout this work, interpretation of experimental measurements of deeply scaled devices are subject to uncertainties in series resistance Rsd and channel length Left. This is especially critical for the results of Chapter 4, the relation between mobility and Left in super-halo bulk devices: errors in Rsd estimation affect not just the quantitative results but the physical interpretation. We have relied heavily on inverse modeling for our Rsd and Left values; these numbers depend on the mobility model chosen, and are at the present time not definitive. Therefore it is preferable to derive an alternative mobility 123 extraction method for deeply scaled MOSFETs that does not require precise knowledge of Rsd and Leff. In [93] it is shown that the slope of the Rtot (total MOSFET series resistance) versus Lmask relationship, within one technology, corresponds to low-field mobility effective mobility. This mobility is not constant with channel length, but it should nonetheless be possible to extract a mobility-vs.-length relationship from the local slope of a fit to a sufficient number of Rtot vs. Lmask data points. This approach is illustrated for a small data set in Figure 8.1. (a) (b) 300 800 - Vds =50 mV 000 0 0 0 0 C 600 - a 400 - - s0op 200- E 0 250 1200 -- $150-r : 100 . e ffW Q i 50-- 0501 100 150 200 250 100 150 200 250 Lmask (nm) Figure 8.1: Illustration of alternative method for egff determination in short NMOS devices, adapted from [93]. For given Lmask, mobility is found from dRtot / dLmaskInversion charge density Qj is determined from long-device CV integration, corrected for short device according to Eqn. (4.6). Results are extremely sensitive to the polynomial fit (here, to degree 3) to the data, suggests that more points are required for reliable results. Technology A. In addition, the exploration in NMOS devices of electron mobility, velocity, and their interrelation should be repeated for holes in deep-sub-100-nm PMOS devices, for a complete understanding of complimentary device behavior. 124 Fabrication Chapter 7 outlined the development of key process modules for the fabrication of thinfilm aligned double-gate FDSOI devices. Integration of these modules is a significant challenge, but to date there has been demonstrated no alternative scheme for double-gate MOSFETs that does not have serious drawbacks. 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For the former, solutions are found numerically to Poisson's equation coupled with the Driftdiffusion equation, which for electrons can be expressed as [94]: Jn(x) = qgnEx + qDnVn where n is electron density and Jn, 9n, and Dn are electron current density, mobility and diffusivity, respectively. N is related to lateral electric field Ex through the Caughey-Thomas relationship [64] which accounts for velocity saturation effects: i-to p(E ) = 1+ E 2 vs at In this case velocities higher than vsat are not permitted. While DD simulations are in many circumstances sufficient for modeling MOSFET electrostatics, in scaled devices with high drain bias carrier velocity (and hence drain current) may be severely under-predicted. As discussed in Section 2.2 we know the restriction ve vsat to be non-physical in deeply-scaled MOSFETs. Electrons transitioning abruptly from low to high lateral electric field regions can be accelerated to beyond vsat for a time characterized by t',, the energy relaxation time [66]. t, is the decay time for carriers with kinetic energy values 135 out of equilibrium with the semiconductor lattice: this situation can be modeled the Energy balance approach. In this case EX in the Caughey-Thomas expression is replaced by an "effective" electric field ET, which is related to the local homogeneous carrier temperature Tc according to [95]: 2 p(E )E- 3 kTC kTe 2T q q = where k is Boltzmann's constant and To the lattice temperature. A fuller description of the DD and EB models, their relation to the Boltzmann transport equation, can be found in [66]. A full description of the relations between electric field, carrier and lattice temperature, and current density can be found in [13]. Neither of these modeling approaches take into account the thermal limit to source-tochannel injection velocity discussed in Chapter 2. For the EB model this can lead to serious over-prediction of carrier velocity and drive current in MOSFETs if Ty is not properly chosen. As noted in Section 5.4, we have found that for a wide range of channel lengths (down to Leff 40 nm) in an advanced NMOS technology, Ion/off characteristics can be matched closely to experimental values for T, = 0.11 ps. 136