CMS EMU
DMB/CFEB Programmers Manual
Version 2.3
12/16/2005
VME address space organization and FPGA instruction descriptions.
Page 1
12/16/2005
Table of Contents
VME A24 D16 ADDRESS SPACE DECLARATION................................................... 3
DEVICE SELECTION SPACE DECLARATION ....................................................................... 3
X10000—X7FFFC....................................................................................................... 3
VME INTERFACE FPGA............................................................................................... 4
CFEB’S (JTAG PORT).................................................................................................... 5
Shift Data with TMS header only ................................................................................ 5
DMB CONTROLLER FPGA (JTAG PORT) ............................................................... 6
Shift Data with TMS header only ................................................................................ 6
DMB CONTROLLER PROM (JTAG PORT) .............................................................. 7
Shift Data with TMS header only ................................................................................ 7
VME INTERFACE PROM (JTAG PORT) ................................................................... 8
Shift Data with TMS header only ................................................................................ 8
DUAL DAC (MAX5154) .................................................................................................. 9
SERIAL DATA FORMAT ..................................................................................................... 9
FIFO’S ............................................................................................................................. 10
DMB ADC’S .................................................................................................................... 11
CONTROL BYTE FORMAT SPECIFIC TO DMB ADC’S (MAX1271) ................................ 12
LOW VOLTAGE MONITORING ............................................................................... 13
CONTROL BYTE FORMAT SPECIFIC TO LV MONITOR ADC’S (MAX1270).................... 14
CONTROL BYTE FORMAT FOR MAX1270/1271................................................... 16
FLASH MEMORY FOR BUCKEYE SHIFTING ...................................................... 17
Page 2
12/16/2005
VME A24 D16 Address Space Declaration
Address Bits
A23…A19
A18…A12
A11…A2
A1..A0
A24…A19
GA4…GA0
Function/Meaning
Geographical Address GA4…GA0
Device Selection
User Defined per Device
Byte Alignment (not used)
A18…A12
Device
A11…A2
Instruction Space
A1
A0
Not used
Device Selection Space Declaration
[A18…A12]
Address in Hex
X00XXX
X01XXX
X02XXX
X03XXX
X04XXX
X05XXX
X06XXX
X07XXX
X08XXX
X09000
X0A000—X0FFF8
X0FFFC
X10000—X7FFFC
Device
VME Interface
CFEB’s
DMB Controller FPGA
DMB Controller PROM
VME Interface PROM
Dual DAC
FIFO’s
DMB ADC’s
LV Monitoring
Flash Memory for Buckeye Shifts
Future Expansion
Emergency Prom. Prog. (data bit0-TMS,bit1-TDI)
Future Expansion
Page 3
12/16/2005
VME Interface FPGA
Address in Hex
00000
00004
00008
0000C
00010
00014
00018
0001C
00020
00024
00028
0002C
00030
00034
00038
0003C
00040
00044
00048
.
.
.
R/W/Ex
Ex
R
Description
NOOP
Read Status
00FF8
00FFC
Page 4
12/16/2005
CFEB’s (JTAG Port)
A11…A8
Shift Bit Count
A7…A2
Instruction
Note: A11 thru A8 contain the number of bits to be shifted minus 1, if applicable.
For example: when shifting 8 bits then Y in the table below should be 7.
In the table below Y represents the bit count.
Address in Hex
01Y00
01Y04
01Y08
01Y0C
01Y10
01Y14
01Y18
01Y1C
01Y20
01Y24
01Y28
01Y2C
01Y30
01Y34
01Y38
01Y3C
01Y40
01Y44
.
.
.
R/W/Ex
W
W
W
W
Description
Shift Data; no TMS header; no TMS tailer
Shift Data with TMS header only
Shift Data with TMS tailer only
Shift Data with TMS header & TMS tailer
R
Ex
W
W
R
Read TDO register
Reset JTAG State Machine
Shift Instruction Register
Write Select Register
Read Select Register
Page 5
12/16/2005
DMB Controller FPGA (JTAG Port)
A11…A8
Shift Bit Count
A7…A2
Instruction
Note: A11 thru A8 contain the number of bits to be shifted minus 1, if applicable.
For example: when shifting 8 bits then Y in the table below should be 7.
In the table below Y represents the bit count.
Address in Hex
02Y00
02Y04
02Y08
02Y0C
02Y10
02Y14
02Y18
02Y1C
02Y20
02Y24
02Y28
02Y2C
02Y30
02Y34
02Y38
02Y3C
02Y40
02Y44
.
.
.
R/W/Ex
W
W
W
W
Description
Shift Data; no TMS header; no TMS tailer
Shift Data with TMS header only
Shift Data with TMS tailer only
Shift Data with TMS header & TMS tailer
R
Ex
W
Read TDO register
Reset JTAG State Machine
Shift Instruction Register
Page 6
12/16/2005
DMB Controller PROM (JTAG Port)
A11…A8
Shift Bit Count
A7…A2
Instruction
Note: A11 thru A8 contain the number of bits to be shifted minus 1, if applicable.
For example: when shifting 8 bits then Y in the table below should be 7.
In the table below Y represents the bit count.
Address in Hex
03Y00
03Y04
03Y08
03Y0C
03Y10
03Y14
03Y18
03Y1C
03Y20
03Y24
03Y28
03Y2C
03Y30
03Y34
03Y38
03Y3C
03Y40
03Y44
.
.
.
R/W/Ex
W
W
W
W
Description
Shift Data; no TMS header; no TMS tailer
Shift Data with TMS header only
Shift Data with TMS tailer only
Shift Data with TMS header & TMS tailer
R
Ex
W
Read TDO register
Reset JTAG State Machine
Shift Instruction Register
Page 7
12/16/2005
VME Interface PROM (JTAG Port)
A11…A8
Shift Bit Count
A7…A2
Instruction
Note: A11 thru A8 contain the number of bits to be shifted minus 1, if applicable.
For example: when shifting 8 bits then Y in the table below should be 7.
In the table below Y represents the bit count.
Address in Hex
04Y00
04Y04
04Y08
04Y0C
04Y10
04Y14
04Y18
04Y1C
04Y20
04Y24
04Y28
04Y2C
04Y30
04Y34
04Y38
04Y3C
04Y40
04Y44
.
.
.
R/W/Ex
W
W
W
W
Description
Shift Data; no TMS header; no TMS tailer
Shift Data with TMS header only
Shift Data with TMS tailer only
Shift Data with TMS header & TMS tailer
R
Ex
W
Read TDO register
Reset JTAG State Machine
Shift Instruction Register
Page 8
12/16/2005
Dual DAC (MAX5154)
Address in Hex
05000
05004
05008
0500C
.
.
.
R/W/Ex
W
Description
Set Calibration DAC
Serial Data Format
MSB…………………………………………………………………..…….……..LSB
16 Bits of Serial Data
Address Bit
Control Bit
MSB……..Data Bits……..LSB
Sub bit
A0
C1,C0
D11…………………..……D0
S0
1 Address Bit/2 Control Bits
12 Data Bits
0
A0
0
1
DAC Port Function
Internal charge injection voltage setting (trigger test pulses).
External capacitor charge injection voltage setting (precision calibration).
16 Bit Serial Word
D11…………D0
A0 C1 C0
MSB
LSB
0 0 1
12 bits of DAC data
1 0 1
12 bits of DAC data
0 1 0
12 bits of DAC data
1 1 0
12 bits of DAC data
Function
S0
0
0
0
0
Load input register A; DAC register is unchanged.
Load input register B; DAC register is unchanged.
Load input register A; all DAC registers are updated.
Load input register B; all DAC registers are updated.
Load all DAC registers from the shift register (start up
both DACs with new data).
Update both DAC registers from their respective input
registers (start up both DACs with data previously stored
in the input registers).
0 1 1
12 bits of DAC data
0
1 0 0
xxxxxxxxxxxx
0
1 1 1
xxxxxxxxxxxx
0
0 0 0
0 0 1 x xxxxxxxx
0
0 0 0
1 0 1 x xxxxxxxx
0
0 0 0
1 1 0 x xxxxxxxx
0
Shut down DAC A when PDL =1.
0 0 0
1 1 1 x xxxxxxxx
0
Shut down DAC B when PDL =1.
0
0
0
0
0
0 1 0 x xxxxxxxx
0 1 1 x xxxxxxxx
1 0 0 1 xxxxxxxx
1 0 0 0 xxxxxxxx
0 0 0 x xxxxxxxx
0
0
0
0
0
UPO goes low (default).
UPO goes high.
Mode 1, DOUT clocked out on SCLK’s rising edge.
Mode 0, DOUT clocked out on SCLK’s falling edge.
No operation (NOOP).
0
0
0
0
0
0
0
0
0
0
Shut down both DACs if PDL =1.
Update DAC register A from input register A (start up
DAC A with data previously stored in inpu register A).
Update DAC register B from input register A (start up
DAC B with data previously stored in inpu register B).
Page 9
12/16/2005
FIFO’s
Address in Hex
06000
06004
06008
0600C
06010
06014
06018
0601C
06020
R/W/Ex
W
W
W
W
R
R
R
R
W
06024
06028
0602C
.
.
.
R
Description
Write data; (no lastword, no overlap)
Write data; (lastword, no overlap)
Write data; (no lastword, overlap)
Write data; (lastword, overlap)
Read low order 16 bits; does not Incr. FIFO
Read low order 16 bits; Incr. FIFO
Read high order 2 bits; does not Incr. FIFO
Read high order 2 bits; Incr. FIFO
Write Select Register
(more than 1 FIFO can be enabled)
Read Select Register (for verification)
Ex
Increment FIFO read counter
Normal Procedure for Writing/Reading FIFO’s
Writing to FIFO’s
1. Select which FIFO(s) to write to (address 6020) in order to output enable the
correct buffer(s).
2. Load data in VME interface FPGA by writing to address 6000, 4, 8, or C. This
will present the data to the FIFO(s) and produces a write enable signal as well as
the write clock.
3. Repeat step 2 until all data is written or the FIFO(s) is (are) full.
4. Restore normal operation by writing zero to the select register disabling the
buffers and enabling the channel link path.
Reading From FIFO’s
1. Select which FIFO to read back by sending JTAG instructions to the controller
FPGA. Use JTAG instruction XXXX along with data for the read enable register.
2. If 18 bits are to be read, read the high order 2 bits first (address 6018). Then read
the low order 16 bits with an increment (address 6010).
3. Repeat step 2 until all data has been read from that FIFO.
4. Repeat step 1-3 until all FIFO’s have been read.
Page 10
12/16/2005
DMB ADC’s
Address in Hex
07000
07004
07008
0700C
07010
07014
07018
0701C
07020
07024
07028
0702C
07030
07034
07038
0703C
07040
07044
07048
0704C
07050
07054
07058
0705C
07060
07064
07068
0706C
.
.
.
R/W/Ex
W
R
Description
Write Control Byte to MAX1271’s
Read Data Back from 1271 Register
R
Read Data Back from Burr Brown Reg.
W
R
Write Select Register
Read Select Register
Page 11
12/16/2005
Control Byte Format Specific To
DMB ADC’s (MAX1271)
Vref = internal reference = 4.096 V
Normal operation (always on)
External Clock Mode
Control-Byte Format
Bit 7
(MSB)
Start
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SEL2
SEL1
SEL0
RNG
BIP
PD1
Measurement
Select Chan
Range
Reg.
Conversion
DMB Temp
CFEB1 Temp
CFEB2 Temp
CFEB3 Temp
CFEB4 Temp
CFEB5 Temp
1.8V Ref.
Virtex Temp
Comp. DAC 1
Comp. DAC 2
Comp. DAC 3
Comp. DAC 4
Comp. DAC 5
N/C
1.8V Ref.
Int. Cal. DAC
DMB GND
CFEB1 GND
CFEB2 GND
CFEB3 GND
CFEB4 GND
CFEB5 GND
1.8V Ref.
Ext. Cal. DAC
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
ADC*4.096/4096
ADC*4.096/4096
ADC*4.096/4096
ADC*4.096/4096
ADC*4.096/4096
ADC*4.096/4096
ADC*4.096/4096
ADC*4.096/4096
ADC*4.096/4096
ADC*4.096/4096
ADC*4.096/4096
ADC*4.096/4096
ADC*4.096/4096
ADC*4.096/4096
ADC*4.096/4096
ADC*4.096/4096
ADC*2*2.048/4096
ADC*2*2.048/4096
ADC*2*2.048/4096
ADC*2*2.048/4096
ADC*2*2.048/4096
ADC*2*2.048/4096
ADC*2*2.048/4096
ADC*2*2.048/4096
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0-4.096
0-4.096
0-4.096
0-4.096
0-4.096
0-4.096
0-4.096
0-4.096
0-4.096
0-4.096
0-4.096
0-4.096
0-4.096
0-4.096
0-4.096
0-4.096
+/-2.048
+/-2.048
+/-2.048
+/-2.048
+/-2.048
+/-2.048
+/-2.048
+/-2.048
Page 12
Bit 0
(LSB)
PD0
Control
Byte
Binary
10001001
10011001
10101001
10111001
11001001
11011001
11101001
11111001
10001001
10011001
10101001
10111001
11001001
11011001
11101001
11111001
10000101
10010101
10100101
10110101
11000101
11010101
11100101
11110101
Control
Byte
Hex
89
99
A9
B9
C9
D9
E9
F9
89
99
A9
B9
C9
D9
E9
F9
85
95
A5
B5
C5
D5
E5
F5
12/16/2005
Low Voltage Monitoring
Address in Hex
08000
08004
08008
0800C
08010
08014
08018
0801C
08020
08024
08028
0802C
08030
08034
08038
0803C
08040
08044
08048
0804C
08050
08054
08058
0805C
08060
08064
08068
0806C
.
.
.
R/W/Ex
W
R
Description
Write Control Byte to MAX1270’s
Read Data Back
W
R
Write Low Voltage Power Register
Read Low Voltage Power Register
W
R
Write ADC Chip Select Register
Read ADC Chip Select Register
Page 13
12/16/2005
Control Byte Format Specific To
LV Monitor ADC’s (MAX1270)
Vref = internal reference = 4.096 V
Normal operation (always on)
External Clock Mode
Control-Byte Format
Bit 7
(MSB)
Start
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SEL2
SEL1
SEL0
RNG
BIP
PD1
Measurement
Select
Reg.
Chan
CFEB1 OCM 3
CFEB1 OCM 5
CFEB1 OCM 6
CFEB2 OCM 3
CFEB2 OCM 5
CFEB2 OCM 6
CFEB3 OCM 3
CFEB3 OCM 5
CFEB3 OCM 6
CFEB4 OCM 3
CFEB4 OCM 5
CFEB4 OCM 6
CFEB5 OCM 3
CFEB5 OCM 5
CFEB5 OCM 6
ALCT OCM 3.3
ALCT OCM 1.8
ALCT OCM 5B
ALCT OCM 5A
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
3
3
3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
Range
Conversion
0-10 V
0-10 V
0-10 V
0-10 V
0-10 V
0-10 V
0-10 V
0-10 V
0-10 V
0-10 V
0-10 V
0-10 V
0-10 V
0-10 V
0-10 V
0-10 V
0-10 V
0-10 V
0-10 V
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
Page 14
Bit 0
(LSB)
PD0
Control
Byte
Binary
10001001
10011001
10101001
10111001
11001001
11011001
11101001
11111001
10001001
10011001
10101001
10111001
11001001
11011001
11101001
11111001
10001001
10011001
10101001
Control
Byte
Hex
89
99
A9
B9
C9
D9
E9
F9
89
99
A9
B9
C9
D9
E9
F9
89
99
A9
12/16/2005
Control Byte Format Specific To LV
Monitor ADC’s (MAX1270)
Continued
Vref = internal reference = 4.096 V
Normal operation (always on)
External Clock Mode
Control-Byte Format
Bit 7
(MSB)
Start
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SEL2
SEL1
SEL0
RNG
BIP
PD1
Bit 0
(LSB)
PD0
Control
Byte
Binary
10110001
11001001
11011001
11100001
11111001
10001001
10010001
10101001
10111001
11000001
11011001
11101001
11110001
10001001
10011001
10100001
10110001
11001001
11011001
11101001
11111001
Control
Byte
Hex
B1
C9
D9
E1
F9
89
91
A9
B9
C1
D9
E9
F1
89
99
A1
B1
C9
D9
E9
F9
Measurement
Select
Reg.
Chan
CFEB1 3.3V
CFEB1 5V
CFEB1 6V
CFEB2 3.3V
CFEB2 5V
CFEB2 6V
CFEB3 3.3V
CFEB3 5V
CFEB3 6V
CFEB4 3.3V
CFEB4 5V
CFEB4 6V
CFEB5 3.3V
CFEB5 5V
CFEB5 6V
ALCT 3.3V
ALCT 1.8V
ALCT 5.5V B
ALCT 5.5V A
Analog Feed
Digital Feed
3
3
3
3
3
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Range
Conversion
0-5 V
0-10 V
0-10 V
0-5 V
0-10 V
0-10 V
0-5 V
0-10 V
0-10 V
0-5 V
0-10 V
0-10 V
0-5 V
0-10 V
0-10 V
0-5 V
0-5 V
0-10 V
0-10 V
0-10 V
0-10 V
ADC*5/4096
ADC*10/4096
ADC*10/4096
ADC*5/4096
ADC*10/4096
ADC*10/4096
ADC*5/4096
ADC*10/4096
ADC*10/4096
ADC*5/4096
ADC*10/4096
ADC*10/4096
ADC*5/4096
ADC*10/4096
ADC*10/4096
ADC*5/4096
ADC*5/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
ADC*10/4096
Page 15
12/16/2005
Control Byte Format for MAX1270/1271
(Taken from data sheet)
Control-Byte Format
Bit 7
(MSB)
Start
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SEL2
SEL1
SEL0
RNG
BIP
PD1
Table 2. Channel Selection
SEL2
SEL1
SEL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Bit 0
(LSB)
PD0
Table 4. Power Down and Clock Selection
Channel
Ch0
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
PD1
PD0
MODE
0
0
Normal Operation (always on),
Internal Clock Mode
0
1
Normal Operation (always on),
External Clock Mode
1
0
Standby Power-Down Mode (STBYPD),
Clock Mode Unaffected
1
1
Full Power-Down Mode (FULLPD),
Clock Mode Unaffected
Table 3. Range and Polarity Selection for MAX1270/MAX1271
Input Range
RNG
0 to 5 V
0 to 10 V
+/- 5 V
+/- 10 V
0
1
0
1
Input Range
RNG
0 to Vref/2
0 to Vref
+/- Vref/2
+/- Vref
0
1
0
1
MAX1270
Negative
BIP
Full Scale
0
0
1
-Vref*1.2207
1
-Vref*2.4414
MAX1271
Negative
BIP
Full Scale
0
0
1
-Vref/2
1
-Vref
Page 16
Zero Scale (V)
Full Scale
0
0
0
0
Vref * 1.2207
Vref * 2.4414
Vref * 1.2207
Vref * 2.4414
Zero Scale (V)
Full Scale
0
0
0
0
Vref/2
Vref
Vref/2
Vref
12/16/2005
Flash Memory for Buckeye Shifting
Address in Hex
09000
09004
09008
0900C
09010
09014
09018
0901C
09020
09024
09028
0902C
09030
09034
09038
0903C
09040
09044
09048
0904C
09050
09054
09058
0905C
09060
09064
09068
0906C
.
.
.
R/W/Ex
Ex
W
Ex
R
Ex
Ex
Page 17
Description
Initialize the Programming Process
Load Buckeye Pattern into FPGA Reg.
Program Flash with Data in Register
Readback FPGA Register
Write Buckeye’s with Flash Content
Erase Flash Memory
12/16/2005