ELECTRONICS LAB PHYSICS DEPARTMENT THE OHIO STATE UNIVERSITY 174 WEST 18TH AVE
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FEBCNTRL ELECTRONICS LAB PHYSICS DEPARTMENT THE OHIO STATE UNIVERSITY 174 WEST 18TH AVE COLUMBUS OHIO 43210 mojo Design goal: CFEB control, SCA addressing, Data transfer COMMENT: RESET must last 800ns or longer Revision history: Mar. 7, 2000: Combined the logic D741F(XC9536XL), D741G(XCS30XL) and D741H(XCS30XL) together MUX150 must synchronize with OE[6:1] Apr. 20, 2000, Refine the timing, logic for production version Apr. 25, 2000, Modify PREBLKEND logic June 12, 2000, Modify LCT and GTRG synch logic to accept 50ns signal June 20, 2000, Using VOTE logic to mitigate the radiation SEU July 14, 2000, Modified the MUX part to disable OE by DATALOAD Aug. 2, 2000, Modified the timing for 40MHz, 20MHz hybrid Aug. 8, 2000, Modified the ADC Clock, SCA write clock, so the external delay can be minimized, only one 1ns step delay needed Oct. 10, 2000, Add the Comparator Reset and Double the Comparator clock, re-arrange the pinout ELECTRONICS LAB PHYSICS DEPARTMENT THE OHIO STATE UNIVERSITY 174 WEST 18TH AVE COLUMBUS OHIO 43210 mojo A B C SCA Master Controller D The standard output setting are Fast 12mA. For other setting, there may be extra delay P40 BLKSCAM 1 SCAMCLK 1 SYNC_RST CLK CLK150NS P132 IPAD P131 IPAD GTRG RAWLCTIN RAWGTRIG PUSH MOVERLAP DATAAVAIL RSTCPLD P87 IPAD GLOBAL_RST GRST IBUF CLK25NS LASTWORD GRST XLOAD XCHECK CLK25NS OECRCMUX 2 CMPRST OPAD P53 OBUF OFD RDENA SCAM150NS LCT SYNC_RST DATAOUT[15:0] RDENA PUSH MOVLAP DATAAVAIL D OPAD P169 OPAD P133 CLK25NS Q RDEN OPAD P186 C LOCAL_RST LASTWORD DATALOAD CRCCHECK OECRCMUX DATA[15:0] 2 CHADR[3:0] AD[3:0] CHADR3 CHADR2 RADR[6:0] ADR[6:0] CHADR1 CHADR0 RADR0 SW1 WADR[6:0] OWADR[6:0] 3 RAD0 RADR1 OBUF RADR2 OBUF RADR3 OBUF RADR4 OBUF RADR5 OBUF RADR6 OBUF RAD1 RAD2 RAD3 RAD4 RAD5 RAD6 IOPAD P201 IOPAD P202 IOPAD P203 IOPAD P205 P192 OPAD P193 OPAD P194 OPAD P173 OPAD P174 OPAD P175 OPAD P176 OPAD OBUF WADR0 WADR1 WADR2 WADR3 WADR4 WADR5 WADR6 3 IOPAD P200 IOPAD P199 IOPAD P195 IOPAD P189 IOPAD P191 IOPAD P187 IOPAD P188 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 $1I1287 TITLE Top Level SCA Controller CMS CSC Electronics BY PARENT PAGE VKS DATE 0 PROJECT D741FEB FILE 10-10-2000_8:55 PAGE FEBCNTRL . 1 10 A B C D DATA transfer controller 1 1 P20 PERIOD=20NS P92 IPAD CMSCLK CLKIN CLKIN IBUFG LOCAL_RST PUSH 2 DATALOAD CRCCHECK SYNC_RST IPAD CMPCLK RST PUSH LASTWORD P213 BLKCPLD LASTWORD XLOAD SENDCHECK SYNC_RST PERIOD=20NS CMPCLKIN IBUFG CLK SCAWCLK SCAM150 C50NS OEN[6:1] LPUSH END SCAWRITE ADCCLK CLK25NS CLK25 FAST OPAD OBUF P54 SCACLK SCAM150NS SCAMCLK 2 OE[6:1] LPUSH P171 IOPAD ENDWORD P170 OPAD SCAWRITE ADC150NS FAST OPAD P215 OPAD P232 ADC CLOCK 3 4 3 SENDCHECK is a hand-wired positive logic signal from SCAM. THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Top Level DATA Transfer Controller CMS CMS Electronics 4 BY JRG PARENT PAGE 0 DATE PROJECT D741FEB FILE 10-10-2000_9:39 PAGE FEBCNTRL .2 10A A B C D Device virtex version 1 P86 IPAD ADC3B0 P206 IPAD ADC2B0 P9 IPAD ADC1B0 P85 IPAD ADC3B1 P207 IPAD ADC2B1 P7 IPAD ADC1B1 P84 IPAD ADC3B2 P208 ADC2B2 P6 P82 IPAD ADC3B3 P216 ADC2B3 P5 P81 IPAD ADC3B4 P217 ADC2B4 P4 P80 IPAD ADC3B5 P218 ADC2B5 P3 P79 IPAD ADC3B6 P220 ADC2B6 P238 P78 IPAD ADC3B7 P221 ADC2B7 P237 P74 IPAD ADC3B8 P222 ADC2B8 P236 P73 IPAD ADC3B9 P223 ADC2B9 P235 P72 IPAD ADC3B10 P224 ADC2B10 P234 P71 IPAD ADC3B11 P228 ADC2B11 P231 P70 IPAD ADC3B12 P229 ADC2B12 P230 IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD FPGA Multiplexer The Six ADC inputs latched by 150ns clock, Output latched by 25ns clock ADC1B2 ADC1B4 ADC1B5 ADC1B6 ADC1B7 ADC1B8 ADC1B9 P30 ADC1B10 BLKMUX ADC1B11 ADC1B12 ADC1B[12:0] K1ADC[12:0] OVERLAP OVERLAP ADC2B[12:0] K2ADC[12:0] ADC3B[12:0] OUT[15:0] K3ADC[12:0] 2 OUT0 OUT1 K4ADC[12:0] ADC6B[12:0] K6ADC[12:0] ADC5B[12:0] P11 P12 P13 P17 P18 P19 P20 P21 P23 P24 3 P25 P26 IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD ADC4B0 ADC4B1 ADC4B2 ADC4B3 ADC4B4 ADC4B5 ADC4B6 ADC4B7 ADC4B8 ADC4B9 ADC4B10 ADC4B11 ADC4B12 P93 IPAD P94 IPAD P95 IPAD P96 IPAD P97 IPAD P99 IPAD P100 IPAD P101 IPAD P102 IPAD P103 IPAD P107 IPAD P108 IPAD P109 IPAD ADC6B0 ADC6B1 ADC6B2 ADC6B3 ADC6B4 ADC6B5 ADC6B6 ADC6B7 ADC6B8 ADC6B9 ADC6B10 ADC6B11 ADC6B12 ADC5B0 P130 IPAD P128 IPAD ADC5B1 IPAD ADC5B2 P127 P126 IPAD P125 IPAD P118 IPAD P117 IPAD P116 IPAD P115 IPAD P114 IPAD P113 IPAD P111 IPAD P110 IPAD ADC5B3 ADC5B4 K5ADC[12:0] OECRCMUX ADC5B7 ADC5B8 P161 OPAD P160 OUT3 OPAD P159 OPAD P155 OUT5 OPAD P154 OUT6 OPAD P153 OECRC OUT7 OPAD P152 OPAD P149 OPAD P147 OPAD P146 OPAD P144 OPAD P142 OPAD P141 OPAD P140 OPAD P139 OUT8 OUT9 CLK150 ADC5B6 CLK25NS PUSH P162 OPAD DLOAD OE[6:1] SCAM150NS OPAD DATA[15:0] OE[6:1] ADC5B5 P168 OUT2 OUT4 DATA[15:0] DATALOAD OPAD OUT[15:0] ADC4B[12:0] P10 1 ADC1B3 OUT10 DCLK25 OUT11 START OUT12 ADC5B9 OUT13 ADC5B10 OUT14 ADC5B11 OUT15 2 3 ADC5B12 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Top Level Front End Board Output Multiplexer & CRC CMS CSC Electronics BY PARENT PAGE JG&GU DATE PROJECT 0 D741FEB FILE 10-10-2000_8:44 PAGE FEBCNTRL . 3 10B A B C CLKDLL CLKDLL CMPCLKIN P210 CLKIN IPAD CLKIN CLKFB CLKIN CLK0 CLKFB CLK90 CLK0 CLK 15NS BUFG CLK12NS CMPFDBK D CLK90 IBUFG CLK180 CLK180 1 1 CLK270 CLK270 CMPMUX CLK2X OPAD CLK2X P209 BUFG OBUF VCC FDC D XLOAD RST LOCKED FDC Q LOAD PENA CLK Q C CLR D Q OEN2 OEN3 CE C CHECKPUSH SENDCHECK CLR RST AND2 LOAD PUSH RST OEN6 2 OR2B1 RST FDPE RST RST FDPE FDP GND CLR LOCKED FDCE D CLK C CHECKPUSH is controlled by OE2 at 150ns Checksum must be on the bus during OE3 (OE2 in MUX). SENDCHECK goes true during OE5 after PUSH goes low. ADCCLK goes high when OE2 goes true here (also OE1 goes true in MUX). ADCCLK goes low when OE5 goes true here (also OE4 goes true in MUX). CLKDV CLKDV RST CLK12NS 10NS T LPUSH PRE DIN PENA CLK NOR2 OR2B1 OR2 PRE D Q PUSH_1 CE PRE D Q PUSH_2 CLK TRUE Q OBUFT AND2 CE C D CLK 2 C C LLPUSH IBUF OEN1 Assume that RST from FPGA comes (or goes) when C50NS goes high. INV RSTCLK FDP D FDP FDC PRE Q OEN1 C D Q OEN2 FDP PRE D Q OEN3 D C C FDP PRE Q OEN4 C FDP PRE D Q OEN5 C OEN[6:1] OEN6 PRE D Q OEN1 C OEN1 OEN2 OR2 OEN2 OEN3 OR2 OEN3 OEN4 OR2 OEN4 OEN5 OR2 OEN5 OR2 OEN6 CLR 3 CLK VCC FDC D XLOAD LLPUSH RST OR2B1 XRST Q LXLOAD LASTWORD FDC XLAST LAST PREEND TRUE D Q D C OBUF OR2 CLR CLK FDCE LASTWORD D END Q AND2 CLK C RST 4 FDC CLR RST OEN6 LXLOAD C 3 CLR OR2 FDC Q D Q 4 INV OEN1 CE CLK OEN6 AND2 RST NAND2 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 CLK C CLR RST TITLE C CLR ADC and Clock Control Cathode Front End Board CMS CSC Electronics BY PARENT PAGE JRG&GU 10A DATE PROJECT D741FEB FILE 10-10-2000_8:43 PAGE BLKCPLD . 1 20 A B C FDC SCAWCLK 1 D FDC D Q D SCAM150 Q BUFG 1 20NS C50NS Q C 40NS BUFG C CLR C CLR CLR CLK C CLR RSTCLK FDC D INV INV CLK FDC Q D RSTCLK VCC FDC D SYNC_RST 2 FD D Q CLK C RSTCLK Q 2 C CLR Reset the clock to synchrounize the CLK50 with Motherboard CLK50 3 ADC clock generator 25ns delay FD 75ns delay SCAM150 D 20NS 25ns delay 6ns delay FD Q D 3 OFD_1 Q D Q ADCCLK INV CLK CLK C CLK12NS C C SCA Write clock generator FD FD_1 C50NS D D FD Q D OFD_1 Q D Q SCAWRITE Q AND2 4 CLK CLK12NS C CLK12NS C CLK12NS 4 C C THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE ADC and Clock Control Cathode Front End Board CMS CSC Electronics BY GU PARENT PAGE 10A DATE PROJECT D741FEB FILE 8-8-2000_8:26 PAGE BLKCPLD . 2 20A A B C D FD DLOAD OE1 D 1 OEN1 Q BUFT13 FD13CE OECHECK OR3B1 K1ADC[12:0] C INT[12:0] FD DLOAD OE2 D Q OEN2 K2ADC[12:0] C T ADC2B[12:0] D[12:0] Q[12:0] D Q OEN3 OR3B1 K3ADC[12:0] C D BUFT13 FD13CE OECHECK 2 FD_1 DATA13 C FD DLOAD OE3 C BUFT13 FD13CE OR3B1 OUT[15:0] Q[12:0] DCLK25 C OECHECK OUT[12:0] D[12:0] Q[12:0] CLK150 1 OFD13 T ADC1B[12:0] D[12:0] Q C T ADC3B[12:0] D[12:0] 2 Q[12:0] FD_1 C FD DLOAD OE4 D D Q OEN4 BUFT13 FD13CE OECHECK OR3B1 K4ADC[12:0] C CLK150 Q C T ADC4B[12:0] D[12:0] Q[12:0] OECHECK INV C FD DLOAD OE5 D Q FD OEN5 BUFT13 FD13CE OECHECK OR3B1 K5ADC[12:0] C OFD T Q DT13 T ADC5B[12:0] D[12:0] D D Q OUT13 BUFT DCLK25 C Q[12:0] C 3 3 FD DLOAD OE6 OE[6:1] C D FD_1 Q OEN6 BUFT13 FD13CE OECHECK OR3B1 K6ADC[12:0] C D DT14 Q D Q OUT14 BUFT T ADC6B[12:0] D[12:0] DATA14 OFD T CLK150 C C Q[12:0] FD_1 C DATA15 D CLK150 C OFD Q D Q OUT15 FD DLOAD D Q OEN7 C BUFT13 INV T DCLK25 C 4 Removable, but be careful! It won't hurt to keep it... OFD DATA[12:0] D OVERLAP Q 4 C DATA[15:0] THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Multiplexer Logic Front End Board Output CMS CSC Electronics BY PARENT PAGE JG&GU DATE 10B PROJECT D741FEB FILE 8-8-2000_7:56 PAGE BLKMUX . 1 30 A B C D 1 1 CRC-15 check, Primitive Polynomial: X^15+X+1 For CRC-15 correctable logic, see this page OECHECK VCC FDC D FDC_1 Q D FD OECRC5 Q FD D Q BUFT13 D T Q INV OECRC 2 OEN5 C C CLR CRC[13:1] DCLK25 DCLK25 C CLR C INT[12:0] T 2 CRC14 DT13 INV BUFT T CRC15 DT14 BUFT CRC[15:1] P35 CHECKCRC FD13 ADCIN[12:0] D[12:0] FD15C ADCBIT[12:0] Q[12:0] CRC[15:1] CHECKB[15:1] DCLK25 CHKBITS[15:1] D[14:0] C VCC INT[12:0] PRECHK[15:1] Q[14:0] CE DCLK25 C CLR 3 3 VCC FDC D START FD D D OEN6 C CLR OEN1 FDC_1 Q C Q CLR FD_1 Q D Q INV DCLK25 C C 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE CRC dataout logic Front End Board Output CMS CSC Electronics BY GU PARENT PAGE DATE 10B PROJECT D741FEB FILE 4-21-2000_11:26 PAGE BLKMUX . 2 30A A B C D CRC-15 Primitive Polynomial: X^15+X+1 1 1 ADCBIT[12:0] CHECKB[15:1] ADCBIT12 ADCBIT11 ADCBIT10 ADCBIT0 CHECKB1 PRECHK3 XOR2 ADCBIT9 ADCBIT8 ADCBIT7 ADCBIT6 ADCBIT5 ADCBIT0 ADCBIT1 CHECKB2 PRECHK4 PRECHK3 XOR4 ADCBIT4 ADCBIT3 ADCBIT2 ADCBIT1 ADCBIT0 2 ADCBIT1 ADCBIT2 CHECKB3 PRECHK4 PRECHK5 2 XOR4 ADCBIT2 ADCBIT3 CHECKB4 PRECHK5 ADCBIT8 PRECHK6 ADCBIT9 XOR4 CHECKB10 ADCBIT3 PRECHK12 ADCBIT4 PRECHK11 CHECKB5 XOR4 PRECHK6 PRECHK[15:1] ADCBIT9 PRECHK7 PRECHK15 ADCBIT10 XOR4 PRECHK14 PRECHK13 PRECHK12 3 PRECHK11 CHECKB11 ADCBIT4 PRECHK13 ADCBIT5 PRECHK12 CHECKB6 XOR4 PRECHK7 ADCBIT10 PRECHK8 PRECHK10 PRECHK9 ADCBIT5 PRECHK8 ADCBIT6 PRECHK7 PRECHK8 PRECHK6 PRECHK9 3 ADCBIT11 XOR4 CHECKB12 PRECHK14 PRECHK13 CHECKB7 XOR4 ADCBIT11 ADCBIT12 XOR4 PRECHK5 CHECKB13 ADCBIT6 PRECHK14 PRECHK4 ADCBIT7 PRECHK3 CHECKB8 PRECHK15 PRECHK9 XOR4 PRECHK2 PRECHK10 ADCBIT12 PRECHK1 XOR4 PRECHK15 ADCBIT7 CHECKB14 PRECHK1 ADCBIT8 CHECKB9 XOR3 PRECHK10 PRECHK2 4 PRECHK11 CHECKB15 4 BUF XOR4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE CRC-15 Logic Front End Board Output CMS CSC Electronics BY GU PARENT PAGE DATE 30A PROJECT D741FEB FILE 3-8-2000_11:20 PAGE CHECKCRC . 1 35 A B P60 1 WADR[6:0] WADR[6:0] YGTRG[3:0] BADR[3:0] NADR[3:0] NGTRG[3:0] WRENA RST CLK BADR[3:0] ENAREG RSTA[3:0] SELPATHA SELPATHB SELPATHC STATES FIFO1 DOUT[3:0] NBADR ENAREG LCTADR[3:0] NADR[3:0] PATHASEL NGDATA PATHBSEL Q[3:0] PATHCSEL NGDATA STATUS[19:16] LCTADR[3:0] LCTADR[3:0] NGDATA ENAFR CER OWADR[6:0] W[6:0] Q[3:0] OVERWR DCLKSTAT CLK25NS STATUS[3:0] DCLKSTAT PFIFO1 EMPT- LCLKSTAT FULL RST OVERWR CLK EMPTY- CLK150NS MOVERLAP NEXTRD LOUT[7:0] ENAFR ENAFW PREBLKEND EFLG RST FULL FULL3 XLOAD CER EFLG EFLG CEW NOGTRG Q[3:0] PREBLKEND CLK RST RST DOREAD DDONE OECRCMUX TEMPTY TEMPTY DIGIDONE DIGIDONE LASTWORDD ERRLOAD ERRLOAD XLOAD 1 RDENA BUSY LASTWORD RST XCHECK XCHECK CSTAT[2:1] DATAAVAIL DAV BUSY EFLG S[3:0] PUSH TRGDONE RDENA CSTAT[2:1] NOGTRG STATUS[8:5] DEFLG PUSH RADR[3:0] PFIFO1 CLK READOUT DEFLG LCTBIN[7:0] NEXTRD TRGDONE C50 CLK RADR[3:0] PFIFO1 RDBUSY TRGDONE OVERWR CLK CSTAT[2:1] NXTRD GTRG BUSY FULL1 P80s LOADPBLK3 DOUT[3:0] LCT GTRIG POP RST SELA LCT ALMOSTFUL D RDCNTRL STATES BLOCKSEL DIN[3:0] CSTAT[2:1] OVERWR MOVLP CLK25NS LCLKSTAT LOUT[7:0] SELPATHA PUSH CLK CLK DATAOUT0 FULL_1 LCTYENA LCLKSTAT WRENA RST DIN[3:0] NGDATA C P70s P55 DATAOUT[15:0] S[3:0] DATAOUT[15:0] AD[3:0] ADO[3:0] XCHK ADR[6:0] ADR[6:0] STATUS[3:0] FIFO1Q[3:0] RSTA[3:0] RSTA[3:0] 2 2 P50 P90 SCAMCNTRL LCT P58 LCT LCTYENA TRGDONE DONE DEFLG DEFLG OVERWR JTAG TEMP2 LLCT OVERWR FULL1 LLCT WADR[6:3] SELB SELPATHB RADR[3:0] SELC SELPATHC STATUS[20:0] RADR[3:0] TRBLOUT TRBLOUT RDENA FULL3 TEMPTY RST NOGTRG LOADPBLK[3:0] ENAFIFOR NGDATA ENAFR NOGTRG S[3:0] 3 STATUS15 STATUS[19:16] STATUS20 BUF FD S[3:0] LOADPBLK[3:0] PREBLKEND CLK FDC PREBLKEND D RAWLCTIN GRST CLK25NS LCT Q C C FD TRUE RST1 NOLCT D FDC RSTCPLD RSTCPLD NOLCT Q CLR SYNC_RST RST CLK LCLKSTAT LCT VCC JRST GRST Q FD C IBUF JRST D TRUE SYNC_RST CLK JRST STATUS14 TRBLOUT VCC NGDATA ENAFW JTAGRST STATUS13 BUF BUF ENAFIFOW STATUS12 BUF BUSY ENAREG STATUS11 BUF PUSH EFLG ENAREG STATUS10 BUF BUF PFIFO1 STATES LOADPBLK3 STATUS[20:0] STATUS9 BUF EMPTY- RDENARST WRENA STATUS[8:5] WADR[3:0] 3 4 STATUS4 BUF SELPATHA STATEOUT LOADPBLK[3:0] LOADPBLK[3:0] SELA WRENA STATUS[3:0] LCTYENA D Q D GTRIG Q 4 RST RAWGTRIG BUF CLK25NS C IBUF C CLR GTRIG THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Block Diagram SCA CONTROLLER CMS CSC Electronics BY PARENT PAGE G,G,S DATE 8-6-2000_9:46 PROJECT D741FEB 10 FILE BLKSCAM . 1 PAGE 40 A B C BUFE4 1 XLOAD STATUS[19:0] D DATAOUT[15:0] 1 E STATUS3 DATAOUT3 STATUS2 DATAOUT2 STATUS1 DATAOUT1 DATAOUT0 STATUS0 BUFE4 FULLLOAD E STATUS8 DATAOUT7 STATUS7 DATAOUT6 STATUS6 DATAOUT5 STATUS5 DATAOUT4 BUFE4 FULL1 FULLLOAD FULL3 FULLLOAD XLOAD ERRLOAD LASTWORD LASTWORDD OR2 OR2 E DATAOUT10 OR2 2 2 DATAOUT12 DATAOUT13 VCC DATAOUT15 BUFE4 FULLLOAD E DATAOUT14 DATAOUT11 DATAOUT9 GND DATAOUT8 BUFE4 ERRLOAD E DATAOUT12 VCC DATAOUT15 DATAOUT9 BUFE4 3 ERRLOAD DATAOUT13 3 E DATAOUT8 GND DATAOUT10 DATAOUT11 DATAOUT14 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Block Diagram SCA CONTROLLER CMS CSC Electronics BY PARENT PAGE G,G,S DATE 3-9-2000_8:45 PROJECT D741FEB 10 FILE PAGE BLKSCAM . 2 40A A B C D Bus S[2:0] is the primary state machine of the device. PREBLOCKEND is the reference used to determine which blocks belong to the LCT. It is also used in READCONTROL to determine which blocks are saved for digitization. F2 LLCT 1 FDCE F2 D SF2 STATES CLK D STATES CLK C FDCE D F2 FDCE F1 Q D CE FDC F2 Q D F3 Q D Q C CE C LCTYENA 1 S0 C C CLR CLR C AND2 Mark Current Adr BUSY S1 CLR CLR CLR F4 INV C Q RST RST FDC_1 OR3 QLCT CE CLR VCC LCT Q CE OR2 1 FDCE SELA S2 AND3B2 RST 6 S2 OR2 AND2B1 2 S1 LRST1 STATES LLCT FDCE D F2 FDCE SF1 Q D CE LCT FDC Q SF2 D SF4 SF3 Q D Q SELC S1 AND3B1 C CLR Mark YesGTRG adr FREE after Readout S0 CE C AND3B2 2 S2 FDC_1 C CLR C CLR AND2 Enable the NBADR memory DONE CLR 2 NOLCT NGDATA AND3B1 CLK VCC Mark NoLCT adr FREE ENAFIFOW S0 WRENA DEFLG AND2B1 NOGTRG RST 3 S1 OR2 AND2B1 OR4 Mark NoGTRG adr FREE S0 LRST2 SELB BUF S2 3 3 OVERWR FDC S2 S0 STATES D AND5B2 Q STATEOUT Do not free addresses on EFLG!! S1 AND3B2 CLK C CLR S1 LOADPBLK0 Q0 XNOR2 Q1 PREBLKEND LOADPBLK1 XNOR2 S2 4 AND3 Q3 C S[3:0] AND3B3 S0 S1 S2 S2 S1 S3 S0 7 ENAFIFOR SYNC_RST AND3 CE LOADPBLK2 LOADPBLK[3:0] VCC Q2 ENAREG S2 CB4CE S0 S1 0 S0 RST CLK XNOR2 CEO C TC CLR FD_1 BUF 4 GRST RSTCPLD JRST D Q RST RST OR2 CLK THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Control SCA Controller CMS CSC Electronics BY VKS PARENT PAGE DATE C 40 PROJECT FILE 8-7-2000_10:00 D741FEB SCAMCNTRL . 1 PAGE P50 A B C RAMB4_S16_S16 D P57 VOTE D0 DATAOUT0 DATAOUT15 CE_WR VCC WEA DATAOUT5 ENA OVERWR Q D1 DATAOUT10 D2 DOUT[3:0] RSTA 1 CB5CE DOA[15:0] CLK WA[4:0] ADDRA[7:0] DATAOUT6 DIA[15:0] DATAOUT11 VOTE D0 WA6 D2 CLR DATAOUT2 GND GND GND WEB GND DATAOUT12 CLKB DATAOUT3 ADDRB[7:0] DATAOUT8 DIB[15:0] DATAOUT13 D0 RA[7:0] RA5 CE D2 CLR DATAOUT4 D0 DATAOUT9 2 DATAOUT14 Q0 D1 Q1 GND D2 2 D2 Q0 FDP RST Q1 PRE Q2 Q2 D3 DOUT3 Q Q[3:0] CB4VJ D0 VOTE D1 GNDGNDGND D Q3 Q3 EMPTY Q OR2 AND2 AND4B3 CE_WR LAST AND2B1 C CE_RD UP CE_WR L CE EMPTAND3B2 CEO C XOR2 DOUT2 Q RA7 C 3 VOTE D1 DATAIN[15:0] RA6 CE_RD DOUT1 Q D2 DOB[15:0] Q[4:0] VOTE D1 DATAOUT[15:0] RSTB CLK RA[4:0] D0 DATAOUT7 ENB CB5CE CLK Q WA7 C CE_WR 1 DOUT0 D1 DATAIN[15:0] WA5 CE CLK DATAOUT1 WA[7:0] Q[4:0] CE_WR CLKA INV FDC TC D CLR LAST Q 3 RST AND2 DIN[3:0] OR3 DATAIN[15:0] C CLR NGDATA DATAIN15 BUF DIN3 BUF DIN2 BUF DIN1 BUF DIN0 BUF BUF BUF BUF BUF BUF BUF 4 BUF BUF BUF LCLKSTAT BUF DATAIN14 AND3B1 DATAIN13 AND4B1 DATAIN12 FDC DATAIN11 CE_WR DATAIN10 D LAST DATAIN9 Q FULL OR2 AND2 DATAIN8 AND2B1 CE_RD C CLK DATAIN7 CLR DATAIN6 PUSH DATAIN5 DATAIN4 DATAIN3 DATAIN2 CE_WR FULL CER POP CE_RD FULL_1 4 AND2B1 EMPTY DATAIN1 AND3B1 DATAIN0 BUF THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Local Trigger Storage SCA Master CMS CSC Electronics BY PARENT PAGE VKS DATE 7-20-2000_8:40 PROJECT 40 FILE D741FEB FIFO1 . 1 PAGE 55 A B C D 1 1 WADR[3:0] WADR3 WADR2 WADR0 RADR0 WADR1 XOR2 WADR0 This will test if there is a write during read in the same block. WADR1 FDC VCC RADR1 XOR2 2 WADR2 RADR[3:0] WHOOPS RADR2 RADR3 RADR2 RADR1 TROUBLE RDENAXOR2 D Q TRBLOUT 2 C CLR AND2B1 RST NOR4 WADR3 RADR3 XOR2 RADR0 3 3 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Temporary For Trouble shooting Only, again! SCA Controller CMS CSC Electronics BY JRG PARENT PAGE DATE 4-21-2000_11:56 40 PROJECT FILE D741FEB TEMP2 . 1 PAGE 58 A B C D Current Block Address WADR[6:0] P63 P62s P61 MULTIPEX CURR[3:0] NGTRG[3:0] B YGTRG[3:0] C YGTRG[3:0] LCTADR[3:0] NOLCT[3:0] PATHASEL PATHBSEL PATHCSEL NADR3 A NGTRG[3:0] WADR[6:3] RDADR[3:0] NADR[3:0] NADR2 NADR1 BADR[3:0] Q[3:0] Other Q[3:0] PATHASEL SELB WRENA SELC RST NADR0 WRENA FDCE NBC- CLK D ENAREG Q D ENAREG CE CLK D FDCE CLK Q DATA RST Q RST 3 INV WADR4 INV OBUF WADR3 INV OBUF WADR2 INV OBUF WADR1 INV OBUF WADR0 INV OBUF INV OBUF OPAD P134 OPAD P138 P145 OPAD P156 OPAD P163 OPAD P167 OPAD P177 LCTADR2 LCTADR1 DDO1 CE CLK CLK LCTADR0 DDO0 P64 2 C WADR2 CO2 OPAD OBUF P124 WADR1 CO1 NADR3 NADR3 WADR0 CO0 NADR2 NADR2 NADR1 NADR1 NADR0 NADR0 RST W[2:0] W[2:0] RST CLK OBUF OPAD LCTADR[3:0] LCTADR3 GCOUNT3 To LED'S WADR5 WADR3 RST NGDATA LED8 RST WADR6 DO0 CE NOR2 WADR[6:0] DI0 WADR4 DDO2 DATA RST CLR RST DO1 WADR5 DDO3 C CLR DI1 CLR CE CLK C ENAREG DO2 1 WADR6 RST Choose NBASELVS for Vijay's Proirity scheme. Choose NBASELBB FDCEfor Ben's Proirity scheme. INV DI2 NBC- ENAREG 2 DO3 SELA CLK NBC- DI3 NADR[3:0] WRADR[3:0] OUT[3:0] SELA W[6:3] W[3:0] WADR[6:3] 1 W[6:0] REG3 NBASELVS ENA CLK 3 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Next Block Address Generator SCA Controller CMS CSC Electronics BY PARENT PAGE VKS DATE 8-6-2000_10:46 PROJECT 40 D741FEB FILE PAGE NBADR . 1 60 A B FDCE FDCE C FDCE FDCE FDCE D FDCE FDCE 1 1 WADR4 ENAREG ENB BUF D Q D ENB CE CLK X1 ENB CLK Y1 ENB CE CLK C D ENB CLK C CLR CLR RST RST D X4 ENB D ENB CE CLK C CLR D ENB CE CLK C D RST D ENB C CLR CLK C FDCE Y6 Q ENB CE CLK C CLR RST CLK FDCE CE D Y7 Q CE C CLR CLR RST RST X7 Q CE RST Y5 Q CLR D CLR RST FDCE Y4 ENB C CLR Q X6 Q CE CLK C RST FDCE Y3 D ENB CLR Q X5 Q CE CLK C RST FDCE Y2 Q CE CLR Q CE D CLK C FDCE Q X3 ENB RST FDCE D Q CE CLR RST RST WADR3 D CLK C CLR X2 ENB CE CLK C Q RST 2 2 WADR4 X4 WADR4 XOR2 FD X1 X1 XOR2 X5 D XOR2 WADR3 X2 CLK Y1 X6 XOR2 Q JUMP NOR2 OR4 C XOR2 X3 FD X7 3 3 REVERT XOR2 D CHECKENB WADR3 Q REVERTED OR2 AND2 Y4 CLK C XOR2 Y1 Y5 VCC COUNT[7:0] Q[7:0] XOR2 VCC Y6 OR4 CE CLK Y3 CEO C D COUNT6 TC Q CHECKENB C CLR CLR Y7 FDC COUNT6 CB8CE XOR2 Y2 JUMP JUMP XOR2 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Next Block Address Generator SCA Controller CMS CSC Electronics BY PARENT PAGE VKS DATE 8-5-2000_11:10 PROJECT 40 D741FEB FILE PAGE NBADR . 2 60A A B C D 1 1 NOLCT[3:0] NGTRG[3:0] CURR[3:0] OUT[3:0] YGTRG[3:0] M2_1 NOLCT3 D0 YGTRG3 D1 M2_1 O M2_1 D0 NGTRG3 O D0 D1 CURR3 S0 O OUT3 D1 S0 S0 2 M2_1 NOLCT2 D0 YGTRG2 D1 M2_1 M2_1 D0 O NGTRG2 O D0 D1 CURR2 S0 O OUT2 O OUT1 O OUT0 2 D1 S0 S0 M2_1 NOLCT1 D0 YGTRG1 D1 M2_1 O M2_1 D0 NGTRG1 O D0 D1 CURR1 S0 D1 S0 S0 3 SELC M2_1 NOLCT0 D0 YGTRG0 D1 M2_1 O S0 NGTRG0 SELB O D0 D1 S0 3 M2_1 D0 CURR0 SELA D1 S0 NOTE: LOW ON SEL WILL PASS THROUGH D0 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Multiplexer SCA Controller CMS CSC Electronics BY PARENT PAGE VKS DATE 3-9-2000_9:09 60 PROJECT D741FEB FILE PAGE MULTIPEX. 1 61 A B DATA O D D1 CLK NAND2 WRADR[3:0] S0 1 GND LRST RST FD D C 2 D0 Q0 D1 Q1 D2 Q2 D3 Q3 RAM16X1D ENA D CLK WRADR[3:0] ADR3 RAM16X1D ENA OR2 BADR1 WRADR3 OR2 BADR[3:0] RDADR1 A0 A1 P0 A2 P1 A3 P2 A4 P3 A5 P4 A6 P5 A7 P6 A8 P7 A9 P8 AA P9 AB PA AC PB AD PC AE PD PE PF PRIO0 PRIO1 PRIO2 PRIO3 PRIO4 PRIO5 PRIO6 PRIO7 PRIO8 PRIO9 PRIOA PRIOB PRIOC PRIOD PRIOE PRIOF RDADR2 RDADR[3:0] RDADR3 174 WEST 18TH AVE, COLUMBUS OH 43210 NADR1 DPRA1 RDADR2 DPRA2 RDADR[3:0] DPRA3 NADR2 INV RDADR3 D0 Q0 NADR3 D1 Q1 D2 Q2 D3 DATA Q0 RST Q1 WRENA Q2 CLK AND2B1 Q3 TITLE Q3 NBCBUF Q0 Q1 PRIOF AND5B5 T Q3 Q[3:0] NADR[3:0] RDADR0 NADR0 RDADR1 NADR1 UP RDADR2 NADR2 L RDADR3 NADR3 RDADR[3:0] CE CEO C TC CLR Select Next Block Address SCA Controller CMS CSC Electronics BUFT4 Q2 4 Blocks 9,11,13,15 are always marked busy. GND PHYSICS DEPARTMENT ELECTRONICS LAB NADR0 RDADR1 CB4VJ DATA THE OHIO STATE UNIVERSITY T RDADR0 DPRA0 INV 3 NADR[3:0] BUFT4 A3 GND 4 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUTA OUTB OUTC OUTD OUTE PRIO2 VCC BADR3 RDADR0 PRENCDVS OUT2 DPO A2 WRADR3 P65 OR2 55FF A1 WRADR2 WRADR2 ADR3 NADR3 SPO A0 WRADR1 OR2 BADR2 NADR2 WCLK WRADR0 3 ADR2 NADR1 INV VKS1 WE CLK WRADR[3:0] WRADR1 T RDADR3 RDADR[3:0] 2 NADR0 RDADR2 D ADR1 P U DPRA3 WRADR0 BADR0 L P L U U P NADR[3:0] RDADR1 DPRA2 WRADR[3:0] ADR0 PRIO1 INV RDADR3 RDADR[3:0] L P L U U P BUFT4 RDADR0 DPRA1 RDADR2 L L U P P U OUT1 DPO DPRA0 TC INV L L U P 55FF A3 RDADR1 CLR NADR3 A2 RDADR0 C NADR2 RDADR3 A1 WRADR3 RST NADR1 RDADR2 SPO A0 WRADR1 CEO NADR0 WCLK WRADR0 WRADR2 CE BUFT4 VKS1 WE ADR1 L U P DPRA3 UP CLK RDADR[3:0] DPRA2 ADR0 ADR2 P U U P L L T INV RDADR1 DPRA1 CB4VJ Q PRIO0 INV RDADR3 RDADR[3:0] P U U P L L NADR[3:0] RDADR0 DPRA0 RDADR2 P U L L U P 1 A3 RDADR0 P U L L OUT0 DPO A2 WRADR3 RDADR1 Low Enables TBUFS A1 WRADR2 Low on SEL Selects D0 SPO A0 WRADR1 D UP BLOCKS: 0,3,5,6,A,C DOWN BLOCKS: 1,2,4,7,8,E WCLK WRADR0 SELA 55FF VKS1 WE OR2 D0 WRADR0 RAM16X1D ENA WRENA M2_1 WRADR3 C Busy=zero available=1 BY VKS PARENT PAGE DATE 4-21-2000_11:57 60 PROJECT FILE D741FEB NBASELVS . 1 PAGE 62 A B C D 55FF RAM16X1D ENA VKS1 WE DATA CLK WRADR[3:0] 1 D WRADR0 WRADR1 WRADR2 WRADR3 RDADR0 A0 NADR[3:0] BUFT4 A1 PRIO3 A2 A3 DPRA1 RDADR2 1 OUT3 DPO DPRA0 RDADR1 RDADR[3:0] SPO WCLK RDADR[3:0] DPRA2 T RDADR0 NADR0 RDADR1 NADR1 RDADR2 NADR2 RDADR3 NADR3 INV RDADR3 DPRA3 INV RAM16X1D ENA VKS1 WE DATA 2 D CLK WRADR[3:0] A0 WRADR1 A1 WRADR2 WRADR3 RDADR0 RDADR[3:0] RDADR1 INV RDADR2 INV SPO 2 WCLK WRADR0 OUT4 DPO NADR[3:0] T A3 RDADR0 RDADR1 INV DPRA0 NADR1 RDADR2 INV NADR2 DPRA1 RDADR[3:0] DPRA2 RDADR3 BUFT4 PRIO4 A2 NADR0 RDADR3 NADR3 DPRA3 55FF RAM16X1D ENA 3 VKS1 DATA D CLK WRADR[3:0] WRADR1 WRADR2 WRADR3 RDADR1 RDADR3 A0 OUT5 DPO PRIO5 A2 T RDADR0 A3 RDADR1 DPRA0 NADR0 INV NADR1 RDADR2 DPRA1 RDADR[3:0] DPRA2 RDADR3 NADR[3:0] BUFT4 A1 INV RDADR2 RDADR[3:0] SPO WCLK WRADR0 RDADR0 3 WE NADR2 INV NADR3 INV DPRA3 55FF 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Select Next Block Address SCA Controller CMS CSC Electronics BY PARENT PAGE VKS DATE 3-9-2000_9:13 60 PROJECT FILE D741FEB 2 62A PAGE NBASELVS. A B C D RAM16X1D ENA VKS1 WE DATA CLK WRADR[3:0] 1 D WRADR0 A0 WRADR1 NADR[3:0] WRADR3 RDADR1 INV NADR0 NADR1 RDADR1 DPRA1 RDADR3 T RDADR0 A3 DPRA0 INV BUFT4 PRIO6 A2 RDADR0 RDADR2 1 OUT6 DPO A1 WRADR2 RDADR[3:0] SPO WCLK RDADR[3:0] DPRA2 RDADR2 INV NADR2 RDADR3 INV NADR3 DPRA3 55FF RAM16X1D ENA DATA 2 D CLK WRADR[3:0] WRADR0 WRADR1 WRADR2 WRADR3 RDADR0 RDADR1 SPO 2 WCLK A0 OUT7 DPO NADR[3:0] BUFT4 A1 PRIO7 A2 T RDADR0 A3 RDADR1 DPRA0 INV NADR0 INV NADR1 RDADR2 DPRA1 RDADR2 RDADR[3:0] VKS1 WE RDADR[3:0] DPRA2 NADR2 RDADR3 NADR3 INV RDADR3 DPRA3 INV 55FF RAM16X1D ENA 3 3 DATA WRADR0 A0 A1 WRADR2 A2 WRADR3 OUT8 DPO NADR[3:0] PRIO8 BUFT4 T RDADR0 A3 NADR0 RDADR1 DPRA0 RDADR1 RDADR[3:0] WCLK WRADR1 RDADR0 RDADR2 SPO D CLK WRADR[3:0] VKS1 WE RDADR2 DPRA1 INV RDADR[3:0] DPRA2 NADR1 INV NADR2 RDADR3 NADR3 INV RDADR3 DPRA3 INV 55FF 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Select Next Block Address SCA Controller CMS CSC Electronics BY VKS PARENT PAGE DATE 3-9-2000_9:14 60 PROJECT FILE D741FEB 3 62B PAGE NBASELVS. A B C D RAM16X1D ENA DATA D CLK WRADR[3:0] 1 WRADR0 WRADR1 WRADR2 WRADR3 RDADR0 A0 OUT9 DPO 1 NADR[3:0] BUFT4 A1 PRIO9 A2 A3 T RDADR0 NADR0 RDADR1 NADR1 RDADR2 DPRA1 RDADR2 RDADR3 SPO WCLK DPRA0 RDADR1 RDADR[3:0] VKS1 WE RDADR[3:0] DPRA2 RDADR3 INV NADR2 INV NADR3 INV DPRA3 INV 55FF RAM16X1D ENA DATA 2 D CLK WRADR[3:0] A0 WRADR1 A1 WRADR3 RDADR0 SPO 2 WCLK WRADR0 WRADR2 RDADR[3:0] VKS1 WE OUTA DPO NADR[3:0] PRIOA A2 RDADR0 A3 INV RDADR2 INV RDADR3 INV DPRA1 RDADR[3:0] DPRA2 NADR0 INV NADR1 RDADR2 INV NADR2 RDADR3 INV NADR3 RDADR1 DPRA0 RDADR1 BUFT4 T DPRA3 55FF RAM16X1D ENA 3 DATA WRADR0 WRADR1 WRADR2 WRADR3 RDADR0 RDADR[3:0] 3 SPO D CLK WRADR[3:0] VKS1 WE WCLK A0 OUTB DPO NADR[3:0] PRIOB A2 RDADR1 RDADR2 INV T RDADR0 A3 DPRA0 INV BUFT4 A1 DPRA1 RDADR[3:0] DPRA2 NADR0 RDADR1 INV NADR1 RDADR2 INV NADR2 RDADR3 NADR3 INV RDADR3 DPRA3 INV 55FF 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Select Next Block Address SCA Controller CMS CSC Electronics BY PARENT PAGE VKS DATE 3-9-2000_9:14 60 PROJECT D741FEB FILE PAGE NBASELVS . 4 62C A B C D RAM16X1D ENA DATA 1 D CLK WRADR[3:0] WRADR0 WRADR1 WRADR2 WRADR3 RDADR0 RDADR1 RDADR3 SPO 1 WCLK A0 OUTC DPO PRIOC A2 NADR[3:0] BUFT4 A1 T RDADR0 A3 RDADR1 DPRA0 INV NADR0 INV NADR1 RDADR2 DPRA1 RDADR2 RDADR[3:0] VKS1 WE RDADR[3:0] DPRA2 RDADR3 INV NADR2 INV NADR3 INV DPRA3 INV 55FF RAM16X1D ENA DATA 2 D CLK WRADR[3:0] WRADR0 WRADR1 WRADR2 WRADR3 RDADR0 2 SPO WCLK A0 OUTD DPO NADR[3:0] PRIOD A2 INV RDADR3 INV T RDADR0 A3 NADR0 RDADR1 DPRA1 RDADR2 BUFT4 A1 DPRA0 RDADR1 RDADR[3:0] VKS1 WE RDADR[3:0] DPRA2 NADR1 RDADR2 INV NADR2 RDADR3 INV NADR3 INV DPRA3 INV 55FF RAM16X1D ENA 3 DATA D CLK WRADR[3:0] WRADR0 WRADR1 WRADR2 WRADR3 RDADR0 RDADR[3:0] VKS1 WE 3 SPO WCLK A0 OUTE DPO NADR[3:0] PRIOE A2 INV RDADR2 INV RDADR3 INV T RDADR0 A3 DPRA1 RDADR[3:0] DPRA2 NADR0 INV NADR1 RDADR2 INV NADR2 RDADR3 INV NADR3 RDADR1 DPRA0 RDADR1 BUFT4 A1 INV DPRA3 INV 55FF 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Select Next Block Address SCA Controller CMS CSC Electronics BY PARENT PAGE VKS DATE 3-9-2000_9:14 60 PROJECT FILE D741FEB 62D . 5 PAGE NBASELVS A B C D 1 1 BUFT4 BUFT4 T LRST T INV DI0 DI1 VCC DI2 GND DI3 2 2 W[3:0] and DO[3:0] and DDO[3:0] go out of block W[3:0] D0 CE C C FD4VJ3 W0 Q0 D1 Q1 D2 Q2 D3 Q3 400ns LCT latency 800ns LCT latency OFDX4T W1 IBUF W2 IBUF W3 IBUF IBUF CE C DO0 C DO1 C DO2 C DO3 CE C D0 Q0 D1 Q1 D2 Q2 D3 Q3 FB0 FB1 FB2 FB3 CE CE C Must be reset to ZERO! FD4VJ1 C D0 Q0 D1 Q1 D2 Q2 D3 Q3 FC1 FC2 FC3 CE CE C FD4CE FC0 C CLR C D0 Q0 D1 Q1 D2 Q2 D3 Q3 DDO0 DDO1 DDO2 DDO3 CE C CLR CLR FD 3 3 LRST RST D CLK Q C 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE LCT Latency Register SCA Controller CMS CSC Electronics BY VKS PARENT PAGE 60 DATE PROJECT D741FEB FILE 4-21-2000_11:57 PAGE REG3. 1 63 A B C D UP LRST Will count 0 1 3 2 6 7 5 4 when up is high Will count 4 5 7 6 2 3 1 0 when up is low SPCS2 CO2 CO1 CO1 CO2 1 AND5B4 1 UP W[2:0] LRST CO0 SPCS1 UP AND5B4 CO2 CO0 LRST AND5B3 OFDT GND CO1 CO2 CO0A CO1 CO0B LRST CO0C D0 VOTE T Q D CO0 W0 Q C IBUF D1 D2 C UP CO1 OR6 AND5B3 CO2 LRST CO1 UP AND4B3 2 CO2 2 UP CO[2:0] RST CO0 AND4B1 UP LRST CO2 AND4B2 CO2 CO1A UP CO1B LRST CO1C OR3 CO1 OFDT GND CO0 AND4B2 D0 VOTE T Q D CO1 W1 Q C IBUF D1 D2 C CO0 LRST 3 3 AND3B2 SPCS2 CO1 CO0 CO2 GND UP CO0 AND5B4 CO2B UP CO2C VOTE Q CO2 W2 Q D CO2 CO0 CLK D2 C CO0 NADR2 UP ENA XOR2 NADR1 LRST CO1 UP1 CO2 Q UP INV CE CLK NADR0 AND4B3 LRST D XOR2 AND4B2 CO0 FDCE NADR3 AND5B5 CO1 LRST C IBUF D1 SPCS1 CO1 CO2 D0 OR5 LRST UP 4 CO2A CO1 OFDT T CLR ENA1 OR2 UP XOR2 AND2B1 CO0 RST AND3B1 AND4B3 CO2 C CO1 RESET AND4B1 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE GREY COUNTER SCA Controller CMS CSC Electronics BY VKS PARENT PAGE 60 DATE PROJECT FILE 6-12-2000_15:44 D741FEB GCOUNT3 . 1 PAGE 64 4 A B C D UP LRST UP SPCS2 CO1 CO2 CO2 CO2 CO1 CO0 UP CO1 LRST LRST 1 AND5B4 CO0 SPCS1 UP FD D SPCS1 1 C AND5B2 AND5B4 CO0 CO1 CO2 CO0 LRST CO2 AND5B3 FD CO1 UP CO0B CO1 CO2 LRST LRST D Q SPCS2 C AND5B4 UP CO1 OR6 AND5B3 CO2 FD LRST CO1 UP AND4B3 2 Q LRST D Q RESET CO2 2 UP C RST CO0 AND4B1 FD UP RST LRST D Q LRST CO2 CO0 CLK C AND4B2 CO2 CO1B UP D AND4B2 NADR1 LRST NADR0 AND3B2 Q INV ENA XOR2 CO0 3 UP2 NADR2 OR3 CO1 FDCE NADR3 LRST CE XOR2 C CLR 3 XOR2 SPCS2 RST CO1 CO0 CO2 UP CO0 CLK CO0 AND5B4 CO1 CO2B CO2 CO1 UP UP OR5 LRST CO1 CO2 CO0 CO2 ENA2 OR2 UP AND2B1 CO0 AND5B5 CO1 CO1 LRST 4 AND4B3 CO2 SPCS1 UP RESET AND4B1 UP 4 AND4B2 LRST CO0 AND4B3 LRST AND3B1 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE GREY COUNTER SCA Controller CMS CSC Electronics BY VKS PARENT PAGE 60 DATE PROJECT FILE 7-17-2000_10:46 D741FEB GCOUNT3 . 2 PAGE 64A A B C D UP LRST SPCS2 CO1 CO2 CO2 CO1 1 AND5B4 1 UP LRST CO0 SPCS1 UP AND5B4 CO1 CO2 CO0 LRST CO0C CO2 AND5B3 CO1 LRST UP CO1 OR6 AND5B3 CO2 LRST CO1 UP AND4B3 2 CO2 2 UP RST CO0 AND4B1 UP LRST CO2 CO0 AND4B2 CO2 CO1C UP FDCE NADR3 NADR2 D LRST OR3 CO1 AND4B2 NADR1 CO0 CE CLK D0 UP2 VOTE Q UP D1 UP1 C NADR0 LRST 3 XOR2 UP3 Q INV ENA XOR2 D2 CLR XOR2 3 RST AND3B2 SPCS2 CO1 CO0 CO2 CO0 UP CO0 CO1 AND5B4 CO2C CO2 UP CO1 AND4B3 UP CO1 CO2 CO0 4 CO2 VOTE Q ENA D1 ENA1 D2 RESET AND4B1 CO1 LRST AND2B1 CO1 AND5B5 D0 ENA2 OR2 UP CO0 SPCS1 UP ENA3 CO2 OR5 LRST UP 4 AND4B2 LRST CO0 AND4B3 LRST AND3B1 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE GREY COUNTER SCA Controller CMS CSC Electronics BY VKS PARENT PAGE 60 DATE PROJECT FILE 6-12-2000_15:44 D741FEB GCOUNT3 . 3 PAGE 64B A B C D A8 P8 A4567 1 A0 P0 1 A0123 INV A1 A0 NAND3 A9 A8 P1 NAND2B1 2 AB AA A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2 A1 A0 A89AB A3 A2 A1 A0 A4567 NAND3 AA A9 A8 PA A4567 AND3B2 P3 A0123 NAND3 AB AA A9 A8 NAND4B3 AND4B4 A0123 A0123 P2 NAND3B2 AND4B4 P9 A4567 AND2B1 A4 PB A4567 A0123 P4 A0123 2 AND4B3 NAND3 AND4B4 NAND2 AC A89AB A5 A4 A0123 PC A4567 P5 A0123 AND2B1 NAND4 NAND2 3 AD AC A6 A5 A4 A89AB AND2B1 P6 A0123 AND3B2 3 A0123 NAND2 NAND4 AE AD AC A7 A6 A5 A4 PD A4567 A89AB AND3B2 P7 PE A4567 A0123 A0123 AE AD AC NAND2 AND4B3 NAND4 A89AB AND3B3 PF A4567 A0123 NAND4 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Priority Encoder SCA Controller CMS CSC Electronics BY GU PARENT PAGE 62 DATE PROJECT D741FEB FILE 4-25-2000_13:37 PAGE PRENCDVS . 1 65 A B C D 1 1 D0 T D1 BUFT 2 D1 2 T D2 Q BUFT D2 T D0 BUFT 3 3 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Voting logic SCA Controller CMS CSC ELECTRONICS BY GU PARENT PAGE 55 DATE PROJECT D741FEB FILE 3-15-2000_15:38 PAGE VOTE . 1 57 A B C D In TRIGREG: synchronize LCT and GTRG signals. Also pipline LCT for 2400ns GTRG latency and generate MATCH signal (dataavail). Then determine MATCHed LCT times relative to BLOCKEND and store in LCT Register DLCT[7:0]. 1 Finally, write DLCT and SCA-BLOCKADR in FIFO3 and pop FIFO1. Free the block in NBADR if NOGTRG. FDC OR2 FDCE FDCE L1 BLOCKEND D D BLOCKEND CLK Q D BLOCKEND CE CLK C L3 Q D BLOCKEND CE CLK C CLR L4 DLLCT L2 OR3 C CLR RST L3 Q CE CLK C CLR RST FDCE L2 Q AND2B1 NO_MATCH 1 CLR RST RST FDCE D SELA 2 AND2B1 OR2 NOGTRG Q PFIFO1 CE CLK 2 P72 C CLR RST PREBLKEND D D CLK LCLKSTAT FDCE BLOCKEND Q SELA C CLR YESGTRG Q DIN[3:0] DLCT[7:0] RST OR3 CLK D Q GCLKSTAT LCT[7:0] F2 RDBUSY BUSY CER CER CEW CEW F3 DLGTRG 3 C DOUT[3:0] TRGDONE POP RST RST CLK CLK NXTRD NXTRD EFLG EFLG TEMPTY EMPTY PUSH F4 LOUT[7:0] DIN[3:0] DOUT[3:0] C CLR FD LCLKSTAT LOUT[7:0] OVERWR OVERWR CE CLK RST FIFO3 GCLKSTAT GCLKSTAT FDC FULL FULL Q[3:0] Q[3:0] 3 CSTAT[2:1] CSTAT[2:1] P71s TRIGREG FDC OR2 LCT BLOCKEND LIN D LCTOUT[7:0] GTRG GIN FDCE Q F1 BLOCKEND AND2B1 LOUT[7:0] CLK CLK C CLR CLK25NS OFD CLK25NS MISS_MATCH D MOVLP BUF RST D NO_MATCH NO_MATCH THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 CLK Q D FDCE BLOCKEND CE CLK C Q CLK C CLR RST RST D BLOCKEND CE CLR F3 F4 Q CE C CLR RST OFD Q CLK RST 4 MATCH MISS_MATCH CLK MATCH RST FDCE F2 D C CLK TITLE Q DAV 4 C Read Control SCA CONTROLLER CMS CSC Electronics BY JRG PARENT PAGE PROJECT D741FEB 40 DATE FILE 8-7-2000_10:01 RDCNTRL . 1 PAGE 70 A B C D FDCE FDC LOOPCONT D MATCH Q D Q CE CLK C CLR CLK C 1 RST CLR 1 RST FDCE FDC D D Q Q CE CLK C CLR C RST CLR FDCE FDC D D Q Delayed LCT Register. Q FD4CE CE CLK CLR C RST CLR 2 FDCE FDC D D Q BLOCKEND Q Q0 D0 Q0 D1 Q1 D1 Q1 D2 Q2 D2 Q2 D3 Q3 D3 Q3 SELA CE DLCT0 DLCT1 DLCT2 2 DLCT3 CE CLK C C CLR C CLR RST CLR C D0 CLK CE CLK DLCT[7:0] FD4CE C RST RST CLR FDCE FDC D D Q CLK The position of STATES on this loop depends on the total GTRG delay relative to LCT, that is the total delay length on page 71s plus the MATCH delay FD4CE Q RST CLR FDCE 3 FDC D0 Q0 D0 Q0 DLCT4 D1 Q1 D1 Q1 DLCT5 D2 Q2 D2 Q2 D3 Q3 D3 Q3 C CLR C FD4CE CE D BLOCKEND CLK Q SELA CE CE Q CLK C CLK DLCT7 CE 3 C CLR D DLCT6 CLR RST RST C CLR C RST CLR FDCE FDC STATEX D D Q FD Q CE CLK STATES D M2_1 D0 Q C D1 BLOCKSEL S0 CLR C RST CLR CLK C O STATES STATEX FDCE FDC 4 D D Q LOOPCONT CLK Q 4 CE C CLR C CLR THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 RST TITLE Read Control SCA CONTROLLER CMS CSC Electronics BY PARENT PAGE GU PROJECT D741FEB 40 DATE FILE 8-7-2000_10:07 PAGE RDCNTRL . 2 70A A B C D LCT REG. LCT is synchronized in DAQMB Global Trigger Synchronized at DAQMB, Matching with pipelined LCT. 1 VCC FDC FD D Q D LLOUT2 CLK CLR FD C GIN AND2B1 GIN2 FD LLOUT4 NO_MATCH GIN1 Q D LOUT1 OR2 LOUT2 LLOUT5 OR3 D OR2 LLOUT3 C LLOUT6 Q OR2 LLOUT7 CLK25NS CLK25NS C LLOUT8 C VCC FDC LLOUT_1 C C PREMATCH LLOUT9 LLOUTA MATCH Q LLOUTC C CLR MATCH3 OR2 OR3 MATCH2 OVERLAP FDC AND2B1 MATCH_DISABLE AND2 MAT0 AND2 MATCH3 LLOUTE FD LOUT3 LOUT4 LOUT5 LOUT6 2 OR2 LOUT7 LLOUTF MISS_MATCH D PMISS_MATCH AND2B1 OR2 LLOUTD MATCH C LLOUT_2 C CLK VCC GIN1 C D OR2 LLOUTB PMATCH MATCH2 LLOUT0 FD Q MATCH1 MATCH1 AND2 2 D 1 LOUT0 LLOUT1 NO_MATCH Q LLOUT_1 C LOUT[7:0] LLOUT0 Q D CLK C Q OR2 C CLR MISS_MATCH AND2 CB4VJ GND 3 D0 Q0 D1 Q1 D2 Q2 D3 Q3 OVERLAP 3 UP SR8CE_R MATCH MATO0 SLI CLK MAT[7:0] XOR2 CEO TC C CLR Q[7:0] RST VCC VCC Q[7:0] CE CE MAT0 SLI MATO[7:0] CLK L SR8CE_R CE CLK C CLR C CLR RST RST 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Trigger & LCT Register SCA Controller CMS CSC Electonics BY PARENT PAGE JRG&GU DATE 70 PROJECT D741FEB FILE 8-6-2000_9:43 TRIGREG . 1 PAGE 71 A B C D First part of LCT Pipline, 875ns. CLK25NS FDC 1 LIN D FDC Q D C D C D FDC D FDC Q D C D FDC D FDC Q D C D C CLR FDC D C CLR FDC Q D C D C CLR FDC D C CLR D C D Q C C CLR FDC Q D 3 Q C CLR CLR FDC Q D Q HALFWAY C C CLR CLR CLR C D Q C D FDC Q D FDC Q CLR FDC FDC Q FDC Q CLR C CLR CLR C D 2 Q C D FDC Q D FDC Q CLR FDC Q FDC Q CLR C CLR CLR C D Q C D FDC Q D FDC Q CLR FDC Q Q CLR C CLR FDC D FDC C CLR CLR C D 1 Q C FDC Q CLR Q D CLR C FDC Q C CLR D CLR Q C FDC Q FDC D CLR C CLR FDC Q C FDC Q C CLR D CLR FDC Q FDC Q C CLR FDC D 3 D C CLR 2 FDC Q CLR CLR RST BUF RST 4 RST BUF THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 RST BUF TITLE Trigger & LCT Register SCA Controller CMS CSC Electonics BUF BY 4 PARENT PAGE JRG PROJECT D741FEB 70 DATE FILE 4-21-2000_15:52 PAGE TRIGREG . 2 71A A B C D Second part of LCT Pipline, 1050ns. CLK25NS FDC 1 HALFWAY D FDC Q D C D C D FDC D FDC Q D C D FDC D C CLR FDC Q D C FDC Q D C CLR C CLR FDC D D C FDC Q D C CLR C CLR FDC D D FDC C D Q C C CLR D CLR CLR FDC Q D C FDC C CLR FDC FDC D Q D D Q Q C C CLR 3 Q CLR C C CLR CLR Q C D CLR Q D FDC Q C FDC Q FDC Q CLR D CLR CLR C FDC Q 2 Q C D CLR C CLR FDC Q D D FDC Q C FDC Q FDC Q CLR D CLR CLR C FDC Q Q C D CLR C CLR FDC Q D D FDC Q C FDC Q FDC Q CLR D CLR CLR C FDC Q C D CLR C CLR Q 1 Q FDC D FDC D CLR C D FDC Q C FDC Q CLR Q D CLR C FDC Q C CLR D CLR Q C FDC Q FDC D CLR C CLR FDC Q C FDC Q C CLR D CLR FDC Q FDC Q C CLR FDC D 3 D C CLR 2 FDC Q CLR CLR RST BUF RST 4 RST RST BUF THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 BUF TITLE Trigger & LCT Register SCA Controller CMS CSC Electonics BUF BY HALFWAY2 PARENT PAGE JRG PROJECT D741FEB 70 DATE FILE 4-21-2000_15:54 4 PAGE TRIGREG . 3 71B A B C D Second part of LCT Pipline, 975ns. CLK25NS FDC 1 HALFWAY2 D FDC Q D C FDC Q D C CLR FDC Q C CLR D FDC LLOUTF Q C CLR D FDC Q D C CLR FDC FDC Q D C FDC Q D C CLR FDC Q C CLR D D C CLR C CLR FDC Q D FDC D FDC Q D C FDC Q D C C D D C C CLR LLOUT7 D C CLR CLR CLR FDC FDC FDC FDC FDC C Q D C CLR Q C CLR D Q D C CLR C CLR LLOUT6 Q D Q 3 D FDC Q D FDC Q D FDC Q D Q C CLR LLOUT5 FDC Q D CLR LLOUTB FDC LLOUT1 FDC C CLR D LLOUT0 C FDC Q D Q FDC LLOUT4 3 D C C CLR C CLR C CLR C CLR 2 Q FDC C CLR D CLR LLOUTC D FDC Q C CLR Q LLOUT2 FDC Q CLR D Q CLR FDC Q D C CLR FDC Q FDC Q LLOUTD 2 LLOUT3 LLOUT8 C CLR Q CLR FDC Q 1 D C CLR LLOUTE D FDC Q Q C CLR C CLR CLR LLOUTA FDC D FDC Q D FDC Q D FDC Q D LLOUT_1 C FDC Q D Q FDC LLOUT9 D C C CLR C CLR C CLR Q C CLR CLR C RST CLR RST BUF BUF RST RST THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 LLOUT_2 BUF BUF 4 TITLE Trigger & LCT Register SCA Controller CMS CSC Electonics 4 BY PARENT PAGE JRG PROJECT D741FEB 70 DATE FILE 7-18-2000_12:25 PAGE TRIGREG . 4 71C B VCC CE_WR WEA CE_WR CB5CE WA[7:0] WA[4:0] CE DATAIN[15:0] 1 CLKA ADDRA[7:0] DATAIN[15:0] DATAIN[15:0] DIA[15:0] WA5 DOA[15:0] CLK WA[7:0] CLKA ADDRA[7:0] DIA[15:0] WA6 C ENA RSTA DOA[15:0] CLK WA[7:0] ADDRA[7:0] WA7 CE_WR CLK WEA RSTA CLKA Q[4:0] CE_WR ENA DOA[15:0] CLK RAMB4_S16_S16 WEA ENA RSTA 1 D RAMB4_S16_S16 VCC Fifo3 stores LCT timing & SCA block number for blocks with matching triggers. C RAMB4_S16_S16 VCC A DIA[15:0] CLR GND RST ENB CB5CE DATAIN[15:0] RA7 CE_RD CE DOB[15:0] CLKB ADDRB[7:0] DATAIN[15:0] DATAIN[15:0] DIB[15:0] RA5 DATAC[15:0] RSTB CLK RA[7:0] CLKB ADDRB[7:0] DIB[15:0] RA6 C DOB[15:0] CLK RA[7:0] ADDRB[7:0] Q[4:0] ENB DATAB[15:0] RSTB CLKB RA[7:0] WEB ENB DOB[15:0] CLK RA[4:0] WEB DATAA[15:0] RSTB GND GND WEB GND GND GND DIB[15:0] CLR 2 2 GND GND GND Q[3:0] CB4VJ D0 Q0 D1 Q1 GND D2 Q2 D3 Q3 Q0 PRE Q2 D Q3 CE_WR LAST C CE_WR L CE CLK AND2B1 CE_RD UP XOR2 EMPTY Q OR2 AND2 AND4B3 CE_WR FDP RST Q1 EMPTAND3B2 CEO C INV FDC TC D CLR LAST Q AND2 OR3 3 C DATAIN[15:0] DIN[3:0] LCT[7:0] DIN3 CLR AND3B1 DIN2 BUF DATAIN14 DIN1 BUF DATAIN13 DIN0 BUF DATAIN12 OVERWR BUF DATAIN11 CE_WR BUF DATAIN10 LAST LCT7 LCT6 LCT5 LCT4 LCT3 LCT2 LCT1 LCT0 4 AND4B1 FDC D CE_RD Q FULL OR2 BUF DATAIN9 BUF DATAIN8 BUF DATAIN7 BUF DATAIN6 BUF DATAIN5 CEW BUF DATAIN4 PUSH BUF DATAIN3 FULL BUF DATAIN2 CER GCLKSTAT LCLKSTAT 3 DATAIN15 AND2 EMPT- AND2B1 CLK C CLR NXTRD BUSY AND2B1 FULL_1 CE_WR 4 GND BUF DATAIN1 POP BUF DATAIN0 EMPTY AND3B1 CE_RD BUF AND3B1 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Fifo3 SCA Master CMS CSC Electronics BY PARENT PAGE VKS DATE 7-20-2000_8:40 PROJECT 70 FILE D741FEB FIFO3 . 1 PAGE 72 A B C D 1 1 DATAA[15:0] DATAB[15:0] DATAC[15:0] DATAA15 DATAB15 DATAC15 DATAA14 DATAB14 DATAC14 DATAA13 DATAB13 DATAC13 P57 VOTE D0 DATAB12 DATAC12 DATAA11 DATAB11 DATAC11 Q DOUT3 LOUT[7:0] DATAA[15:0] DATAB[15:0] D1 DATAC[15:0] D2 DATAA10 DATAB10 D1 DATAA9 D0 D2 DATAB9 Q D1 DATAA8 D0 D2 DATAB8 D0 VOTE Q DATAA7 D2 DATAB7 VOTE DATAC7 Q EFLG D1 DATAA6 D2 DATAB6 DATAB2 DATAC2 DATAA1 3 DATAB1 DATAC1 D0 VOTE DATAC6 Q CSTAT2 D1 DATAA5 D2 DATAB5 D0 VOTE DATAC5 Q LOUT6 VOTE Q LOUT5 D1 2 D2 DOUT0 D1 D0 Q DOUT1 DATAC8 Q VOTE D1 D2 VOTE LOUT7 Q DOUT2 DATAC9 D0 VOTE D1 D2 VOTE CSTAT[2:1] DATAA2 D0 DATAC10 D0 2 DATAA12 DOUT[3:0] CSTAT1 D1 DATAA4 D2 DATAB4 DATAC4 DATAA3 DATAB3 DATAC3 D0 VOTE LOUT4 Q D1 D2 D0 VOTE LOUT3 Q D1 D2 D0 VOTE LOUT2 Q D1 D2 D0 VOTE 3 LOUT1 Q D1 D2 D0 VOTE LOUT0 Q D1 D2 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE LCT voting SCA Master CMS CSC Electronics BY PARENT PAGE GU DATE 4-21-2000_12:22 PROJECT 70 FILE D741FEB FIFO3 . 2 PAGE 72A A B C D BUSY FDP RST READ D BUSY_1 RDENA RDENA Q INV TC EFLG CLK FDC_1 C JB1 DONE CE5 DONE_1 D D DDONE VCC D AND5B4 D CLK CLK C Q BUFE4 DEFLG CLR CLR CLR DATAOUT6 RADR0 START C CLR TC READ RST OR2 FDC FDC AND4B3 RDENA D CLK PSH-3 Q D CLK C PSH-2 Q CLK C CLR D PSH-1 Q CLK C CLR D Q PSH RADR1 ADR4 RADR2 BUF ADR5 RADR3 BUF ADR6 DONE CLR CLR DEFLG FDC D FDC Q D FDC Q D D G[2:0] C LASTWORD GCOUNT2E CLK CLK C CLK C CLR CLK C CLR CLR FDCE_1 G2 CO2 OR2 C CLR CO1 G1 D CO0 G0 CE RST C 3 FDC XLOAD D FDC Q D FDC Q D START START RADR1 UPSIE UP RST RST CLK CLK D CE CE Q INV XOR2 CLK C CLR CLK C RADR3 C CLR XOR2 CLR XOR2 BUSY_1 CLK DEFLG OR2B1 FDC PSH D Q TC PSH_1 XCHK AND2B1 C FDC FDC_1 PSH CLK FDCE_1 CLR RST D Q C Q C CLR CLR RST THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 RST START LE LCTBN0 OR3 LCTB0 D TC CE CLK C XCHECK causeschecksum to be sent. RST It goes true on OE5-==OEN4- in MUX Changed delay time of PUSH and LASTWORD to MBRD Changed from 16 samples to 8 samples, needs checked 12/11/98 TITLE TC_1 SCA Readout SCA Controller CMS CSC Electronics Q ADR0 ADR[2:0] CLR CB4CEO ADO[3:0] FDCE RST 4 AND3B1 TC_1 XCHECK CLK CLK D C GE READ ADR1 3 TC RST Q CLR RADR0 RADR2 CLK ADR2 CLR P81 AND4B4 Q CE G0 DIGIDONE Q CLR FDCE_1 AND3B1 G1 Q C RST AND4B2 RST FDC DONE_1 2 CLK OR2 D Q OR2 PUSH G2 LAST D AND2 OR2 C FDC_1 BUF DEFLG LCTBN0 FDC ADR[6:0] ADR3 BUF EDONE START OR2 FDC DATAOUT5 DATAOUT4 Q BUSY CLK START RST DATAOUT7 FDC_1 Q RST C DATAOUT[7:4] E RADR[3:0] YES C C50 2 ERRLOAD BUSY_1 RST D AND2 1 C CLR RST Q CE6 CLR BUF FDC FDC C RST OR2 BUSY Q DDONE Q CE CLR RST FDC AND2 DONE D C50 C OR2 AND2B1 LDONE FDCE LDONE Q DDONE NAND5B3 DOREAD D CE5 PRE START 1 VCC FDC_1 Q[3:0] AD[3:0] QI[3:0] Q AD0 AD1 AD2 AD3 LAST TC_1 AND2 RDENA CLR CLK CE 4 CEO C TC TC CLR RDENA RST OR2 BY VKS PARENT PAGE DATE 7-18-2000_8:45 40 PROJECT FILE D741FEB READOUT . 1 PAGE 80 A B C D Lct0 is the first time-ordered LCT bin in the block. Lct7 is the last bin in a block. Serialized bits are written to memory lowest bit first! FD8CE 1 LCTBIN[7:0] 1 LCT[7:0] D[7:0] Q[7:0] M8_1E LCT0 D0 LCT1 D1 LCT2 D2 LCT3 D3 LCT4 D4 CSTAT[2:1] LCTREG CSTAT2 CE C CLR O LCT5 EFLG D Q M2_1 LCTREG D0 D5 LCT6 D6 LCT7 D7 AD0 S0 AD1 S1 AD2 S2 VCC FDCE 2 CSTAT1 O SCABLOCK D1 AD3 S0 FD D CLK M8_1E CLR D0 RSTA1 D1 RSTA2 D2 RSTA3 D3 RSTA[3:0] CSTAT2 D4 CSTAT1 D5 ADR5 ADR4 VCC ADR3 D0 Q0 D1 Q1 D2 Q2 D3 Q3 RSTA3 DEFLG D6 RSTA2 VCC ADR6 RSTA1 RSTA0 OVERLAP FD C CLR S0 CLK C PUSH Q C FD C D T DATAOUT15 Q BUFT PUSH SCA BLOCK C Q0 AD0 S0 Q1 AD1 S1 Q2 AD2 S2 Q3 DEFLG E CE CLK EDONE OVERLAP CB4VJ CEO C INV RST TC CLR START LCTBIN[7:0] CE5 D OR2 D[7:0] 2 DATAOUT14 CB4CE SLI S2 FD Q T Q BUFT DEFLG SR8CLE_R GND S[3:0] CLK O D INV GND RST 3 D D7 VCC CE YES DATAOUT13 FD DEFLG RSTA0 T C E C FD4CE XLOAD Q BUFT CE ADR[6:3] DATAOUT[15:0] DATAOUT[7:4] D0 Q0 D1 Q1 D2 Q2 D3 Q3 AND3B2 READ ONE 3 OR2 AND3B2 S1 LCTBN[7:0] AND3B1 UP Q[7:0] START S1 SR8CE_1R CE6 S2 S0 CE CLK AND3B1 LCTBN0 LB0 SLI GE CLK DONE 4 TC CLR RST Multiple overlap monitor Q[7:0] CE CLK C CLR RST AND2B1 CEO C LCTB[7:0] CE OR2 OR2 CE XOR2 SLI Q[7:0] CLR LCTB0 END AND2 LB[7:0] C RST START SR8CE_1R M_OVERLAP AND2 L L C CLR CLK RST INV BUSY_1 4 TC_1 SRE READ START DEFLG DONE OR2B1 AND3B1 DEFLG OR2 AND2B1 OR2 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE SCA Readout SCA Controller CMS CSC Electronics BY PARENT PAGE VKS&G DATE 40 PROJECT FILE 7-18-2000_8:40 D741FEB READOUT. 2 PAGE 80A A B C D UP Will count 0 1 3 2 6 7 5 4 when up is high Will count 4 5 7 6 2 3 1 0 when up is low RST START CO1 CO2 CO1 AND5B4 CO2 1 1 UP RST START CO2 AND5B4 FDCE CO1 UP D START CE RST CO1 Q C OR4 C1O0 C2O0 C3O0 D0 VOTE CO0 Q D1 D2 CLR AND5B4 CO2 UP START CO[2:0] RST 2 2 AND5B2 UP CO0 START CO2 RST CO0 AND5B3 FDCE CO2 UP D RST CE START CO1 Q OR3 C C1O1 C2O1 C3O1 D0 VOTE CE CO1 Q ENACNT START D1 OR2 D2 CLR AND5B3 CO0 RST 3 3 START AND4B3 CO0 CO2 RST START CO2 AND4B2 FDCE CO1 UP ENACNT CLK RST CO1 AND4B3 OR4 UP 4 Q CE C C1O2 C2O2 C3O2 D0 VOTE CO2 Q D1 THE OHIO STATE UNIVERSITY D2 PHYSICS DEPARTMENT ELECTRONICS LAB CLR RST RST D 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE GREY COUNTER SCA Controller CMS CSC Electronics START CO0 START AND5B3 PARENT PAGE UP PROJECT D741FEB 80 RST BY VKS AND3B2 A 4 B C DATE FILE PAGE GCOUNT2E. 1 7-18-2000_8:51 D 81 A B C D UP RST START CO1 CO2 CO1 AND5B4 CO2 1 1 UP RST START CO2 AND5B4 FDCE CO1 UP D START CE RST CO1 Q C2O0 C OR4 CLR AND5B4 CO2 UP START RST 2 2 AND5B2 UP CO0 START CO2 RST CO0 AND5B3 FDCE CO2 UP D RST START CO1 Q C2O1 CE OR3 C CLR AND5B3 CO0 RST 3 3 START AND4B3 CO0 CO2 RST START CO2 AND4B2 FDCE CO1 UP ENACNT CLK RST CO1 AND4B3 OR4 UP 4 Q C2O2 THE OHIO STATE UNIVERSITY CE PHYSICS DEPARTMENT ELECTRONICS LAB C CLR RST RST D 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE GREY COUNTER SCA Controller CMS CSC Electronics START CO0 START AND5B3 PARENT PAGE UP PROJECT D741FEB 80 RST BY VKS AND3B2 A 4 B C DATE FILE PAGE GCOUNT2E. 2 6-12-2000_11:14 D 81A A B C D UP RST START CO1 CO2 CO1 AND5B4 CO2 1 1 UP RST START CO2 AND5B4 FDCE CO1 UP D START CE RST CO1 Q C3O0 C OR4 CLR AND5B4 CO2 UP START RST 2 2 AND5B2 UP CO0 START CO2 RST CO0 AND5B3 FDCE CO2 UP D RST START CO1 Q C3O1 CE OR3 C CLR AND5B3 CO0 RST 3 3 START AND4B3 CO0 CO2 RST START CO2 AND4B2 FDCE CO1 UP ENACNT CLK RST CO1 AND4B3 OR4 UP 4 Q C3O2 THE OHIO STATE UNIVERSITY CE PHYSICS DEPARTMENT ELECTRONICS LAB C CLR RST RST D 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE GREY COUNTER SCA Controller CMS CSC Electronics START CO0 START AND5B3 PARENT PAGE UP PROJECT D741FEB 80 RST BY VKS AND3B2 A 4 B C DATE FILE PAGE GCOUNT2E. 3 6-12-2000_11:14 D 81B A B C JTAG Instruction Decode -------------------------------1 OpCode || 0 || 1 || 2 |||| 3 || 4 || 5 || 6 |||| 7 || 8 || 9 || || 10 || 11 || UPDATE SHIFT Function [OpName] No Operation [NOOP] SCAM Reset [] Check CFEB status, Capture and shift Check CFEB status, shift only Program Comparator DAC [] D BSCAN_VIRTEX UPDATE SHIFT RESET TDI TDO1 INV SEL1 TDOF232 DRCK1 TDOF42 TDO2 TDOF82 TDO1 SEL2 TDO2 DRCK2 BTDI 1 SEL1 DRCK1 SEL2 DRCK2 TDOF92 TDOFAB2 NOR5 Load PRE_BLOCK_END Load COMPARATOR mode and time BUCKEYE mask, default 111111 BUCKEYE shift in/shift out 2 2 P91 P97 INSTRGDC STAT_MON F3 F3 F2 F2 DRCK2 DRCLK STATUS[20:0] TDO TDOF232 F1 JTAGRST BTDI BTDI DRCK1 LSHCK F[16:0] SEL1 SEL1 RAW0 BUF STATUS[20:0] BTDI TDI SEL2 SEL2 SHIFT LSHFT F[16:0] F0 F1 F2 F3 F4 F8 F9 F10 F11 TDO1 UPDATE UPDATE 3 3 P94 LOAD_PREBLK F8 BTDI SEL2 DRCK2 UPDATE JTAGRST LOADPREBLK[3:0] LOADPBLK[3:0] F8 BTDI TDO SEL2 TDOF82 LSHCK UPDATE RST 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE JTAG Signals SCA Controller CMS CSC Electronics BY PARENT PAGE GU&JRG DATE 40 PROJECT FILE 7-14-2000_16:28 D741FEB JTAG . 1 PAGE 90 A B C D P93 1 1 PROGDAC F4 P67 BTDI SEL2 SEL2 DRCK2 LSHCK CDAC_RTN IPAD F4 BTDI DACCLK DACCLK DACDAT DACDAT OBUF DAC_ENB DAC_ENB OBUF P65 OPAD P66 OPAD P68 OBUF TDOF42 TDO OPAD CDAC_RTN IBUF P98 2 2 COMPARATOR UPDATE F9 BTDI SEL2 DRCK2 JTAGRST UPDATE F9 CMODE0 OBUF CMODE1 BTDI CTIME0 SEL2 CTIME1 LSHCK CTIME2 OBUF TDO CMODE0 OPAD P63 CMODE1 OPAD P64 CTIME0 OPAD P55 CTIME1 OPAD P56 CTIME2 OPAD P57 OBUF OBUF TDOF92 OBUF AMPCLK1 RST AMPCLK2 AMPCLK3 AMPCLK4 AMPCLK5 AMPCLK6 3 OPAD P35 OPAD P31 OPAD P42 OPAD P39 OPAD P52 OPAD P48 OBUF OBUF OBUF OBUF OBUF 3 OBUF P99 UPDATE P27 IPAD P33 IPAD P36 IPAD P40 IPAD AMPOUT1 IBUF IBUF IBUF IBUF P46 IPAD P49 IPAD IBUF IBUF AMPOUT2 AMPOUT3 AMPOUT4 AMPOUT5 AMPIN2 AMPSHIFT UPDATE F10 FSEL F11 FSHFT BTDI AMPIN1 AMPIN3 AMPCLK[6:1] AMPCLK[6:1] BTDI SEL2 SEL2 DRCK2 LSHCK JTAGRST RST AMPIN4 AMPIN5 AMPIN[6:1] AMPIN6 AMPIN[6:1] AMPOUT6 AMPOUT[6:1] AMPOUT[6:1] TDO OPAD P34 OPAD P28 OPAD P41 OPAD P38 OPAD P50 OPAD P47 OBUF OBUF OBUF OBUF OBUF OBUF TDOFAB2 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE JTAG Signals SCA Controller CMS CSC Electronics BY GU PARENT PAGE DATE 40 PROJECT FILE 10-2-2000_12:32 D741FEB JTAG . 2 PAGE 90A A B C D 8 Bit Instruction Register FDCE BTDI 1 D SEL1 decode first 16 OpCodes (4 bits) FD Q RAW7 D Q CE LSHCK C C CLR D4 D0 D3 D0 D1 D0 D1 F16 D2 D2 FDCE D GND Q D Q D6 F0 D0 D4 AND5B5 D3 D1 CE C F1 D2 D4 D FD Q RAW5 D D1 Q D5 C CLR FDCE F2 D Q D D2 D4 D4 Q AND5B4 D3 D1 D4 F3 D2 FDCE D FD Q RAW3 D Q D3 F4 D2 FDCE D FD Q RAW2 D1 D4 C CLR D D4 AND5B4 AND5B3 D3 D0 Q F5 C CLR D4 AND5B3 FDCE D D1 D4 C FD Q RAW1 D Q D2 D3 D1 D2 D0 D1 F6 D4 C CLR D2 FDCE 4 F14 D0 D4 C AND5B2 D1 D3 CE F13 D0 D3 CE 3 D2 D1 D2 F12 D0 D3 C AND5B2 D2 D0 D3 F11 D4 AND5B3 D1 CE AND5B3 D2 D4 CLR 2 D1 D3 C C F10 D0 D2 CE AND5B3 D0 D3 D0 FD RAW4 D3 D1 D2 C 3 D4 AND5B4 D0 CE 2 F9 D1 D3 FDCE AND5B4 D0 D2 C CLR F8 D2 D4 AND5B4 1 D1 D3 D3 FD RAW6 F[16:0] D7 D RAW0 D Q D0 C D[7:0] CLR AND5B2 D0 D0 CE C D3 D1 FD Q AND5B3 D1 F7 D3 D2 D4 D4 AND5B2 F15 4 AND5B1 UPDATE THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE JTAG Instruction Decode SCA Controller CMS CSC ELECTRONICS BY G, G PARENT PAGE 90 DATE PROJECT D741FEB FILE 4-21-2000_14:29 PAGE INSTRGDC . 1 91 A B C D 1 1 CDAC_RTN TDO AND2 BTDI DACDAT AND2 LSHCK SEL2 2 DACCLK 2 F4 AND2 AND2 DAC_ENB INV "DAC" 3 3 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE DAC Programming Logic SCA Controller CMS CSC ELECTRONICS BY GU PARENT PAGE 90 DATE PROJECT D741FEB FILE 3-9-2000_10:10 PAGE PROGDAC . 1 93 A B C D 1 1 FDPE RST BTDI F8 2 LOAD SEL2 LSHCK AND2 FDP PRE D Q RR3 PRE D Q LOADPREBLK3 CE 2 C C FDPE FDP PRE D Q RR2 PRE D Q LOADPREBLK2 Q LOADPREBLK1 CE C C FDPE FDP PRE D Q RR1 PRE D CE C C 3 3 FDPE FDP PRE D Q RR0 PRE D Q LOADPREBLK0 LOADPREBLK[3:0] CE C C F8 UPDATE TDO AND2 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Load Preblk_end SCA Controller CMS CSC Electronics BY PARENT PAGE GU DATE 90 PROJECT D741FEB FILE 7-18-2000_9:04 LOAD_PREBLK . 1 PAGE 94 A B C D Check Status LOGIC (F2), shift test (F3) 1 1 STATUS20 2 LSHFT 2 FDCE NSHFT AND2 D TDI CLKENA OR2 DRCLK AND2 Q STAT20 Q STAT19 Q STAT18 Q STAT17 Q STAT16 CE C CLR GND STATUS19 RST FDCE NSHFT LSHFT AND2 D STAT20 CLKENA OR2 DRCLK AND2 CE C CLR STATUS18 RST FDCE NSHFT LSHFT AND2 D 3 STAT19 CLKENA OR2 DRCLK AND2 3 CE C CLR STATUS17 RST FDCE NSHFT LSHFT AND2 D STAT18 CLKENA OR2 DRCLK AND2 CE C CLR STATUS16 RST FDCE NSHFT LSHFT AND2 D STAT17 CLKENA OR2 DRCLK AND2 4 CE C 4 CLR RST THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE SCAM JTAG Status Monitor SCA Controller CMS CSC Electronics BY GU PARENT PAGE DATE 90 PROJECT FILE 4-21-2000_15:20 D741FEB STAT_MON . 1 PAGE 97 A B C D STATUS7 FDCE NSHFT LSHFT STATUS15 1 2 CLKENA OR2 DRCLK AND2 STATUS20 STATUS19 STATUS18 STATUS17 STATUS16 STATUS15 STATUS14 STATUS13 STATUS12 STATUS11 STATUS10 STATUS9 STATUS8 STATUS7 STATUS6 STATUS5 STATUS4 STATUS3 STATUS2 STATUS1 STATUS0 Q STAT15 STATUS6 CE LSHFT RST CLKENA OR2 DRCLK AND2 Q LSHFT OR2 DRCLK STATUS12 2 C LSHFT DRCLK AND2 Q LSHFT OR2 DRCLK AND2 LSHFT D CLKENA OR2 DRCLK AND2 STATUS9 Q LSHFT CLKENA OR2 DRCLK AND2 Q CLKENA DRCLK STAT9 LSHFT FDCE AND2 D STAT1 FDCE CLKENA OR2 DRCLK AND2 AND2 D CLKENA OR2 AND2 DRCLK C RST NSHFT C RST STAT9 CE CLR STATUS0 CE NSHFT LSHFT D OR2 CLR STATUS8 4 FDCE AND2 AND2 STAT10 NSHFT RST STAT2 FDCE D Q STAT1 C NSHFT C AND2 Q 3 CE CLR STATUS1 RST CLKENA INV DRCLK STAT10 CE NSHFT LSHFT CLKENA OR2 CLR AND2 D AND2 STAT11 STAT2 FDCE AND2 STAT3 FDCE AND2 Q C RST NSHFT C NSHFT CE CLR STATUS2 CE RST OR2 DRCLK STAT11 CLR STATUS10 SEL2 CLKENA AND2 CLKENA STAT3 FDCE D OR2 Q Q C AND2 STAT4 FDCE D STAT4 RST NSHFT C AND2 Q CE CLR STATUS3 RST STAT12 AND2 DRCLK STAT12 CE NSHFT LSHFT D CLKENA OR2 CLR F3 AND2 AND2 D STATUS11 F2 FDCE STAT5 AND2 OR2 C RST NSHFT FDCE CLKENA CE CLR STATUS4 RST STAT13 LSHFT DRCLK STAT13 CLR LSHFT CLKENA OR2 CE NSHFT STAT5 FDCE D STAT6 Q Q C AND2 AND2 D CLKENA STAT6 RST NSHFT C AND2 Q CE CLR FDCE AND2 3 DRCLK STATUS5 RST STAT14 LSHFT CLKENA STAT14 CE NSHFT LSHFT D OR2 CLR STATUS13 LSHFT FDCE AND2 AND2 D STAT15 1 RST STAT7 FDCE AND2 STAT7 C NSHFT C NSHFT Q CE CLR CLR STATUS14 LSHFT DRCLK AND2 D STAT16 STATUS[20:0] CLKENA OR2 AND2 LSHFT D STAT8 FDCE NSHFT AND2 STAT8 Q CE C CLR 4 RST CE STAT0 C CLR RST TDO CLKENA AND2 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE SCAM JTAG Status Monitor SCA Controller CMS CSC Electronics BY GU PARENT PAGE DATE 90 PROJECT D741FEB FILE 4-21-2000_15:20 PAGE STAT_MON . 2 97A A B C D 1 1 RST FDPE BTDI F9 LOAD SEL2 LSHCK AND2 FDP PRE D Q PRE C5 D Q CTIME2 CE C C FDCE D FDC Q C4 D Q CTIME1 CE C C CLR CLR FDPE FDP 2 2 PRE D C3 Q PRE D Q CTIME0 CE C C FDPE FDP PRE D C2 Q PRE D Q CMODE1 CE C C 3 3 FDPE FDP PRE D C1 Q PRE D Q CMODE0 CE C C UPDATE TDO F9 AND2 4 4 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Load Programmable Delay Bits SCA Controller CMS CSC Electronics BY PARENT PAGE GU DATE 90 PROJECT D741FEB FILE 4-21-2000_14:38 COMPARATOR . 1 PAGE 98 A B C D AMPIN[6:1] SHIN AMPIN1 BUF M2_1 D0 O 1 AMPOUT[6:1] AMP1 M2_1 RST M2_1 OAMPOUTP1 FDP FSEL LOAD SEL2 LSHCK AND2 PRE D Q D Q O AMPIN3 O AMPIN4 O AMPIN5 O AMPIN6 D1 AMP2 AMPCLK1 PRE D0 D1 AMPOUT2 SHCLK BTDI S0 D0 AMPOUT1 FDPE AMPIN2 D1 AMPOUT1 1 S0 S0 AMP1 AMP1 AND2 CE AMPP1 AMP2 C C OR2 M2_1 AMPOUTP1 FDPE M2_1 D0 OAMPOUTP2 FDP D0 D1 AMPOUT3 D1 PRE D D AMP3 AMPCLK2 PRE Q Q S0 S0 AMP2 AMPP1 AND2 CE AMPP2 AMP3 C C OR2 M2_1 AMPOUTP2 2 FDPE M2_1 D0 OAMPOUTP3 FDP 2 D0 D1 AMPOUT4 D1 D Q AMP4 AMPCLK3 PRE PRE D Q S0 AMP3 S0 AMPP2 AND2 CE AMPP3 AMP4 C C OR2 M2_1 AMPOUTP3 FDPE M2_1 D0 OAMPOUTP4 FDP D0 D1 AMPOUT5 D1 PRE D Q D AMP5 AMPCLK4 PRE Q S0 S0 AMP4 AMPP3 AND2 CE AMPP4 AMP5 C M2_1 OR2 C AMPOUTP4 D0 O FDPE FDP AMP6 3 PRE D D S0 3 AMPCLK5 PRE Q SHOUT D1 AMPOUT6 Q AMP5 AND2 CE SEL2 C C SHCLK LSHCK FDPE FDP PRE PRE D Q D FSHFT AND3 AMPCLK6 Q AMP6 SEL2 C SHIN AMPCLK[6:1] AND2 CE BTDI AND3 C UPDATE FSEL TDO AND2 4 4 FSHFT OR2 SHOUT AND2 THE OHIO STATE UNIVERSITY PHYSICS DEPARTMENT ELECTRONICS LAB 174 WEST 18TH AVE, COLUMBUS OH 43210 TITLE Load Programmable Delay Bits SCA Controller CMS CSC Electronics BY PARENT PAGE GU DATE 90 PROJECT FILE 4-21-2000_14:39 D741FEB AMPSHIFT . 1 PAGE 99
