An Implementation of a 5.25GHz ... High Data Rate Wireless Applications

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An Implementation of a 5.25GHz Transceiver for
High Data Rate Wireless Applications
by
Nir Matalon
Submitted to the Department of Electrical Engineering
and Computer Science
in partial fulfillment of the requirements for the degree of
Master of Science
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
July 2005
@
Massachusetts Institute of -Technology 2005. All rights reserved.
A u th o r ..............................................................
Department of Electrical Engineering and Computer Science
July 1, 2005
Certified by.
Charles G. Sodini
Professor, Electrical Engineering and Computer Science
Thesis Supervisor
Accepted by ...
Arthur C. Smith
Chairman, Department Committee on Graduate Students
MASSACHUSETTS INS
OF TECHNOLOGY
BARKER
MAR 2 8 2006
LIBRARIES
E
An Implementation of a 5.25GHz Transceiver for High Data
Rate Wireless Applications
by
Nir Matalon
Submitted to the Department of Electrical Engineering and Computer Science
on July 1, 2005, in partial fulfillment of the
requirements for the degree of
Master of Science
Abstract
Recent advances in data conversion and radio frequency circuit design have opened
up a new research area in high data rate transceivers. This work presents a discrete
implementation of a transmitter/receiver pair operating at the 5.25GHz RF band
with a bandwidth of 128MHz. The Design is optimized to meet the specifications of
the Wireless Gigabit LAN (WiGLAN) project, a 1 Gbit/s wireless LAN system that
uses Orthogonal Frequency Division Multiplexing (OFDM) with adaptive modulation.
The complete transceiver along with the MATLAB-implemented DSP algorithms
enable the transmission and reception of raw data at rates of up to 600Mbit/s as
well as the observation of the indoor wireless channel. Through measurement, it was
shown that the use of adaptive modulation significantly increases the data rate due
to the frequency selective nature of the channel.
Thesis Supervisor: Charles G. Sodini
Title: Professor, Electrical Engineering and Computer Science
3
4
Acknowledgments
First and foremost I'd like to thank my advisor, Charlie Sodini, for providing me the
opportunity to take on this project and guiding me along the way. Even when things
didn't appear to be working too well, he always had some interesting suggestion that
helped alleviate any trace of lost motivation.
The next 2 people who deserve mention are Farinaz and Ken for the hours upon
hours spent trying to understand all the small details of the WiGLAN system and
later for helping to fill in holes in my understanding of many of the communications
and signal processing concepts discussed in this work.
The masters of RF circuit and microwave design, Albert, Anh, Lunal, and Todd
always made themselves available to help resolve many of the issues I was attempting
to address over the past 2 years. When it came to PCB design no one had more
knowledge than Mark Spaeth who after slight convincing was always willing to help
out. Also, when overall advice was needed about something and I wasn't sure who to
turn to, the sage, Andy Wang always made himself available. One more person who
definitely deserves mention, and who actually helped build this system by making sure
all the FPGA functions were up in running, is Khoa Nguyen. These measurements
would not have been able to take place without his help.
I want to also thank the remaining members of the Sodini/Lee group for providing
me with an enjoyable work environment, and forcing me to eat lunch at the very
early hour of 12pm. Oh, and of course thanks to many of the folks in the Perrott
and Chandrakasan group (especially Fred, Dave, Denis, Scott and Ethan) who were
always willing to help out when asked.
Finally, I'd like to thank my parents and my brothers for their support and guidance over the past 2 years, and their ability to cope with the fact that coming home
for a weekend is not as easy as it was before. I also want to thank my roommates,
Mehdi, Denis, and Kenny for their hours of valuable entertainment, and indeed I
also thank Jacklyn for slowing down my work pace and forcing me to enjoy my last
semester much more than I had planned.
5
Ok... I think that is everybody. At this point I will stop blabbering so you can
read what you really came here to read.
Cheers!
~Nir
6
Contents
17
1 Introduction
2
1.1
High Data Rate Wireless Transceivers . . . . . . . . . . . . . . . . . .
17
1.2
Orthogonal Frequency Division Multiplexing . . . . . . . . . . . . . .
17
1.3
WLAN Standards .............................
21
1.4
Project Objective .................
..
..
..
...
.
22
23
WiGLAN System Overview
2.1
Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
2.2
Adaptive Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
2.3
Peak-to-Average Power Ratio in OFDM Systems . . . . . . . . . . . .
26
29
3 The WiGLAN Node
3.1
Transceiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . .
29
3.2
Frequency Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
3.3
5.25GHz Transmission Lines . . . . . . . . . . . . . . . . . . . . . . .
32
3.4
Receive Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
3.4.1
Noise Figure and Receiver Sensitivity . . . . . . . . . . . . . .
33
3.4.2
Low Noise Amplifier
. . . . . . . . . . . . . . . . . . . . . . .
35
3.4.3
Downconverting Mixer and Image Reject Filter
. . . . . . . .
37
3.4.4
Receiver Linearity . . . . . . . . . . . . . . . . . . . . . . . . .
38
3.4.5
The Noise-Linearity Tradeoff . . . . . . . . . . . . . . . . . . .
39
. . . . . . . . . . . . . . .
40
. . . . . . . . . . . . . . . . . . . . . . . . . .
40
3.5
The Transmit Chain and Power Amplifier
3.5.1
Transmit Path
7
3.5.3
Power Amplifier Linearity
40
41
3.6
I/Q Imbalance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
3.7
Frequency Synthesis
. . . . . . . . . . . . . . . . . . . . . . . . . . .
46
3.7.1
Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . .
46
3.7.2
LO Distribution . . . . . . . . . . . . . . . . . . . . . . . . . .
47
Data Conversion
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
3.8.1
DACs and ADCs . . . . . . . . . . . . . . . . . . . . . . . . .
48
3.8.2
Clock Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . .
49
Baseband Signal Conditioning . . . . . . . . . . . . . . . . . . . . . .
51
3.9.1
Lowpass Filters . . . . . . . . . . . . . . . . . . . . . . . . . .
51
3.9.2
Variable Gain Amplifiers . . . . . . . . . . . . . . . . . . . . .
51
3.10 Transceiver Measurements . . . . . . . . . . . . . . . . . . . . . . . .
52
Non-Real-Time DSP Implementation
57
4.1
Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
4.2
Channel Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
4.3
The Cyclic Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
4.4
Local Oscillator Phase and Converter Sampling Time Offsets . . . . .
60
4.5
OFDM Symbol Synchronization . . . . . . . . . . . . . . . . . . . . .
62
4.6
Frequency Offset
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
4.6.1
Coarse Correction . . . . . . . . . . . . . . . . . . . . . . . . .
63
4.6.2
Fine Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
Peak-to-Average Power . . . . . . . . . . . . . . . . . . . . . . . . . .
65
3.9
4.7
5
The Power Amplifier
. . . . . . . . . . . . . . . . . . . .
3.8
4
3.5.2
Channel Measurements
5.1
5.2
Measurement Procedure
67
. . . . . . . . . . . . . . . . . . . . . . . . .
67
5.1.1
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
5.1.2
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
5.1.3
Symbol Error Rate . . . . . . . . . . . . . . . . . . . . . . . .
69
Test 1: W ired Channel . . . . . . . . . . . . . . . . . . . . . . . . . .
70
8
6
5.3
Test 2: Input Signal Power Range . . . . . . . . . . . .
70
5.4
Adaptive Modulation over a Wireless Channel . . . . .
71
5.5
Test 3: im . . . . . . . . . . . . . . . . . . . . . . . . .
74
5.6
Test 4: 7m . . . . . . . . . . . . . . . . . . . . . . . . .
74
5.7
Test 5: 4m, Not Line-of-Sight
74
. . . . . . . . . . . . . .
81
Analysis and Conclusions
6.1
Maximizing Data Rate Through Adaptive Modulation
. . . . . .
81
6.2
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . .
84
6.3
Future Research . . . . . . . . . . . . . . . . . . . . . .
. . . . . .
84
A Circuit Schematics and PCB Layout
87
103
B PLL Parameters
B .1 PLL D esign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
B.2 Programming the PLL ..........................
104
105
C Acronyms
9
10
List of Figures
1-1
(a) Time domain representation of OFDM symbols.
(b) Frequency
. . . . . . . . . . . . . . .
19
1-2
OFDM baseband transmitter. . . . . . . . . . . . . . . . . . . . . . .
20
1-3
OFDM baseband receiver.
. . . . . . . . . . . . . . . . . . . . . . . .
20
2-1
A central network controller communicating with various WiGLAN
domain representation of OFDM symbols.
adapters..........................................
24
2-2
Adaptive modulation example. . . . . . . . . . . . . . . . . . . . . . .
25
2-3
An OFDM symbol with inherently large PAPR. . . . . . . . . . . . .
26
3-1
Simplified WiGLAN node schematic.
. . . . . . . . . . . . . . . . . .
30
3-2
LNA configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
3-3
LNA input matching network. . . . . . . . . . . . . . . . . . . . . . .
37
3-4
The IIP3 represents the input power level where the third-order spur
equals the first order tone. . . . . . . . . . . . . . . . . . . . . . . . .
39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
3-5
RF receive path.
3-6
RF transmit path.
3-7
(a) Spectrum of a single transmitted OFDM symbol. (b) The adjacent
channel power ratio measurement. . . . . . . . . . . . . . . . . . . . .
43
3-8
(a) Setup for sideband suppression test. (b) The output signal. . . . .
45
3-9
Sideband suppression plotted against the phase imbalance for different
amplitude imbalance values. . . . . . . . . . . . . . . . . . . . . . . .
3-10 PLL schematic.
46
The frequency divider, PFD and charge pump are
found on chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
47
3-11 Wilkinson power splitter. . . . . . . . . . . . . . . . . . . . . . . . . .
48
3-12 Detailed schematic of the data converter PCB. . . . . . . . . . . . . .
50
3-13 (a) Receiver gain measured from receiver input to VGA output. (b)
Receiver noise figure measured from receiver input to VGA output.
.
52
3-14 Sideband suppression measurements for (a) transmit (spectrum ana-
lyzer) and (b) for receive (MATLAB) . . . . . . . . . . . . . . . . . .
53
3-15 (a) Spectrum of captured sinusoid at 5MHz. (b) Spectrum of captured
sinusoid at 63M Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-16 Photograph of a WiGLAN Node.
54
. . . . . . . . . . . . . . . . . . . .
55
4-1
Block diagram of the measurement setup . . . . . . . . . . . . . . . .
58
4-2
The cyclic prefix must be longer than the delay spread of the channel.
59
4-3
Simplified I/Q transmitter receiver pair.
. . . . . . . . . . . . . . . .
60
4-4
Rotation of received constellation points. . . . . . . . . . . . . . . . .
61
4-5
Samples at the output of the ADC. . . . . . . . . . . . . . . . . . . .
63
4-6
LO frequency offset causes a frequency shift in the baseband OFDM
sym bol.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
Block diagram of the setup.
5-2
(a) Received constellations for a wired channel. (b) Received points
. . . . . . . . . . . . . . . . . . . . . . .
without performing fine phase tracking. . . . . . . . . . . . . . . . . .
5-3
71
72
SNR per bin of a received signal. Bins with SNR over 28dB are considered "used bins". . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-5
68
Measured SNR per bin and received constellations for a wired channel:
(a) PIN of -55dBm. (b) PIN of -33dBm . . . . . . . . . . . . . . . . .
5-4
64
73
Channel Response and received constellations for 1m transmission in
(a) a large room and (b) a laboratory. Magenta represents used bins
while blue represents un-used bins in the channel response. . . . . . .
5-6
75
Channel Response and received constellations for 7m transmission in
(a) a large room and (b) a laboratory . . . . . . . . . . . . . . . . . .
12
76
5-7
Channel Response and received constellations for 4m transmission in
(a) a large room and (b) a laboratory. Laboratory transmission was
not line-of-sight, but through a large lab bench.
. . . . . . . . . . . .
77
5-8
Channel measurements at 4m taken 1 minute apart. . . . . . . . . . .
79
6-1
Waterfall curves plotting the symbol error rate vs. SNR for various
constellation sizes.
6-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
SNR per bin of the received signal over 7m. The horizontal lines represent threshold values that determine which bins are used in different
adaptive modulation schemes. . . . . . . . . . . . . . . . . . . . . . .
83
Schematic: Receiver front-end (RF to IF) . . . . . . . . . . . . . . . .
88
A-2 Schematic: I/Q downconverter and VGAs. . . . . . . . . . . . . . . .
89
A-3 Schematic: Complete transmitter (except PA) . . . . . . . . . . . . .
90
A-4 Schematic: Phased locked loop and LO distribution . . . . . . . . . .
91
A-5 Schematic: Analog-to-digital converters . . . . . . . . . . . . . . . . .
92
A-6 Schematic: Digital-to-analog converters . . . . . . . . . . . . . . . . .
93
Board layout: WiGLAN RF front-end . . . . . . . . . . . . . . . . . .
94
A-8 Board layout: Data converter PCB top metal and silk layers. . . . . .
95
A-9 Board layout: Data converter PCB bottom metal and silk layers.
96
A-10 Bill of materials for RF front-end. . . . . . . . . . . . . . . . . .
97
A-11 Bill of materials for RF front-end, continued. . . . . . . . . . . .
98
A-12 Bill of materials for data converter PCB. . . . . . . . . . . . . .
99
A-13 Bill of materials for data converter PCB, continued. . . . . . . .
100
A-14 Bill of materials for data converter PCB, continued. . . . . . . .
101
A-i
A-7
13
14
List of Tables
3.1
Possible combinations of RF, IF, LO and image frequencies for different
values of D where fLo2
= fIF . . . . . . . . . .
. . . .
.. . . . . . .
31
3.2
R04003 PCB parameters.
. . . . . . . . . . . . . . . . . . . . . . . .
33
3.3
Summary of receiver attributes. . . . . . . . . . . . . . . . . . . . . .
40
3.4
Summary of PA attributes. . . . . . . . . . . . . . . . . . . . . . . . .
44
3.5
Combined performance of AD9753 DAC and AD9480 ADC.
. . . . .
53
5.1
Performance summary for minimum and maximum input power levels.
71
5.2
Performance summary for transmission over im. . . . . . . . . . . . .
75
5.3
Performance summary for transmission over 7m. . . . . . . . . . . . .
76
5.4
Performance summary for transmission over 4m. . . . . . . . . . . . .
77
6.1
Performance analysis for OFDM symbols experiencing SNR/bin plot
. . . . . . . . . . . . . . . . . . . . . . . . . . .
83
. . . . . . . . . . . . . . . . .
103
. . . . . . . . . . . . . . . .
103
B.3 Other PLL parameters . . . . . . . . . . . . . . . . . . . . . . . . . .
104
shown in Figure 6-2.
B.1 PLL design assistant input parameters
B.2 PLL design assistant output parameters
15
16
Chapter 1
Introduction
1.1
High Data Rate Wireless Transceivers
The desire for transmission of high data rate information across wireless channels has
grown immensely over the past decade. Wireless devices available today including
mobile phones, wireless local area networks (WLANs) and Bluetooth radios have realized a wide variety of applications at data rates ranging from 10s of kbit/s to 10s of
Mbit/s. Mobile telephone design strives for large transmit distances, Bluetooth technology enables communication between two close range devices, and wireless LAN
strives to achieve a high data rate wireless link within an office or home environment.
This link is traditionally implemented through a central access point that
communicates with one or more workstations. Due to the large number of applications demanding high speed wireless links, the aspiration for even higher data rates
is prevalent.
1.2
Orthogonal Frequency Division Multiplexing
One type of communication system architecture that has facilitated the increased
transmission data rates involves the use of multiple carriers. To understand how this
approach works, single carrier transmission must first be addressed. In a single carrier
approach, symbols representing a certain number of bits are generated. For high data
17
rate transmission, complex M-Quadrature Amplitude Modulation (QAM) symbols are
used where M represents
log 2 M bits. Traditionally, these symbols are then converted
into an analog waveform and upconverted onto a desired carrier frequency before being
sent to the antenna. In the receiver, the radio-frequency (RF) signal is downconverted
back to baseband, and the symbols are mapped back into bits using some detection
mechanism.
In order to recover the transmitted symbols, the impulse response of the transmitter gT(nT), the channel c(nT), and receiver gR(nT), must be known. The purpose of
the digital receiver (or equalizer) is to reverse the effects of the channel as well as the
analog circuitry. The complete response of the transceiver and the channel, x(nT),
is given by the convolution of these impulse responses:
x(nT)
=
gT(nT) * c(nT)
*
gR(nT)
= 1, n=0
1
0, n:/0
where T is the sample time and
9R(nT) is the impulse response of the receiver
that also includes the equalizer. Equivalently, the Fourier Transform, X(f), must
satisfy:
X(f +
)z=T
(1.2)
In realizable systems, this condition holds when the symbol time, T, is larger than
1 over twice the baseband bandwidth, W [1]:
T >
1
(1.3)
It is therefore observed that the only way to increase the sample rate is by using
a large signal bandwidth.
A significant problem arises when considering the multi-path inherent in wireless
channels. Multi-path can cause inter-symbol interference (ISI) or delayed copies of
18
the transmitted signal to combine at the receiver. Depending on their phase, different
frequency components of these combined signals can add constructively or destructively. A channel attributed with a lot of variation across its frequency band is called
a frequency selective channel.
In order to recover the received data, a relatively
complex receiver must be designed.
One way to ease receiver complexity is to use a multi-carrier approach known as
Orthogonal Frequency Division Multiplexing (OFDM), a data transmission scheme
invented in the early 70s[2].
Multiple lower-rate data streams running in parallel
can be modulated onto different subcarrier frequencies. Instead of utilizing multiple
Digital-to-Analog Converters (DACs), filters, and mixers, the modulation all takes
place in the digital domain before the DACs. The sum of the modulated carriers is
called a single OFDM symbol and it can be implemented using an inverse discrete
fourier transform (IDFT). In the time domain, the OFDM symbol can be viewed
as a sum of time-bounded sinusoids of different amplitudes, frequencies and phases
(Figure 1-la). In the frequency domain, the time-bounded sinusoids map to impulses
convolved with sinc functions (Figure 1-1b).
If all subcarriers within the OFDM
symbol contain an integer number of periods, and if the peak of every sinc function
aligns with the zero crossing of all the others, then inter-carrier interference (ICI) is
avoided, and the symbols can be recovered[3].
NVVWWfVVWN'
(b)
(a)
Figure 1-1: (a) Time domain representation of OFDM symbols. (b) Frequency domain
representation of OFDM symbols.
19
R/n OFDM Symbols/s
R Symbols/s
e
S
S
S
S
S
0
S
S
S
S
Iff
+DAC
L
1% -,I
Figure 1-2: OFDM baseband transmitter.
""
R Symbols/s
/P
""
-
R/n OFDM Symbols/s
444-
4444-
S
S
S
S
S
S
S
S
S
S
DFT
4-
4-
IS IRe
IM
Figure 1-3: OFDM baseband receiver.
20
ADC
- -
The complete block diagram of the baseband OFDM system is shown in Figures 1-2 and 1-3. Complex-valued symbols representing b bits arrive at a rate of R
Symbols/s. The serial to parallel converter sends the symbols to an N-point IDFT
block N symbols at a time. After the output is serialized, OFDM symbols emerge
at a rate of R/N OFDM Symbols/s. The samples of the OFDM symbols are separated into their real (in-phase) and imaginary (quadrature) components before being
sent to the analog transmitter through a pair of digital-to-analog converters. At the
receiver, the reverse operation is performed, and the original symbols are recovered.
Note that the inverse of an IDFT block is a discrete fourier transform (DFT).
The main advantage posed by OFDM is that every subband can be treated independently. As long as the bandwidth of each subband is smaller than the coherence
bandwidth, the channel can be approximated as flat. That is, the impulse response of
the channel for that subband can be given by a single tap[3]. Assuming the channel
response is known for all subbands, the receiver only needs to adjust the gain and
phase of each subband in order to recover the symbols.
1.3
WLAN Standards
Today, the dominant standards in wireless LAN technology are 802.11b, 802.11a, and
802.11g. 802.11b, the most commonly used standard, was ratified in 1999 and has a
maximum raw data rate of 11Mbit/s but can scale back to 5.5 and lMbit/s when the
channel quality is low. It uses the CSMA/CA protocol and operates in the 2.4GHz
band.
802.11a, also ratified in 1999, is the only 1 of the 3 that uses OFDM and operates
in the 5GHz band. The standard requires 52 subcarriers spaced apart by 312.5kHz.
The symbols are generated using different modulation schemes (Binary Phase-Shift
Keying (BPSK), Quadrature Phase Shift Keying (QPSK), 16-QAM, or 64-QAM)
depending on the quality of the wireless channel. The duration of each OFDM symbol
produced by the IDFT is 4ps[3]. It should also be noted that at any given time, all
the bins use the same constellation size.
21
802.11g works similar to 802.11a but operates in the 2.4GHz band similar to
802.11b.
In addition to the above standards with products currently in market, another
standard known as 802.11n uses multiple antennas and strives to achieve transmission
with a minimum data rate of 10OMbit/s. This OFDM standard is currently in its
infancy stages but is expected to become popular as its implementation becomes more
feasible.
1.4
Project Objective
This project focuses on the design and implementation of a wideband transceiver
capable of accommodating signals with bandwidths of up to 128MHz transmitted
in the 5.25GHz radio frequency band. Although the transceiver is designed to be
used for a wide variety of systems, its specifications and its optimizations have been
selected based on the Wireless Gigabit LAN (WiGLAN) project.
This work addresses the many issues involved in the design of the analog front-end
of the WiGLAN transmitter and receiver pair. When designing a wireless transceiver,
certain issues including power consumption, size, and performance are of significant
importance. Henceforth, it is expected that as much of the design as possible will
be integrated on a single chip. Integrated transceivers have significant advantages
because they are smaller, and can be designed to consume very little power. Nevertheless, an integrated transceiver for such a novel, high-speed, wideband system is a
challenge, and must therefore be approached in steps. The purpose of this project is
to design a transceiver on a printed circuit board built out of discrete components.
The primary goal is to create a prototype that will enable observation of the 5GHz
wireless channel. Power consumption and size, though important, are of secondary
concern. There are many issues and design considerations that affect the performance
of a wireless transceiver, and these are addressed in this work. Before diving into the
details of the WiGLAN node, which is the focus of Chapter 3, Chapter 2 will introduce
the WiGLAN system and its specifications.
22
Chapter 2
WiGLAN System Overview
2.1
Specifications
Perhaps one of the most limiting factors facing wireless system and RF circuit designers today is the need to adhere to standards. Though necessary for compatibility,
and facilitation of product development and sales, standards tend to block the paths
to new ideas. Players in industries are more likely to design in accordance with an
existing wireless standard, then to come up with their own.
Today, WLANs are generally used to communicate from a computer to the internet
or to other users in the network. Indoor WLAN, however, should not be limited to
communication between computers exclusively. One can envision a system where data
flows in and out of a central location in a home or an office building. The data can be
transmitted via a wireless channel to the appropriate appliances such as telephones,
television screens, workstations or kitchen appliances. These communicate directly
with one or more access points that are connected via wireline to an exterior network
(Figure 2-1).
The goal of the WiGLAN project is to Design a WLAN that will transmit and
receive information at a raw data rate of 1 Gbit/s. Though the system is implemented
with Orthogonal Frequency Division Multiplexing in a way similar to 802.11a, several
new techniques are employed to further enhance the transmission data rate. These
include wider and more numerous subcarriers, adaptive modulation, and large QAM
23
El
Figure 2-1:
A central network controller communicating with various WiGLAN
adapters.
constellations.
The WiGLAN system transmits and receives at the 5.25GHz center frequency
with a signal bandwidth of roughly 128MHz. This band is consistent with the WLAN
Federal Communications Commission (FCC) spectrum allocation. The 2.4GHz Industrial, Scientific and Medical (ISM) band is avoided due to its already large usage
by the common 802.11b standard. Other bands, such as the one centered around
5.8GHz is avoided due to deficient availability of discrete components. The 128MHz
of bandwidth are selected to meet the 1 Gbit/s specifications as will be explained
shortly. Furthermore, wideband transceiver design poses many interesting research
challenges that are addressed within this work.
It has been shown that at 5.25GHz, an indoor wireless channel's frequency response can be approximated as "flat" for a band of 1MHz [4]. This width was therefore chosen to be that of each subband. As mentioned in Section 1.2 the number
of periods of each subcarrier must be integer, and henceforth the lowest frequency
24
component of the OFDM symbol is 1MHz. To maintain orthogonality, the remaining
bins are located at 2MHz, 3MHz, ... 64MHz and the equivalent negative 1MHzincrement frequencies. The duration of the OFDM symbol is l1s, and therefore an
IDFT operation is performed every lps. At full transmission, each incoming symbol
uses 256-QAM and represents 8 bits. The data rate is calculated:
Rate
~
2.2
128Symbols
ps
8bits
symbol
=
(2.1)
1 Gbit/s
Adaptive Modulation
OFDM systems utilize the frequency selectivity of the wireless channel by treating
each subband separately and undoing the channel effects in each with a single tap.
The frequency selectivity can be further exploited by adapting the number of bits
sent per bin depending on the signal-to-noise ratio (SNR) of that bin. As shown in
Figure 2-2, 256-QAM or 64-QAM constellations are sent in the good channels, while
16-QAM, 4-QAM or nothing are sent in the deep fading channels.
Assuming the
SNR of each bin can be measured, the data rate can be adapted to the quality of the
wireless channel, and throughput maximized. The concept of adaptive modulation
has been explored in the past but primarily in simulation. [5] for example, shows a
method of estimating the channel response and determining constellation allocation.
256 QAM
64 QAM
__
16 QAM
4QAM
128 MHz
Figure 2-2: Adaptive modulation example.
25
2.3
Peak-to-Average Power Ratio in OFDM Systems
Despite their apparent simplicity, OFDM systems introduce issues that are not of
significant concern in single-carrier systems.
One of these is the inherently large
peak-to-average power ratio (PAPR). The total PAPR consists of two components.
The first is the PAPR attributed to the constellation points of a single carrier. When
using quadrature amplitude modulation beyond 4-QAM, the constellation points are
not of equal power. For 256-QAM, the PAPR is 4.2dB[6] (assuming that all points
are equally probable).
This value, however, is quite minuscule compared to the large PAPR introduced
by the use of multiple carriers. Every time the number of carriers is doubled, the peak
power increases by 6dB while the average power increases by 3dB. For 128 subcarriers,
the induced PAPR is 21dB, and the total PAPR is 25.2dB. In practice the PAPR can
be reduced using signal clipping or PAPR reduction algorithms. The real part of a
typical OFDM symbol is plotted in Figure 2-3. The units on the Y-axis are arbitrary
for the purpose of this example.
0
0
200
5
250
sample
Figure 2-3: An OFDM symbol with inherently large PAPR.
Another important metric is the total signal dynamic range, and it is defined by:
26
Peak Power
Signal Dynamic Range = Nois Power
Noise Power
(2.2)
In order to detect 256-QAM in an Additive White Gaussian Noise (AWGN) channel with a symbol error rate of 10-', 30dB of SNR are required. The signal dynamic
range is therefore given by:
Signal Dynamic Range =
SNR256-QAM
=
55.2dB
+ PAPRTOTAL
(2.3)
Both parameters impose various constraints on certain circuit components including the power amplifier, the low noise amplifier and the data converters. These
constraints will be discussed in Chapter 3.
27
28
Chapter 3
The WiGLAN Node
Figure 3-1 shows a complete diagram of a WiGLAN node consisting of 4 printed circuit
boards (PCBs). A Field Programmable Gate Array (FPGA) and its evaluation kit
are responsible for generating and processing the samples of the OFDM symbols and
communicating with a PC. A board dedicated to data conversion contains a pair
of high-speed digital-to-analog and analog-to-digital converters.
The primary RF
front-end PCB performs almost all the analog processing at baseband and at RF
frequencies. Finally, a separate power amplifier (PA) evaluation board is responsible
for that function.
3.1
Transceiver Architecture
Two of the most popular receiver architectures are the homodyne (or direct conversion
receiver) architecture and the heterodyne architecture. The former downconverts the
incoming received signal directly from the RF to baseband, while the latter uses
an intermediate-frequency (IF) as well. A typical direct conversion receiver uses a
pair of mixers driven by local oscillators (LOs) phased 900 apart to downconvert the
received RF signal into its in-phase/quadrature (I/Q) or real and imaginary baseband
components. The primary advantage of this receiver is its low implementation cost the number of components is small and no image rejection filter is required.
Although the homodyne architecture has numerous benefits, a heterodyne archi29
POWER
AMPLIFIER
RF FRONT-END
DATA CONVERTERS
10
Ror
9(
10
DAC
FPGA
- - -83M~ Freqep
f0
=4.664GHz
ft =5.247GHz
NA
FIN
Figure 3-1: Simplified WiGLAN node schematic.
tecture was chosen for both the receiver and transmitter despite the additional mixers
and filters required. For one, the precise quadrature phases needed for I/Q up and
down conversion are much more easily generated at a lower IF frequency than at an
RF frequency. Furthermore, any coupling from the RF to LO or LO to RF will be
located out of band. For a direct conversion transmitter, the powerful RF signal can
couple onto the LO and degrade the spectral purity of the carrier, and for such a
receiver, the powerful LO can couple onto the potentially very weak signal path of
the incoming RF signal. The latter, however, is not a primary concern because the
system does not transmit data at the DC frequency bin.
3.2
Frequency Planning
In a low-side LO injection receiver, the local oscillator is multiplied by an incoming
RF waveform, and two parts of the spectrum are converted onto the desired IF. These
are the desired signal located at fRF
= fLO
+
fIF
and the image located at fIM
=
fAO-fIF- Once the downconversion takes place, the image, whose power may be much
larger than that of the desired signal, translates to the IF band and cannot be filtered.
30
It is therefore essential to filter out or reject as much of image as possible before the
first mixer. Fortunately, discrete ceramic bandpass filters are readily available and can
perform this operation quite well. There are many possible IF and LO frequencies that
can be selected and this choice can have a significant impact on receiver performance.
If the IF is too low, the image can be difficult to reject due to its proximity to the
desired signal, and if it is too high the problems of the homodyne approach such
as accurate quadrature LO generation remain. Furthermore, certain highly utilized
frequency bands such as the 900MHz cellular band and the 2.4GHz ISM band should
be avoided when selecting the IF and image locations. Finally, since this design is
built out of discrete components, the availability and quality of components such as
filters and mixers must be considered.
One additional property of OFDM systems can be exploited to reduce receiver
complexity. Since the symbols modulated onto each OFDM subcarrier are all recovered and detected in the digital domain, once a carrier frequency is selected by the
designer it need not be changed. For a heterodyne receiver, two carriers are needed
to downconvert first to the IF and then to baseband. Though two carriers generally
require two frequency synthesizers, with careful planning one of these phase locked
loops (PLLs) can be eliminated. Specifically, fRF =
fLo1
+ fIF must be satisfied. If
the 2nd LO can be generated from the 1st through frequency division by an integer D,
then only one synthesizer is required. Table 3.1 shows the possible values of fIF, RF,
fLo and the image frequencies for feasible values of D (fRF is fixed around 5.25GHz).
D
fRF
4
6
8
9
5.25
5.25
5.247
5.25
12
5.252
(GHz)
fLoi (GHz)
fIM (GHz)
1050
750
583
525
4.2
4.5
4.664
4.725
3.15
3.75
4.081
4.2
404
4.848
4.444
fIF
(MHz)
Table 3.1: Possible combinations of RF, IF, LO and image frequencies for different
values of D where fAo2
= fIF-
This design chooses an IF center frequency of 583MHz. This frequency is precisely
31
a factor of 8 lower than the first LO of 4.664GHz. The image can easily be rejected
since it is almost 1.2GHz away from the band of interest, and the IF is sufficiently
low so that precise quadrature signaling can be generated.
3.3
5.25GHz Transmission Lines
When designing a prototype using discrete components, it is expected that the connecting wires will have lengths on the order of mm or cm. The lumped element model
used in the teaching of basic electronics assumes the propagation time of the wires is
negligible, and therefore the voltage at the beginning of a wire is the same as that at
the other end of the wire at any given time.
At 5.25GHz, however, these approximations do not hold, and the propagation of
the wave must be taken into account. Whether or not a transmission line design is
necessary depends roughly on the following metric: A line length longer than the
quarter wavelength, A/4, generally requires the use of a transmission line to avoid
wave reflections.
signal frequency,
The wavelength is a function of a few parameters including the
f,
and the speed of light, c. For this design
f
A =
(3.1)
f VE,.p,.
where the relative permittivity er, is material dependent, and the relative permeability, yr is approximately 1. As will be seen shortly, the calculated wavelength
value is comparable to the PCB wire lengths and therefore proper transmission line
design is essential.
A strip of wire has an inherent characteristic impedance given by
ZO =
zo=
(3.2)
where L and C represent the inductance and capacitance per unit length.
In order to avoid wave reflections at the termination of the line, the characteristic
32
impedance of the line must be matched by an equivalent load impedance located
at the end of the line. Since most discrete components such as amplifiers and filters
present an input impedance of 50Q, this value is used for the transmission line design.
In order to minimize the loss in the transmission lines caused by parasitics, Rogers
4003 low dielectric loss PCB material is used. The required width for a 50Q microstrip
line can be calculated using various parameters. These include the relative permittivity Er, board thickness TB, and metal thickness
TMET.
These are summarized in
Table 3.2[7]. The wavelength for this material is given by:
A
c
=
f0r
30.6mm
zo
E,
50 Q
3.48
TB
TMET
.020 in.
0.0014 in.
calculated width
.0438 in.
(y
(3.3)
Table 3.2: R04003 PCB parameters.
3.4
3.4.1
Receive Signal Path
Noise Figure and Receiver Sensitivity
The limitation of receiver sensitivity is a direct consequence of its first few stages.
Even with perfect image rejection, the incoming signal will always have some amount
of in-band noise. The presence of this noise can significantly degrade the SNR if the
signal power level is low. The noise power at the receiver input, P",s, is given by:
PnoiseIdBn = PRSIdBm/Hz + 10 log B
33
(3.4)
where PRs is the noise power spectral density attributed to thermal noise that the
source resistance delivers to the receiver and B is the signal bandwidth.
4kTRs 1
PRs~dBm/H4
RH
-174dBm/Hz
-
(3.5)
where T = 300K and Rs = R,,. The noise power at the input with B = 128MHz
is -93dBm. The SNR at the input to the digital portion of the receiver, however,
must be larger than PRS/Pnise due to noise contribution of the receiver components.
To quantify the additional SNR degradation contributed by the receiver, the concept
of noise factor (or noise figure (NF) in dB) is introduced. Noise figure is defined as
SN RIN
NF = 10 log SNRU
S NRoUT
(3.6)
In other words, it is the degradation of SNR from the input to the output of
the receive chain. If 30dB of SNR are desired at the end of the receive chain, the
minimum signal power at the antenna can now be computed.
Pin,minldBm = -93d Bm +
(3.7)
30dB + NFTOTAL
Due primarily to the large signal bandwidth, the receiver sensitivity is heavily
constrained and Pinmin is very small compared to achievable sensitivities of 802.11a
transceivers who's values are often less than -70dBm[8][9][10].
A small noise figure
value is therefore essential for good performance.
The total noise figure can be related to the noise figure of each stage in the receive
chain [111:
FToTAL= + (F1
- 1) +
F 2 -1
A1
- +
Fm-l
A1
m
...
Am-(
3.8)
where F is the noise factor (non-log). It is observed that the noise figure of a latter
stage hardly contributes to the overall noise figure if sufficient gain is introduced prior.
34
A low noise amplifier (LNA) stage should therefore be placed as close to the front of
the receiver as possible.
3.4.2
Low Noise Amplifier
Agilent Technologies' MGA-85563 was chosen due to its large gain of 16dB, minimum
noise figure of 1.6dB, and ease of implementation. The chip consists of 2 gain stages
with an internal bias network. The IC also contains an option to place an external
resistor that controls the bias current and the linearity of the amplifier[12]. As shown
in Figure 3-2, the output is tied to a 3V supply through an RF choke with a reactance
of 270Q. This value is large enough to isolate the supply while maintaining a 50Q
output impedance.
8.2 nH
RIF
Input
RF2p
Matching
MGA22p
Network
85563
1 RIF
Output
20UA
Figure 3-2: LNA configuration.
The input to the device, however, is not matched to 50Q at 5.25GHz. A matching
network was designed to transform this input impedance to the 50Q expected by the
preceding component.
Discrete reactive components, though generally well suited
for such a network, are not used. Since
111
or IS11 of the LNA is non-zero, any
transmission line delay will cause a clockwise rotation in the F-plane. Due to the short
3cm wavelength of the 5.25GHz signal, precise placement of the reactive components
is required to achieve good matching. A matching network was therefore designed
using transmission lines.
35
F1 is rotated to yield an angle of 1800. At
In the first step, the complex valued
5.25GHz, the reflection coefficient looking into the LNA given by the data sheet is
1 =
10.481/ - 1160
(3.9)
Since traversing an entire wavelength, A, corresponds to rotating twice around the
F-plane, the length of the transmission line is given by[13]:
=
(-1160 - (-1800))
2 3600
(-1160 - (-180'))
c
2 3600
f y7r -I
2.7mm
(3.10)
After this transformation, the new reflection coefficient, Fr, is completely real and
the next step is to transform its respective ZL into 50Q.
ZL
=
ZoZ7
ZL
=
50(
1-F,
1 + r )
18Q
=
(3.11)
The 18Q can be transformed into 50M using a quarter wave transmission line with
characteristic impedance given by:
Zqw
=
VZLZ
= 30Q
(3.12)
The length and width of the transmission line can be calculated given the PCB
parameters. The design was verified using Sonnet[14], and the matching network is
shown in Figure 3-3. Due to a calculation error, however, the line width was designed
36
for a 35Q characteristic impedance. It should be noted that an input impedance of
50Q is not necessarily the optimal impedance for achieving minimum noise figure[15].
The input impedance presented in this work, who's value is not precisely 50Q, may
slightly improve or degrade the LNA noise figure, and henceforth that of the entire
receive chain. For the complete analysis of optimal LNA noise figure design see [15].
35Q line
i
J4
00
Figure 3-3: LNA input matching network.
3.4.3
Downconverting Mixer and Image Reject Filter
The discrete downconverting mixer was chosen to support the RF, IF and LO frequencies previously mentioned. The HMC488MS8G double-balanced passive mixer from
Hittite Microwave Corporation was selected[16]. Active Gilbert cell mixers, though
preferred, are not available for the 5.25GHz band. The local oscillator drive required
is only 2dBm due to an internal LO amplifier, and the conversion loss from RF to IF
is -6dB.
Since the downconverting mixer translates both the desired band and the image
bands onto the IF band, the image must be adequately attenuated. For this design,
2 discrete ceramic bandpass filters from Murata Electronics are considered.
Both
are centered at 5.25GHz and have a bandwidth of approximately 200MHz. Ceramic
bandpass filters often trade off between good cutoff at the stopbands and low insertion
loss at the passband. For example, Murata's DFCB25G25LAHAA has a typical inband loss of less than 1dB and an attenuation of 35dB at the image-band[17]. The
DFCB35G25LAHAA has an insertion loss of over 2dB but rolls off much more quickly
than the former[17]. (Note that the 2 part numbers differ by only a single digit) Both
37
filters are in fact used to attain sufficient image rejection, and their placement will
be explained shortly.
3.4.4
Receiver Linearity
While the noise floor and receiver noise figure determine the lower bound on the input
signal power, component linearity determines the upper bound. The maximum receiver input power level is determined by the linearity of the receiver stages. Linearity
can be quantified using two different metrics.
The first, called the output 1-dB compression point, signifies the condition in
which the output power of a stage stops increasing proportionally to its input. That
point signifies the input signal power level in which the actual output power is 1dB
lower or higher than the expected linear output. Most often, actual gain is lower and
not higher than the expected gain due to the saturating nature of MOS and bipolar
transistors.
The second measure of linearity is called the 3rd input intercept point (IIP3).
It is assumed that a non-linearity of an element can be modeled by a polynomial
with 1st, 2nd and 3rd order terms. Though both the 2nd and 3rd order terms are
undesired, the 3rd order term tends to degrade performance the most. To illustrate
this point, we consider the case when the input signal consists of two closely spaced
tones at w, and w2 . After passing through a gain non-linearity, the 3rd order terms
of the signal include components located at 2w, - w2 and -w, +
2w 2 .
These 3rd order
intermodulation products can lie directly in the signal band and cannot be filtered out
(Note that the second order terms have components outside the signal band located
at wi
-
w 2 , w1 + w 2 , 2wi, 2w 2 and DC). The input power level at which a 3rd order
output intermodulation spur is equal to the 1st order, or expected output tone is
known as the IIP3 point. This power level should be calculated through interpolation
of these two tones so the third order polynomial approximation holds. (The IIP3 level
is typically above the 1-dB compression point.) This linearity problem is compounded
in a multi-carrier approach such as OFDM since many more input tones are present,
and many intermodulation spurs arise. This issue will be addressed in Section 3.5.
38
................
......
2Olog(Afufld)
-i~
da
1111olflla
IN.
1 lert11
R
Al-dB
20log(A)
Aiip3
Figure 3-4: The IIP3 represents the input power level where the third-order spur
equals the first order tone.
3.4.5
The Noise-Linearity Tradeoff
The loss attributed to the downconverting mixer must be preceded by sufficient gain
so that the receiver noise figure is low and henceforth 2 LNAs must be utilized. Introducing too much gain, however, can cause the intermodulation products of powerful,
out-of-band interferers to fall in-band. As a compromise, Murata's low loss filter is
placed at the beginning of the chain. It is followed by the first LNA, Murata's other
strong cutoff filter, and finally the 2nd LNA. The receiver front-end diagram is shown
in Figure 3-5. Table 3.3 summarizes the measured receiver attributes.
fIo, = 4.664GHz
N
f1F
NA
fRF
= 583MHz
= 5.247GHz
Figure 3-5: RF receive path.
39
RFIN
..
.. .............
Gain (RF, to IF,,)
26 dB
Noise Figure
Sensitivity
4 dB
-56 dBm
(30dB of SNR at ADC output)
Input P1dB
-27.5 dBm
Input IP3
-14 dBm
Image Rejection
-75 dB
Table 3.3: Summary of receiver attributes.
3.5
3.5.1
The Transmit Chain and Power Amplifier
Transmit Path
While the receive chain from the antenna to the IF output requires careful design, and
is often addressed in more detail than the transmit path, the latter involves various
important design considerations as well.
The transmit path from the IF input to the RF output is shown in Figure 3-6. Like
the receive path, Hittite Microwave's HMC488MS8G passive mixer was used to upconvert the IF centered at 583MHz to the 5.247GHz RF. Murata's DFCB35G25LAHAA
bandpass filter rejects the undesired lower sideband, while the PA and PA driver amplify the signal to the desired output power level. ERA-21SM is a high frequency RF
amplifier produced by Mini Circuits and acts as the PA driver.
3.5.2
The Power Amplifier
Since the 5.25GHz band is assigned and used by 802.11a, a discrete power amplifier
optimized for this frequency and the 802.11a standard is chosen. Maxim Integrated
Products' MAX2841 was selected based on its large gain value of 22dB and the
availability of a separate evaluation PCB used in this prototype. This component has
three gain stages and internal bias circuitry. It also contains a built-in power detector
and this value can be probed by the user[18]. The input and output matching networks
were included on the evaluation PCB by the manufacturer.
40
fLo, = 4.664GHz
RFOUT
fIF =
583MHz
8RF = 5.247GHz
Figure 3-6: RF transmit path.
3.5.3
Power Amplifier Linearity
In modern wireless communication systems, particularly those expected to function
in mobile battery-powered environments, significant attention is paid to the design
and selection of the power amplifier because it is typically the most power hungry
analog component.
Various classes of power amplifiers can be selected, and they generally trade efficiency, defined as
POUT
(3.13)
PSUPPLY
with linearity attributed to the non-linear large signal operation of transistors.
Section 3.4 explained that receiver linearity must be maintained in order to prevent
intermodulation products of out-of-band interferers from appearing in-band. On the
transmitter, the large signals at the output tend to be non-linear and can distort the
transmitted constellations. The previous section explained how the P1dB and IIP3
points can be measured. This section explains how these numbers are related to the
maximum OFDM symbol power that can be tolerated. In order to detect 256-QAM
constellations at symbol error rate of 10- 3 , the intermodulation spurs must lie 30dB
below the desired subcarriers. Relating the power of these spurs to the spurs generated
41
in a two-tone test, however, is non-trivial due to the large number of carriers and to
the many spurs they generate.
The large peak-to-average power ratio inherent in OFDM signals requires the PA
to linearly amplify amplitude values much larger than the signal RMS amplitude. As
a result, the PA must back off extensively from its 1dB compression point. More
specifically, it must back off by a value larger than the PAPR of the signal. This
value calculated in Section 2.3 to be 25.2dB is unreasonably large and severely limits
the PA output power. As will be explained in Chapter 4, the PAPR for this work
was limited to 10dB.
Instead of obtaining the maximum output signal power analytically, it is obtained
through an Adjacent Channel Power Ratio (ACPR) measurement. Because many of
the intermodulation spurs lie in the exact same frequency as a desired tone, their
power cannot be measured. It is assumed that the intermodulation spur appearing
in the first unused subchannel has approximately the same power as those located
in-band. Its value can be measured by continuously transmitting a single OFDM
symbol, and observing the spectrum at the output of the PA. The input signal's
power can then be raised until the spur's value is about -30dBc relative to the desired
tones. The initial output power tested is given by
POUT = PdB -
PAPR
(3.14)
and this value is adjusted until the specification is met.
Figure 3-7(a) shows the spectrum of a single 128MHz-wide transmitted OFDM
symbol. Figure 3-7(b) shows the adjacent channel power of the zoomed in spectrum.
The total output power is 7.5dBm.
Given the insufficient ACPR value of -26dBc shown in Figure 3-7(b), it can be
inferred that 256-QAM will not be possible to detect given this output power. If
30dB of ACPR are required, then the PA output power must be further decreased.
Table 3.4 summarizes the PA specifications.
42
1' 2
5.247GHz
---
128 MHz
(a)
-26 dBc
5.183GHz
(b)
Figure 3-7: (a) Spectrum of a single transmitted OFDM symbol. (b) The adjacent
channel power ratio measurement.
43
Output Power
Power Gain
Output P1dB
Output IP3
7.5 dBm
20.7 dB
19.6 dBm
28.0 dBm
ACPR
-26 dBc
(at 5.247GHz - 65MHz)
Table 3.4: Summary of PA attributes.
3.6
I/Q Imbalance
Almost all wireless transceiver designs exploit the orthogonality property of cosine
and sine functions by upconverting both an in-phase and a quadrature component
onto the same frequency carrier. This orthogonality enables the two components to
be extracted during I/Q downconversion so long as appropriate lowpass filtering takes
place. If, however, the upconvert and downconvert local oscillators are not exactly
the same amplitude and their phase difference is not precisely 900, the orthogonality
property is lost and some ISI between the in-phase and quadrature components occurs.
In addition to mismatch between the quadrature carriers, I/Q imbalance can also be
caused by any mismatch in the gain or phase delay of the baseband analog components
including low pass filters, variable gain amplifiers (VGAs), and data converters.
To quantify the interference caused by I/Q imbalance, the following experiment
can be conducted on the transmitter.
As shown in Figure 3-8(a), two sinusoids,
cos(wBt) and sin(WBOt), are fed as inputs to an I/Q upconverter. The chip respectively
multiplies these two sinusoids by cosine and sine carriers at WLO and combines the
products.
The expected RF output should be a single tone at WLO +WB or WLO --WB (depending on whether the I lags the
Q
or vice versa). If, however, the carrier's amplitudes
are not the same or their phase is not separated by precisely 900, an undesired output
spur will be present, located on the other side of WLO. The quality of an I/Q upconverter can therefore be measured by its ability to suppress this unwanted sideband.
The sideband is measured in dBe and its suppression value must be larger than the
30dB of SNR required to detect 256-QAM modulation[19]. Figure 3-8(b) shows the
44
Desired Output
cos(wt)
LO Leakage
-
AF
.
Unwanted Sideband
900
sin(O 11t)f
5.25GHz
.LO
(b)
(a)
Figure 3-8: (a) Setup for sideband suppression test. (b) The output signal.
effect of I/Q imbalance. An LO feedthrough component is also present but is not
of significant concern because no data is sent at the subcarrier located at DC. Nevertheless, this feedthrough should still be minimized in order to avoid transmitting
superfluous power.
Figure 3-9 was obtained through a MATLAB simulation and it illustrates the
relationship between the sideband suppression and the phase/amplitude imbalance.
As a conservative estimate, the phase imbalance should be less than 2' and the gain
imbalance less than 0.2dB. The phase and gain imbalance of the receiver can be
measured after the I/Q downconverter.
Analog Devices' AD8345 is used to perform I/Q upconversion. It accepts differential baseband I and
Q
inputs and a differential LO (achieved with a balun). The
primary advantage of this component is its ability to process baseband inputs of up
to 80MHz[20].
Linear Technology's LT5517 performs the I/Q downconversion. It also accepts a
differential LO and outputs differential I and
Q
baseband signals. The chip is fed a
signal at twice WLO and divides it down with internal divide-by-two circuitry. Similar
to its counterpart, this component was also selected based on its high baseband
frequency processing capabilities[2 1].
It is important to note that this section referred to the 2 ICs as an I/Q upconverter
45
-
-
-
----------
-30-
-40
-451
O.OdB
e- 0.IdB
C
0.2dB
0.3dB
-50--59
2
4
6
8
10
Phase (degrees)
Figure 3-9: Sideband suppression plotted against the phase imbalance for different
amplitude imbalance values.
and downconverter. The author feels that the commonly used term "modulator" is
misleading because that action represents a mapping of bits to symbols. In an OFDM
system, modulation occurs digitally because the IDFT maps a set of bits to a carrier
of a certain frequency, amplitude, and phase. The analog mixers do not modulate,
but simply translate in frequency the already modulated signal.
3.7
3.7.1
Frequency Synthesis
Phase Locked Loop
A block diagram of the phase locked loop is shown in Figure 3-10. Analog Devices'
ADF4106 synthesizer chip contains a phase/frequency detector (PFD), a divide-byN with programmable divide value, and a charge pump[22]. The lowpass loop filter is implemented externally using a type 2, 2nd order RC configuration and Zcommunications' SMV4780A voltage controlled oscillator completes the loop[23].
Since the PLL does not perform channel selection, its output frequency remains
fixed at 4.664GHz. Unlike many PLL designs, this one does not focus on providing
fine frequency resolution, and therefore, other parameters including phase noise can
46
ADF4106
fREF
=
44MEZ
V
faLO
= 4.664GHz
f2LO2 =
1.166GHz
Figure 3-10: PLL schematic. The frequency divider, PFD and charge pump are found
on chip.
be optimized. To maximize phase noise performance, N should be small and the PFD
frequency high. A 22MHz PFD frequency is obtained by dividing down the 44MHz
crystal reference. The 4.664GHz output carrier is synthesized with an N value of 212.
The PLL loop gain and filter parameters were determined using PLL Design
Assistant[24] in order to achieve stability and maximize phase noise performance.
3.7.2
LO Distribution
The synthesized local oscillator must drive 2 mixers at 4.664GHz, 1 at 1.166GHz,
and 1 at 583MHz. In order to control the power delivered to each, the LO must
pass through a power splitter. Power splitting at 4.664GHz is implemented using a
Wilkinson power splitter that produces 2 outputs, each with precisely half the power
of the input signal.
In Figure 3-11, each quarter wavelength transmission line transforms the 50Q
impedance seen at its load into 100Q. The input impedance is therefore the parallel
combination of the two, or 50Q. The output ports are not matched to 50Q, however
any reflected signal will go through a 1800 phase shift as it propagates through the
2 A/4 transmission lines and cancellation will occur.
dissipate power, and hence:
47
The 100Q resistor does not
X/4 -
IN
50
50
OUT1
50Q
OUT2
100Q
70.7Q line
Figure 3-11: Wilkinson power splitter.
POUT1 = PIN - 3dB
(3.15)
POUT2 = PIN - 3dB
(3.16)
Prior to distribution, the LO signal is amplified by Mini Circuits' ERA-21SM[25].
3.8
3.8.1
Data Conversion
DACs and ADCs
As mentioned in Section 2.1, an OFDM symbol is generated by an IDFT every 1ps,
and has 128 samples. Since 64MHz is the largest frequency component of the signal,
the system operates at the Nyquist rate. In order to ease the requirements on the
anti-aliasing and reconstruction lowpass filters before and after the Analog-to-Digital
Converters (ADCs) and DACs respectively, the OFDM symbols are upsampled by 2x
yielding a data converter sample rate of 256 Mega Samples per Second (MSPS). In
the implementation, upsampling is achieved by zero-padding an additional 128 bins
corresponding to the positive and negative frequencies from 65MHz to 128MHz and
taking a 256-point inverse fast fourier transform (IFFT).
Due to the large peak-to-average power ratio and henceforth the large signal dynamic range of 55dB, the number of bits required by the DACs and ADCs is quite
large and is given by[26]:
48
SNR = 6.02(B - 1) + 10.8 - 20 log Xm
(3.17)
where B is the number of bits, Xm is half the full scale voltage, o-, is the rms
value of the signal amplitude, and SNR here refers to the total signal dynamic range.
(Note: the PAPR is already taken into account in "SNR". Therefore O, = .707Xm,
the rms value of a full scale sinusoid) The smallest value of B that fits Equation 3.17
is 10.
Only recently have data converters with such specifications become commercially
available. As will be explained in Chapter 4, the PAPR was limited to 10dB primarily
in order to transmit with reasonable output power. Due to this consideration and to
limited component availability, Analog Devices' AD9753 10-bit DAC[27] and AD9480
8-bit ADC[28] were selected.
In order to maintain signal integrity at a high sample rate, the digital-to-analog
converter operates using two input ports. It accepts 2 digital samples in parallel but
at 1/2 the sample rate. The 128MHz input clock is internally multiplied by 2, and
the data is serialized before being converted into an analog waveform.
The analog-to-digital converter uses low voltage differential signaling (LVDS) to
transmit the 256MHz data and clock outputs.
3.8.2
Clock Synthesis
For the system to be completely self sufficient, the data converter clock is synthesized
on the PCB.
An on-board 128MHz crystal oscillator clocks the DAC, the ADC
(through a 2X clock multiplier), as well as the entire FPGA.
The noisy digital
circuitry of the FPGA prevents it from providing a sufficiently clean clock signal,
and in order to synchronize the clock with the data, it must be clocked by the onboard 128MHz oscillator. A detailed schematic of the data converter PCB is shown
in Figure 3-12.
The maximum tolerable aperture jitter can be calculated and is a function of the
DAC resolution and the input frequency[29]:
49
DATA CONVERTERS
101
10
PAC
-+0Tx
FPGA +-
-
64MHzz
+-IRX
84
Figure 3-12: Detailed schematic of the data converter PCB.
At
<
1
2Brf,,
1
<210r - 64MHz
=
In addition to random
(3.18)
4.8ps
jitter, the clock signal should be free of any spurs nearby
128MHz that can arise due to signal coupling from the incoming DAC data lines.
Otherwise, these spurs can couple directly onto the analog DAC output. The spurious
components in the clock signal can be minimized through careful layout and the use
of differential signaling.
In addition to clock jitter, clock skew between the I and
Q
paths must also be
carefully controlled in order to avoid I/Q phase imbalance. Using a dual DAC or
ADC IC resolves the issue of clock skew but these chips are not available at 256MSPS
50
sample rate. Again, the clock skew problem is mitigated through careful PCB layout.
For example, the PCB wire length between each pair of DACs and ADCs is kept the
same.
3.9
Baseband Signal Conditioning
3.9.1
Lowpass Filters
Lowpass reconstruction and anti-aliasing filters are used after the DACs and before
the ADCs respectively. The 75MHz filters are implemented passively with a 3rd order
Chebychev LC ladder design. Active filters are avoided due to the large baseband
bandwidth requirements.
3.9.2
Variable Gain Amplifiers
A pair of variable gain amplifiers amplify the I/Q baseband signals in order to maximize the dynamic range of the ADC. Though many parts that perform this function
are available, the large baseband bandwidth poses more stringent performance specifications.
As with the I/Q down and up converters, the amplifiers must function
linearly up to 64MHz. In addition they must be low noise. Specifically, their outputreferred noise power should be less than the quantization noise power introduced by
the ADCs. Linear Technology's LT5524 amplifiers were selected for this purpose[30].
Similar to the issue of clock skew mentioned in the previous section, when using two separate ICs to perform the amplification, any variation in gain or phase
between them can cause I/Q imbalance. It turns out that the amplifiers do exhibit
some variation in gain, but not significant variation in phase. This gain variation is
compensated for digitally.
51
Transceiver Measurements
3.10
to VGA
Figure 3-13 shows the receiver gain and noise figure from receiver input
Any
output. The gain value can be varied according to the input signal strength.
response.
gain variation across the frequency band is incorporated into the channel
6
39
38.5
5.5
38
-
37.5
37-5
36.5
4.5
3635.5
5.18
5.2
5.22
5.26
5.24
RF Frequency
5.28
5.3
5.18
5.32
5.2
5.22
5.26
5.24
RF Frquency
5.28
5.3
5.32
(b)
(a)
output.
Figure 3-13: (a) Receiver gain measured from receiver input to VGA
output.
VGA
to
input
Receiver noise figure measured from receiver
(b)
Figure 3-14(a) shows the measured unwanted sideband in dBc when 2 64MHz
the DACs.
quadrature baseband sinusoids are supplied to the I/Q upconverter from
(before the
The signal is measured on a spectrum analyzer at the transmit output
at the
PA), and the suppression is -37dBc. Figure 3-14(b) shows the I/Q imbalance
The
receiver. The I/Q downconverter block accepts a sinusoid at WIF + 64MHz.
in MATLAB
baseband inputs are digitized, and ideally upconverted back to the IF
is -43dBc.
so the unwanted sideband level can be observed. The sideband suppression
To characterize the combined performance of the DAC and ADC, sinusoidal waveforms were generated in MATLAB, passed through a DAC, amplified, digitized,
Kit
and captured using Analog Devices' High Speed ADC USB FIFO Evaluation
(HSC-ADC-EVALA-DC).
Figure 3-15 shows the fast fourier transform (FFT) plot
of two sinusoids captured by the ADC at 5MHz and 63MHz.
The performance
the
for both frequencies is summarized in Table 3.5. Parameters measured include
and
fundamental power in decibels below full scale (dBFS), SNR, signal-to-noise
52
-W.IWA
WIN
0
Desired Signal
-20
Carrier Feedthrough
F-40
Undesired
Sideband
-43dB
-60
-80
300
I--- 128 MHz -H
400
600
500
00
800
(b)
(a)
Figure 3-14: Sideband suppression measurements for (a) transmit (spectrum analyzer) and (b) for receive (MATLAB).
distortion (SINAD), worst spur, noise floor and the effective number of bits (ENOB).
The spurs shown on the 63MHz FFT plot arise from the coupling of the DAC data
lines onto the 128MHz clock as explained in Section 3.8. The largest of these spurs is
-54dBc. These spurs are not apparent in the 5MHz FFT plot because the data lines
change at a slower rate and less signal coupling occurs.
5MHz
63MHz
-1.4(dBFS)
45.8(dB)
45.7(dB)
-67.2(dBc)
-89.3(dBFS)
7.3(bits)
-1.4(dBFS)
44.2(dB)
43.9(dB)
-54(dBc)
-87.0(dBFS)
7.1(bits)
Parameter
Fundamental
SNR
SINAD
Worst Spur
Noise Floor
ENOB
Table 3.5: Combined performance of AD9753 DAC and AD9480 ADC.
53
U
-20
-40
V
a2
..........
.......... .
-60-
A U6 1LL
-80
-100
-lz
U
0
50
40
30
Frequncy (MHz)
20
10
60
70
8C
60
70
80
(a)
-20-40-60
Jill,
II.
-80
-100*
qi
-120
10
0
10
[I
20
20
~
r
50
40
30
50
40
30
Frequncy (MHz)
(b)
Figure 3-15: (a) Spectrum of captured sinusoid at 5MHz. (b) Spectrum of captured
sinusoid at 63MHz.
54
Figure 3-16: Photograph of a WiGLAN Node.
55
56
Chapter 4
Non-Real-Time DSP
Implementation
4.1
Motivation
In order to measure the channel response and in order to successfully receive data, the
analog front-end must be accompanied by a robust real-time digital signal processing
unit. The unit should be capable of generating OFDM symbols on the transmit side
and detecting the QAM symbols on the receive side. Due to the high data rate, the
Digital Signal Processor (DSP) implementation is non-trivial and introduces another
area of research.
Since the primary objective of this work involves the analog front-end implementation, the necessary DSP algorithms are implemented in MATLAB in a non-real-time
fashion. A block diagram of the measurement setup is shown in Figure 4-1. A set
of OFDM symbols is first generated on a PC. The samples are then stored in the
Virtex-4 FPGA. Using a counter, the set of symbols is repeatedly sent to the analog
front-end for transmission. On the receive side, the receiver captures the data, adjusts
the VGA gain to fill the dynamic range of the ADC, and sends the ADC samples
back to the PC for post-processing.
The DSP algorithms explained in this section are selected primarily based on their
ease of implementation, and as a result they are not optimized for performance. They
57
ADI
RXFIFO
TX
MA
BOARD
UTX
Pre & Post
Processing
Figure 4-1: Block diagram of the measurement setup.
do, however, enable the transmission of high-data rate information.
The issues addressed in this chapter include channel estimation, the cyclic prefix,
symbol synchronization, LO phase and sampling time offsets, LO frequency offset and
peak-to-average power ratio.
4.2
Channel Estimation
Most wireless systems rely on some form of channel estimation in order to recover
the received data. Oftentimes, a known sequence is transmitted so the receiver can
obtain the channel information. The receiver then utilizes this information to undo
the effects introduced by the channel.
Due to their ability to effectively resolve multipath, OFDM systems can correct
the received constellation point in each bin with a single tap. In other words, the
receiver uses the channel estimator to undo the attenuation and the phase delay of
the channel for each bin.
In this implementation, each set of OFDM symbols is preceded by a training
sequence consisting of 2 known OFDM symbols from which the receiver extracts a
58
magnitude vector and a phase correction vector. These vectors are then averaged and
applied to the subsequent data payload. Averaging is used to increase the accuracy
of the channel estimator. A very noisy channel estimate would result in non-optimal
correction values, which can increase the symbol error probability.
4.3
The Cyclic Prefix
Despite their ability to avoid inter-carrier interference between adjacent frequency
subbands, OFDM systems are still susceptible to inter-OFDM-symbol interference.
Since the channel's impulse response consists of multiple delayed taps, copies of one
OFDM symbol can arrive at the same time as another OFDM symbol.
To resolve the ISI problem, the concept of a cyclic prefix is introduced.
The
transmitter copies the last M samples of each OFDM symbol and places them at
its front. The receiver later removes these samples. With the cyclic prefix in place,
the OFDM symbol undergoes cyclic convolution instead of linear convolution with
the channel impulse response[19]. As shown in Figure 4-2, the duration of the cyclic
prefix is chosen such that it is longer than the delay spread, rDs, of the channel, and
thus inter-OFDM-symbol interference is avoided.
h(t)
JI I? ?,t
Delay Spread
I
I
Figure 4-2: The cyclic prefix must be longer than the delay spread of the channel.
59
Z4r-
with some
Another advantage of the cyclic prefix is that it can provide the receiver
This flexibility
flexibility when determining on which samples to perform the DFT.
will be explained in Section 4.5
rate, and
Despite its benefits, the cyclic prefix does reduce the OFDM symbol
prefix consisttherefore the overall data rate. Since this implementation uses a cyclic
to 1.25ps and
ing of 25% of the OFDM symbol, the symbol time increases from ips
the data rate reduces by 20%.
4.4
Local Oscillator Phase and Converter Sampling
Time Offsets
The mixers
Figure 4-3 shows a simplified diagram of an I/Q transmitter and receiver.
end, they
at the transmit end are driven by COS(WLOt) and sin(WLOt). At the receive
are driven by COS(WLOt +<
) and sin(WLOt + <)).
I'
cos(2u f t)
cos(2Tr f t + ()
sin(27 f t)
sin(2U f t + 0)
-\
Q
Figure 4-3: Simplified I/Q transmitter receiver pair.
When D
=
0,
1
(4.1)
Q' =Q
(4.2)
I'
=
60
The receive and transmit end, however, stand alone and their local oscillators are
not synchronized. In this case,
I' = Icos(?) + Qsin(4)
(4.3)
Q
(4.4)
=
Qcos(4) - Isin((D)
where D is a random variable uniform from 0 to 21r. The effect of the random
phase of the local oscillator manifests as a random rotation of the constellation points
of every single bin (Note: all bins undergo the same rotation)[191. Figure 4-4 shows
the effect of LO phase offset on the received constellation points.
Figure 4-4: Rotation of received constellation points.
The phases of the sampling clocks of the DACs and ADCs are similarly not synchronized. The constellation phase rotation, T, caused by a mismatch of At seconds
between a pair of data converters is given by:
T = 27rf (At)
(4.5)
Each bin corresponds to a different input frequency, f, and henceforth this effect
manifests as a different random rotation of the symbol in each bin.
Fortunately, the rotation effect from both the LO phase offset and the data converter sampling clock offset can be combined into the overall channel estimation
vector.
61
4.5
OFDM Symbol Synchronization
The sampling time offset, At, between the starting point of a transmitted OFDM
symbol and the same received OFDM symbol is not limited to values smaller than
the sampling clock period. In fact, the addition of the cyclic prefix can allow for some
flexibility in the selection of the precise starting and ending point of the first OFDM
symbol in a packet. This implementation uses a cyclic prefix of 25%, or 64 samples.
Out of the 320 samples, any 256 can be selected so that the starting sample, S of the
OFDM symbol lies in the range:
TDSIsamples < S < 64
TDS . 256MHz < S < 64
Due to the potentially large range of
(4.6)
S, the starting point is chosen by inspection.
Prior to the 2 training symbols, a low power tone of 60MHz is inserted. Figure 4-5
shows that the starting point can be selected at the point where the symbol power
becomes large. Once the starting point of the first symbol is selected, the starting
point of the second is located 320 samples later. In the figure, each 60MHz tone is
followed by about 45 OFDM symbols after which the tone is repeated.
4.6
Frequency Offset
Section 4.4 addressed the presence of a phase offset between the transmit and receive
local oscillator signals. The two oscillators have a frequency offset as well. To illustrate the cause, assume that the 44MHz crystal reference oscillator has an accuracy
of 50 parts per million (PPM). The frequency error in the local oscillator is given by:
fLo
=
44MHz ± 2.2kHz .212
2
= 4.664GHz ± 230kHz
62
(4.7)
(4.8)
250
2 00 -
-
-.
.
.
... .
-...
-..
-.
.... .
-.. -..
15010050
0
0
-.
. ..... -...
--...
-
1
0.5
1.5
2
2.5
3
3.5
Samples
Figure 4-5: Samples at the output of the ADC.
When the LO is used to downconvert to baseband, the effect of the offset is seen
as a frequency shift in the baseband OFDM signal (Figure 4-6). The subcarriers are
now no longer orthogonal and inter-carrier interference arises. The degradation in
SNR occurs twofold: For one, the DFT no longer samples the OFDM subcarriers at
the peak of the sinc function causing a reduction in signal power. In addition, the
sampling point does not coincide with the zero crossing of the remaining subcarriers. Henceforth, it can be seen that the larger the frequency offset, the larger the
degradation in SNR.
4.6.1
Coarse Correction
This implementation resolves the issue of ICI caused by LO frequency offset by selecting a pair of crystal oscillators that are sufficiently close in frequency for a given
transmitter/receiver pair. An overall offset of 8kHz between the transmit and receive LOs maintains the SNR of 30dB required for successful detection of 256-QAM
symbols[311:
SNR
1
31n(10)
10 (7rTfA) 2
63
= - I-
-=- -
-
_-
-
-
--
- - -
the baseband OFDM
Figure 4-6: LO frequency offset causes a frequency shift in
symbol.
-
(4.9)
30.4dB for Tfn, = 0.008
where T is the inverse of the frequency bin spacing and
fN
corresponds to the
frequency offset.
4.6.2
Fine Tracking
on the system.
The frequency offset, even when kept to less than 8kHz, has an effect
oscillator signals
In Section 4.4 it was assumed that once the phase offset of the 2 local
into the
has been determined, it remains fixed and its value can be incorporated
overall channel estimate. A residual difference in local oscillator frequency, however,
OFDM
will induce an accumulation in phase offset over time. That is, in every
1 M. This phase
symbol duration the constellation will be rotated by a small amount, A
the wireless
accumulation occurs quickly in comparison to the coherence time of
channel, and therefore must be continuously corrected.
8 of the
This work performs the tracking by inserting 8 known pilot symbols into
all the
128 frequency bins. After every DFT operation, the residual phase rotation of
Like with
bins is estimated using the pilots, and applied to the remaining data bins.
64
-
ot=
the cyclic prefix, the presence of pilots in 8 of the bins cuts the data rate by a factor
of
120
128'
4.7
Peak-to-Average Power
Sections 3.5 and 3.8 addressed the need to lower the peak-to-average power ratio
inherent in OFDM systems. Various algorithms exist to reduce the PAPR and ease
the restrictions on data converter dynamic range, and more importantly on the PA
backoff power. In addition, since large peaks in the OFDM symbol are rare, some
signal clipping is tolerable if the error introduced is small compared to the required
symbol error probability.
This work does not rely on peak reduction algorithms nor on signal clipping, but
instead exploits the non-real-time generation of the OFDM symbols by only sending
ones with PAPR < 10. When OFDM symbols are randomly generated, typically
95% of them meet this requirement. Those that do not, are simply not transmitted
in this implementation.
65
66
Chapter 5
Channel Measurements
5.1
Measurement Procedure
The WiGLAN transceiver discussed in Chapter 3 is used in conjunction with the
MATLAB implemented DSP algorithms of Chapter 4 to transmit, receive, and detect
data bits.
Despite the effort to transmit data at 1Gbit/s using 256-QAM, it was
found that such a large constellation poses strict requirements on the SNR. In order
to transmit 7.5dBm with sufficient linearity, and in order to ease the requirements
of the data converter signal dynamic range, 64-QAM constellations are used in these
measurements. Such a reduction, cuts the data rate by 25%.
The block diagram of the setup shown in the previous chapter, is repeated here
in Figure 5-1.
The steps taken by both the transmitter and receiver are summarized in the
following 2 lists.
5.1.1
Transmitter
* One channel estimation vector, EST, of length 128 is generated. Each element
or bin with the exception of that located at DC, contains a randomly generated
16-QAM constellation.
* 50 vectors, DATA 1 , DATA 2 ,... DATAO, of length 128 are generated contain67
ADI
FPGA
-+
RX
TX
FF
BOARD
Pre & Post
Processing
Figure 5-1: Block diagram of the setup.
ing randomly generated 64-QAM constellations. Interspersed in each data vector are 8 known pilots (also 64-QAM) who's values are known to the receiver.
The input matrix, 1 is given by:
I, = [EST, EST, DATA 1 , DATA 2 ,.
..
DATA5 O}
(5.1)
* One at a time, a 256-pt IFFT is performed on each of the vectors. Before
the IFFT, 128 zeros are appropriately inserted so that the operation would be
equivalent to taking a 128-pt IFFT and then up-sampling by 2x.
" The cyclic prefix is then generated by copying the last 64 samples and placing
them at the beginning of each OFDM symbol effectively increasing the OFDM
symbol time by 25%.
" After appropriate scaling, OFDM symbols with PAPR above 10dB are omitted
as explained in Section 4.7.
" The set consisting of about 16000 samples defined as a single packet, is prepended
by a low power 60MHz sinusoidal tone used to detect the start of the packet.
68
e The samples are then stored in the FPGA, and continuously transmitted using
a counter.
5.1.2
"
Receiver
Using the Analog Devices ADC evaluation board, the receiver captures 32K
samples of data digitized by the ADC.
" The VGA gain is manually adjusted so the OFDM symbols maximize the ADC
dynamic range without clipping.
" Once captured, the first sample of the packet is determined by observing where
the 60MHz tone ends and the high power signal begins.
" The first 2 OFDM symbols (those used for channel estimation) pass through
an FFT and the output symbol vectors are averaged to give the received vector
X. The correction vectors are given by
|x'
IEST
XcorMag
XcorAng
=
(5.2)
LX - LEST
(5.3)
* The two channel estimation vectors are applied to the subsequent FFT outputs, and the 64-QAM symbols are obtained.
In order to account for the
time-dependent constellation rotation caused by the residual frequency offset,
a residual vector, XcorAngFine, is obtained by finding the best line fit to the
8 pilots.
5.1.3
Symbol Error Rate
To compute a lower bound on symbol error rate, the received symbols are compared
to the transmitted symbols, and the condition for error is given by:
69
IDATAijITX - DATAijIRXI
d
(5.4)
>
where DATAij corresponds to the jth bin of the ith OFDM symbol and d is the
distance between adjacent constellation points.
Given the limited number of symbols transmitted, the measurements presented in
this section do not always produce errors. When no errors are produced the symbol
error rate is given by:
1
5E R =(5.5)
TotalSymbols
The SNR per bin can also be computed:
SNR- = 10 log
Y
I
si2
iDATAIjITx - DATAijRX|
2
(5.6)
where Pig is the power of a typical OFDM symbol.
5.2
Test 1: Wired Channel
In this test, the 7.5dBm output signal was attenuated by 47.5dB down to -40dBm,
and connected directly to the receiver through a short SMA cable. Figure 5-2a shows
the received constellation points after correcting for both the magnitude and phase
response of the channel. The dominant contributor to the apparent large noise variance is the error introduced by PA non-linearities. Nevertheless, this measurement
still manages to successfully detect all the transmitted points. To illustrate the effect
of the residual LO frequency offset, Figure 5-2b show the output constellations when
fine phase tracking is not used.
5.3
Test 2: Input Signal Power Range
The sensitivity and linearity parameters were measured using sinusoidal inputs in
Chapter 3. In this section we attempt to measure the smallest and largest input
70
20
20
151
15
ab
............
10
10
5
............ ............
0
-
-5
qSP
...
........... ........
-10
-1
4p cj3 Il
-15
-15
-20
0
-10
0
10
20
-2 0
10
0
-10
20
real
(b)
real
(a)
Figure 5-2: (a) Received constellations for a wired channel.
without performing fine phase tracking.
(b) Received points
OFDM signal power that allows for successful data transmission for all subchannels.
Through experimentation, these values are found to be -55dBm and -33dBm. The
measured SNR per bin and received constellations are shown in Figure 5-3 and performance is summarized in Table 5.1
Channels Used
Total Symbols
Errors
Symbol Error Rate
Data Rate
Pi = -55dBm
all
10710
7
7e-4
571 Mbit/s
Channels Used
Total Symbols
Errors
Symbol Error Rate
Data Rate
Pi = -33dBm
all
10710
0
1.Oe-4
571 Mbit/s
Table 5.1: Performance summary for minimum and maximum input power levels.
5.4
Adaptive Modulation over a Wireless Channel
As previously explained, adaptive modulation exploits the frequency selectivity of the
channel by transmitting large constellations in the good channels and small constel71
.............
...
..
...
35
35
35 35
..... .
30[
25
. ...
30[
............
-....
zV).
z
20
-
20
-
15
15
10'
25
I It5I
20
20
10
10
9aeb
0
0
-20
*
.
..
...
..
..
.
..
..
...
...............L .
.....*
-10
2*0
-10
50
Bin
Bin
-10
0
-50
50
0
-50
*0d:
0
real
10
-20
20
0
0
-10
10
20
real
(b)
(a)
Figure 5-3: Measured SNR per bin and received constellations for a wired channel:
(a) PIN of -55dBm. (b) PIN of -33dBm.
72
lations in the deep fading channels. To simplify the implementation, 64-QAM and
nothing are the only 2 options used in this experiment.
A problem in a non-real-time system arises since the transmitter must have knowledge of the channel response in order to determine which bins should be used. Due
to the rapidly changing (on the order of 1s) channel response, the receiver does not
have ample time to relay this information back to the transmitter.
Instead of relaying back information, the transmitter sends 64-QAM data in all
the bins, and depending on the average received SNR of each bin, the receiver selects
which bins to include. The SNR threshold used to determine whether a bin should
be used is 28dB. This value, which is larger than that of the SNR required to detect
64-QAM, provides a comfortable error margin. One reason that the error margin is
necessary has to do with the fact that the fine phase tracking algorithm is non-optimal
and a precise rotation angle cannot be predicted. Figure 5-4 shows a typical SNR
per bin plot averaged over 1 packet. The black horizontal line indicates the threshold
over which a bin is considered to be used.
35
30-
................
-,14 -4y6j
V
TV
......
.......
25
z
20
151-
10'
-50
0
50
Bin
Figure 5-4: SNR per bin of a received signal. Bins with SNR over 28dB are considered
"used bins".
73
It should be noted that the performance attained by this method is in fact a lower
bound for the potential data rate achieved in a real-time system. When adaptive
modulation is used properly (i.e., the receiver relays the channel information back to
the transmitter), the power transmitted in each used bin can be larger in order to
keep the average OFDM symbol power the same.
5.5
Test 3: 1m
This and the following sections show results for measurements conducted in two
different wireless indoor environments: A large room, and a laboratory containing
many potential multi-path sources. In this test, the transmit and receive nodes were
placed
1m apart. The received constellations and channel responses are shown in
Figure 5-5. The performance is summarized in Table 5.2.
5.6
Test 4: 7m
Still within the 2 environments, the transmit and receive nodes were placed 7m apart.
The received constellations and channel responses are shown in Figure 5-6.
The
performance is summarized in Table 5.3.
5.7
Test 5: 4m, Not Line-of-Sight
A similar test was conducted for a distance of 4m. This time, however, the nodes in
the lab were placed so that their antennas were not in line of sight of one another.
The received constellations and channel responses are shown in Figure 5-7.
performance is summarized in Table 5.4.
74
The
5
5
0
0
~.
.
~~..
4~-.
.
S-5
-5
-10
-10
<-15
-15
-20
-20
-25
25r
i
-60
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-20
-40
20
40
60
20
20
10
10
0
se
*a..*,S
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go
ese*ee
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10
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- -
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-0000.
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-10
-40
10
20'
-2(
20
20
40
60
&1
OD
aS
0 C*
20
0
Bin
PA --I :
W -....
......
_
..:
.
..
..
.
..
......
.
....... ..
0e
0A
10A
2
10
20
V
Vee
-
s
D:
wee
-10[ 400.
0
real
-20
es
0g 4Ved%#:s
-20'
-2 0
-60
0
10
real
(b)
(a)
Figure 5-5: Channel Response and received constellations for 1m transmission in (a)
a large room and (b) a laboratory. Magenta represents used bins while blue represents
un-used bins in the channel response.
Channels Used
Total Symbols
Errors
Symbol Error Rate
Data Rate
Large Room
112
10080
0
le-4
538 Mbit/s
Channels Used
Total Symbols
Errors
Symbol Error Rate
Data Rate
Laboratory
77
6930
0
2e-4
370 Mbit/s
Table 5.2: Performance summary for transmission over im.
75
Z
_'
-a--
ANEE
5
5
-w
0
0.
.. . ...
...........
-..
. .....
...
-5
-5
0
-10
-10
-15
-15
-20
-20
-25
-60
-40
20
0
Bin
-20
40
..
-... .
-25
60
40
20
0
-20
-40
60
Bin
20
20
..
. .....
10
. .. ...
....
.
0
10
wse
@D4
..
. ........
bO
0
01p
e
*
10 s e te#
-10
-10
-
-20
-10
0
real
10
,
-20
20
.
0
-10
. .. .
10
20
real
(b)
(a)
Figure 5-6: Channel Response and received constellations for 7m transmission in (a)
a large room and (b) a laboratory.
Channels Used
Total Symbols
Errors
Symbol Error Rate
Data Rate
Large Room
70
6300
0
2e-4
336 Mbit/s
Channels Used
Total Symbols
Errors
Symbol Error Rate
Data Rate
Laboratory
50
4500
6
1.3e-3
240 Mbit/s
Table 5.3: Performance summary for transmission over 7m.
76
5
5
0
0
-5
-5
.. . . .
-.
z -10
-10
-15
<-15
-20
-20
-25
-25
-60
-40
20
0
-20
40
60
I,
-60
-40
10
I
--
-.
20
*AA
db 0
.
60
10
0
0
-10
-10'
-20
-240
40
20
20
9b:
4b
0
-20
Bin
Bin
0e
20'
0
-10
10
-2 0
20
real
4
14
0
-10
10
20
real
(b)
(a)
Figure 5-7: Channel Response and received constellations for 4m transmission in (a)
a large room and (b) a laboratory. Laboratory transmission was not line-of-sight, but
through a large lab bench.
Channels Used
Total Symbols
Errors
Symbol Error Rate
Data Rate
Large Room
65
5850
1
2e-4
312 Mbit/s
Channels Used
Total Symbols
Errors
Symbol Error Rate
Data Rate
Laboratory
50
4500
14
3. le-3
240 Mbit/s
Table 5.4: Performance summary for transmission over 4m.
77
The measurements shown in this chapter provide some insight into the nature of
the wireless channel. In a large room with the nodes closely placed, minimal multipath is expected and henceforth the channel response does not contain significant
nulls. In the remaining cases, however, the channel experiences significant multipath
demonstrated by the peaks and nulls in the response. The similarity in the response
between the crowded environment and the large room suggest that there is no difference between the two. Despite the apparent similarity in the frequency selectivity,
the lab environment consistently required more VGA gain implying that the input
signal and henceforth the overall SNR was lower for that environment. The tables
furthermore indicate that fewer bins were selected for use in the crowded environment
and that the symbol error rate was not always less than 10'.
One important conclusion that can be drawn from these measurements is the
necessity of adaptive modulation. If not utilized, the bins experiencing nulls will produce errors and significantly increase the symbol error probability beyond acceptable
levels or the data rate must be reduced.
One final measurement presented in this section shows the effect of time passage
on the channel response. Figure 5-8 shows 4 measurements of the channel response
taken in a large room with the nodes placed 4m apart.
The measurements were
taken 1 minute apart. No significant change is seen between the plots. Channel
estimation, however, must still be performed frequently due to movement of other
objects including people which can change the response.
78
I -- - -
--
-
0'
S-10
..
S-15
..
-20
-25'
-10
15
... . .. . . ..
0
Bin
-50
20
.. . .. ...-
-25'
50
5.. .
5
-25,
50
. . .. .. . . .. .. . .. .. . ..
-5
S-5
S-10
0
Bin
-50
10
....
-25'
5000
5
0
50
Figre -8:Channel measurements at 4m taken 1 minute apart.
79
- -- - , -
W.
"-, io4
80
Chapter 6
Analysis and Conclusions
6.1
Maximizing Data Rate Through Adaptive Modulation
Chapter 5 demonstrated successful reception of data at various distances and environments. Adaptive modulation was applied by selecting bins with an SNR above
28dB and identifying them as "used bins". The choice of 28dB differs from the typical
24dB of SNR required to detect 64-QAM with a 10
3
symbol error rate. Aside from
providing an error margin, the choice of 28dB also accounts for the fact that the fine
phase tracking algorithm does not always pick the optimal rotation angle.
In a similar fashion, the system could have sent 16-QAM or 4-QAM constellations
and performed the same measurements.
In this case, however, the threshold for
"used bins" can be chosen lower due the larger noise that can be tolerated in these
constellations and as a result, more bins are included. In this section we attempt to
show the potential data rate that can be achieved using different adaptive modulation
schemes.
The symbol error probability vs. SNR waterfall plot of symbols transmitted over
an AWGN channel is shown in Figure 6-1.
The SNR values needed for successful
detection of 64-QAM, 16-QAM and 4-QAM with symbol error rate of 1018dB, and 10dB respectively.
81
are 24dB,
.. . . . .
10
......... 4-QAM
...
16-Q A M .
............
..
....
..I.
6-QAM
.......
256 QAM
.... ..
......*
10
0
10
. .. . .
.... .....
-3
0
5
10
20
15
25
30
35
SNR(dB)
Figure 6-1: Waterfall curves plotting the symbol error rate vs. SNR for various
constellation sizes.
The previous chapter used 28dB as the threshold for determining which bins to
include when sending 64-QAM. It is now assumed that this threshold value should
be 22dB and 14dB for 16-QAM and 4-QAM. Figure 6-2 shows the measured SNR
per bin of a packet consisting of 45 OFDM symbols transmitted over 7m. The black
horizontal lines correspond to the 3 threshold values.
Table 6.1 shows the potential data rate achieved for various adaptive modulation
schemes: In each bin, the transmitter sends 64-QAM or nothing, 16-QAM or nothing,
or 4-QAM or nothing. The total data rate for each is given by:
DataRate = log. M.
e
(6.1)
1.25s
where 1.25pis is the symbol time including the cyclic prefix, M is the constellation
size, and binsUsed are all the bins who's SNR value is above the threshold. The final
line shows the data rate when the constellation size can be adapted to any of the 3
values yielding maximum throughput. (119 is the maximum number of bins that can
be used for data.)
82
-- --
-------
---
I
35
. .. .
-..
. .. .
30-A
25-
-..-
-
z4
-V
20 --
15 V
10
0
-50
50
Bin
Figure 6-2: SNR per bin of the received signal over 7m. The horizontal lines represent
threshold values that determine which bins are used in different adaptive modulation
schemes.
It can be observed through Table 6.1 that the optimal modulation scheme (with
the exception of the last) highly depends on the quality of the channel, and more
specifically, on the SNR received per bin. Though dropping from 64-QAM to 16QAM results in only 4 bits per symbol instead of 6, 48 additional bins are now
available for use and the data rate is increased. If the analysis were done for data
of
transmitted over 1 meter, it is expected that almost all the bins would be capable
detecting 64-QAM constellations and a reduction to 16-QAM would cut the data rate
by 33%. On the other hand, if data were sent over 10 or 12 meters, then dropping
Bins Used
Adaptive Modulation Scheme
64-QAM or Nothing
16-QAM or Nothing
4-QAM
64-QAM, 16-QAM, 4-QAM or nothing
70
118
119
119
Data Rate
336
377
190
491
Mbit/s
Mbit/s
Mbit/s
Mbit/s
Table 6.1: Performance analysis for OFDM symbols experiencing SNR/bin plot shown
in Figure 6-2.
83
,
-t t
-
down to 4-QAM is quite helpful because many more bins could be used compared to
the case of 16-QAM.
Throughput is of course maximized when the adaptive modulation scheme allows
for maximum flexibility. Recall, however, that in a real-time adaptive modulation
system, the receiver must relay the information back to the transmitter.
If each
bin can contain one of 4 possible modulation schemes, the information needed to be
relayed back to the transmitter is much larger and system complexity is increased.
6.2
Conclusion
This work demonstrated a functioning transceiver prototype capable of transmitting, receiving and detecting data successfully over 7m at data rates ranging from
200Mbit/s to 600Mbit/s. The transceiver acts as a prototype through which channel
measurements can be conducted.
The measurements in Chapter 5 showed that the 5GHz channel, when observed
over 128MHz of bandwidth, is quite frequency selective. The variation between the
tallest peaks and deepest valleys of the magnitude response, as well as the data rate
achieved depends on the distance between the nodes and the wireless environment.
In addition, it was explained that in order to maximize throughput, some form
of adaptive modulation scheme must be used. This result is due primarily to the
high probability of the channel experiencing large nulls produced by the inherent
multi-path found in the channel.
6.3
Future Research
This prototype, though capable of transmitting and receiving data at high rates, was
far from ideal and the potential for improvement exists.
Chapter 3 noted that the receiver sensitivity is severely limited by the large SNR
requirement and the wide bandwidth of 128MHz. Multiple Input Multiple Output
(MIMO) techniques could be used to improve the receiver sensitivity. Having multiple
84
antennas can reduce the SNR required to detect a given constellation, and allow for
operation with lower receiver input signal power. This improved sensitivity can help
increase the data rate or the transceiver range.
The strict linearity requirements addressed in this work force the use of power
amplifiers with very low efficiency. Various PA linearization techniques can be employed so the system can amplify linearly while maintaining low power consumption.
In addition to the potential power reduction, the output power can be increased and
larger transmit distances can be achieved.
More robust DSP algorithms can help increase the data rate or reduce the symbol
error probability. A reduction in the cyclic prefix length will allow for a higher data
rate. An improved channel estimator and a more robust phase tracking algorithm
will improve the received SNR and henceforth reduce the symbol error probability.
Also, in a real-time system, the inherently large PAPR must be either reduced or
properly handled.
Finally, in order to reduce cost, area, and power, it is useful to integrate the design.
An integrated design will facilitate the use of the WiGLAN adapter in a larger variety
of devices particularly in battery-powered mobile applications.
85
86
Appendix A
Circuit Schematics and PCB
Layout
Figures A-1, A-3, A-2 and A-4 show schematics of circuitry located on the main RF
front-end PCB. Figures A-5 and A-6 contain schematics of the DACs and ADCs.
Figure A-7 shows the top and silk layers of the RF front-end PCB. The board is
made from Rogers' R04003 material and is 0.02" thick. The bottom layer (with the
exception of a few locations) is covered by a ground plane. Power is provided through
regulators located on a separate PCB. The required supplies are 1OV, 5V and 3V.
Figures A-8 and A-9 show the top and bottom layers of the data converter PCB.
The board is made from FR4 material and consists of 4 layers. Layer 2 and 3 are the
ground plane and power plane respectively. Power is provided to this PCB through 3
separate on-board 3.3V voltage regulators used for analog signaling, digital signaling,
and clock generation. A fourth regulator is located on this PCB and is used to supply
the 3.3V needed by the power amplifier.
Figures A-10 through A-14 list the bill of materials for this design.
87
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94
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96
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97
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Figure A-11: Bill of materials for RF front-end, continued.
98
Bill of Materials
for Data Converter PCB
C60.
CAP_6036
ComponentName
RefDes
PattemName Value
AD9480
U1.
U5.
U1
U2
C3.
C5.
C6.
TQFP44
-------------171
AD9573
(D
CAP 4025
------------- --------------- ----------- --CAP_603B
LOFP48
402B
O.1uF
CAP_603B
CAP_603B
C9
C12.
C17.
CAP_603B
C18.
C19.
C20.
C21.
C22.
C23.
C25
C26
(D
'-1
CAP_402B
n)
CAP_6038
CAP_603B
CAP_603B
CAP_603B
603B
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603B
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6036
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603B
x
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27p
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603B
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C25.
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402B
x
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Figure A-13: Bill of materials for data converter PCB, continued.
100
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Figure A-14: Bill of materials for data converter PCB, continued.
101
102
Appendix B
PLL Parameters
B.1
PLL Design
The phase locked loop used to generate the 4.664GHz was designed using PLL Design
Assistant. A second order type II PLL was selected with a butterworth type
loop
filter response.
The input parameters are listed in Table B.1:
Bandwidth, f.
20kHz
fZ/fO
1/4
Parasitic Pole
PFD
Synthesizer noise floor
VCO noise (dlOkHz)
210kHz
22MHz
-84dBc/Hz
-84dBc/Hz
Table B.1: PLL design assistant input parameters
The output parameters are summarized in Table B.2
K
3.75e+09
f,
51.3Hz
f., 5.OkHz
Table B.2: PLL design assistant output parameters
The remaining parameters are shown in Table B.3. R 1 , C1, C2, Rp and Cp are
103
derived based on the following equations:
KLP =
27rfz =
KN(B.1)
KI,a
1
R1
KLP
1
1
R1(C1||C2)
27rfp =
=
+
C1 + C2
N
212
Kv
209MHz/V
Ce
Ic,
C1
C2
1
1.85mA
0.44piF
66Q
45.6nF
Cp
Rp
1.4nF
1.OkQ
R1
(B1
(B.2)
(B.3)
(B.4)
Table B.3: Other PLL parameters
B.2
Programming the PLL
The PLL was programmed through an FPGA and required 3 separate inputs consisting of a clock, data, and latch. 4 registers with 24 values in each are programmed
serially through the data port. Once 24 bits are serially entered, the latch input
latches the values. The primary values programmed were R, P, B and A where
N
fPFD
=
PB+A
(B.5)
=
16-13+4
(B.6)
=
fREF
(B.7)
104
Appendix C
Acronyms
ACPR
Adjacent Channel Power Ratio
ADC
Analog-to-Digital Converter
AWGN
Additive White Gaussian Noise
BPSK
Binary Phase-Shift Keying
DAC
Digital-to-Analog Converter
dBFS
decibels below full scale
DFT
discrete fourier transform
DSP
Digital Signal Processor
ENOB
effective number of bits
FCC
Federal Communications Commission
FFT
fast fourier transform
FPGA
Field Programmable Gate Array
ICI
inter-carrier interference
IF
intermediate-frequency
105
IDFT
inverse discrete fourier transform
IFFT
inverse fast fourier transform
11P3
3rd input intercept point
I/Q
in-phase/quadrature
ISI
inter-symbol interference
ISM
Industrial, Scientific and Medical
LNA
low noise amplifier
LO
local oscillator
LVDS
low voltage differential signaling
MSPS
Mega Samples per Second
NF
noise figure
OFDM
Orthogonal Frequency Division Multiplexing
PA
power amplifier
PAPR
peak-to-average power ratio
PCB
printed circuit board
PFD
phase/frequency detector
PLL
phase locked loop
PPM
parts per million
QAM
Quadrature Amplitude Modulation
QPSK
Quadrature Phase Shift Keying
RF
radio-frequency
106
SINAD
signal-to-noise and distortion
SNR
signal-to-noise ratio
VGA
variable gain amplifier
WiGLAN Wireless Gigabit LAN
WLAN
wireless local area network
107
108
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