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Electronic Systems for Interfacing with
New Materials and Devices
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by
Sungjae Ha
B.Eng., Pohang University of Science and Technology (2009)
S.M., Massachusetts Institute of Technology (2011)
Submitted to the Department of Electrical Engineering and Computer
Science
in partial fulfillment of the requirements for the degree of
DOCTOR OF PHILOSOPHY
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
June 2015
@
Massachusetts Institute of Technology 2015. All rights reserved.
Sig nature redacted
Author ..
Department of Electrical Engineering and Computer Science
May 20, 2015
Certified by.
Signature redacted
Anantha P. Chandrakasan
Joseph F. and Nancy P. Keithley Professor
Thesis Supervisor
Signature redacted
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Accepted by
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.....................
Tomis Palacios
Associate Professor
Thesis Supervisor
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Certified by.
....... Signature redacted ............
lalie A. Kolodziejski
Chair, Departmental Committee on Graduate Theses
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Electronic Systems for Interfacing with
New Materials and Devices
by
Sungjae Ha
Submitted to the Department of Electrical Engineering and Computer Science
on May 20th, 2015, in partial fulfillment of the
requirements for the degree of
DOCTOR OF PHILOSOPHY
Abstract
The focus of this thesis is to explore and demonstrate electronics systems utilizing
new materials and devices beyond the traditional ones solely based on Si CMOS
technology. The first part of this thesis is to explore the combination of Bio-MEMS
devices with traditional electronics as an effective diagnostic tool. In the case study
of malaria, we report a microfluidic device as part of a continuous-flow cellular
impedance spectroscopy system and a new data analysis method to differentiate Plasmodium falciparum-infected human erythrocytes including the early ring stage. The
next parts of this thesis focus on two-dimensional (2D) materials which are believed
to be a tool set for future electronics. In particular, graphene is explored as a new
infrared sensitive material that can be used for sensors in mid- and long-wavelength infrared spectrum (A = 2- 15pm) imaging systems. We demonstrate a Si CMOS-based
readout IC and monolithic integration of an array of > 4000 electronically tunable
graphene thermocouples. The prototype system shows that use of 2D material as
add-on parts of the conventional technology can lead to development of new types of
electronic applications. In addition to combinational uses with Si CMOS technology,
2D materials and their heterostructures have the potential to be used as stand-alone
electronic systems. In the latter part of the thesis, we present a computer-aided design (CAD) flow for large-scale MoS 2 electronics. Combined with the state-of-the-art
fabrication technology and the physics-based device model for MoS 2 FETs, a switched
capacitor DC-DC converter, a half-wave rectifier, and a voltage doubler are implemented, and good agreement between simulation and measurement is observed. The
presented CAD flow enables large-scale integrated circuit design on MoS 2 technology
and paves the way for ubiquitous, flexible and possibly transparent electronics, such
as printed RFID tags and transparent display drivers. Utilizing these design concepts,
we push the capability of current electronics beyond its traditional boundaries.
3
Thesis Supervisor: Anantha P. Chandrakasan
Title: Joseph F. and Nancy P. Keithley Professor
Thesis Supervisor: Toma's Palacios
Title: Associate Professor
4
Acknowledgments
First and foremost I would like to thank my advisors, Professor Anantha Chandrakasan and Professor Tomas Palacios, for their unceasing care, inspiration, and
guidance over the years. I appreciate the priviledge to work with Anantha and Toma's;
I cannot imagine my journey to Ph.D. without their mentorship. I would also like to
thank my thesis committee, Ming Dao, not only for his time and dedication to this
thesis but also for his caring and cheerful comments throughout the years. It had
been a great pleasure to collaborate with Ming during my Master's and Doctorate
study.
To Sarah E Du and Monica Diez-Silva, I am very thankful to have worked with
them in such interesting interdisciplinary topic. I also want to show my deep appreciation to Allen L. Hsu, Charles Mackin, Cosmi Yuxuan Lin, and Marek Hempel, for
they have spent days and nights in the fab with me and without me. I appreciate
Yi Song, Wenjing Fang, and Xu Zhang for FIB and Raman spectroscopy assists; I
must have bothered them so much. To Lili Yu, nothing would have been possible
without her dedication and great fab works. I thank Amir, Daniel, Min, Ahmad, and
everyone else in Palacios group.
To Arun Paidimarri and Philip Nadeau, I would like to express special thanks for
being with me for past years with the wonderful friendship. To Frank Yaul, it has
been such a pleasure to have such a wonderful cube-mate with full of academic curiosity, and I also thank Dina El-Damak for great collaboration. I thank Hyung-Min,
Dongsuk, Nachiket, Mehul, Georgios, Avishek, Chuhong, Preet, Chiraag, Bonnie,
Sirma, Michael, Gilad, Priyanka, Nathan, Saurav, Marcus, Masood, Margaret, Andreina, and all other ananthagroup members. Pursuing Ph.D. is at times a solitary
one, but I am honored to have worked with many brilliant people.
To my dear friends, I especially thank Yongjoo Kim, Jeongwon Lee, and Changmin
Lee for going through my most difficult moments together. I also thank Chung Jong
5
Yu, Hyangsoo Jeong, Jouha Min, Jeremy Lee, David T. Kim, Hyun Ho Boo, Sung
Sik Woo, Donghun Kim, Grace Han, Hokyung Choi and Bon Jun Koo for their
great friendship. I also want to express my warm thanks to KGSA, KGSA-EECS,
POSTECH alumni, and UNITAS for sharing and supporting my life at MIT.
I acknowledge Fulbright Science and Technology Award for financial support.
Prof. Sung Jae Kim, Prof. Jongyoon Han, Prof. YongKeun Park and Prof. Subra
Suresh helped in the initial system development and discussion in background experimental work. I also acknowledge MIT Center for Integrated Circuits and Systems
and Institute for Soldier Nanotechnology for their fundings. The readout IC fabrication was supported by Taiwan Semiconductor Manufacturing Company Limited's
University Shuttle program. Other fabrications were carried out at MIT Microsystems Technology Laboratories and US Army Research Laboratory. I would like to
thank Prof. Jae-Yoon Sim, Prof. Byungsub Kim, and Taeyoung Chung for fruitful
discussions.
Internship at Samsung Advanced Institute of Technology and Maxim Integrated
has taught me in-field design experience; I enjoyed practicing and excerising circuit
design for commercial ICs. In addition, Rev. Dominic Jung, Haepyoung Chung, and
Sangbeom Kim were my dearest mentors during my life in Boston. In addition, I
want to thank Dr. Austin Patrick Egan at MIT Medical.
Moreover, my forever appreiciation goes to my family. My wife, an exceptional
violinist, Dr. Yura Hyun, thank you for always standing by my side during this lone
journey to dissertation. Since I am yours and you are mine, our cozy little world has
become twice as nice. I appreciate my lovely daughter, Irene, for she has taught me
what a daily progress meant and how much my father had loved me. My mother,
Myungja Kim, who has raised me to be a sincere person, always gives me warm comfort, and my sister, Salim, also has been a big support. In addition to them, I give
thanks to all my family members who have sent endless love, care, and prayers from
Korea, Saudi Arabia, and Boston.
6
Cleanse me with hyssop, that I may be pure;
wash me, and I will be whiter than snow.
You will let me hear gladness and joy;
the bones you have crushed will rejoice.
Psalm 51:9-10
Sungjae Ha
Cambridge, MA
MAY 20th 2015
7
S
Contents
23
1 Introduction
2
1.1
Materials and Devices for Next-Generation Electronics
. . . . . . . .
23
1.2
Challenges in System Design with Emerging Technologies . . . . . . .
26
1.3
Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
Cellular Electric Impedance Spectroscopy for Characterization of
29
Malaria States
2.1
2.2
2.3
2.4
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
2.1.1
Cellular Electric Impedance Spectroscopy . . . . . . . . . . . .
29
2.1.2
Disease States of Malaria and Detection Target for Early Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
Materials and Methods . . . . . . . . . . . . . . . . . . . . . . . . . .
32
2.2.1
Microfluidic Probe Device Fabrication . . . . . . . . . . . . . .
32
2.2.2
Malaria-Infected Human Erythrocyte Sample Preparation
. .
32
2.2.3
Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . .
34
Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . .
35
2.3.1
Data Acquisition and Preprocessing . . . . . . . . . . . . . . .
35
2.3.2
Analysis with a Dimensionless Parameter 6 . . . . . . . . . . .
39
2.3.3
Effect of BSA Concentration in Buffer Solution
. . . . . . . .
42
Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
Graphene-Silicon Hybrid IC for Thermal Imaging
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
47
47
48
3.1.2
Photovoltaic and Photoconductive Detectors . . . . . . .
3.1.3
Thermal Detectors
.
.
.
52
.
. . .
50
53
. . . . . . . . . . . .
54
3.3.1
Readout IC Architecture . . . . . . . . . . . . . . . . . .
54
3.3.2
Sub-Block Designs
. . . . . . . . . . . . . . . . . . . . .
56
3.3.3
Considerations for Back-End Graphene Sensor Integration
66
.
Mechanically Suspended Graphene Thermocouples
50
Graphene-CMOS Hybrid Infrared Imager . . . . . . . . . . . . .
68
3.4.1
.
3.4
. . . . . . . . . . . . . . . . . . . . .
Graphene for Photosensing . . . . . . . . . . . . . . . . . . . . .
3.2.1
68
.
Readout IC for Graphene IR Sensor Array
.
3.3
.
History of Electronics for Infrared Sensing . . . . . . . .
.
3.2
3.1.1
Graphene Thermocouple Device for On-Chip Integration
an
3.7
73
3.5.1
ADC Characterization . . . . . . . . . . . . . .
. . . . . . .
73
3.5.2
Pseudo Photoresponse Measurement
. . . . . .
. . . . . . .
77
3.5.3
Off-Chip Graphene Thermocouple Measurement
. . . . . . .
77
3.5.4
Integrated Graphene Sensor Array Measurement
. . . . . . .
81
D iscussion . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . .
87
3.6.1
Graphene Models for Pixel Readout . . . . . . .
. . . . . . .
87
3.6.2
Power Line Shorting Issues . . . . . . . . . . . .
. . . . . . .
91
3.6.3
Revised Metalization . . . . . . . . . . . . . . .
. . . . . . .
94
Concluding remarks . . . . . . . . . . . . . . . . . . . .
. . . . . . .
98
.
.
.
.
.
.
. . . . . . .
.
3.6
M easurements . . . . . . . . . . . . . . . . . . . . . . .
.
3.5
4 MoS 2-Based Next Generation Electronics
. . . . . . . . . . . . .
99
4.1.1
Demands for MoS 2-Based Electronics
. . . . . . . . . . . . .
100
4.1.2
Material Growth
. . . . . . . . . .
. . . . . . . . . . . . .
100
4.1.3
Device Fabrication
. . . . . . . . .
. . . . . . . . . . . . .
101
4.1.4
Design Flow . . . . . . . . . . . . .
. . . . . . . . . . . . .
102
Computer-Aided Design Flow . . . . . . .
. . . . . . . . . . . . .
104
.
.
.
.
4.2
Introduction . . . . . . . . . . . . . . . . .
.
4.1
99
10
4.3
4.4
5
4.2.1
Modeling of MoS 2 -Based Devices . . . . . . . . . . . . . . . .
105
4.2.2
Technology Library and Parameterized Cell for MoS 2 Layout
110
Circuit Design Demonstration . . . . . . . . . . . . . . . . . . . . . .111
. . . . . . . . . . . . .111
4.3.1
Switched Capacitor DC-DC Converter
4.3.2
Half-Wave Rectifier . . . . . . . . . . . . . . . . . . . . . . . .
115
4.3.3
Voltage Doubler . . . . . . . . . . . . . . . . . . . . . . . . . .
117
Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . .
118
Outlook and Future Work
5.1
5.2
121
Thesis Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . .
121
5.1.1
Cellular Electric Impedance Spectroscopy . . . . . . . . . . . .
121
5.1.2
Graphene-Silicon Hybrid Infrared Imager . . . . . . . . . . . . 122
5.1.3
MoS 2 -Based Electronics
. . . . . . . . . . . . . . . . . . . . .
124
Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.2.1
2D Scan Imaging with Graphene Thermocouple Array
. . . .
125
5.2.2
MoS 2 RFID Tags . . . . . . . . . . . . . . . . . . . . . . . . .
126
5.2.3
MoS 2 Display Driver . . . . . . . . . . . . . . . . . . . . . . .
129
Appendices
130
A Process Flow
131
A.1
EIS Probe Device Fabrication . . . . . . . . . . . . . . . . . . . . . .
131
A.2 Graphene IR Imager Integration . . . . . . . . . . . . . . . . . . . . .
134
A.3 MoS 2 Device Fabrication . . . . . . . . . . . . . . . . . . . . . . . . .
143
B Test Setup and PCB Design
B.1 PCB Designs
145
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C CAD Environment
145
153
C.1 Model Implementations for MoS 2 Devices . . . . . . . . . . . . . . . .
153
C.2 Technology Library for MoS 2 Device Layout . . . . . . . . . . . . . .
160
162
Bibliography
11
12
List of Figures
1-1
Illustration of a Bio-MEMS device for electric impedance spectroscopy
of red blood cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
Illustration of monolayer graphene (top) and molybdenum disulfide
(bottom ).
2-1
24
. ..
...
.. ..
. . . . . ..
. . . . . ..
. . ..
. .. .. .
25
Asexual intraerythrocytic phase of the life cycle of Plasmodium f alciparum
m alaria parasite [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
2-2
Fabrication of microfluidic probe chip [2] . . . . . . . . . . . . . . . .
33
2-3
Measurement setup of microfluidic EIS of malaria infected human blood
sam ple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
2-4
Dynamic impedance transitions at cell passage over probe electrodes .
35
2-5
Overlaid transient El results of uninfected RBCs and Pf-iRBCs crossing over the electrodes with the measurement conditions: 2MHz 1Vpp
and 0.2% (w/v) BSA-PBS. . . . . . . . . . . . . . . . . . . . . . . . .
2-6
Scatter plot of 113 El data (Ap, AM) consisting of 78 uninfected
RBCs, 12 ring stage iRBCs, and trophozoite stage iRBCs.
2-7
37
. . . . . .
38
Block diagram of cellular impedance measurement setup and simplified
cellular circuit model. A simplified cellular impedance model is shown
in the inset. The extraction of model parameters requires an excitation
source with variable frequency. . . . . . . . . . . . . . . . . . . . . . .
2-8
38
Scatter plot of normalized EI transitions of uninfected RBCs in three
different BSA-PBS concentrations . . . . . . . . . . . . . . . . . . . .
13
40
2-9
Scatter plot of normalized El transitions for 0.2% BSA-PBS condition
and definition of an offset parameter 6
. . . . . . . . . . . . . . . . .
40
2-10 Statistical box chart of two-sample t-test for 6's collected from the
Pf-iRBC sample in 0.2% BSA-PBS concentration . . . . . . . . . . .
41
2-11 Statistical box chart of two-sample t-test for 6's collected from the
Pf-iRBC sample in 0.5% BSA-PBS concentration . . . . . . . . . . .
42
2-12 Statistical box chart of two-sample t-test for 6's collected from the
Pf-iRBC sample in 1.0% BSA-PBS concentration . . . . . . . . . . .
3-1
(a) Illustration of the MEMS-enhanced graphene thermopile.
43
Small
holes in the center of the infrared absorber are meant to facilitate suspension of the thermal isolation stack, while the large openings along
the periphery help define the thermal isolation legs. (b) The measured
signal shown as a function of actuator position. The thermal image
was formed by placing a laser cut stainless steel aperture in front of
the blackbody source (T = 472 K, fmod = 173 Hz) and scanned in
position using a series of motorized X-Y translation stages. The step
size was 0.5 mm and the integration time was 3 s per pixel [3,4]. . . .
3-2
Conceptual floorplan for integrated graphene IR imager.
54
An array
of 80 by 60 graphene thermocouple pixels is fabricated on top of the
Si-CMOS readout IC. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
55
Schematic of an imager block consisting of 8-column by 60-row pixel
amplifiers, a 8-to-1 MUX, a variable gain amplifier, and an ADC. The
prototype chip consists of 10 of this imager block that complete a 80
x 60 pixels image sensor. . . . . . . . . . . . . . . . . . . . . . . . . .
3-4
55
Circuit model of a graphene photodetector and a transimpedance amplifier. The transimpedance amplifier converts the input current (In)
3-5
into the output voltage (V) by a conversion gain. . . . . . . . . . . .
56
Illustration of photo-signal modulation and extraction scheme. .....
57
14
3-6
(a) Schematic of the proposed pixel transimpedance amplifier. The bias
tail current is set to satisfy the current deviation less than 1% of the
bias current. The matching of g, thus minimizing Zi, has fine-tune
control by the VB node. (b) Simulated input impedance adjustment of
the PTIA with VB range from 1.1V to 1.8V across the process corners.
58
3-7
Schematic of Successive Approximation Register ADC.
61
3-8
Simulated DNL and INL of the capacitive DAC across 8 bit digital
. . . . . . . .
codes. IDNLIMAX < 0.04 and IINLMAx < 0.07 are achieved. ....
3-9
Timing diagram of the implemented successive approximation logic
62
.
63
3-10 Schematic of a testbench for imager block readout simulation. 8 graphene
pixels with unique
(R-PD
=
'ph
values (0 - 12 nA) and low output impedance
150 Q) were assumed. . . . . . . . . . . . . . . . . . . . .
3-11 Simulated Photoresponse Readout of Multiple Pixels
. . . . . . . . .
64
65
3-12 Die photo of the readout IC for graphene-CMOS hybrid IR imager.
The chip shown is before the integration of graphene thermocouples. .
67
3-13 Diagram of a graphene thermocouple fabricated on top of the CMOS
substrate.
Two gate metal lines are embedded in Si0 2 passivation
layer for electrostatical doping of MLG, and the ohmic contact and
plug ensure electrical connection to the pixel amplifier.
. . . . . . . .
69
3-14 Fabrication processes for integrated graphene IR imager chip (1)-(4)
.
70
3-15 Fabrication processes for integrated graphene IR imager chip (5)-(8)
.
71
3-16 Die photos of the fabricated graphene IR imager prototype chip (left)
along with the original die for comparison (right)
. . . . . . . . . . .
72
3-17 Close-up micrographs of the pixel area shows the fabricated structures, including monolayer graphene, ohmic contacts, and back gates
for graphene thermocouple array.
. . . . . . . . . . . . . . . . . . . .
72
3-18 Measured linearity of ADC at the sampling rate of 800 kSPS. |DNL| <
0.3 LSB and JINLI < 0.4 LSB across all 8 bit digital codes are achieved. 73
3-19 Measured linearity of ADC at the sampling rate of 800 kSPS. IDNLI <
1 LSB and IINLI < 1 LSB across all 8 bit digital codes are achieved. .
15
74
3-20 FFT plot of ADC output code at 240 kSPS where input tone is at
1.952 kH z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
3-21 Measured ENOB of ADC . . . . . . . . . . . . . . . . . . . . . . . . .
75
3-22 Power consumption of ADC . . . . . . . . . . . . . . . . . . . . . . .
76
3-23 (a) Schematic diagram of pseudo photoresponse measurement shows
test setup, and (b) sub-nA resolution is measured with linear input
current range of 160 nA. . . . . . . . . . . . . . . . . . . . . . . . . .
77
3-24 Schematic diagram (top) and photograph (bottom) of discrete graphene
thermocouple measurement setup . . . . . . . . . . . . . . . . . . . .
3-25 FFT plot of the photoresponse measured at Pi,
=
157 puW and
78
=
fmod
250 Hz input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
3-26 Estimated photoresponse amplitudes at various Pj,'s by integrating
power spectral density of the signal peak at fmod= 2 5 0 Hz . . . . . . .
80
3-27 Average output code measured at various Pi's. The signal nature
that only non-negative response is generated allows the photoresponse
estimation by simple averaging. . . . . . . . . . . . . . . . . . . . . .
81
3-28 Micrograph of delaminated graphene layers in thermocouple array
.
82
3-29 Raman spectroscopy of graphene layers of on-chip thermocouples.
.
83
3-30 Raman spectroscopy of graphene layers of on-chip thermocouples shows
electrostatical doping of graphene. . . . . . . . . . . . . . . . . . . . .
84
3-31 Measurement setup for graphene-integrated sensor chip. The sensor
chip is sealed with a vacuum cap for stable performance. The beam
shares the same path described in Figure 3-24. . . . . . . . . . . . . .
85
3-32 IR beam spot size at the focal plane was measured by burn marks
of thermal paper and found to be ~30 pm in diameter, which allows
in-pixel local heating for thermoelectric effect. . . . . . . . . . . . . .
85
3-33 Graphical user interface for IR detection experiment showing output
FFT plot centered at the light modulation frequency (center) and 2-D
colored map for array readout. . . . . . . . . . . . . . . . . . . . . . .
16
86
3-34 Signal peak values extracted from FFT of the photoresponse measured
by an graphene-integrated readout IC show a linear relationship to
.
laser excitation duty cycle. . . . . . . . . . . . . . . . . . . . . . . .
86
3-35 Readout architecture with pixel transimpedance amplifier and Norton
equivalent circuit model of the graphene photodetector. Contact resis.
tance is neglected .. . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
3-36 Readout architecture with pixel transimpedance amplifier and Thevenin
.
equivalent circuit model of graphene photodetector. . . . . . . . . .
88
3-37 Readout architectures with pixel transimpedance amplifier including
. . . . . .
.
contact resistance from ohmic metal-graphene junctions.
88
3-38 Illustration of a single-junction model (left) and a parallel multi-junction
.
m odel (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
3-39 Schematic circuit of a series multi-junction model (left) and its illus.
tration (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
3-40 Scratches occurred during graphene integration process; Narrow spac.
ing in top metal layout should be avoided. . . . . . . . . . . . . . .
92
3-41 Scratches and excessive metal residue at pad region cause electrical short 93
94
3-43 SEM image of a FIB cut near pad region . . . . . . . . . . . . . . .
94
3-44 SEM image of disconnected metal routing at dummy gap region . .
95
3-45 SEM image of metal-filled gap in the dummy metal region
96
.
.
.
3-42 Excessive graphene residue at pad region cause electrical short. . . .
.
. . . . .
be either of 300 or 60 .. . . . . . . . . . . . . . . . . . . . . . . . . .
.
97
3-47 SEM image showing sidewall coverage from tilted metal deposition.
.
3-46 Aluminum wedge piece for tilted metal deposition. The tilt angle can
97
17
4-1
(a) A schematic illustration of the MoS 2 growth by CVD. (b) The
temperature profile for the growth process. [5] (c) Optical micrographs
and thickness profile (inset) of monolayer MoS 2 . (d) High resolution
TEM image and the corresponding selected area electron diffraction
(SAED) pattern (inset) show the hexagonal crystal nature and the
101
4-2
Gate-first fabrication process for MoS 2 FET . . . . . . . . . . . . .
102
4-3
Performance comparison of gate-last and gate-first processes: (a) I-V
.
.
high quality lattice structure [6]. . . . . . . . . . . . . . . . . . . . .
characteristics in linear (right y-axis) and log scale (left y-axis) and (b)
Gate-first devices have average VT of 0.54V with standard deviation of
0.12V while those from gate-last process have average VT of -4.20V
and standard deviation of 175V [6]. .. ............
...
. .
103
4-4
Proposed design flow for large-scale MoS 2 integrated circuit development103
4-5
Gate-Drain connected MoS 2 FET was used as MoS 2 diode. . . . . . . 105
4-6
Fitted diode equation shows a good agreement with the measurement. 106
4-7
High order polynomial equation cannot model the reverse bias diode
current due to its non-monotonicity and large error. . . . . . . . . . . 107
4-8
Comparison plot of MoS 2 FET models . . . . . . . . . . . . . . . . .
4-9
Layout of MoS 2 thin-film transistors (W/L = 40[m/ 4pm and 20pim/2pm)
109
using P-cells in Cadence software. The layer definition is given in the
legend........
....................................
111
4-10 Schematic diagram of the switched capacitor converter and micrograph
of the fabricated converter . . . . . . . . . . . . . . . . . . . . . . . .
112
4-11 Optical Micrograph of the fabricated test chip using CVD-grown monolayer MoS 2 , showing arrays of FETs, diodes and switched capacitor
DC-DC converters
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
113
4-12 Photos of the probe station setup showing (a) an optical microscope
and probe tips (a), and closed up view of ground plate and held chip
(b ,c) . . . . . . . . . . . . . . .. ..
18
. . . . . . . . . . . . . . . . . . .
113
4-13 Simulation (dotted) and measurements (solid) of the output voltage
.
versus the load current of MoS 2 SC DC-DC converter . . . . . . . .
114
4-14 Schematic diagram of testbench for diode rectifier (left) and micro. . . . . . . . . . . . . . . .
.
graph of fabricated MoS 2 diode (right)
115
4-15 Transient waveforms of 1 MHz 8 V,, sinusoidal input and measured
output voltage of the diode rectifier circuit along with the simulated
. . . . . . . . . . . . . . . . . . . . . . . . . .
.
output (dashed line)
116
4-16 Rectifier output at various frequencies at 10 pA load current where
116
4-17 Schematic diagram of voltage doubler circuit . . . . . . . . . . . . .
117
.
7 VP.. and Ct
.
= 10 nF . . . . . . . . . . . . . . . . . . . . .
Vin=
4-18 Voltage doubler outputs at 6 V,_, sinusoidal input and IL = 0.1, 1, 10
118
..................................
3-Phase Development Plan for MoS 2 RFID Tags . . . . . . . . . . .
126
5-2
Illustration of Wireless Power Link Operation with On-Chip Inductor
127
5-3
Simulated transferred power at various coupling coefficient (k) . . .
128
5-4
Full-wave rectifier with cross-coupled FETs and two diodes . . . . .
128
5-5
Testbench of MoS 2 LED driver array . . . . . . . . . . . . . . . . .
129
B-1 PCB for ADC characterization . . . . . . . . . . . . .
. . . . . . . .
146
B-2 Wirebonding Diagram for ADC characterization . . .
. . . . . . . .
147
B-3 PCB for Graphene Sensor Array Test . . . . . . . . .
. . . . . . . . 148
.
.
.
.
.
.
5-1
.
[A..............
B-4 Wirebonding Diagram for Graphene Sensor Array Test . . . . . . . .
149
. . . . . . . . 150
. . . . . . .
. . . . . . . . 151
B-6 Wirebonding diagram for unified testing
19
.
.
B-5 PCB for Unified Testing . . . . . . . . . . . . . . . .
20
List of Tables
. . . . . . . . . . .
26
[7]
49
1.1
Research highlights on 2D-material-based devices
3.1
Comparison table of D* for various infrared detection technologies
3.2
Summary of ADC performance
4.1
Qualitative comparison table of device models . . . . . . . . . . . . . 109
.
. . . . . . . . . . . . . . . . . . . .
21
76
22
Chapter 1
Introduction
The silicon semiconductor industry has been advancing and expanding at an exponential rate over the last few decades, making the silicon CMOS technology used
everywhere. However, no matter how much traditional silicon technology is improving
every year, demands for interfacing materials always exist. Due to the inevitable need
for extra materials or devices, silicon-based electronics have utilized other materials
not only as sensor interfaces, such as biochemical detectors, piezoelectric films, non-Si
solar cells and many, but also in actuator interfaces including MEMS resonators, light
emitting diodes (LEDs), and acoustic speakers.
1.1
Materials and Devices for Next-Generation Electronics
More recently, a broad range of new materials and devices, including nano-materials,
such as quantum dots, carbon nanotube, graphene, hexagonal boron nitride, and transition metal dichalcogenides, have been introduced for a wide range of applications.
First, some of the new materials and devices are capable of providing new features
to the silicon-based electronics, as in the recent demonstrations of carbon nanotube
chemical sensors [8], biological cell interfaces [9-12], DNA-sequencing IC [13] and
many more. In other cases, the non-Si emerging materials and devices have been
23
Figure 1-1: Illustration of a Bio-MEMS device for electric impedance spectroscopy of
red blood cells
adopted for performance improvement of the traditional electronics, as in GaInP/GaInAs/Ge solar cells [14], quantum dot and OLED displays [15,16], MEMS-based
RF oscillators [17,18], high speed graphene interconnects [19], and graphene infrared
detectors [20]. Furthermore, the increasing interest in foldable and lightweight electronic devices has raised the need for new materials more than ever. Alternative
technologies are necessary where applications require the electronic devices to be
flexible and/or transparent such as flexible touch screen displays, flexible solar cells,
printed RFIDs, film speakers, and flexible lightings [21].
Bio-MEMS
Among innovative materials and devices introduced to address new applications,
biomedical (or biological) micro-electromechanical systems (Bio-MEMS) are especially interesting in terms of their unique capability to interface with biological targets.
The Bio-MEMS devices, PDMS-based microfluidic devices in particular, such as illustrated in Figure 1-1, have gained a great interest for their compatibility to biological
targets and effective uses in miniaturized biosensors [12, 22], point-of-care diagnostic
chips [23-25], and other electrophoresis and electric impedance spectroscopy applications [26-28]. Moreover, Bio-MEMS devices are not just limited to discrete parts, as
on-silicon-CMOS integration of microfluidic devices, also, has been explored [29,30].
24
*Mo
Figure 1-2: Illustration of monolayer graphene (top) and molybdenum disulfide (bottom)
Two-Dimensional Materials
Two-dimensional (2D) materials offer excellent mechanical flexibility, optical transparency, and favorable transport properties for realizing electronic, sensing, and optical systems on arbitrary surfaces. As recent research efforts toward 2D-materialbased devices have brought improvements in material growth, switching frequency,
subthreshold slope, on-off current ratio, and complex circuit design (see Table 1.1),
2D materials are believed to bring dramatic changes in the electronics market with
atomically thin, lightweight, bendable, and low-power devices [31]. Among a variety of 2D materials, graphene and MoS 2 , illustrated in Figure 1-2, are exceptionally
attractive from a circuit/system designer's standpoint, since they can be grown in
large sheets and then be subsequently patterned and etched using standard lithography methods, so results in better control and higher reproducibility and possibly
large-scale circuits and system-level demonstrations.
First, graphene is a planar sheet composed of carbon atoms, exhibiting high intrinsic mobility [32,33], high current capacity [34-36], tunable optical absorption [37],
large mechanical strength [38], and most importantly as discussed later in the thesis,
it offers a thermal interface [20,39]. While the majority of graphene research focuses
on methods to improve the material quality or finding innovative device architectures,
25
Table 1.1: Research highlights on 2D-material-based devices
Material
Report
[40]
Graphene
[41]
[42]
Work
Switching device with micromechanical cleavage.
100-GHz electronics based on graphene grown on SiC.
Large-area reproducible monolayer growth by CVD.
This
Large-scale integration with Si CMOS.
h-BN
[43]
[44]
CNT-based TFET with SS < 60 mV/dec.
Atomically thin insulating layer growth on metal.
WS 2
[45]
CVD growth of WS 2 on glass substrate.
WSe 2
[46]
[47]
[48]
[5]
CMOS inverter on WSe 2 flake.
Monolayer MoS 2 flake transistor
Complex circuits based on MoS 2 flakes.
Large-area reproducible monolayer growth by CVD.
Computer-aided design of large-scale CVD-grown MoS 2 IC.
CNT1
MoS 2
This
the research focus must extend to interfacing circuit design and integration with Si
CMOS.
At the same time, monolayer MoS 2 , consisting of molybdenum atoms sandwiched
by two layers of sulfur atoms, exhibits excellent semiconducting characteristics with
the bandgap of 1.8 eV, different from graphene (0 eV) and that of its bulk phase (1.3
eV, indirect). While research efforts in material growth and device fabrication extend
beyond the scope of this thesis, the outstanding maturity of the technology compared
to those of other transition-metal dichalcogenides makes the atomically thin material
ready for system level design.
1.2
Challenges in System Design with Emerging
Technologies
The use of emerging technologies in system level applications can enable gamechanging advantages, such as highly selective sensing of cancer cells, lOx performance
enhancement, drastically improved energy efficiency, and so on. However, while new
materials and devices provide a great tool set for new designs, it is very important
to consider the broad aspects of the interface, which includes that new devices often
1Carbon nanotube is not considered as 2D material.
26
come with highly variable parameters.
For example, in the case of a chemical sensor, when the fundamental sensing
mechanism or noise characteristic of the device are not fully understood, one may
not properly model the device and may end up in a wrong topology for the system.
In addition to that, the sensing mechanism can be altered after the design process is
finished, as technology evolves. In another common case, if the fabrication technology
is immature, the designer may have to deal with the devices with enormous variations.
Therefore, the designer is required to have an excellent understanding of both
readout circuit design and interfacing material/device design. Trade-offs should be
made depending on the degree of uncertainty. For example, if SNR is a concern,
further characterization of the device should be conducted, so that a proper signal
processing scheme (modulation and filtering) can be used to improve SNR. If the
variation between devices is a problem, the readout may be designed to have large
dynamic range at cost of sensitivity and power. Furthermore, the topology should be
determined based on whether the device can be integrated with the readout electronics
or if it is better to have discrete sensor devices. This thesis had to deal with many of
the issues described above.
1.3
Thesis Overview
The thesis explores three applications of new materials and devices at a system level.
Chapter 2 presents an electric impedance spectroscopy system with a microfluidic
probe device to interface with human red blood cells, which aims for more accurate
malaria diagnosis. Chapter 3 discusses a Si CMOS readout IC and its monolithic
integration with a graphene-based thermocouple array to realize a new type of infrared
imager. Chapter 4 introduces integrated circuits based on molybdenum disulfide and
a computer-aided design flow which makes large-scale design feasible. Utilization of
new materials and devices, that can expand the boundary of traditional electronic
systems, is studied along three directions: (1) as discrete add-on devices for sensing,
(2) as monolithically integrated add-ons, and (3) as stand-alone electronic systems.
27
Finally, chapter 5 briefly discusses future work and opportunities.
28
Chapter 2
Cellular Electric Impedance
Spectroscopy for Characterization
of Malaria States
2.1
2.1.1
Introduction
Cellular Electric Impedance Spectroscopy
Cellular electric impedance spectroscopy (EIS) is a technique to measure biochemical changes in live cells and has been widely studied in the development of various
biosensors [49]. The first system in the history of microfluidic single-cell analysis
system is the Coulter counter introduced in 1956 [50] in which the conductivity of a
narrow fluidic channel is monitored to detect the flow of insulating particles or biological cells. While the basic mechanism to monitor the impedance of fluidic channel
remained the same from the Coulter counter, cellular impedance analysis systems
have introduced new concepts such as high frequency and multi-frequency measurement with microfabricated electrodes [51-54], highly confined flow of cells [55], and
digitally coded excitation [56], and thus enabled cell characterization based on cellular electric impedance. As a result of the development of more sensitive analytic
systems, it has been suggested that cellular EIS can offer a fast, effective and low-cost
29
technique for detection of intracellular variation in electrical properties of cells which
may be induced by malaria infection [57,58]. In this thesis, a microfluidic device [2] is
utilized to probe tiny (diameter < 10pm) human red blood cells (RBCs) with an accurate measurement setup, seeking for cellular impedance change induced by malaria
infection.
2.1.2
Disease States of Malaria and Detection Target for
Early Diagnosis
The cause of malaria is Plasmodium parasites. Among four types of Plasmodium
parasites which infect human, P. falciparum is the most common, causing more than
90% of the deaths
[59]. The parasites undergo three reproduction stages after the
invasion: ring, trophozoite and schizont. In most of the real life cases, the parasites
are tranferred by infected female mosquitos and introduced into the blood stream.
They make their first way to the liver to invade liver cells.
Once inside, a single
parasite, also called as a sprozoite, multiplies to produce thousands of merozoites.
They make liver cell swell and, eventually, burst, so that they flow into the circulation
beginning invasion of erythrocytes (RBCs). The asexual intraerythrocytic phase of
the life cycle of Plasmodium falciparum malaria parasite is illustrated in Figure 2-1.
As the parasite invades a human erythrocyte, it forms a spherical shape by engulfing
a portion of erythrocyte cytosol so that in section it appears as a thin ring. The ring
stage parasite grows to become a trophozoite. After that, the parasite subdivides into
20 - 30 daughter merozoites at the schizont stage. These merozoites burst the host
erythrocyte and flow into the blood stream again to start a new cycle. The overall
reproduction cycle takes about 48 hours [1].
While a P. falciparum parasite grows and develops in a host erythrocyte, the
infected cell undergoes pathological modifications of its optical, mechanical, magnetic
property and also the electrical property classified as impedance [60-63]. Especially, a
study on malaria infected human erythrocytes trapped in a microfabricated structure
already suggested a potential use of cellular impedance spectroscopy for diagnostic
30
RBC
parasite
Invasionof
malaria parasite
released parasites
a
b
e
d
C
)
Ringstage
Trophozoite stage
SchiZontStag
Figure 2-1: Asexual intraerythrocytic phase of the life cycle of Plasmodium
falciparum malaria parasite [1]
screening [63]. However, an effective malaria diagnostic test requires much higher
throughput (>100,000 cells per hour), because the parasitemia of malaria (as the
ratio of the number of infected RBCs to the entire RBC population) is very low,
often under 0.002%, at the early stage of the disease [64]. Therefore, microfluidic
EIS with continuous cell flow is essencial for such applications. In addition and more
importantly, the detection of the early (ring) stage infected erythocytes is critical for
diagnostic test since the infected population in the blood circulation are dominantly
in their early stage.
Thus highly demanded was a microfluidic EIS system as a
characterization tool for malaria states including the ring stage, which had never
been reported yet.
31
2.2
2.2.1
Materials and Methods
Microfluidic Probe Device Fabrication
Figure 2-2 shows the overall process of microfluidic device fabrication. The fabrication
is conducted at Microsystems Technology Laboratories, MIT. While photopatternable
silicone (PPS) and an epoxy-based negative photoresist (SU-8) are widely used in
microfluidic device fabrication, thanks to convenience of fabrication without silicone
etching process.
However, the pattern resolutions are limited to 10tm and 6pm,
respectively [65]. While planar geometry is determined by the exposure pattern, the
fluidic channel height is determined by the depth of the pattern. In case of PPS or
SU-8, the film thickness sets the depth, which can be controlled by spinning speed.
Once we targeted a channel height of a few times higher of the thickness disk-shaped
RBCs to make sure the concentrated cell flow with the consistent orientation of RBCs,
the patternable film thickness around 5pm must be achieved. Therefore, in this study,
the standard silicon etching techniques are applied, which etch a bare silicon wafer
with SF6 plasma. This ensures higher resolution and uniform patterns across the large
area wafer and, more importantly, better control of the depth of the mold structure.
Details of the fabrication process are provided in Appendix A.
2.2.2
Malaria-Infected Human Erythrocyte Sample Preparation
Human blood samples were prepared with the malaria parasites, P. falciparum,by
Monica Diez-Silva as described in [28]. The parasites were cultured in leukocyte-free
human blood samples (Research Blood Components, Brighton, MA) under an atmosphere of 5% CO 2 balanced with N 2 , at 5% hematocrit in RPMI culture medium
1640 (Gibco Life Technologies) supplemented with 25 mM HEPES (Sigma), 200 mM
hypoxanthine (Sigma), 0.20% NaHCO 3 (Sigma) and 0.25% Albumax II (Gibco Life
Technologies). The cultured samples contained a mixture of multi-stage infected erythrocytes (iRBCs) and uninfected erythrocytes (uRBCs) at the parasitemia of 5%
32
5 mm
H20
(a150
Un
(b) Microchannel mask design
(a) Electrodes mask design
Silicon
substrate
Glass
substrate
I
I
I
I
Develop
-
PR
Reactive
ion etching
-
Ti-Au
PDMS
deposition
curing
I
I
Hole
Lift-off
--
PR
W
M
.
Alignment
& bonding
(c) Fabrication process
(e) Full view of probe part
(d) Electrodes alignment with
microchannel
Figure 2-2: Fabrication of microfluidic probe chip [2]
33
punching
Faraday cage
Rsmicroflpidic
cha nt-
Ilm
2pm$
cell fjlw-
Figure 2-3: Measurement setup of microfluidic EIS of malaria infected human blood
sample
to 8%. To maintain osmotic pressure and prevent RBC adhesion to the microfluidic channel, the working solution for El measurement was phosphate-buffered saline
(PBS; 2.67 mmol/1 KCl, 1.47 mmol/1 KH 2 PO 4 , 137.93 mmol/1 NaCl, 8.06 mmol/l
Na 2 HPO 4 .7H 2 0) mixed with Bovine Serum Albumin (BSA) (Sigma-Aldrich, St Louis,
MO). Three concentrations of BSA-PBS, 0.2%, 0.5%, and 1% weight/volume (w/v)
were utilized in the experiments to achieve optimum performance and sensitivity of
EI measurement.
The cultured P. falciparum samples were cooled down to room
temperature after being removed from the incubator, then washed with PBS solution
at 2000 rpm for 5 minutes at 21'C and diluted by 200 times in the working solution.
2.2.3
Measurement Setup
Figure 2-3 illustrates the measurement setup. The EIS was performed under continuous flow precisely controlled by water column pressure difference, allowing minimum
hydrodynamic disturbance during EI measurement. The actual flow rate was around
150 fL/s to capture the optical image of the cell in the flow. This extremely slow
flow is only necessary when visual data acquisition is required to provide the relation
between EI data and the disease states. In other words, 100x speed can be easily
achieved for EIS only system. The probe electrodes were connected to an LCR meter
34
(Agilent Technology, Inc.), and the El data were collected using an interface program
(LabVIEW). The excitation source in the LCR meter was set to be 1 Vp.. at 2 MHz
while the magnitude and the phase of the channel impedance were measured at the
of
sampling rate of 50 Hz. While continuously measuring the electrical impedance
the channel, each cell passing over the electrodes was visually monitored with a 100 x
magnification optical microscope (Olympus IX71) to make sure single-cell analysis
and to identify the disease state. To remove electrical signal interference, the device
was surrounded by a grounded Faraday cage made of aluminum foil with a hole for
the microscope lens.
The test samples were also ready in three different BSA concentrations (2%, 5%,
and 10% in PBS). In each measurement, the steady flow was acheived by manual
control of water column height. Preprocessing of the raw data to extract El transition
for each cell is conducted by E Du, and each EI transistion is mapped with its disease
states as confirmed by the visual inspection.
2.3
2.3.1
Results and Discussion
Data Acquisition and Preprocessing
When a cell approaches and crosses the electrodes, the presence of the cell at the
measuring zone forms a lossy capacitor, creating a dynamic impedance transition
Electric Impedance Spectroscopy on RBCs
0.0
0.02-
Uninfected
RBC
-. 2infected RC
-0.06
0
20
40
80
60
100
120
140
Time
Figure 2-4: Dynamic impedance transitions at cell passage over probe electrodes
35
AZ as shown in Figure 2-4. The impedance transition from the base impedance
is given by
Zmedium to Zedium+RBC
Z\Z=Zedium+RBC
-
Zmedium
= (M + AM)eOw
- Me3n
(2.1)
(2.2)
where the magnitude deviation AM and the phase deviation Ao are taken from
the center peaks of each impedance transition. They are complex functions of cell
size, composition, dielectric properties of cytoplasm and the cell membrane, and the
enclosure of the medium surrounding the cell.
The present El measurement was
performed under a single frequency of 2 MHz with sampling rate of 50 Hz in order
to probe both interfacial and intracellular changes of Pf-iRBCs.
selection falls into the
f
The frequency
dispersion regime (within the range of 0.1 - 10 MHz for
biological cells) [66] where the large discrepancy in conductivity of cellular membrane
and cytoplasm causes a lag in charging response of the intracellular and extracellular
substances.
Figure 2-5 shows a typical example of the transient EI measured when cells crossing over the electrodes.
The magnitude and phase transitions, AM and A O, are
shown in two sub-plots, respectively.
The insert in the phase sub-plot displays a
representative image of each sub-population, from uninfected RBCs to Pf-iRBCs at
ring stage, trophozoite stage, and schizont stage, respectively. The working solution
was 0.2% w/v BSA-PBS. The ring stage iRBCs only have delicate parasitic cytoplasm with single or double small chromatin dots. In contrast, the trophozoites have
denser cytoplasm with yellow pigment and the schizonts have dense dark pigment.
The differntiation of the cells are not trivial with the transient plot, but it at least
shows that the proposed continuous flow cellular EIS system possesses a cell-counting
function.
Figure 2-6 shows the initial measurement data of 113 erythrocytes including
78 uRBCs, 12 ring stage iRBCs, and trophozoite stage iRBCs.
The El changes
(Ao, AM) are only plotted noting that the magnitude of the base channel impedance
36
0.1
0
-0.1
9-
Nonmifected
Trophozoite
Ring
Schizont
-02
-0-3
600
400
200
-L14
0
-200
0
2
6
4
8
10
12
Time (Sec)
Figure 2-5: Overlaid transient El results of uninfected RBCs and Pf-iRBCs crossing
over the electrodes with the measurement conditions: 2MHz 1Vp-p and 0.2% (w/v)
BSA-PBS.
37
2MHz EIS Results
1000
-
0
-
900
00
-
*
800
0
0.
0
700
-
0
600
-
0
a)
*
Ec
as
**
0
-
500
0
400
-
)
.)
300
-
E
-
200
-
0
-0.5
Normal
Ring
Trophozoite
*
0
100
-0.45
-0.4
-0.35
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
phase shift(deg)
Figure 2-6: Scatter plot of 113 El data (Aro, AM) consisting of 78 uninfected RBCs,
12 ring stage iRBCs, and trophozoite stage iRBCs.
Simplified Circuit Model
membrane
(buffer
solution
E
E
cytoplasm
E
0
0.
Rfeedback
Excitation
Source
Eedbc
ADC
DFT
Figure 2-7: Block diagram of cellular impedance measurement setup and simplified
cellular circuit model. A simplified cellular impedance model is shown in the inset. The extraction of model parameters requires an excitation source with variable
frequency.
38
(OOkQ-1MQ) is much larger than that of transitions. The plot hinted that we might
be able to classify the cells just by their data point locations. It is a different approach from traditional cellular EIS systems which often assumed a circuit model
for the target cell and tried to extract the circuit parameters, such as Rcytopasm and
as in Figure 2-7, to classify the cells by the range of the parameters and
also possibly differentiate infected cells from healthy ones [63]. Although the analysis
Cmembrane
with circuit models, whether simplified or complicated, may provide a good physical
interpretation of the cell structure and the pathological modifications, the measurements is subject to extremely large cell-to-cell variation (which can be treated as
noise) [63]. Moreover, the model fitting often require a frequency sweep measurement
which results in low throughput due to the slow multi-frequency measurement.
2.3.2
Analysis with a Dimensionless Parameter 61
In order to systematically evaluate different experimental conditions, EI transitions
(Ap, AM) were normalized by,
x
=
A O/A
y = A M/A M
(2.3)
(2.4)
where A~p and AM are the mean values of the phase change and the magnitude
change of uninfected erythrocytes for each experimental condition. Figure 2-8 plots
the normalized El transitions of uRBCs where the mean values are (1.0, 1.0) for each
group, along with their linear fitting lines and the line equations in form of,
y
=
kx + a.
(2.5)
As Figure 2-8 shows, the normalized El transitions of uRBCs at each BSA concentrations can be well-fitted with the linear curves despite of the cell-to-cell variations.
Utilizing these curves as reference lines, we introduced a dimensionless parameter, El
offset 6, as the graphical distance from each data point of Pf-iRBC to the reference
'Original data and figures are from [28]
39
2.0
1.5
II
X
1.0
-
0.5
X
*.2%BSA
y=O.3953x+O.60 4 8
0I.5%BSA
7
y=.621x+O.53 9
X 1% BSA
y=0.4088x+0.5912
0.0
1.5
1
0.5
0
x=a/
2.5
2
p
Figure 2-8: Scatter plot of normalized EI transitions of uninfected RBCs in three
different BSA-PBS concentrations
2.0
1.5
Ii
0AI*
-0
c
et4
1.0
0.5
* Uninfected
e
Trophozoite
" Ring
" Schizont
0.0
0
1
0.5
1.5
Figure 2-9: Scatter plot of normalized El transitions for 0.2% BSA-PBS condition
and definition of an offset parameter J
40
p<0.001
1.5
p<0.001
1.0-
p<0.00 1
LO
a4
-0.5
0.51P<o-00
Uninfected
Ring
1
P <.0 1
Trophozoite
Schizont
Figure 2-10: Statistical box chart of two-sample t-test for 6's collected from the PfiRBC sample in 0.2% BSA-PBS concentration
line as depicted in Figure 2-9. In other words,
6 = -(kx, + a - ys)/ /k 2 + a2
(2.6)
where k and a are the linear interpolation coefficients of the reference lines as in Eq.
2.5, and x, and y,, are the normalized impedance transitions of individual RBCs.
From 6 in Figure 2-9, uRBCs and Pf-iRBCs at various stages indicated a monotonic
trend in the relation of 6 and the pathological progress.
We also noted that the
normalized El transitions varied between the experiments even in the same conditions
as we replaced samples and devices in the experimental setup. However, the similar
scatter pattern was observed. To collect a vast number of data points, we combined
data from each experiment using the commonly aligned reference lines from the scatter
plots of EI transitions for Pf-iRBCs.
El offsets 6 for various Pf-iRBC stages were systematically compared using statistical box charts for different BSA concentrations. The statistical analysis was carried
out using a two-sample t-test. When BSA concentration was 0.2% w/v, all intraerythrocytic stages of Pf-iRBCs showed a statistically significant difference (P<0.001),
41
P<
0.001
p<0-001
1.0
p<0.00 1
-
0.0
p
0.0 2
pz
-0.5
.0 5
I
Uninfected
Ring
Trophozoite
Schizont
Figure 2-11: Statistical box chart of two-sample t-test for 6's collected from the PfiRBC sample in 0.5% BSA-PBS concentration
as indicated in Figure 2-10. We found that our new El measurement method can
be used to effectively distinguish Pf-iRBCs not only from uRBCs but also between
adjacent asexual stages (ring vs. trophozoite, and trophozoite vs. schizont) with
high statistical significance.
2.3.3
Effect of BSA Concentration in Buffer Solution
While BSA was added to maintain osmotic pressure and prevent RBC adhesion to
the microfluidic channel, we studied the effect of BSA concentration in the working
solution within a reasonable range of concentrations.
The same EIS experiments were performed on Pf-iRBC samples with BSA concentration of 0.5% and 1.0% (w/v), and the results were as shown in Figure 2-11 and
2-12. In the case of 0.5% BSA, all stages of Pf-iRBCs were still statistically distinguished (P<0.001). When BSA concentration was increased further to 1% w/v, the
ring stage bears only moderate statistical significance (P = 0.134) despite trophozoite
and schizont stages still having high statistical significance (P<0.001). It was clear
that the EI offset 6 was less scattered at higher BSA concentrations. In addition, the
42
p< 0.001
1.5
p<0.00
1
-
1.0
p 00. 13
*
0.0
pzQ009
p=O.O 7
-0.5
Uninfected
Ring
Trophozoite
Schizont
Figure 2-12: Statistical box chart of two-sample t-test for 6's collected from the PfiRBC sample in 1.0% BSA-PBS concentration
overlap between uRBCs and Pf-iRBCs, especially for ring and trophozoite stages,
increased with BSA concentration making classification difficult. While deeper investigation in the electro-chemical effect of BSA in the sample solution is still required, it
is believed that BSA introduce more mobile ions in the solution which can effectively
shield the electric field across the cell, reducing the measurement sensitivity.
The sensitivity of the Pf-iRBC detection and the performance of the present
cellular EIS system were found to be significantly influenced by BSA concentration
and a number of other relevant factors, such as cell concentration, flow rate, and
sampling rate.
The results indicate that 0.2% w/v BSA in PBS is optimum for
the present measurements with sufficient detection sensitivity while minimizing cell
adhesion to microfluidic channel.
The newly developed analytic method using a
composite parameter 6, instead of extracting circuit model parameters or using only
one of EI components, is also expected to be more broadly applicable in differentiating
other types of diseased cells for disease diagnostics and cell separation.
43
2.4
Concluding Remarks
In conclusion, we reported a cellular EIS system for electrical screening test of the
malaria parasites in human erythrocytes [28], which achieved a high SNR not just
enough to distinguish intracellular electro-chemical changes of tiny live cells but also
capable of early stage malaria detection. The fabrication of microfluidic probe device and the proper measurement setup allowed highly sensitive electric impedance
measurement of individual erythrocytes. We further developed an dimensionless parameter 6 to quantify the deviation in the magnitude and phase shift of electric
impedance of malaria infected cells. With the newly introduced analytical method,
the ring stage malaria parasites were confirmed, suggesting a use in early diagnosis
with fully electrical tests. Since there had been no available automated, low-cost
and miniaturized electrical diagnostic tests for malaria, this opens up a possibility in
development of such devices.
In this study, the detection of the ring stage P. falciparum iRBCs was achieved
along with the use of the very high parasitemia sample and the visual monitoring
setup for the cell states verification. However, we can actually leverage the fact that
uninfected erythrocytes are the vast majority in the blood stream (>99.8% before
immunes show symptoms and >90% even at severe mortality) [64] and get rid of the
visual monitoring by defining the reference lines for 6 analysis based on the entire
population without the need of selective uRBC data. This allows the measurement
setup and analysis to be simplifed by far, and significant differentiation of infected
RBCs still be possible for in-field tests.
However, given that the specificity of this diagnostic test has not been verified, the
test may result in false positives in cases of (1) infection by malaria parasites other
than P. falciparum and (2) RBC's cellular modification induced by other diseases.
While selective detection is not guaranteed, the cellular EIS can still be used as an
effective screening test for the abnormality in RBCs.
The present cellular EIS system provides not only a breakthrough in electrical
diagnostic tools that directly interface with biological cells but also a fine example
44
of electronics with non-traditional add-on devices (i.e. the microfluidic probe device). By this example, it is clearly shown that new interface materials can bring an
additional feature of sensing pathological modification of biological cells.
45
46
Chapter 3
Graphene-Silicon Hybrid IC for
Thermal Imaging
While in the previous chapter, the thesis has focused on a biomedical sensing application utilizing microfluidic devices to interface biological cells with an impedance
analyzer, in the next part of the thesis, we discuss a graphene-silicon hybrid infrared
(IR) imager where a graphene-based sensor interfaces IR light with a silicon readout
IC. The presented system utilizes an array of graphene thermocouples to detect midand long-wavelength infrared spectrum (A
=
8 - 15pm), wavelengths at which the
photon energy is lower than the direct bandgap of Si, and a readout IC built in commercially available Si-CMOS technology. This hybrid integrated circuit provides an
example of electronic systems closely integrated with emerging 2D materials, in our
study, graphene. It also leads silicon based technology to broaden its application's
range, thanks to the capability added by the new materials. However, it is important
to acknowledge the inherent issues with the new materials, both from their intrinsic
properties and due to their early developmental phase.
3.1
Introduction
Before discussing the details of the proposed hybrid imaging IC, we first review some
background of traditional electronics for photosensing applications.
47
3.1.1
History of Electronics for Infrared Sensing
Radiation detectors, as a more general term for photodetector, span far beyond the
visible part of the spectra not only in direction of X-rays and gamma (-y) particles
(high energy) but also in the other direction of millimeter waves and microwaves
(low energy). Interestingly, one of the first photodetectors invented was the thermal
radiation receiver which reacted to the temperature change in sensing elements, where
the heating by radiation often occurs in the infrared spectrum.
This principle is
still widely used since Thomas A. Edison used compressed carbon as a temperature
sensitive resistor and called it tasimeter [67]. The device was then further improved
as S. P. Langley developed the bolometer, an instrument which used a blackened
platinum strip for the same purpose [68]. Inherited from them, thermal detectors,
including thermopile, microbolometer, and Golay cells, are generally sensitive to all
infrared wavelengths and operate at room temperature.
Another family of detectors, the photon detectors, were mainly developed during
the 20th century. These devices are based on intrinsic and extrinsic transitions of
electron induced by photon absorption within the semiconductor grid. Lead sulfide
(PbS)-based photon detector was the first practical IR sensing system with sensitivity
to infrared wavelengths up to ~ 3pm. While efforts to improve sensitivity and response time had continued, discovery of variable bandgap HgCdTe alloy [69] opened
a new area in IR detector technology and has provided an unprecedented degree of
freedom in detector design. However, the main drawback is operating temperature,
in other words, cryogenic cooling is required to suppress thermally excited electrons.
There are a few types of detectors that do not need cooling such as Ge and InGaAsbased ones, but the response spectra is limited in high photon energy regime far from
long- and very long-wavelength infrared range (A > 8[tm) [70].
Improvements in uncooled thermal detectors and high performance photon detectors would trigger the adoption of these technologies in applications, such as, IR
imaging in medical diagnostics, Fourier transform IR spectroscopy, IR astronomy, assisted car driving, global monitoring of environmental pollution and climate changes,
48
Table 3.1: Comparison table of D* for various infrared detection technologies [7]
Response
Operating
D*
Spectra
Temperature
(cmHz1/2/W)
Ge
InGaAs
0.8-1.8
0.7-1.7
(K)
300
300
Photovoltaic
Ex. InGaAs
InAs
1.2-2.55
1-3.1
253
77
Photoconductive
InSb
HgCdTe
PbS
PbSe
InSb
Type
Detector
(m)
77
77
300
300
213
77
300
300
ined
DDetemBolometer
by window
300
300
material
1-5.5
2-16
1-3.6
1.5-5.8
2-6
2-16
HgCdTe
Thermopile
Golay cell
PZT, TGS, LiTaO 3
chemical process monitoring, and others.
1, 000 x 108
50, 000 x 108
2, 000 x 108
100 x 108
200 x 108
100 x 108
10 x 101 x 108
20 x 108
200 x 108
6 x 10 8
1 X 108
10 x 108
2 x 108
While the interest has mainly centered
on the wavelengths of the two atmospheric windows from 3 - Sjm and 8 - 141Lm,
there has been an increasing interest in longer wavelength detection for applications
in astronomy.
In summary, Table 3.1 shows a variety of infrared detection technologies in terms
of wavelength, detectivity, and operating temperature. In comparing the different IR
detection technologies, it is convenient to use a figure of merit, which is the detectivity
(D*), defined as
Rt
SAdAf
NEP
(3.1)
-f
where Ad is the active area, Af is the bandwidth, NEP is the noise equivalent power,
R is responsivity (V/W), and V is the total noise voltage of the detector, respectively.
This figure of merit gives a normalized parameter in terms of the area, thus, is useful
not only for performance comparison among various sensing technologies, but also for
understanding the fundamental limitations of the detectors.
It should be also noted that the field of infrared imaging is already a field where
49
silicon technology requires heavy leveraging on other materials in an integrated form,
regardless of the maturity, high yield, and low cost of silicon technology.
In the
following sections, we take a deeper look in the three main phenomena utilized for
infrared detection and then graphene-based infrared detectors.
3.1.2
Photovoltaic and Photoconductive Detectors
The photovoltaic and photoconductive effects are two main operating mechanisms of
optical infrared detectors. Incident photons are converted into excited charged carriers in optical detectors, and either a measurable voltage or a change in conductivity
is generated. In order for these to occur, the material's electronic band structure
must allow direct transition (or excitation) between the valence band and the conduction band induced by infrared light. Therefore, for LWIR detection, materials
with appropriate band gap (0.024-0.3 eV), such as InSB or HgCdTe family, have been
traditionally used [71-74]. In addition to the direct bandgap detectors, extrinsic intraband photodetectors and quantum well infrared photodetectors (QWIPs) can be
used, where electrons can be excited from mid-bandgap states or from quantum well
intersubbands, respectively [75-77]. In the optical infrared detectors, the carriers require excitation by low energy photons, therefore, thermal energy from the ambient
environment can also lead to excess carriers. In order to suppress the thermal generation of excess carriers, optical detectors often require cooling to liquid nitrogen
temperature (77K).
3.1.3
Thermal Detectors
In addition to the photon-based systems, thermal detectors are another important
group of infrared detectors. In the thermal infrared detectors, incident infrared photons are absorbed and transformed into a temperature gradient. While thermal detectors benefit from broadband absorbance depending on the choice of the absorption
material and the window material, background radiation has to be taken into account. Besides, the response time of thermal detectors are slow in general because
50
the time constant of the device is mainly limited by the thermal time constant rather
than the electronic time constant. In short, with properly designed thermal detection
system and its isolation, the temperature increment induced by infrared radiation
can be translated into electrical signal by a few different thermoelectric transduction
mechanisms.
Bolometer
Bolometers utilize a material that changes electrical conductivity depending on the
These type of thermal detectors are commonly adopted in thermal
temperature.
imaging applications. The output voltage of a bolometer can be expressed as
Votal =
Ke,
where
aTCR
hiasRo(1 + aTCR)AT
AV
AT
= aTCRIbiasfRO
(3.2)
(3.3)
is the temperature dependent change in resistivity (TCR) of the material.
The current state-of-the-art materials, in terms of large TCR, are amorphous silicon
with 2.5%/K and vanadium oxide with >4%/K [78]. Since a bolometer uses a passive
resistor (Ro) and needs to measure the change in resistance, the detection mechanism
requires a bias current to convert the conductance change into voltage signal, and
the output voltage can be increased by setting Iias large. Therefore, bolometers can
consume more power to achieve higher sensitivity. However, trade-off exists since the
larger bias current results in self-heating effect as well as additional shot noise.
Thermopile
Thermopile's or thermocouples operate on another mechanism to convert temperature
gradient to electronic signal. Thermocouples directly generate voltage signal in active
manner, as a temperature gradient across the detector induces thermoelectric voltage. The output voltage of a thermocouple is linearly dependent on the temperature
gradient, that is,
51
V = SAT
(3.4)
where S is the Seebeck coefficient (V/K), and
Kcom,
=
AV
= S
AT
(3.5)
Although the signal from these devices is limited by the magnitude of the Seebeck
coefficient (~
10-100 pV/K), they have large dynamic range and good linearity. Thus,
it is possible to cascade many thermocouples in series in order to increase the signal
magnitude. In addition, since they have self-powering nature without the need for an
input bias, the noise contributions from shot noise and flicker noise are minimized.
Therefore, higher detectivities compared to bolometers are achievable as shown in
Table 3.1. A wide variety of materials (metals and semiconductors) are available for
thermoelectric detectors, but in order to create a large thermal voltage, two materials
of different carrier type (p-type or n-type) are required.
3.2
Graphene for Photosensing
While we have discussed the conventional detectors for the infrared regime, we now
change the subject to graphene applications for the IR detection. Many experiments
have begun to explore graphene's unique optoelectronic properties, attempting to
make use of its unusual broadband optical absorption from the far-infrared all the
way to the visible regime [39, 79-83].
In the near-infrared (NIR) regime (Eph= 0.8-1.6eV), atomically thin monolayer
graphene (MLG) have been adopted for broadband photodetectors and optical modulators, capable of ultra-fast response times (>10 GHz) [84, 85].
However, these
demonstrations were limited in high energy spectra where photon energies are much
larger than the intrinsic energies of the system, such as the optical phonon energy
(Eo,
~ 0.2eV) or the electrostatically controllable Fermi energy of MLG (Ef ~
0.5eV) [84,86-88]. For detection of lower energy photons with graphene, very recent
52
work has shown active modulation due to Pauli blocking [37,89] as well as interesting
plasmonic effects [90-92].
However, more recent experiments in the visible regime have begun to show
that not only are optical effects possible within graphene, but thermal effects as
well [86-88].
Furthermore, a tunable ambipolar thermocouple operating at LWIR
regime has been demonstrated, in which MLG plays a key role in a hybrid ambipolar
infrared thermocouple, converting a temperature gradient into a voltage signal at the
thermocouple junction [20]. While current technologies for infrared (A = 5 - 15pim)
imaging, such as HgCdTe-based photovoltaic detectors, can achieve high performance [7], graphene-based thermocouples have a potential to avoid drawbacks of
photon based detectors, for example, low yield, ROIC integration, as well as cooling
requirement.
3.2.1
Mechanically Suspended Graphene Thermocouples
In very recent work of our team at MIT, led by Allen L. Hsu and Patrick Herring, a
graphene-based thermal imaging system has been demonstrated by using graphenebased tunable thermopile that offers high sensitivities at operating temperature of
300K [3,4]. Unlike graphene photovoltaic detectors, where the photovoltaic signal
can only be generated by photons absorbed by the graphene layer, the graphene thermal detector benefits from decompling on the materials used for heat absorption and
thermoelectric conversion to maximize sensor performance. Therefore, by choosing
better infrared absorbing materials and by integrating with silicon MEMS structures
as shown in Figure 3-1(a), the graphene-based ambipolar thermopile achieves sensitivities able to detect the emitted radiation from a black body source as shown in Figure
3-1(b). Furthermore, analysis suggests the intrinsic performances to surpass state-ofthe-art thermopile imagers, when ultra-high carrier mobility of graphene is involved.
This enables new classes of low cost, environmental-friendly, and high performance
thermal imagers when integrated with Si ROIC technologies.
53
H
(b)
a.
Thermal
(SiN/SiOA)I
10
15
M0
25
x (mm)
Figure 3-1: (a) Illustration of the MEMS-enhanced graphene thermopile. Small holes
in the center of the infrared absorber are meant to facilitate suspension of the thermal
isolation stack, while the large openings along the periphery help define the thermal
isolation legs. (b) The measured signal shown as a function of actuator position. The
thermal image was formed by placing a laser cut stainless steel aperture in front of the
blackbody source (T = 472 K, fmod = 173 Hz) and scanned in position using a series
of motorized X-Y translation stages. The step size was 0.5 mm and the integration
time was 3 s per pixel [3,4].
3.3
Readout IC for Graphene IR Sensor Array
In parallel to developing the graphene thermocouple for IR sensing, we have worked
on building an integrated imager solution to bring this graphene application to the
next level.
3.3.1
Readout IC Architecture
The readout IC (ROIC) for 4,800-pixels IR image sensor is proposed as illustrated in
Figure 3-2. Each pixel contains a graphene IR sensor fabricated on the top surface
and a pixel amplifier built in the Si substrate. The differential output lines of 8x60
pixels are connected to an ADC through a column selection multiplexer (MUX) and
a variable gain column amplifier, thus each set completes a fully functional imager
block as shown in Figure 3-3. The full chip contains ten of the imager blocks as
in column-parallel architecture. The column-parallel architecture allows not only a
good-trade-off between frame rate and power consumption, but also proves scalability
of the sensor. The prototype chip size including pads is 5mm by 5mm.
54
Pixel Transimpedance
Amplifier
In
0.
,
Parallel
ADCs
lOMOOOOEEODDDDD=D0D
Graphene sheet
~30um x 10 um
5mm
Figure 3-2: Conceptual floorplan for integrated graphene IR imager. An array of 80
by 60 graphene thermocouple pixels is fabricated on top of the Si-CMOS readout IC.
*
0
L 0000
0
0
0
0
0
0
6000
0
8-1 MUX
SAR
ADC
8
Figure 3-3: Schematic of an imager block consisting of 8-column by 60-row pixel
amplifiers, a 8-to-1 MUX, a variable gain amplifier, and an ADC. The prototype chip
consists of 10 of this imager block that complete a 80 x 60 pixels image sensor.
55
3.3.2
Sub-Block Designs
This section discusses the design of sub-block circuits. The pixel transconductance
amplifier is the front-end block directly connected to the graphene thermocouple. To
properly design the pixel amplifier, the signal source must be carefully characterized.
Unfortunately, at the time of initiating the IC design, the specifications of the sensor
device were not fully confirmed, and the graphene-based sensor was assumed to be a
photon-based detector, not thermal detectors as we developed later. Photoresponse
of the sensor was thought, initially, to be generated at the p-n junction of a graphene
sheet or a graphene-metal junction. Interestingly, the graphene junctions in either
case can only have low impedance, thus, it cannot collect the charge over time and
store in the junction capacitance, unlike Si p-n junction photodiodes do. Therefore,
a high speed (large bandwidth) direct conversion of photovoltage or photocurrent
signal was required for a pixel amplifier which also needs to meet the area constraint
of 10pbm by
3 0 pm.
Pixel Transconductance Amplifier
3.2nA
3kg'
-V
Graphene
Photodetector
Trans-Z
Amplifier
Figure 3-4: Circuit model of a graphene photodetector and a transimpedance amplifier. The transimpedance amplifier converts the input current ('in) into the output
voltage (V,,) by a conversion gain.
The pixel amplifier design required a different photoresponse integration scheme
because of the graphene device's nature of low output impedance. While high impedance
56
Signal Amplitude
Extraction
Modulated IR
Photoresponse + Noise
'-"ke
Square Wave at Modulation Frequency
Figure 3-5: Illustration of photo-signal modulation and extraction scheme.
sensors, such as Si p-n junction based photodetectors, often use an integration capacitor, either intrinsic or extrinsic, at the front-end to accumulate the signal and
cancel out high frequency noise, our device would provide a significant leakage path
by its own sensing material. As shown in Figure 3-4, the earlier detector model was
assumed to be a -3.2 nA current source with 200 -3, 000 Q output impedance, where
the values vary depending on the doping of graphene, the device geometry, the material quality, and the choice of contact metal. Despite that the graphene device was
yet assumed to be an active sensor that does not require bias current or static power
consumption, a transimpedance amplifier with low input impedance (< 1 kQ) was
desired.
Although the charge integration scheme often employed in high impedance photovoltaic detectors where longer light exposure (longer charge integration) improves
SNR, we used a current amplification scheme with input light modulation. As shown
in Figure 3-5, amplitude of a noisy photoresponse can be extracted from the correlation of the detector output signal and a square waveform at the modulation frequency.
In this scheme, on-time signal and off-time signal are sampled multiple times. By extracting the signal component at the modulation frequency, the dark current (off-time
response) can be effectively canceled out just as the correlated double sampling (CDS)
technique does [93-95]. In this scheme, noise reduction is achieved by longer expo57
(a)
1
2
=+
Igbs
(b)
1
FF
Q1MA
pg
0-l1kfl
Zin
Graphene
Photodetector
Model
MPI
MP2
MN1
-cuit)
MN2
(Norton circuit)
- - - -
I
0-6kQ
MN4
MN3
- -- -
FS
TT
-
adjustment
Zin
1~p
Figure 3-6: (a) Schematic of the proposed pixel transimpedance amplifier. The bias
tail current is set to satisfy the current deviation less than 1% of the bias current.
The matching of gm, thus minimizing Zij, has fine-tune control by the VB node. (b)
Simulated input impedance adjustment of the PTIA with VB range from 1.1V to
1.8V across the process corners.
sure which results in more sampling points and thus improves spectral resolution and
SNR.
The schematic of the proposed pixel transimpedance amplifier (PTIA) is shown
in Figure 3-6(a). The PTIA is implemented with thick oxide I/O transistors for gain
and output dynamic range. The PTIA utilizes a cross-coupled pair of NMOS (MN1
and MN2) and diode-connected PMOS (MP1 and MP2), which minimizes the input
impedance (Zin) looking from the tails of the NMOS pair when the transconductances
of PMOS and NMOS transistors match (gm,p
= gm,n).
An additional pair of NMOS
tail transistors (MN3 and MN4) are added to fine-tune gm,n, thus Zin, with the
VB node. This topology allows medium-to-large I-V conversion gain and low input
impedance at the same time. A similar topology was also adopted in a highly energyefficient current-mode receiver circuit [96], removing bias current and reducing load
58
impedance at the same time.
In this amplifier design, the bias tail current was set to 1pA. Assuming the largest
current deviation induced by the graphene photodetector to be less than 1% of the
bias current, gm matching can be assured during the photodetector operation. The
input impedance of the amplifier (Zi,) can be fine-tuned to near zero by a bias voltage
(VB) of the tail NMOS transistors in triode regime as shown in Figure 3-6(b).
In the end, however, we need to note that the initial graphene photodetetor is later
replaced with an electrostatically tunable ambipolar graphene-based thermocouple as
discussed in the previous section. The consequences of the change in the key detection
device must be reviewed. Although the graphene thermocouple operates on a different
fundamental mechanism, it can still be modeled as a Norton equivalent circuit in
terms of signal amplitude as long as it is a single-junction and two-port device. When
modeled, the new thermocouple devices would result in typical parameters of 10 kQ
resistance and 5 nA photocurrent.
They are actually better values for the PTIA
scheme compared to those of the graphene photodetector devices. Especially, the
increased resistance of the detector device would ease the requirement for the gm
matching in PTIA, therefore, the original design could still be applied for the new
devices.
However, the current amplification scheme with the proposed PTIA is not optimal
when we include the effect of the contact resistance between the graphene device
and the readout circuit. The contact resistance is serially added to the amplifier's
input impedance, thus it can significantly reduce the input current, while the effect
is neglected in high-impedance voltage-input amplification. We will discuss on this
matter in depth in Section 3.6.
Analog-to-Digital Converter
Another key block in the readout IC is the ADC where a major portion of power
is consumed. In the column-parallel architecture, the requirements of ADC can be
relaxed in terms of speed and area.
In comparison, single-ADC readout schemes
require super-fast data conversion rates to read out N-pixels within a reasonable time
59
frame. On the other hand, in-pixel-ADC schemes suffer from the area constraints
related to placing an ADC in each pixel including the routing of the data lines.
Traditionally, in a column-parallel architecture, single/dual-slope ADCs have been
one of the favorable choices for image sensor readout ICs not only because that
type of ADC offers a good trade-off in resolution, speed and power when tightly areaconstrained, but also because it is straightforward to implement with the CDS feature
[97-99]. However, in the present prototype IC, a successive approximation register
(SAR) ADC was used for ease of design. SAR ADCs, in general, are considered a
good choice for medium-to-high-resolution (8-16 b) with moderate sampling rates (<
5 MSPS) [100}. SAR ADCs also provide low power consumption as well as a small
form factor, thus becoming our choice in the readout architecture of 8-bit resolution,
1.2-MSPS speed, small area (< 0.05 mm 2) with a moderate power consumption (<
200pW). Given the small number of pixels and the large pixel pitch compared to
those of concurrent state-of-the-art focal plane arrays in the visible, our ADC area
constraint is not too tight. Furthermore, we get serialized output data in binary code
for free. Therefore, SAR ADC was an effective choice to reduce the design complexity.
The schematic of the proposed SAR ADC is shown in Figure 3-7.
It consists
of a binary weighted capacitive DAC, a clocked comparator, and the control logic
implementing the successive approximation algorithm. Each data conversion of the
ADC takes a sampling phase where the input signal is sampled by the capacitive DAC,
and a bit cycling phase where the digital output bits are resolved by the comparator.
In each cycle of the bit cycling phase, one most significant bit (MSB) is resolved, and
then DAC is reconfigured for the next MSB until it gets to LSB.
In the proposed ADC, differential MSB-split capacitive DACs are used for sampling input signal and generate comparator inputs to reduce power consumption of
ADC (by 37% compared to the conventional array [101]). In SAR ADCs, the linearity of DAC is critical for integral non-linearity (INL) and differential nonlinearity
(DNL) of the system. The DNL in units of LSB (least significant bit) for each code
transition is defined as the deviation from the ideal LSB, and the INL for each code
is defined as the deviation from the ideal output. In the binary weighted capacitive
60
8bit Differential SAR ADC
Main DAC
VIN
,I
4
II
-
Vrefp
4
Vref*
SuDA7
8C
4 C2
CP
C
Co parator
SAR
I
CLK
Timing Manager
8
-
VCM 00
i
Bit Decision
Figure 3-7: Schematic of Successive Approximation Register ADC.
61
DNL (in LSB)
0.04
0.02I
-0.02
-0.04
I
1 11
161
177
1 11 1 1 1 1 1 1
I
INL (in LSB)
0.1
0.05
-0.05
-0.1
1
17
33
49
65
81
97
113
129
145
193
209
225
241
Code
Figure 3-8: Simulated DNL and INL of the capacitive DAC across 8 bit digital codes.
IDNLIMAx < 0.04 and |INL|MAX < 0.07 are achieved.
DAC, skews in the DAC capacitors, especially the skew of the MSB capacitors, have
the biggest impact in DNL and possibly in INL. To minimize the skews, good layout
of the capacitor array is crucial, and it requires some iterations of tuning and extraction of the layout. Starting from the common centroid layout , iterative fine-tune of
the capacitor matching resulted in IDNLIMAX < 0.04 and IINLIMAX < 0.07 in LSBs
with C+CC layout extraction as shown in Figure 3-8.
While the global clock and the reference voltages are fed off-chip, an internal timing generator controls the cycles for the successive approximation algorithm. Figure
3-9 shows SAR cycles at consecutive data conversions; (1) Once conversion is triggered (TRIG), the internal timing controller asserts a one-clock-period START signal
and purge the capacitors. (2) For the following two cycles, the input signal is sampled
by the DAC capacitors, and (3) output bits are resolved in the rest cycles.
62
TRIG
CLK
START
a)
CYCLE
L
-
SE
M~
-o
~
~
cc~~
E
M~o~
Figure 3-9: Timing diagram of the implemented successive approximation logic
Full Chip Verification
The transient response of the full chip is verified in a testbench simulation. An
imager block containing 16 active graphene detectors is assumed in Figure 3-10. Each
graphene detector model is assigned with different photocurrent value.
The row-
column selection logic chooses one pixel connected to ADC at a time.
Figure 3-
11 shows the transient response at the column output, which is fed to the ADC
input after level shifter circuit, and the ADC output codes. The simulation clearly
shows the readout function of the imager block even at very conservative device
assumptions, such as very small output impedance and photocurrent of the graphene
device
(Ro,G-PD =
150 Q, Iph
=
0
-
12nA).
63
Pixel Amp Array
Row
SeIe4f
Co.# T
Col#1
Column
Select
Gain ctr
Column Amp_
& Level Shifter
One ADC reads
__3V
1.8V
ADC
8x60 pixels as
RS and CS select
Data Output
Valid Code
Figure 3-10: Schematic of a testbench for imager block readout simulation. 8 graphene
pixels with unique Iph values (0 - 12 nA) and low output impedance (Ro,G-PD = 150
Q) were assumed.
64
1
Col-Row
Column Output (p)
/__ vae
Value
Column Output (n)
--
1
00'
700
60C
-
=:
~
50'0
040
2C
150
0
125
0 --
ColO0
Row 6
3 nA
ColO0
Row 5
2 nA
0ColO0
Row 4
1 nA
3(
ColO0
Row 7
4nA
Col
Row 0
8 nA
Coil
Row 1
12 nA
Col1
Row 2
6 nA
32
64
93
Col1
Row 3
0 nA
ADC Output Code
100
.075
0
50
.
F-b
I
I
-1 1
-
goo
16
8
0
24
0
AJ
I
-25
I
l0
0o
l 0 ol
col0o
RO3IROW41IRow5I RowS
160
180
200
220
col0
Row7
240
time (us)
col
col
RORawl
260
280
col
Rw 2
300
colI
Row 3
320
Figure 3-11: Simulated Photoresponse Readout of Multiple Pixels
65
3.3.3
Considerations for Back-End Graphene Sensor Integration
Additionally, the design of the readout chip had to consider post-fabrication steps
for graphene IR detectors in its layout as well as in its schematic design. The layout
was required to ease the post-fabrication process, or at least make it possible, including standard electron-beam lithography, metalization, etching, and graphene transfer
steps.
The readout chip, shown in Figure 3-12, was fabricated in 0.18-pm technology
through TSMC's University Shuttle program.
First of all, the extended chip size
(5mm x 5mm) was intended to ease handling of the chip during the graphene integration process. The active sensor area of the chip, 4mm x 3mm, is filled with the 80
by 60 array of the graphene thermocouple pixels. By locating the regularly patterned
pixel array at the center of the chip and other CMOS only components on the sides,
it is handy to avoid the issues in lithography involving uneven resist thickness toward
the chip edge. The side regions of the chip are used for the row and column selection
logic, current sources, column amplifiers, and ADCs. In addition, a discrete imager
block is implemented for component characterization and testing off-chip detector
readout.
The area of each pixel is 50pum x 50pm; a pixel amplifier and signal paths occupy
the small portion of each pixel area, leaving over 60% of the area empty and flat. This
flat region within the pixel plays a key role when fabricating back gate electrodes for
the graphene thermocouple and transferring graphene layer. Each pixel also has two
contact metal plugs towards the top surface of the chip for ohmic contact to the
graphene thermocouples.
Again for the graphene detector, the contact plugs are
placed within the flat region but still maximizing the space in between.
66
Figure 3-12: Die photo of the readout IC for graphene-CMOS hybrid IR imager. The
chip shown is before the integration of graphene thermocouples.
67
3.4
Graphene-CMOS Hybrid Infrared Imager
Integration of Si CMOS and graphene thermocouple array is one of the main challenges to complete the hybrid IR imaging system. Once realized, the integrated system not only provides a new type of IR image sensor but also confirms the feasibility
of electronic systems that employ graphene devices in a large scale. In our work,
it was indeed a big challenge to develop fabrication processes to integrate >4,000
graphene thermocouples on the CMOS readout chip, and it had been conducted in
collaboration with Allen L. Hsu, Charles Mackin, Marek Hempel, Yuxuan Lin, and
Young Cheol Shin.
3.4.1
Graphene Thermocouple Device for On-Chip Integration
Figure 3-13 shows the integrated graphene thermocouple structure.
Although the
graphene based thermocouple fabricated on a suspended MEMS structure showed an
exceptional IR detection performance thanks to good thermal isolation as described
in the previous section, the proposed thermocouple array for the initial integrated
solution is not built on such suspended structure. Instead, as shown in Figure 3-13,
the thermocouple structure is stacked on top of the CMOS passivation layer, made
of Si0 2 , and electrically connected to the readout circuit. The dielectric layer works
as IR absorption material and also provides thermal isolation.
68
Ohmic Contact
MLG
Plug
CMOS Substrate
Gate
Metal
Figure 3-13: Diagram of a graphene thermocouple fabricated on top of the CMOS
substrate. Two gate metal lines are embedded in SiO 2 passivation layer for electrostatical doping of MLG, and the ohmic contact and plug ensure electrical connection
to the pixel amplifier.
3.4.2
Fabrication of On-Chip Graphene Sensor Array
The floor plan of the chip is already shown in Figure 3-2. The fabrication processes
are initially developed by Allen Hsu [4] and revised as shown in Figures 3-14 and
3-15; (1) Begin with a bare CMOS die received from TSMC. (2) CF4 plasma etch
with and without patterned PMMA mask to expose M6 plugs. (3) Sputter of ohmic
plug, local gate, and gate routing metal. (4) Dielectric deposition, and (5) Via hole
etching follow. (6) Transfer MLG. (7) Sputter ohmic contact metal, and (8) Plasma
etch to pattern the graphene layer. After all, the chip is ready for packaging and
testing. Further details are provided in Appendix A.
Die photo of the fabricated prototype chip is shown in Figure 3-16 (left) along
with a original die for comparison (right). A closer look at the pixel area (Figure
3-17) shows MLG, ohmic contacts, and back gate structures fabricated on top of the
CMOS substrate.
69
(1) Start from the Bare CMOS IC Die
(2) Pattemed I Global CF 4 Etch for Passivation Removal
(3) Sputter of Ohmic Plug and Local Gate Metal Layers
(4) Si02 Gate Dielectric Deposition
Figure 3-14: Fabrication processes for integrated graphene IR imager chip (1)-(4)
70
(5) CF4 Etch to Open Ohmic Contact Via Holes
(6) Graphene Transfer
(7) Sputter Ohmic Contact Metal Layer
(8)02 Etch to Pattem Graphene
Figure 3-15: Fabrication processes for integrated graphene IR imager chip (5)-(8)
71
Figure 3-16: Die photos of the fabricated graphene IR imager prototype chip (left)
along with the original die for comparison (right)
Figure 3-17: Close-up micrographs of the pixel area shows the fabricated structures,
including monolayer graphene, ohmic contacts, and back gates for graphene thermocouple array.
72
3.5
3.5.1
Measurements
ADC Characterization
Characterization of the SAR ADC is conducted using the ADC test block in the
off-chip sensor readout compartment shown in Figure 3-12. It is assumed that the
ADCs used for readout of the graphene thermocouple array have similar performance
to this replica ADC.
Figures 3-18 and 3-19 show the linearity of the ADC, measured at the sampling
rates of 800-kS/s and 1.2-MS/s, respectively.While we tried to minimize capacitor
mismatch through post-layout extraction, IDNLI < 0.3 LSB and JINLI < 0.4 LSB
across the full range input were achieved. At higher sampling rate (1.2 MSPS), the
linearity is degraded to IDNLI < 1 LSB and IINLI < 1 LSB at the full range input.
@ 800-kSPS
INL (BEST END-POINT FIT)
1r
........
- -.................-.................-
0 .5 ------- -- - - -0
-1
0
50
150
100
DIGITAL OUTPUT CODE
200
250
200
250
DNL
1
0
........-..-..--
0
50
-- --------- --
150
100
DIGITAL OUTPUT CODE
Figure 3-18: Measured linearity of ADC at the sampling rate of 800 kSPS. |DNLI <
0.3 LSB and JINLI < 0.4 LSB across all 8 bit digital codes are achieved.
73
@ 1.2-MSPS
INL (BEST END-POINT FIT)
1
0.5
-- ---
-~~~ ----------
U,
0
-j
zj
-0.5
-1
50
150
100
DIGITAL OUTPUT CODE
200
250
200
250
DNL
0.5
-------------
- - -
a,
0
--
-0.5
-1
-1
0
50
--- --
-
-
0
150
100
DIGITAL OUTPUT CODE
Figure 3-19: Measured linearity of ADC at the sampling rate of 800 kSPS. IDNLI <
1 LSB and JINLI < 1 LSB across all 8 bit digital codes are achieved.
FFT PLOT
0
-
-20
-40
-
L0
-60
I--
11
I1
-80
-100
-120 'L
0
2000
8000
6000
4000
ANALOG INPUT FREQUENCY (Hz)
10000
12000
Figure 3-20: FFT plot of ADC output code at 240 kSPS where input tone is at 1.952
kHz
74
Figure 3-20 shows the FFT of the ADC output at 240-kS/s, with input tone of
1.952kHz. The second harmonic distortion term appears below -70dB thanks to the
differential operation. The measured ENOB was above 7.37 at sampling rates up to
1.2-MS/s, as shown in Figure 3-21. The power consumption of the ADC is plotted in
Figure 3-22, and the total power consumption at 1.2-MS/s is measured 171 pW. In
Table 3.2, the measured ADC characteristics are summarized.
ENOB [bits]
9
8
6
- -_
-----___
_
5
4
3
2
1
--
~-
_
__
_
_
_
_
__
_
0
100,000
1,000,000
Sampling Rate [samples/s]
Figure 3-21: Measured ENOB of ADC
75
_
_
_
ADC+IO Power Consumption
+
-U--Analog Power
Digital Power
1.OOE-03
1.00E-04
E-05
.01.00
10
E06~n
1,000,000
100,000
Sampling Rate [samples/s]
Figure 3-22: Power consumption of ADC
Table 3.2: Summary of ADC performance
Process
Resolution
Active Area
0.18 pm
8 b
0.0485 mm2
Supply
1.8 V
Sampling Rate
Power Consumption
(including IO Power)
1.2 MS/s
Input Range
2.4 Vp-p,diff
171 pW
73
ENOB
(fin
= 145 kHz)
45.57 dB
62.48 dB
0.861 pJ/conv.step
SNDR
SFDR
FOM
76
Pseudo Photoresponse Measurement
3.5.2
Before applying the readout chip to the graphene sensors, we tested the off-chip sensor
readout compartment (shown in Figure 3-12) to verify the readout performance. As
shown in Figure 3-23(a), an off-chip current source is connected to one of the four
pixel amplifiers that have pad routings for external connection. The current source
mimics the graphene IR detectors. The measured response is plotted in Figure 323(b) where the linear response range is from -60nA to 100 nA, which allows enough
dynamic range for graphene IR detectors. The resolution in this configuration was
581 pA/code, thus enabling sub-nA photocurrent detection while noise is suppressed.
For instance, we expect 9-LSB output from 5 nA input photocurrent.
(b)
(a)
lava
DVv
-~
r100
-~
80
.
--1 1
y = -5.81E-01x
- 60
+99.99
- 40
VB
'avg
17
nA]
- 20
ADC
Off-Chip
Current
rOnA
DOUT
Output Code
Source
P- Current range: -60nA ~ 100nA
-.-
-0
-20
+-
-40
- -60
Resolution: 581pA/code
Figure 3-23: (a) Schematic diagram of pseudo photoresponse measurement shows test
setup, and (b) sub-nA resolution is measured with linear input current range of 160
nA.
3.5.3
Off-Chip Graphene Thermocouple Measurement
Figure 3-24 shows the laser scanning setup used in the demonstration of off-chip
graphene thermocouples. A temperature stabilized 1W CO 2 infrared laser (Access
Laser Company) provides infrared radiation at 10.6 /im. The power of laser source
77
A = 10.6pm
alvo Mirror
PC
CO,Laser
Z
L1
Excitation
Source
GUI
Light Modulation
5V,, I _LU-L
."3
7
L3
ZeSn Window
Scryostat
Graphene
400mTorr
Vacuum
Thermocouple
Pump]
.. ...
p
Pu..
Readout
IC
PCB
Vacuum
Pumping
Figure 3-24: Schematic diagram (top) and photograph (bottom) of discrete graphene
thermocouple measurement setup
is controlled by the duty cycle of 5 V,.. square wave from a function generator (Tektronix). A beam combiner optics (ULO optics) is used to add a collinear laser (A = 632
nm) for alignment. A galvanometer controlled mirror produces angular deflection centered at the focal point of lens 1 (L1 in Figure 3-24). The deflection is then mapped
through a relay of confocal optics (L1 and L2) onto the back focal plane of an objective (L3). The IR beam is mechanically chopped by a modulator wheel operating at
78
20Hz to 1kHz. The modulated beam hits the sensor substrate through an objective
(L3) and a ZnSe anti-reflection coated window, producing distortion free scanning
over a large (> 4 x 4 mm2 ) area. The incident laser power at the sensor surface was
pre-calibrated by a reference power meter (Thor labs). The optical cryostat (Janis)
allows measurements to be done under vacuum and at low temperatures (77K < T <
300K), but the presented measurements were only conducted at room temperature.
To stabilize the device, the cryostat was lightly vacuum pumped to 200-400 mTorr.
Two source-drain pads from the graphene thermocouple device and two gate pads
are routed out through BNC cables. The source-drain contacts are connected to the
pixel amplifier input of the chip, and the gate bias for the device was applied from
external sourcemeters (not shown in the figure). The photoresponse was recorded by
an FPGA and a PC graphic user interface (GUI).
-
FFT PLOT
2.5
X: 248.9
Y: 2.514
--
1.5
-
2
0-
0.5-
0-
0
500
1500
1000
ANALOG INPUT FREQUENCY (Hz)
2000
Figure 3-25: FFT plot of the photoresponse measured at Pi = 157 p-W and fmod =
250 Hz input.
79
Figure 3-25 shows the FFT of the raw ADC output codes measured at the incident
laser power (Pi,) of 157 pW and the chopper frequency (fmod) of 250 Hz. A clear signal
peak near 250 Hz and the harmonics were observed. Due to the square waveform
of the photoresponse, strong 3rd (~750 Hz) and 5th (-1.25 kHz) harmonics were
observed, while the 4th (-l kHz) was due to ADC nonlinearity. We also noted that
the graphene thermocouples show 1/f noise characteristic at a frequency below -150
Hz.
By integrating the power spectrum density over the signal peak, we estimated
the signal amplitude as the voltage swing at the ADC input node. Figure 3-26 plots
the signal amplitude filtered at the modulation frequency over various incident laser
power level, where the power was limited up 400 pW to prevent burning of the device.
In addition to frequency selective signal estimation, a simple averaging of the output
codes can estimate the photoresponse because of the non-negative photoresponse even
when the chopper blocks the beam path. The averaged output codes along with the
DC offset is shown in Figure 3-27, noting enhanced (- 10x) output swing due to the
mechanically suspended sensor structure.
Signal Amplitude at the Chopping Frequency
10
---
-
-
-
I-
- --- -- --
_
-- ----
-
-
100
--
-
60---
20--
50
-
-
40
-
100
150
-
-_
-_-
80
_
-
120
-
--
140
- ----250
200
Input Power (pW)
300
350
400
Figure 3-26: Estimated photoresponse amplitudes at various Pm's by integrating
250
Hz
power spectral density of the signal peak at fmod=
These measurements demonstrate the readout ability of the presented readout IC.
80
Mid-IR Photoresponse
120
110-
1000
0
0
0)
DC offset
0
(zero input response)
70 ------------------------...............................-------
60
F
100
r
150
F
200
r
F
250
300
350
Input Power (pW)
Figure 3-27: Average output code measured at various Pm's. The signal nature
that only non-negative response is generated allows the photoresponse estimation by
simple averaging.
Furthermore, the whole data acquisition equipment set, including the lock-in amplifier
and the DAQ board (National Instrument), in the previous measurement setup [4]
can now be replaced by a compact PCB with the readout IC.
3.5.4
Integrated Graphene Sensor Array Measurement
Graphene and Dielectric Quality
After integration of the graphene thermocouple array, the quality of the graphene
layer and the gate dielectric were inspected. As Figure 3-28 shows, the structural
integrity of graphene layers were visually inspected under a microscope. The yield
chip.
of the thermocouples with clean monolayer was higher than 80% across the
Furthermore, the graphene's quality was investigated by Raman spectroscopy on four
locations picked across the chip as shown in Figure 3-29. The Raman spectroscopy
81
confirmed the low sample doping, as shown by the 2D-band
G-band
(WG
-
1585cm-1) intensity ratio (I2D
/IG
(W2D
-
2668cm-') to
2), and a low concentration of
defects as indicated by the low D-band to G-band intensity (ID/IG = 0.15
0.4)
[102, 103].
Row 57
Delaminated
Graphene
Row 58
Row 59
Col 20
Col 21
Co1 22
l
Co1 23
Figure 3-28: Micrograph of delaminated graphene layers in thermocouple array
The gate electrodes for the graphene thermocouple are routed to carry two different voltages usually in different polarity. In each pixel, the two gate electrodes (GI
and G2) have 700nm lateral spacing from each other and 70nm vertical spacing to
the graphene layer and metal contacts. Since the gate bias requires an operation in
high voltages ranging from -15 V to +15 V, the quality of gate dielectric layer had
to be verified. At VG, = +16V and VG2 = -16V bias condition, the leakage current
was less than 1 ptA, confirming that neither short between the gate electrodes nor
short through Si CMOS was observed.
Once we confirmed the good dielectric quality, testing of electrostatic doping of onchip graphene was conducted. Figure 3-30 shows the Raman shift of on-chip graphene
82
LO
2400
D-peak
220
2D-peak
G-peak
2 O01 8001600D
-
1 400
a
1200
600-
-
1000-
1000
1200
1400
1600
1800
2000
Raman Shift (cm-)
2200
2400
2600
2800
3000
Figure 3-29: Raman spectroscopy of graphene layers of on-chip thermocouples.
at various gate bias conditions. While the trend of the Raman shift indicates changes
in the carrier concentration, the transition from p-type to n-type was not clearly
observed within the (-15 V, +15 V) gate bias range.
IR Scanning Setup for Graphene-Integrated Chip
For the measurement of the photoresponse by on-chip graphene thermocouples, the
measurement setup was modified as shown in Figure 3-31. While the chip had to be
placed in the socket of the testing PCB, the testing board was too large to put in
the cryostat. Therefore, we replaced the cryostat by an aluminum vacuum cap with
the ZnSe anti-reflection coated window, which allows similar measurement condition
to that of the discrete detector measurement. The testing circuit board was securely
placed on a XYZ stage for IR focusing and spot placement. The size of the IR beam
spot at the focal plane was measured by burning a sheet of thermal paper and found
to be around 30pm in diameter, which allows in-pixel local heating for thermoelectric
effect, as shown in Figure 3-32.
83
On-Chip Graphene Raman Shift with Electrostatic Doping
2675
1600
-+-G-peaks -- D2-peaks
1598
2673
1596
2671
1594
2669
1592
2667
1590
2665
0 1588
2663
2661
4
1586
0
1584
2659
1582
2657
2655
1580
-20
-15
-10
0
-5
5
10
15
20
Gate Voltage [V]
Figure 3-30: Raman spectroscopy of graphene layers of on-chip thermocouples shows
electrostatical doping of graphene.
Preliminary Results
In the prototype chip with integrated graphene thermocouples, unfortunately, there
was an issue with electrical short of IOVDD power line to IOVSS ground line caused
by the graphene integration process. While more details are discussed in the following
section, we could eventually salvage the chip and were able to run the measurement
with limited row-column selection capability. To make the experiment possible, we
scanned the IR beam across a large area with continuous readout from a fixed pixel.
While the process of moving the beam spot around by a few micrometers until it
gets on the right pixel was extremely time-consuming, we managed to put the beam
on the right place. In the meantime, a graphical user interface (GUI) allowed us to
efficiently run the experiment. Figure 3-33 shows the GUI which contains a zoomedin FFT plot centered at modulation frequency in the middle and the color-coded plot
for multi-pixel readout on the right.
While the shown data was taken in multi-pixel scan mode, the overlapped signal
peaks in the circle and the fact that all tiles have similar color on the right map
84
Figure 3-31: Measurement setup for graphene-integrated sensor chip. The sensor chip
is sealed with a vacuum cap for stable performance. The beam shares the same path
described in Figure 3-24.
Figure 3-32: IR beam spot size at the focal plane was measured by burn marks
of thermal paper and found to be rv30 µm in diameter, which allows in-pixel local
heating for thermoelectric effect.
first indicate malfunction of row-column selection in this chip. Figure 3-34 plots
the extracted signal peak values at various input power in terms of excitation duty
cycle, where the chopping frequency was 79Hz and the gate bias was V01 = +16V
and V02 = -16V. While a complete 2D scanning readout demonstration must be
followed for imaging application, this preliminary result proves the integrability of
2D material-based devices with Si CMOS IC.
85
OWl Tesbench vI.1
204E
4
q484A
C w..Uweooe.Ooom..WmxmORLG
4E483
OW row
FFFF
U sf*.
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IMMYJ FL IUS
4A
Photorqsponsei
(6.16
H
I peak t f,
F I&I
78
785
79
79-5
80
Figure 3-33: Graphical user interface for IR detection experiment showing output
FFT plot centered at the light modulation frequency (center) and 2-D colored map
for array readout.
Extracted Peak Height
300
Chopping at 79Hz, Gate bias: 16V
250
54
L5U
-
200
100
50
0
35%
45%
40%
Laser Source Duty Cycle
50%
Figure 3-34: Signal peak values extracted from FFT of the photoresponse measured
by an graphene-integrated readout IC show a linear relationship to laser excitation
duty cycle.
86
3.6
3.6.1
Discussion
Graphene Models for Pixel Readout
Pixel Amplifier
Graphene
Photodetector
U
t
Figure 3-35: Readout architecture with pixel transimpedance amplifier and Norton
equivalent circuit model of the graphene photodetector. Contact resistance is neglected.
Figure 3-35 shows an transimpedance amplifier architecture with a Norton model
of graphene photodetector (G-PD as a current source).
The input current of the
amplifier (Ij,,) is given by a function of the photocurrent Iph, the output impedance
of graphene (RG), and the input impedance of the amplifier (RI ), so that
IIN
=
Ro
Ro + Ri
_Iph(36
Assuming the transimpedance of the amplifier is Gm, the output voltage is given
by
Vo = GmIin = Gm
Ro
Ro + R7
p(37
To maximize the output signal amplitude at given Iph and RO, it is desired to
maximize Gm and minimize Ri. A similar analysis applies to the architecture with a
Thevenin model of graphene photodetector (i.e. G-PD as a voltage source) shown in
Figure 3-36. The output voltage is given by
Vo = GmIin = Gn-
p h(38
RO + Ri
87
Pixel Amplifier
Graphene
Photodetector
amamamama
mmmaam
33535
a
'in
am
mamas mama a~m~a~g
a
a
a
a
a
a
a
a
a
U
a
a
aO
f
:R.
a
-~
+
a
a
a
a
a
U
a
a
a
a
a
a
a
amso
NNO
a
a
a
a
a
a
a
a
a
a
a
a
a
a
mmmmmammmmmmmmmmmaammmm U
Figure 3-36: Readout architecture with pixel transimpedance amplifier and Thevenin
equivalent circuit model of graphene photodetector.
Pixel Amplifier
Graphene
Photodetector
aO
a
IN:
*p "o
a
.
..
R,4,,I
7
.
..
.a.
.
1
Figure 3-37: Readout architectures with pixel transimpedance amplifier including
contact resistance from ohmic metal-graphene junctions.
88
Contact Resistance
Considering the contact resistance (Rc), as shown in Figure 3-37, the output of each
architecture is given by,
VONorton
VO,Thevenin =
(39)
GmRo
Ro + Rc + Ri
M
RO + Rc + Ri
(3.10)
Roft+-ft
R
Therefore, the output reduces by a factor of
Vph
in both cases. Since we
+ +
Ro + Rc + RI
only care about the signal amplitude, not the power, both models are interchangeable.
For best performance, Rc << RO+fR is desired, however, this is not trivial to achieve
along with on-chip integration.
Along with the practical limitation in minimizing
contact resistance and the moderate output impedance (-10 k2) of the integrated
graphene thermocouples, the readout of the thermoelectric voltage may be optimized
with voltage-input amplifiers.
Multi-Junction Graphene Photodetectors
Multi-junction graphene photodetectors may be used to gain better photocurrent or
photovoltage out of the sensor. Figure 3-38 shows a graphene device with parallel
multiple junctions is equivalent to a single graphene junction using the same area.
Therefore, we only consider a series multi-junction devices as shown in Figure 3-39.
Figure 3-38: Illustration of a single-junction model (left) and a parallel multi-junction
model (right)
89
N2,RNoRc
R,
VO
+
N Vpanf
Figure 3-39: Schematic circuit of a series multi-junction model (left) and its illustration (right)
The output voltage of N-junction photodetector (or thermocouple) is given by,
=
Gm
N
7
h
N2Ro+ N 2 Rc + Ri
Gm
R
N(Ro+Rc) +
H
where N is a positive integer, and 100% area utilization is assumed.
(3.11)
(3.12)
(
VoMJ
The multi-
junction device has advantage over a single-junction device when Vouti/V,ingl, > 1,
that is,
N (Ro + Rc) + - < Ro + Rc + R,
N
(3.13)
(N - 1) (Ro + Rc) < (NN)Ri
(3.14)
Ro + Rc <
HN
(3.15)
Here RO and Rc highly depend on the material quality and device fabrication.
The input impedance of transimpedance amplifiers is small, and the condition given
by Eq. 3.15 is hard to meet with N > 1. Thus, we conclude that the single-junction
device always outperform the multi-junction device. Furthermore, more degradation
is expected when we take the area overhead for fabricating multi-junction pixels into
account.
90
3.6.2
Power Line Shorting Issues
Electrical short of power routes (VDD's) to ground routes(VSS's) is one of the most
severe problems in chip testing since the chip cannot be powered at all once it occurs.
As in this work, the additional fabrication process can increase this risk by (1) unintentional scratches, (2) excessive metalization, and (3) excessive graphene residue.
Due to this problem, we lost the row-column selection control in our prototype chip
and could only demonstrate a single pixel photoresponse to infrared laser input as
presented in the previous chapter.
Top Metal Power Routes
The main issue with the initial graphene-integrated chip was electrical short in its
power lines. The chip pads were designed to share a common IOVDD/IOVSS lines
running along the chip edges. While the power lines were kept safe during most of the
post-fabrication process, a few top metal routings of IOVDD and IOVSS get exposed
(or nearly exposed) after the passivation etch process. In addition, the routings of
each IO power were placed very close to each other by 1 prm spacing making the
chip vulnerable even to mild scratches as shown in Figure 3-40. To reduce the risk
of shorting the metal routings during the graphene integration process, the layout of
the readout IC should (1) minimize routings in top metal layer and (2) make the line
spacing in the top metal extensively wider.
91
Figure 3-40: Scratches occurred during graphene integration process; Narrow spacing
in top metal layout should be avoided.
Excessive Metal Deposition
Excessive metal deposition on undesired locations can occur during the fabrication process.
It is often due to overdose of electron beam lithography and over-
developement of resists. Pads are one of the locations where excessive metal can
short two different power routes. As Figure 3-41 shows, we inspected these types of
electrical short a few times during the integration process. To reduce this kind of
risk, wider pad spacing should be used.
92
Figure 3-41: Scratches and excessive metal residue at pad region cause electrical
short.
Excessive Graphene Residue
Electrical short by graphene layer is an additional challenge we had during the fabrication. For fabrication of >4,000 graphene devices at once, the graphene layer that
we transfer onto the silicon substrate has to be large enough to cover the whole chip.
The uncontrollable nature in manual graphene transfer processi, such as sheet's rollup, tear out, and mislocating, often leads to excessive graphene residue on the chip's
near-edge area. Although mesa etching of graphene can clean up those regions, the
residue may occasionally remain as shown in Figure 3-42. However, fortunately, electrical short due to graphene can be alleviated by relatively easy treatments such as
additional mesa etching, local FIB cutting, or flowing excessive current to burn the
material.
Focused Ion Beam Cuttings
Focused ion beam (FIB) cutting tools offer handy post-fabrication fixes. Unlike an
electron microscope, FIB is inherently destructive to the specimen since it uses highenergy gallium (Ga) ions to strike the sample. The ion beam sputters atoms from the
'The graphene transfer process consists of CVD growing of monoloayer graphene on a sheet of
Cu foil, PMMA spin-coating, Cu etching in acid or base solution, manual fishing of floated graphene
by the substrate chip, and solvent cleaning steps.
93
Figure 3-42: Excessive graphene residue at pad region cause electrical short.
sample surface, so excessive metal or graphene structures can be removed. However,
it should also be noted that re-sputtering of the removed material can leave residues
on the sidewalls. A beam current of 0.28 - 0.93 nA, with an approximate dose of
2-5 nC/ptm 2 , was sufficient to cut most metal lines as shown in Figure 3-43, and the
continuous SEM option on the FIB of CMSE was used to monitor the etch.
Figure 3-43: SEM image of a FIB cut near pad region
3.6.3
Revised Metalization
In addition to the original process developed by Allen Hsu, we developed a metalization process that replaces the patterned sputtering step for ohmic plug metalization.
The revised process made in-house-only fabrication possbile while better conforming
94
Figure 3-44: SEM image of disconnected metal routing at dummy gap region
to the in-house fabrication rules in order to reduce the risk of sample and equipment
2
contamination. The details are provided in Appendix A.
Gap Filling Metal
The original Si CMOS chips fabricated from the vendor has regularly patterned top
metal dummies to meet the metal density requirement. As the received chips were
lacked surface planarization, the gaps in between the dummy patterns caused routing
disconnections as shown in Figure 3-44. To alleviate the surface roughness, deposition
of 400nm-thick Ti/Au stack has been conducted at desired locations as Figure 3-45
depicts. After this, regular routing patterns can be deposited over the dummies.
Tilted Ohmic Plug Deposition
In the revised process, an electron-beam evaporator (ebeamFP) replaced the sputterer
for metal deposition, and it resulted in less sidewall coverage. As the subsequent
3
electrical opens at the amplifier input metal plugs (L2) and in-pixel gate routing
(L3) 4 had arose, we switched the order of two deposition steps and had L2 deposition
on a tilted (300) wedge (Figure 3-46). As a result of tilted metal deposition, the
The process was developed in collaboration with Yuxuan Lin, Marek Hempel, and Charles
Mackin.
3 Ohmic Plug mask in the process given in Appendix A
4
Gate electrode mask in the process given in Appendix A
2
95
Figure 3-45: SEM image of metal-filled gap in the dummy metal region
sidewall coverage was recovered (Figure 3-47).
96
Figure 3-46: Aluminum wedge piece for tilted metal deposition. The tilt angle can
be either of 30' or 600.
Figure 3-47: SEM image showing sidewall coverage from tilted metal deposition
97
3.7
Concluding remarks
Starting from exploring graphene as a new infrared sensitive material that can be
used for sensors in mid- and long-wavelength IR spectrum (A = 2 - 15pm) imaging
system, we designed a Si CMOS-based readout IC for graphene thermocouple array.
The readout function was demonstrated both using an external current source and a
discrete graphene thermocouple device. In the measurement, the presented readout
IC replaced the lock-in amplifier and DAQ board combination used in the previous
work [4], demonstrating IR sensing system with significantly reduced form factor.
Based on the integration process developed previously [4], we fabricated an onchip graphene thermocouple array. The readout IC was used as a substrate for the
monolithically integrated array of 4,800 electronically tunable graphene thermocouples. The prototype graphene-Si hybrid IC was presented as a fully-featured sensor
system consisting of IR sensors and readout circuitary on a single 5-mmx5-mm die.
While the fabrication process was compatible with conventional Si CMOS technology,
we noted that the readout architechture and chip layout must be carefully designed
to ease the subsequent fabrication process.
While further development is in need to realize the 2D scanning imager, the presented column-parallel scheme and single on-chip sensor measurement suggest possible development of new types of graphene-Si hybrid applications. Furthermore, along
with the fact that the 2D patterning steps used in this study are applicable to other
planar materials, the fabrication and measurement schemes presented here can be
widely applied to on-silicon-CMOS-IC integration of other materials or structures.
98
Chapter 4
MoS 2 -Based Next Generation
Electronics
4.1
Introduction
The recent rediscovery of stable monolayer graphite or graphene has led remarkable
interest in the physic and applications of two-dimensional (2D) materials [104-107.
Beyond semi-metallic graphene, the rich variety of 2D materials include wide bandgap
insulators such as hexagonal boron nitride (h-BN) [108] and semiconductors as observed in transition metal dichalcogenides (TMDs) [109-111].
While either low off-current or saturated on-current is difficult to achieve in devices
based on zero-bandgap graphene, the semiconducting TMDs, such as molybdenum
disulfide (MoS 2 ), tungsten disulfide (WS 2 ), and tungsten diselenide (WSe 2 ), with
bandgaps in the 1 - 2 eV range, can provide excellent on/off current ratio as well as
current saturation. The feasibility of 2D material-based stand alone systems has been
demonstrated [48,104, 112-115], in addition to heterogeneous combinations with Si.
Taking the flexibility and transparency of the carrier transport substrate as unique
advantages over other bulk semiconductor substrates, 2D materials also enable a new
possible market of flexible, transparent, and ubiquitous electronics.
Furthermore,
recent theoretical analysis and experiments suggest the device performance can be
comparable even to the over-30-year-mature Si CMOS technology that has been a
99
great, and almost the only, main player to provide a variety of ICs in the electronics
ranging from high performance computation units to highly energy efficient systems
[116, 117].
4.1.1
Demands for MoS 2 -Based Electronics
Among the TMD family, MoS 2 is one of the most promising materials that have already demonstrated higher level circuits and systems, at least with a few transistors,
such as [48, 114,118]. While MoS 2 device technology is still in the early development
phase, it has the potential to be a key player in realizing the next generation electronics once given: (1) large scale and high quality production of the material, (2)
fabrication techniques for performance, stability, and yield, and (3) a computer-aided
design flow including good device models to simulate circuit for device performance
prediction and computer aided layout for large scale designs.
4.1.2
Material Growth
First, production of large-area MoS 2 monolayer is necessary to realize large-scale
MoS 2 circuits. While exfoliation of bulk MoS 2 crystal unreliably produces monolayer
sheets in limited size, a uniform and highly crystalline MoS 2 monolayer growth is
achieved with chemical vapor deposition (CVD) by Xi Ling [5].
Figure 4-1(a) shows the CVD system for material growth, that uses sulfur (S) and
molybdenum trioxide (MoO 3 ) as the precursor and perylene-3,4,9,10-tetracarboxylic
acid tetrapotassium salt (PTAS) as the seeding promoter to enhance area and uniformity of MoS 2 . The material growth process is conducted at a relatively low temperature (650 0 C), as the furnace temperature profile is shown in Figure 4-1(b). An
optical image of the CVD-grown MoS 2 is shown in Figure 4-1(c), demonstrating a
good uniformity and a high coverage approaching 100%. The dimensions of monolayer MoS 2 sheets are in order of 30 pm across the sample. The thickness is measured
to be 6.9A, a typical monolayer MoS 2 thickness, using atomic force microscopy (Figure 4-1(c), inset). A high resolution TEM as well as the crystal diffraction pattern
100
(a)
65 - - -
5sccm Ar
-
(b)
Gas out-'
m
in
mn Time
Figure 4-1: (a) A schematic illustration of the MoS 2 growth by CVD. (b) The temperature profile for the growth process. [5] (c) Optical micrographs and thickness profile
(inset) of monolayer MoS 2 . (d) High resolution TEM image and the corresponding
selected area electron diffraction (SAED) pattern (inset) show the hexagonal crystal
nature and the high quality lattice structure [6].
confirm the high quality of CVD-grown MoS 2 by the highly ordered lattice structure
as shown in Figure 4-1(d).
4.1.3
Device Fabrication
Secondly, the device fabrication process must be well-established to demonstrate
large-scale systems. For conventional MoS 2 FETs, with gate-last processes, dielectric
integration is usually conducted at low temperature and/or assisted by seeding layer
to protect the atomically thin channel substrate, both resulting in fixed charge and
trapped states inside the dielectric or at the interface. This causes extra scattering
hence degradation of mobility as well as negative shifts in VT.
In this work, in collaboration with Lili Yu, a gate-first process was adopted for
the gate metal and dielectric components to be fabricated before the MoS 2 transfer
step as illustrated in Figure 4-2.1 By using the gate-first process, high gate dielectric
and interface quality is achieved, which also enables potential scaling of the oxide
thickness down to a few nanometers. In comparison to the gate-last FETs, the gate1The process details are available in Appendix A.
101
Chnannel
source
ALD A1203
Dr1ain
WALD
SIO,/Si Subhst rate
---
SiO 2/Si substrate
Gate fabrication
dielectric layer
$FG annealing
Via hole etching
SD pads deposition
MonolayrMoS%
MoS 2 transfer
Hot KOH
MoS 2 rnesa etch
SD contacts
Passivation
Figure 4-2: Gate-first fabrication process for MoS 2 FET
first FETs not only show larger VT, 10x larger on-current, 100 x smaller off-current,
and steeper subthreshold slope (SS), but also result in far better VT-variation control
as shown in Figure 4-3. Among the advantages mentioned, the large VT (thus VT > 0
V) is especially critical for implementation of integrated circuits. Unless enhancement
mode operation (normally off) is provided with a positive threshold voltage, one stage
of circuit cannot drive the next stage without external level-shifting equipment, which
makes the device not attractive for IC. Therefore, the presented gate-first process
opens the way to the feasibility of large-scale MoS 2 electronics.
4.1.4
Design Flow
Lastly, to realize circuits in larger scale, a complete design flow should be introduced.
As shown in Figure 4-4, the proposed design flow consists of two phases: (1) device
development phase and (2) circuit design phase. The first phase consists of material growth, device fabrication, and device-level performance characterization. It is
followed by the next phase of circuit design that consists of device model implementation, circuit design with simulation, layout generation, fabrication, and system-level
measurement. The results in the end of a cycle provides feedback to improve the basic
device performance. This feedback loop plays a critical role when the technology is
102
(a 102,
10,
.5,(b,.) 30-. . V. I
300 mv/dec
104
10.
20
--
10-2
V =1.5 V15
115 mv/dec
G
Gate last
Gauss fitting of data
25
2000.
-
1
0.5 V
8
010.
10-10
5
-<--, Gate first
- -Gate lost
-4
-2
0
2
-0
4
0
6
-10
Vgs (V)
-8
-6
-4
-2
0
2
V- T(V)
Figure 4-3: Performance comparison of gate-last and gate-first processes: (a) I-V
characteristics in linear (right y-axis) and log scale (left y-axis) and (b) Gate-first
devices have average VT of 0.54V with standard deviation of 0.12V while those from
gate-last process have average VT of -4.20V and standard deviation of 1.75V. [6]
Device Development
rU
Caymtit
r-dd
Circino Comcut Mde
Figure 4-4: Proposed design flow for large-scale MOS2 integrated circuit development
103
still in an immature stage, since the performance of devices based on new materials
improves as the technology evolves, and the circuit design must adapt as well.
As further discussed in the following section, this thesis contribute to the development of the computer-aided design flow for large-scale MoS 2 integrated circuit
design.
4.2
Computer-Aided Design Flow
Over the last few decades, silicon CMOS industry has leveraged the unified design
environment provided by the CAD tools, that support not only circuit simulation
but also layout generation and verification process. A CAD flow typically includes
physical or empirical models of the active and passive components (i.e. diode, FET,
R, L, C), circuit simulators such as SPICE for performance evaluation, parameterized layout cells, as well as verification tools for checking that the layout is compliant
with design rules (such as metal spacing) as well as for comparing the layout versus
the schematic. Since this CAD flow allows the designer to predict and optimize the
performance of the circuits before production of the lithographic masks, significant
reduction in the time required for debugging and consequently cost of fabrication of
silicon CMOS systems have been achieved. In contrast, circuit design with devices
based on new materials has lacked such environment, and the researchers in emerging
fields have only been able to take limited advantage of the CAD software. Therefore,
implementation of electronics based on new materials has often been conducted by
circuit design based on hand calculation and/or intuition and fully manual generation
of layout patterns for each lithographic mask. By implementing device models into
SPICE or Verilog-A language, the complexity of the designs that can be pursed with
such emerging materials can be drastically increased, which enables a new paradigm
for its applications. Furthermore, generation of corresponding layout using parameterized cells is another key procedure for time-efficient circuit implementation. In
this work, we have developed a CAD flow for MoS 2 -based systems that includes: (1)
compact models of MoS 2 devices, (2) schematic design based on circuit simulation,
104
and (3) layout with parameterized cells. In the later part of this chapter, the design of
a switched-capacitor (SC) DC-DC converter and a half-wave rectifier is also discussed
as examples.
4.2.1
Modeling of MoS 2 -Based Devices
For accurate circuit simulations, device models of MoS 2 , either physical or empirical,
must be provided in a form compatible with circuit simulator languages, such as
SPICE, C, or Verilog-A. To develop the CAD flow for MoS 2 technology, a number of
different circuit models were investigated.
Analytic Diode Model
Since a diode is a two-port device, explicit equations that describe the input-output
(VD
-
ID) relation may be derived. The Shockley ideal diode equation gives the I-V
characteristic of an ideal diode as following,
ID = Is(eVD/nVT
_
1
(4.1)
where Is is the reverse bias saturation current, VT is the thermal voltage (kBT/q), and
n is the ideality factor. Compared to the exponential characteristic in ideal diodes,
2111
Figure 4-5: Gate-Drain connected MoS 2 FET was used as MoS 2 diode.
our MoS 2 diodes as shown in Figure 4-5, which really are Gate-Drain connected FETs,
have less steeper slope increment in the forward bias regime. Therefore, a modified
diode equation, instead of Eq. 4.1, is introduced as below,
105
ID
= b4 VA + b3 V3 + b2 VD2+ b1VD+ bo
ID = ISM (eVD/am
-
1)
To make it analytic, ID(VD = 0) = 0 and
when VD > 0
(4.2a)
when VD < 0
(4.2b)
dID
has to be continuous. Therefore,
dVD
bo = 0 and b1 = ISM
am
Figure 4-6 depicts the fitted curve of a MoS 2 diode to the modified diode equation
Eq. 4.2. The forward bias current is fitted with a polynomial (Eq. 4.2a) to effectively
IL) = IsM (clT/""n
-
if)- b1~~+ D .2V bV'
1)
X104
Forward Bias
Region
Reverse Bias
Region
24
++ +
45
4
35
3
-2.5
-2
-1'
-1
0.5
-05
1
1.5
2
25
3
+
14
35
4
45
i
Figure 4-6: Fitted diode equation shows a good agreement with the measurement.
model the diode characteristic less steeper than exponential curves. In the demontrated case, it was fitted to a 4th order polynomial, while higher order polynomials
resulted in negligible improvement. For the reverse bias current, as shown in Figure
4-7, a polynomial equation cannot provide a saturating current toward negative bias
and be monotonic at the same time. Furthermore, it is important to suppress the
measurement noise, otherwise, small signal simulation can go chaotic, therefore, the
exponential equation (Eq. 4.2b) is applied. With these two explicit equations of VD,
106
and
we can also ensure the monotonic I-V characteristic of the modeled diode
2
directly implement the model in Verilog-A code for circuit simulation.
ID,
Diode Fitting
x 10-7
*
4
---
3 ........ ---
Measurement
10th-O rder poly.
Exponentia
- ------- -------------------
.........
-----
.
m t.
..
...
H. gh ......... rd................................ p ..
2 F.gu re.4-.:
.....
- 44......-
-3 ----- 4
4--
.-
--
2--- -1....-.
- ----
0----5
-------------5-1----------------------I-5--------------- -35..
Figure 4-7: High order polynomial equation cannot model the reverse bias diode
current due to its non-monotonicity and large error.
Empirical FET Model
An empirical model of the MoS 2 FET was built using a look-up table derived from the
measurement data and implemented with $table.model function in Verilog-A language. The model generates an approximated output current at any input (VGS, VDS)
utilizing interpolation and extrapolation of the raw data in the way specified with the
3
optional arguments.
The immediate benefit of this behavioral model is that neither prior knowledge
on the device physics nor convergence in fitting algorithm is required, since it is
based on a look-up table solely derived from data, not from any physical analysis.
More importantly, the output current of the model is determined from polynomialfit splines, so it offers the best approximated output values for a given dataset, in
terms of the large signal conformity. However, the empirical is subject to capture
measurement noises unless preprocessing of data filtered them out. Furthermore,
2
3
The Verilog-A code for the fitted diode model can be found in Appendix C.
The Verilog-A code for the empirical model can be found in Appendix C
107
it requires additional modeling for AC characteristics. Therefore, we investigate a
physical model which can give comprehensive device description.
Drift-Diffusion Compact Model
A drift-diffusion compact (DDC) model'is employed to describe the characteristics
of the MoS 2 FET. The DDC model is based on the electron transport properties of
atomically thin MoS 2 [6,119].
The lateral current in the model (ID) can be simplified
as below,
ID=
where
Qj,
I2 WF(Vsat) (Qis + Qid) Vsat
(4.3)
and Qid are the channel charges at source and drain, respectively, and Vsat
is the saturation velocity of the carrier. The F(Vsat) is the empirical function for the
smooth transition from the linear to saturation regimes, which is given by
Qis - Qid
F(Vsat)
CinviVDSAT
=
(4.4)
1+ + Qis - Qid
(CinviVDSAT)
1
VDSAT
=
VsatLG
(4.5)
where Cinvi is the channel-to-gate capacitance at charge inversion, and / is an empirical fitting parameter. The DDC model not only provides a reasonable I-V behavioral
description of MoS 2 FET including the subthreshold current but also allows physical
understanding of the carrier transport dynamics. Figure 4-8 plots the I-V characteristics of the DDC model and the empirical model along with the measurement,
where both of the model provides good agreement to the measurement. In qualitative comparison, shown in Table 4.1, the empirical model has the best agreement to
the original data, thus it allows accurate DC analysis. However, for accurate small
signal and transient/frequency responses, the DDC model is necessary as the model
well-suits for AC simulation thanks to its inherent capacitance parameters.
4
The MoS 2 DDC model is developed by Shaloo Rakheja.
108
3
100
W/L = 40pmi/21 m
VGS = OV to 5V (bottom to top)
in 1V step
2
40pm/2pm
L = ~W
Vs=0.9
V
r
10-5
0
- --
0
0
0.5
1
1.5
10. 01
2
-2
0
VDS (V)
Measurement
-Empirical
DDC
4
2
VGS (V)
Figure 4-8: Comparison plot of MoS 2 FET models
Table 4.1: Qualitative comparison table of device models
Large Signal Conformity
Small Signal Behavior
Channel Length Modulation
Sub-Threshold Current
AC Characteristics
Fair
109
I
Poor
Fair
6
4.2.2
Technology Library and Parameterized Cell for MoS 2
Layout
Custom Technology Library
To effectively utilize the Cadence design environment for layout generation, a custom
technology library is created. 5 The technology library file defines five main layers:
Mesa - to pattern the MoS 2 channel region.
Gate - to pattern the gate metal stack of Cr/Au/Pd.
Contact - to pattern ohmic contact layer (Au).
Pads - to pattern the pad region (Ti/Au).
Vial - to define the via holes for creating connection from Gate layer to Pad/Contact
layer.
Auxi, Aux2 - auxiliary layers for future use.
Parameterized FET Layout Cell
Based on the layer definitions in the custom technology library, a parameterized cell
(P-cell) has been created to allow the automatic generation of the MoS 2 FET layout
from the transistor width and length. Figure 4-9 depicts an example layout with Pcells of 40pm/4pm and 20pm/2pm MoS 2 FETs in the Cadence layout environment.
The dimensions and relative positions of the corresponding layers, i.e. Mesa, Gate,
Contact, Pads, and Vial, are derived from predefined P-cell rules. The user-defined
rules also include the range of transistor size, for instance, W = 4 - 200pum and
L = 1 - 50pm, according to the fabrication capability. Once P-cells are generated,
placement and routing processes are done manually. Then, the full chip layout is
exported in gds format for mask production by commercially available vendors.
5The details are provided in Appendix C
110
Figure 4-9: Layout of MoS 2 thin-film transistors (W/ L = 40µm/ 4µm and
20µm/2µm) using P-cells in Cadence software. The layer definition is given in the
legend.
4.3
Circuit Design Demonstration
The presented design works were conducted in collaboration with Dina El-Damak,
while the measurement was conducted with Lili Yu and Dina El-Damak.
4.3.1
Switched Capacitor DC-DC Converter
Utilizing the proposed CAD flow, a switched capacitor DC-DC converter was implemented. Figure 4-10 shows the schematic diagram (left) and the micrograph (right).
The converter consisted of two MoS 2 switches, a charge transfer capacitor (CJty), and
the output capacitor (Gout)· In this implementation, Cfty was 56pF, and the switch
size was 40µm/ 2µm.
When the switching inputs,
<I> 1
and <I> 2 , are applied in 180° out-of-phase, the
output voltage of the converter, Vout, is given as a function of DC input voltage (Vin) ,
load current Uout), switching frequency Usw) and cfly · That is,
111
vi,,
vaut
Figure 4-10: Schematic diagram of the switched capacitor converter and micrograph
of the fabricated converter
Vout
Vn
Cf lyfw
Vi - Ref 'out
-out
(4.6)
where Reff is the effective resistance of the switched capacitor.
Measurement Setup
A prototype MoS 2 IC, fabricated on top of a SiO 2 substrate, containing the converter
is shown in Figure 4-11. In addition to the SC DC-DC converters, the chip contains
arrays of FETs, diodes and capacitors for basic component re-characterization for
model updates and fabrication feedback.
The measurement was conducted in a probe station, as shown in Figure 4-12.
Tungsten probe tips were used to make electrical contacts to the probing pads of the
MoS 2 devices. A function generator (Agilent) is used to drive the switching signals,
4Di and 4D2, at 5V swing, and a sourcemeter (Tektronix) was used to supply Vin and
Iut and measure Vut all through BNC cables.
Results
The measurement results of the output voltage while varying load current and switching frequency along with the simulated output voltage are shown in Figure 4-13. The
simulation based on the DDC model of FET allowed a good prediction of the actual
circuit performance, proving the effectiveness of the CAD flow.
112
5mm
E
toE
Vi,
Figure 4-11: Optical Micrograph of the fabricated test chip using CVD-grown monolayer MoS 2 , showing arrays of FETs, diodes and switched capacitor DC-DC converters
Figure 4-12: Photos of the probe station setup showing (a) an optical microscope and
probe tips (a), and closed up view of ground plate and held chip (b,c)
113
Measurement (solid) and Simulated (dashed) Output Voltage
-f
3
=
10kHz -f
=
50kHz -f
=
100kHz
2
0
1
0
0
6
2
8
10
Load (pA)
Figure 4-13: Simulation (dotted) and measurements (solid) of the output voltage
versus the load current of MoS 2 SC DC-DC converter
114
4.3.2
Half-Wave Rectifier
Rectifiers are typically used for AC-DC conversion in wireless power transfer and
piezoelectric energy harvesting systems. A diode rectifier was implemented in the test
chip using a MoS 2 FET with its drain and gate connected and an external ceramic
capacitor. Figure 4-14 depicts the test setup where a function generator provide the
input sinusoidal signal to the rectifier and the voltage signal across the output off-chip
capacitor is probed by an oscilloscope. The size of the output capacitor is selected
based on the input signal frequency such that it minimizes the output voltage ripple.
Cout
Rout
--
Figure 4-14: Schematic diagram of test bench for diode rectifier (left) and micrograph
of fabricated MoS 2 diode (right)
Figure 4-15 shows the measurement result of the half-wave rectifier at 1 MHz 8 V p-p
sinusoidal input signal. The output was rectified DC voltage at rv2.6 V with < 150
m V ripple, matching with the simulation. While MoS 2 transistor models worked well
as on-off switches in the switched capacitor based circuits, the rectifier demonstration
shows that we have good analog simulation capability. Furthermore, the bandwidth
of the diode rectifier was measured. As shown in Figure 4-16, a constant rectified
output was measured across the frequency range from 100 kHz and up to 20 MHz
where the load current is kept at 10 µA. The measurement at higher frequencies
were subject to impedance mismatch in the measurement setup, thus suggesting the
rectifier bandwidth to be at > 20 MHz.
Therefore, this demonstration not only
shows the good agreement between simulation and measurement, but also suggests
that MoS 2 diode rectifiers are applicable to high frequency applications, particularly
115
for wireless power receivers operating in the 6.78 MHz and 13.6 MHz ISM bands.
Half-Wave Rectifier Output (VIN = 8V
, fw = 1MHz)
0
-5
-1.5
-2
-0.5
-1
1
0.5
0
1.5
2
Time (ps)
Figure 4-15: Transient waveforms of 1 MHz 8 Vp.. sinusoidal input and measured
output voltage of the diode rectifier circuit along with the simulated output (dashed
line)
Half-Wave Rectifier Output
, COUT = 10nF)
(VIN= 7V
8
-
*
7~
''I'
'i
data1
data2
65-
-
1
0
105
106
f. [Hz]
107
108
Figure 4-16: Rectifier output at various frequencies at 10 pA load current where
Vin= 7 VP-P and C, = 10 nF
116
4.3.3
Voltage Doubler
Additionally, a voltage doubler circuit, as shown in Figure 4-17, was implemented.
The circuit consists of stacked half-wave rectifiers in seriesand the even order output
nodes generate rectified voltages (V2 and V 4 ). In ideal operation, V 2 acts as ground
for charge pumping to V4 , thus generating doubled voltage.
Measurement results are shown in Figure 4-18. 6 VP.. sinusoidal input was applied
for all measurements. The curves of low load current (IL = 0.1 pA) show doubling
behavior between V 4 and V 2 at high frequencies. As the input frequency goes low,
i.e. slower switching, the reverse bias diode current and capacitor leakage reduce
the stored charge in each node significantly, thus, the charge pump efficiency drops.
At high load current (IL = 10 pA), the 4th stage charge pump barely delivers the
excessive charge over the load consumption, resulting in V 4 ~ V 2 . The negative
output voltage in the low frequencies just means that the delivered power through
the charge pumps is less than the load power consumption.
Cl
C
V
VIN
V4
2
C2
C
C4
Figure 4-17: Schematic diagram of voltage doubler circuit
117
Voltage Doubler Output
2.5
x
-
-B-
2 ~
E)
>0
1.
Il=10pA
V4
'L= MA
1
V 2 L= 0pA
-. V
--
1.5
V4
-
-
1
2 ' L=1pA
V 4,
2
V2
1L=0.1p/A
.1 A~
~L
l---
0.5
-0.5
-1
105
107
106
108
f.n [Hz]
Figure 4-18: Voltage doubler outputs at 6 Vp..
sinusoidal input and IL = 0.1, 1, 10
pA
4.4
Concluding Remarks
In this chapter, a complete CAD flow to realize MoS 2-based large-scale integrated circuits is presented. Device models for MoS 2 diodes and transistors, are developed and
implemented in both behavioral and physical forms, which enables circuit simulation
for a wide range of digital and analog circuit design. Combined with the state-ofthe-art fabrication technology, we were able to demonstrate a CAD flow, similar to
the one of standard silicon IC design flow, and its full procedures by building a SC
DC-DC converter, a half-wave rectifier, and a voltage doubler circuits for the first
time with MoS 2 devices. In the demonstrated circuits, the simulation has provided
good agreement with the measurements. Also, the time-efficient IC fabrication was
possible, since the custom technology library and P-cell for MoS 2 have expedited
layout process.
Meanwhile, the presented CAD flow, including device modeling, circuit simulation
and parametric cell-based layout just as in standard Si CMOS technology, is not
a unique solution solely for MoS 2 ICs. Rather, it can be applied to other TMDs
which share similar mechanical properties, carrier transport mechanism, and device
structure (e.g. WSe 2 , WS 2 , and etc.), assuming that large-area material growth and
118
proper circuit models have been achieved.
Nevertheless, our CAD flow for MoS 2
technology has verified its use and potential. Therefore, it has paved the way for
large-scale MoS 2 electronics as well as applications of other 2D materials, so that
the emerging technology of 2D materials and their heterostructures would realize the
new family of ubiquitous electronics (e.g. transparent and flexible ICs on arbitrary
surfaces) over the edge of the traditional technologies.
119
120
Chapter 5
Outlook and Future Work
5.1
Thesis Contributions
In conclusion, I have investigated the utilization of new materials and devices that
extend the boundary of traditional electronic systems in three directions: (1) as
discrete add-on devices, (2) as monolithically integrated add-ons, and (3) as standalone electronic systems.
5.1.1
Cellular Electric Impedance Spectroscopy
Bio-compatible electrical interfaces are the key for low-cost diagnostic tests, health
signal monitoring electronics, and fundamental studies in biology and medication.
In particular, Bio-MEMS devices in micro-/nano-meter scale provide cellular and
molecular interfaces, often in forms of microfluidic devices.
In the first part of the thesis, design of a microfluidic device for cellular EIS and
electrical malaria diagnostic test was discussed. The fabrication of microfluidic probe
device and the proper measurement setup allowed highly sensitive electric impedance
measurement of individual erythrocytes. We further developed an analysis method
using a dimensionless parameter 6 to quantify the deviation in the magnitude and
phase shift of electric impedance of malaria infected cells. In conclusion, the reported
cellular EIS system electrically screened human erythrocytes infected by P. falci121
parum malaria parasites, which achieved a high SNR not just enough to distinguish
intracellular electro-chemical changes of tiny live cells but also capable of early stage
malaria detection, suggesting a use in early diagnosis by fully electrical tests.
The presented cellular EIS system provides not only a breakthrough in electrical
diagnostic tools that directly interface with biological cells but also a fine example of
electronics with non-traditional Bio-MEMS add-on devices. By this example, it was
shown that new interface materials and devices could bring an additional feature of
sensing pathological modification of biological cells.
The following lists contributed publications in this work.
" S. Ha, M. Diez-Silva, E. Du, S. J. Kim, J. Han, M. Dao, and A. P. Chandrakasan,
"Microfluidic Electric Impedance Spectroscopy for Malaria Diagnosis," 16th Int.
Conf. Miniaturized Syst. Chem. Life Sci., pp. 1960-1962, 2012.
" E. Du, S. Ha, M. Diez-Silva, M. Dao, S. Suresh, and A. P. Chandrakasan,
"Electric impedance microflow cytometry for characterization of cell disease
states." Lab on a chip, vol. 13, no. 19, pp. 3903-3909, Oct. 2013.
5.1.2
Graphene-Silicon Hybrid Infrared Imager
Graphene has recently gained significant interest for its exceptional electrical, optical,
and mechanical properties. Research efforts to improve the graphene technology in
terms of bio-chemical functionalization, device performance, and material growth,
have enabled numerous graphene-based sensors, high performance RF electronics,
and high quality and large area device fabrication. In the 2nd part of the thesis,
graphene was investigated for integrated add-on devices for traditional Si technology,
focusing on the thermoelectric effect in graphene and its compatibility to Si substrate.
In development of the graphene-Si hybrid IR imaging systsem, a readout architecture for graphene IR sensor array was discussed. Light modulation scheme and the
front-end transimpedance amplifier were adopted for optimized current readout from
the low impedance sensing material. The readout architecture was verified not only
122
with an external current source equipment, but also with a wire-connected discrete
graphene thermocouple device.
In the prototype chip, >4,000 electronically tunable graphene thermocouples were
fabricated using the readout IC as a substrate. The prototype graphene-Si hybrid
imager IC consisting of IR sensors and readout circuitary on a single 5-mmx5-mm
die was demonstrated. Although the graphene integration process damaged pixelselection function, on-chip photoresponse by single pixel could be measured, suggesting that full 2D scanning imaging is possible in the next batch.
To enable the integration of graphene thermocouples, a post-fabrication friendly
Si CMOS IC design was also implemented. To ease the graphene integration process, it was desired to have larger chip size, minimized top metal routings, excessive
spacing in top metal and pad routings, and most importanly, planarized chip surface. The readout IC design can be further optimized in case of interfacing thermal
sensors with moderate output impedance by (1) voltage-input signal amplification to
neglect graphene-metal interconnect contact resistance, (2) full pixel area utilization
of amplifier design assuming top-side illumination and surface flattening by top metal.
While further development is needed to realize the 2D scanning imager, the scalable column-parallel scheme and single on-chip sensor measurement lead to possible
development of new categories of graphene-Si hybrid applications. Furthermore, the
fabrication and measurement schemes used in this exemplary integrated graphene
interface can be widely applied to other 2D materials to provide conventional silicon
technology a wide range of integrated add-on devices.
The following lists contributed publications in this work.
o A. L. Hsu, P. K. Herring, N. M. Gabor, S. Ha, Y. C. Shin, Y. Song, A. P.
Chandrakasan, J. Kong, P. Jarillo-Herrero, and T. Palacios, "Graphene-based
Thermopile for Thermal Imaging Applications," submitted for publication.
o S. Ha, A. L. Hsu, S. Ha, T. Palacios, and A. P. Chandrakasan, "A 0.18um Column Parallel Readout IC for Graphene-based Thermocouple Array," in preparation.
123
5.1.3
MoS 2 -Based Electronics
Among 2D materials, which all share atomically thin nature, flexibility, transparency,
and large surface-to-volume ratio, Molybdenum disulfide is especially interesting in
system designer's perspective.
With this one molecular thick planar crystal, re-
searchers have not only proven exceptional device performance for flexible/transparent electronics, but also achieved large area material growth and high yield device
fabrication. In the last part of the thesis, the focus was to bring the MoS 2 technology
to the next level in terms of the scale of integrated circuit.
Even though the technology is relatively mature, it is still in a developmental
stage, especially when it comes to large scale integrated circuit design. That is, the
device performance keeps changing or improving, thus the circuit model and design are
required to be continuously updated. To realize large scale ICs in MoS 2 technology,
the cycle of design and fabrication has to run quicker, and the gap between design
and actual performance should be reduced. In order to do that, a computer-aided
.
design flow was introduced for MoS 2
First, device models for MoS 2 diodes and transistors, in both behavioral and physical models, were developed and implemented in a circuit simulator language.Also,
a custom technology library and P-cell for MoS 2 device layout expedited the chip
layout process, so the time-efficient IC fabrication was possible. Within this unified
design environment implemented in Cadence software, circuit simulation and layout
generation were conducted. Combined with the state-of-the-art fabrication technology, SC DC-DC converter, a half-wave rectifier, and a voltage doubler circuits were
demonstrated with MoS 2 devices, and the measurement showed good agreement with
the simulation.
It should be noted that the presented CAD flow is not a unique solution solely
for MoS 2 ICs. Rather, it can be applied to other TMDs and their heterostructures
which share similar mechanical properties, carrier transport mechanism, and device
structures, assuming that large-area material growth and proper circuit modeling
have been achieved. Therefore, the presented CAD flow paves the way for large-scale
124
MoS 2 electronics as well as applications of other 2D materials. The demonstrated
MoS 2 technology also suggests that the technology in new materials and devices would
realize the new family of stand-alone electronics over the boundary of the traditional
electronics.
The following lists contributed publications in this work.
* L. Yu, S. Ha, D. El-Damak, E. McVay, X. Ling, A. P. Chandrakasan, J. Kong,
and T. Palacios, "Two-dimensional materials based transparent flexible electronics," Bull. Am. Phys. Soc., vol. 60, 2015.
" L. Yu, D. El-Damak, S. Ha, S. Rakheja, X. Ling, J. Kong, D. Antoniadis, A.
P. Chandrakasan, and T. Palacios, "MoS2 FET Fabrication and Modeling for
Large-Scale Flexible Electronics," in Symp. VLSI Technology, to be published.
5.2
Future Work
While along the thesis, we have investigated the utilization of microfluidic device,
graphene thermocouple, and MoS 2 transistor in pursuit of next generation electronics,
in the following sections, we examine some future/ongoing work along three different
directions: (1) 2D Scan Imaging with Graphene Thermocouple Array, (2) MoS 2 RFID
tags, and (3) MoS 2 Display Driver.
5.2.1
2D Scan Imaging with Graphene Thermocouple Array
As a follow up of our works discussed in Chapter 3, we are pursuing the demonstration
of 2D scan imaging by the on-chip graphene thermocoule array. While most of the
issues with the original design and fabrication process are already addressed in Section
3.6, we will add additional pixel structures on the chips of the new batch. This is to
have functional verification of integrated graphene thermocouples in the pixel level,
while we could not probe on-chip graphene thermocouple devices externally in the
previous chips.
125
5.2.2
MoS 2 RFID Tags1
MoS 2 Rectifier
Phase #1:
Wireless Power Link
w/ LED Load
-
%--
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
--
----------------------------------------
-
-
--
MoSt
devices
LDO
A
-
Phase #2:
Wireless Transmitter
47
IV
-
Phase #3:
REID
-----
Ref. Gen.
Reu
I
----
----
-------------------
I
-
Figure 5-1: 3-Phase Development Plan for MoS 2 REID Tags
Figure 5-1 shows the 3-phase development plan for MoS 2 RFID tags. In the first
phase, we are demonstrating a wireless power link with MoS 2 technology. While
active power consumption of target RFID tag is estimated in order of 100 PW, we set
the demonstration goal for 1st phase chip to deliever 1 mW. At that level of power
consumption, a low current LED can be used as the load component. The key MoS 2
component in the 1st phase chip is the rectifier. Since we have seen in Chapter 4 that
the bandwidth of MoS 2 diode goes above 20 MHz, it does make sense to implement
an MoS 2 RF rectifier (13.56 MHz) with a corresponding LC tank. Figure 5-2 depicts
such system made on a sapphire substrate. The bottom coil is an external RF source,
e.g. PCB coil, and power is transferred through the inductive coupling of two adjacent
'This work is in collaboration with Lili Yu and Dina El-Damak.
126
coils. The RF signal is then rectified and stored on a capacitor as well as turning on
the LED.
Caps
Light
Emission
Sapphire
substrate
Rectifr
Li
Figure 5-2: Illustration of Wireless Power Link Operation with On-Chip Inductor
The concept design is supported by the simulation. As shown in Figure 5-3, power
transfer > 30pW is expected given k = 0.02 and the resonance at 13.56 MHz. In the
full-wave rectifier, replacing two diodes with a pair of cross-coupled FETs (Figure 54) allows 50% efficiency improvement over 4-diode rectifier, by reducing the effective
threshold voltage of the MoS 2 diodes.
In the 2nd phase of project, we will focus on demonstration of impedance modulation telemetry and digital logics. Then, we will go for integrationi of everything on
chip to make RFID tag in the 3rd phase.
127
Load Power [mVWJ
700
Of
Of
M
Jl2
06
i , ---
04__.X
6.49
6
4
M
k=
M
-.m-k=0.08
-+-k=0.06
I
-U-k=0.04
-@-k=0.02
3
Li
L2
2.61
2
1
0.594
0.030
0
92
94
96
98
-
a0 0
100
C2 [pF]
102
0-0-.
104
106
108
- LED light emission
detectable at >1 pW
k > 0.0 is desired
Figure 5-3: Simulated transferred power at various coupling coefficient (k)
VDD
320/2
VN
VP
300/2
Vss
Figure 5-4: Full-wave rectifier with cross-coupled FETs and two diodes
128
5.2.3
MoS 2 Display Driver
In parallel to the RFID development, we are investigating MoS 2 circuit as heteroplane
of organic LED (OLED) displays. 2 While we eventualy aim for a transparent display
driver circuit integrated with 1" x1" OLED panel, we were able to test the LEDdriving component by connecting a low current LED as shown in Figure 5-5.
for MoS2
-.-
Display Driver
Figure 5-5: Testbench of MoS 2 LED driver array
In the preliminary works, the driver circuit has shown good performance in atmosphere for a limited time. Therefore, as the following steps, we will need to develop a
good passivation technique for MoS 2 devices to enable long-term in-air operation as
well as the integration process for OLED array.
2
This work is in collaboration with Lili Yu.
129
Appendices
130
Appendix A
Process Flow
EIS Probe Device Fabrication
A.1
The process is adopted from [2].
A.1.1
Probe Electrode Parts
1. Start with 0.500mm-thick 6-inch Pyrex glass wafers (Sensor Prep Service Inc.)
2. TRL Hotplate 2 - Bake at 115'C for 3 minutes to get rid of moisture that
degrades the resolution of photoresist (PR).
3. TRL Coater - Spin coat with a negative PR
NR71-3000P (Futurrex Inc.) at 3000 rpm for 40 seconds.
4. TRL Hotplate 2 - Prebake at 140*C for 3 minutes.
5. TRL EV-LC Exposure for 10 seconds with 365nm UV.
6. TRL Hotplate 2 - Postbake at 110'C for 3.5 minutes.
7. Develop PR
RD6 developer solution for 25 seconds.
Check the pattern under microscope.
131
8. Clean with DI water and dry with N 2 gas.
9. Ebeam-FP - Metal Deposition
10 nm Ti - No rotation, Deposition rate = 0.1nm/s
100 nm Au - No rotation, Deposition rate = 0.2nm/s
10. Lift-off
Left in RR41 resist remover overnight then use pipette.
Sonicate with Acetone/IPA and N 2 dry.
Check the pattern under microscope.
Use Microstrip to remove PR residues if necessary.
11. Diesaw
A.1.2
Silicon Mold Part for Microfluidic Channel
1. Start with 6-inch bare Si wafers
2. TRL Oven - Bake at 95'C for 3 minutes to dehydrate.
3. HMDS run
A
0-44. rVDT
TRL Coater
- QSpin CCoat
AZ5214 at 3000 rpm for 40 seconds.
5. TRL Oven - Prebake at 95'C for 3 minutes.
6. TRL EV-LC Exposure for 15 seconds with 365nm UV.
7. TRL Oven - Postbake at 120'C for 3.5 minutes.
8. Develop PR
RD6 developer solution for 25 seconds.
132
Check the pattern under microscope.
9. Clean with DI water and dry with N 2 gas.
10. TRL-STS 1
RIE for 5pm
Check the depth with AFM
11. TRL-Asher
800W for 30 minutes.
A.1.3
PDMS Curing and Bonding Process
1. Start with Si mold wafers.
2. Prepare polydimethylsiloxane (PDMS) base gel and curing agent.
3. PDMS base gel and curing agent in ratio of 10:1.
4. De-gas in a vacuum chamber for 1 hour.
5. While waiting for de-gas, coat Si wafer by trichlorosilane (HSiCl3 ).
6. Pour PDMS mixture on the Si mold and remove air bubbles if any.
7. Bake on hot plate at 95'C for 2 hours, then PDMS is solidified.
8. Peel off PDMS and cut into 1 inch by a half inch cells.
32 microfluidic channel parts per wafer
9. Puncture holes for inlet and outlet of fluid.
10. Oxygen plasma excitation of both the top surface of electrode substrate and the
bottom surface of PDMS cell.
11. Align and bond them under microscope.
133
A drop of IPA can ease the alignment process
12. Bake on hot plate at 95'C for 2 hours for stronger covalent bonding between
PDMS and glass substrate.
13. Attach copper tape or wires to the electrodes and tubes to the fluidic inlet and
the outlet.
A.2
Graphene IR Imager Integration
This process is initially developed by Allen Hsu [4] and revised by Sungjae Ha.
A.2.1
Sample Preparation
1. Solvent Clean
Acetone/IPA/N2 with ultrasonics in teflon beakers (PWR = 5-6)
A.2.2
Passivation Etching - Patterned
1. TRL Coater - MMA/PMMA Layers
MMA 8.5 EL 11.5 (750 rpm for 2s, 4000 rpm for 60s)
TRL Hotplate 2 - Bake at 175 'C for 7 minutes/ Cool for 3 minutes
PMMA A8 (750 rpm for 2s, 4000 rpm for 60s)
TRL Hotplate 2 - Bake at 175 'C for 7 minutes/ Cool for 3 minutes
2. Elionix 125 (Li-ETCH)
Beam Current = 30nA
Dwell Time = 0.08[ts
Dose = 2400 puC/cm 2
3. Develop Bilayer Resist (slight agitation)
134
MIBK:IPA 1:3 for 90s
METH:IPA 2:1 for 20s
IPA for 60s
N 2 and check in microscope
4. Plasmaquest
CF4AH.rcp (213 W/ 24 W/ 313 V - chiller at 15 0 C - Substrate at 21 0C)
Etch for 2 minutes/ Cool down for 3 minutes
Repeat 7x more etching for 2 minutes/ Cool down for 3 minutes
Take out and inspect sample for shiny exposed metal
A.2.3
Passivation Etching - Global
1. Solvent Clean
Acetone/IPA/N2 with ultrasonics in teflon beakers (PWR = 5-6)
2. Asher-TRL
800W for 30 minutes
3. Plasmaquest
CF4_AH.rcp (213 W/ 24 W/ 313 V - chiller at 15'C - Substrate at 21'C)
Repeat 1-2x etching for 2 minutes/ Cool down for 3 minutes
Take out and inspect sample
SEM/AFM plug structures to ensure that all of the top passivation has been
removed and to measure the step height from the top of the passivation to
the area in between metal structures
135
Gap Filling
A.2.4
This step is added to make sure continuous gate metal routings across the M6 tile
structures.
1. TRL Coater
MMA 8.5 EL 11.5 (750 rpm for 2s, 4000 rpm for 60s)
TRL Hotplate 2 - Bake at 175'C for 7 minutes
/
Cool down for 3 minutes
/
Cool down for 3 minutes
PMMA A8 (750 rpm for 2s, 4000 rpm for 60s)
TRL Hotplate 2 - Bake at 175'C for 7 minutes
2. Elionix 125 (L2-GapFill)
Beam Current = 30nA
Dwell Time = 0.08pis
Dose = 2400 pC/cm 2
3. Develop Bilayer Resist (slight agitation)
MIBK:IPA 1:3 for 90s
METH:IPA 2:1 for 20s
IPA for 60s
N 2 and check in microscope - make sure deep undercuts in the bilayer resist.
4. ebeamFP (may be replaced by Sputterer)
Deposit Ti - Thickness 10nm, Rate = 0.1 nm/s, Rotation OFF
Deposit Au - Thickness 390nm, Rate = 0.2 nm/s, Rotation OFF
5. Liftoff
Left in aceton overnight
Place sample in acetone (Teflon beaker) for 2 minutes, ultrasonic PWR 5
136
Place sample in acetone (quartz beaker) for a couple of seconds
Place sample in IPA (Teflon beaker) for 2 minutes, ultrasonic PWR 3
N 2 and check with optical microscope the metal structures
6. Asher-TRL
800W for 30 minutes
A.2.5
Gate Electrodes
1. TRL Coater
PMMA A8 (750 rpm for 2s, 4000 rpm for 60s)
TRL Hotplate 2 - Bake at 175'C for 7 minutes
2. Elionix 125 (L3-GATE)
Beam Current = 10/30nA (fine/coarse structures)
Dwell Time = Depending on dose
Dose = 2200-2400 pC/cm 2
3. Develop PMMA
MIBK:IPA 1:3 for 90s
IPA for 60s
N 2 and check in microscope
4. Asher-TRL
800W for 1 minutes
5. ebeamFP
Deposit Ti - Thickness 10nm, Rate = 0.1 nm/s, Rotation OFF
Deposit Pt - Thickness 20nm, Rate = 0.1 nm/s, Rotation OFF
137
6. Liftoff
Acetone/IPA/N2 and check under microscope
7. Asher-TRL
800W for 30 minutes
8. DC Probe Station
Test connection of Ti/Pt electrodes
A.2.6
Ohmic Plugs
1. TRL Coater
MMA 8.5 EL 11.5 (750 rpm for 2s, 4000 rpm for 60s)
TRL Hotplate 2 - Bake at 175'C for 7 minutes
/ Cool down
for 3 minutes
PMMA A8 (750 rpm for 2s, 4000 rpm for 60s)
TRL Hotplate 2 - Bake at 175 C for 7 minutes
/
Cool down for 3 minutes
2. Elionix 125 (L2-PLUG)
Beam Current = 30nA
Dwell Time = 0.08ps
Dose = 2400 pC/cm 2
3. Develop Bilayer Resist (slight agitation)
MIBK:IPA 1:3 for 90s
METH:IPA 2:1 for 20s
IPA for 60s
N 2 and check in microscope - make sure deep undercuts in the bilayer resist.
4. ebeamFP (may be replaced by Sputterer)
138
This step requires a wedge piece to hold tilted sample for side wall coverage.
Use the wedge sample holder to put NW corner of the chip 30 degrees up.
Deposit Ti - Thickness 5nm, Rate = 0.1 nm/s, Rotation ON
Deposit Au - Thickness 45nm, Rate = 0.2 nm/s, Rotation ON
Remount the sample putting SE corner of the chip 30 degrees up.
Deposit Ti - Thickness 5nm, Rate = 0.1 nm/s, Rotation ON
Deposit Au - Thickness 45nm, Rate = 0.2 nm/s, Rotation ON
5. Liftoff
Place sample in acetone (Teflon beaker) for 2 minutes, ultrasonic PWR 5
Place sample in acetone (quartz beaker) for a couple of seconds
Place sample in IPA (Teflon beaker) for 2 minutes, ultrasonic PWR 3
N 2 and check with optical microscope the metal structures
Check the ohmic interconnects in DC probe station on test dummy structures
to make sure the ohmic connection is achieved.
6. Asher-TRL
800W for 30 minutes
A.2.7
Gate Dielectric
1. TRL STS-CVD
HFSiOLT Recipe for 1 minute
Target thickness = 75 nm
Deposition temperature = 250 C
Deposition rate = 73.85 (nm/min) - calibration required.
139
A.2.8
Gate Vias
1. TRL Coater
MMA 8.5 EL 11.5 (750 rpm for 2s, 4000 rpm for 60s)
TRL Hotplate 2 - Bake at 175 C for 7 minutes
/
Cool down for 3 minutes
/
Cool down for 3 minutes
PMMA A8 (750 rpm for 2s, 4000 rpm for 60s)
TRL Hotplate 2 - Bake at 175'C for 7 minutes
2. Elionix 125 (L2-PLUG)
Beam Current = 30nA
Dwell Time = 0.08[s
Dose = 2400 pC/cm 2
3. Develop Bilayer Resist (slight agitation)
MIBK:IPA 1:3 for 90s
METH:IPA 2:1 for 20s
IPA for 60s
N 2 and check in microscope - make sure deep undercuts in the bilayer resist.
4. Asher-TRL
800W for 1 minutes
5. Plasmaquest
CF4_AH.rcp (213 W/ 24 W/ 313 V - chiller at 15'C - Substrate at 21 'C)
Etch for 2 minutes/ Cool down for 3 minutes
6. Solvent Clean
Acetone/IPA/N2 with ultrasonics in teflon beakers (PWR = 5-6)
140
7. Asher-TRL
800W for 60 minutes
8. Metrology
Inspect using AFM and SEM that the ohmic vias are exposed.
A.2.9
Graphene Transfer
1. Graphene transfer is conducted by Marek Hempel and Yong Cheol Shin.
2. Check graphene quality on copper by SEM before transfer on to the rough
substrate.
3. Check with optical microsopy and SEM to ensure continuous graphene.
4. Make sure thermal reflow step is done and no spin drying.
5. If graphene transfer is bad, use NSL plasmatherm (90s of testp3.prc) to remove
graphene and clean surface before the retransfer
6. Ensure that the PMMA is thin enough to conform to the entire surface
7. Image in SEM at 2.5 keV for graphene contrast using the in-lens detector.
A.2.10
Graphene Ohmic Contacts
1. TRL Coater
PMMA A8 (750 rpm for 2s, 4000 rpm for 60s)
TRL Hotplate 2 - Bake at 175*C for 7 minutes
2. Elionix 125 (L4-OHMIC)
Beam Current = 25nA
Dwell Time = 0.08 pus
141
Dose = 2000 pC/cm 2
3. Develop PMMA
MIBK:IPA 1:3 for 90s
IPA for 60s
N 2 and check in microscope
4. ebeamFP
Deposit Ti - Thickness 1nm, Rate = 0.1 nm/s, Rotation OFF
Deposit Au - Thickness 30nm, Rate = 0.2 nm/s, Rotation OFF
5. Liftoff
Left in aceton overnight. Do not let the sample flip over or scratch the surface.
Acetone/IPA/N2 and check under microscope. No sonication.
A.2.11
Graphene Mesa
1. TRL Coater
PMMA A8 (750 rpm for 2s, 4000 rpm for 60s)
TRL Hotplate 2 - Bake at 175'C for 7 minutes
2. Elionix 125 (L4-OHMIC)
Beam Current = 25nA
Dwell Time = 0.08 ps
Dose
=
2000 pC/cmn
2
3. Develop PMMA
MIBK:IPA 1:3 for 90s
IPA for 60s
142
N 2 and check in microscope
4. NSL-Plasmatherm
testp3.prc for 75 seconds (48 V
/
128 W)
5. Asher-TRL
800W for 5 minutes
6. Solvent Clean
Acetone/IPA/N 2 and check under microscope. Left in acetone for a couple of
hours.
7. Chip Ready for packaging
A.2.12
Chip Packaging
1. Chip Package and Socket Selection
88-pin QFN package (Quik-Pak)
Compatible open top socket for top-side illumination
2. Wirebonding
The work was done by a commercial vendor (VLSIP Technology, Inc.)
Wire-bonding map is provided in Appendix B.
A.3
MoS 2 Device Fabrication
The fabrication process is developed by Lili Yu and conducted in collaboration with
Sungjae Ha and Lili Yu.
1. Substrate Cleaning
Si0 2 /Si substrate
143
Nanostrip' and HCl
2. Gate Electrode
5nm Cr
/
30nm Au
/
30nm Pd by photolithography
3. Gate Dielectric
20nm Al 2 03 by atomic layer deposition (ALD)
Aneal for 30 minutes at 450 'C
4. Via Hole
C1 2 /BC1 3 RIE
5. Source/Drain Electrodes and Pads
5nm Ti
/
90nm Au by photolithography
6. MoS 2 Transfer
Start with CVD-grown sample
Coat with PMMA
Soak in KOH at 85 'C
Transfer to target substrate
7. Mesa Etch
02
plasma etching
8. Ohmic Contact
90nm Au by photolithography
9. Device Ready
Additional passivation step may follow.
1A stabilized
mixutre of sulfic acid (H 2 SO 4 ) and hydrogen peroxide (H 2 0 2 ).
144
Appendix B
Test Setup and PCB Design
The CMOS readout chips were packaged in a 88-pin, 0.5-mm pitch open-top QFN
package. The chips were placed into a socket, also open-top, on the test PCBs.
B.1
PCB Designs
Three PBCs were prepared for ADC and graphene thermocouple readout testing, and
the corresponding wirebonding maps are provided below.
145
B.1.1
ADC Test Board and Wirebonding Map
A test board is designed for ADC characteriation and off-chip detector readout. Since
this board is to measure original chip without the graphene structures, the package
top should be sealed to reduce interference.
..................................
DDH
SMA
PWvR
CL
R S LS
1- FM
CA
G7 1R-BR[--A V4 C
201 4/2"25
f\L'TJGJAE HA
Figure B-1: PCB for ADC characterization
146
67
88
56
\I~
1C
uh
UUu//Z/g/-
==
7=
=
-T-%7
III\\
45
22
44
23N
Figure B-2: Wirebonding Diagram for ADC characterization
147
B.1.2
Graphene Sensor Array Test Board and Wirebonding
Map
A test board is designed for readout of the full grid of graphene array.
..........................................................
......
fALLEN KBU:
IR-B U2
2114/12/26 sLJN9JAE HA:
u
borders for vacuum cap.
Figure B-3: PCB for Graphene Sensor Array Test
148
67
88
66
ipfe/}j/fejsf/
1 ,71
~ i n
\
\M 11111111MiT\
22\V//7/11101111111
4
23
Fiue
W
-:
iebnin
o GaheeSesr
iarm
149
rayTs
4
B.1.3
Unified Test Board and Wirebonding Map
A test board is designed to characterize ADC and to test graphene array readout
from the same chip. However, it cuts the output lines of four readout ADCs due
short number of the wirebonding pads.
0 '000000
(+
_I2"
-0
and 2.V" diameter
borders for vacuum cap.
I NI
WIWuuIssm
--------
Figure B-5: PCB for Unified Testing
150
67
88
~~~~~~~ L MRERM MEIE~fTFF1KF\6
~
1~~
66
11
;00
i~
,2V
f
25
f
i
FiueB6cieodn
Y
YR1 84
4
iga
151
o
nfe
etn
152
Appendix C
CAD Environment
C1
Model Implementations for MoS 2 Devices
C.1.1
//
Analytic Diode Model
Diode lum Model
'include
"disciplines .vams"
'include "constants .vams"
"DLlum_1.va"
'include
module DL1 (vp, vn);
inout vp,
vn;
electrical
11
vp,
vn;
real vd;
analog begin
vd = V(vp, vn);
if (vd > 0)
I(vp, vn) <+ bl*vd + b2*pow(vd,2)
pow (vd, 3) + b4*pow(vd,4);
153
+ b3*
16
else
if (vd < 0)
I(vp, vn) <+ ism*(pow(am,vd) -1);
else
I(vp,vn) <+
0;
end
endmodule
where the fitting is done in MATLAB as code below
1
%% Retreive Data and PolyFit
Id
-
IdDL4_-1; % Diode Measurement Data
DevNun =
xm
6
1;
= [ - 5: 0.1:0];
xp = [0:0.1:5];
yp = Id (51:101)
yp (1) =0;
ym = Id (1: 51);
11
yin (51)
0;
modelFun = @(b, x) b(2) .*
start-m = [2;
(exp(x./b(1))
-
1 );
le-8];
modelim = fitnim (xmn,yn, modelFun, startm);
16
=(b,
polyFun4
startp
=
x) b(4) .*x.^4+b(3) .*x.^3 + b(2) .*x.^2+b(1) .*x;
[le-9; le-6; le-8; -6e-8];
model-p = fitnlm (xp, yp, polyFun4, start _p) ;
154
Empirical FET Model
C.1.2
1
6
//
MoS2FET Empirical model
'include
disciplines .vams"
'include
constants .vams"
module MoS2FET-emp (D, S ,G)
electrical D, S, G;
inout D,
S;
input G;
11
parameter
real W= 60u;
parameter
real L
2u;
analog begin
real Vds
16
=
V(D, S);
real Vgs =V(G, S) ;
I(DS) <+ (W/L)/(60u/2u) * $table-model (Vds,
MoS2FET60um. d at", "3CC,1EL" );
end
endmodule
where raw data table is given by the "MoS2FET60um.dat" file.
155
Vgs,
C.1.3
Drift-Diffusion Compact FET Model
The implementation is done by Shaloo Rakheja.
//
VerilogA transport model for 2D FETs
'include
" constants vams"
'include "disciplines .vams"
5
module DD_2DFETv100(d, g, s);
inout d, g, s;
electrical d, g, s;
electrical
di,
si;
10
/7
Parameters in the MoS2 model
parameter integer type = 1 from [-1
//
1]
exclude
0;
type of transistor. nFET type=1; pFET type=-1
parameter real W = 40e-6 from (0: inf);
15
//
Transistor width [m]
parameter real Lgdr
77
2e-6 from (0: inf);
The designed gate length [m].
parameter real Cinv
= 4e-3 from
(0: in f);
Gate-to-channel areal capacitance at the virtual source
/
77
-
F/m^2]
20
parameter real nO
/7
-
1.5 from
[0: inf);
Subthreshold swing factor [unit-less] { typically between
1.0 and 2.0}
parameter real RsO = 500e-6 from (0: inf);
//
Access resistance on s-terminal [Ohms-meter]
parameter real RdO = 500e-6 from (0: inf) ;
25
//
Access resistance on d-terminal [Ohms-meter]
156
parameter real vsat = 0.2e5 from
77
(0:inf);
Saturation velocity [m/s]
parameter real mu = 20e-4 from (0: inf) ;
30
//
mobility [cm^2/V.s]
Low-field
parameter real beta = 1.7 from
//
Saturation factor. Typ.
nFET=1.8, pFET=1.6
parameter real Tjun = 298 from
77
(0: inf) ;
[173:inf);
Junction temperature [K]
35
parameter real VtO =
77
0.486;
Strong inversion threshold voltage [V]
parameter real alpha = 3.5;
7/
Empirical parameter for threshold voltage shift between
strong and weak inversion.
40
'define
SMALLVALUE
(le-10)
'define
LARGE-VALUE
(40)
real Vds , Vgs, Vgsraw, Vgd, Vgdraw, Vdsi, Vgsi , Vgdi,
dir;
voltages and direction
45
real Rs, Rd;
//
resistances
real phit , nphit , aphit , eVgO,
FF0,
etas
,
etad;
//
for
calculating charges
real Qref, Qis, Qid, Vdsat,
Fsat, Fvsat, Id; //
current
analog begin
50
/Voltage
definitions
157
charges and
Vgsraw = type
*
(
V(g)
- V(si)
Vgdraw = type
*
(
V(g)
- V(di)
(Vgsraw >=
if
* ( V(d) - V(s)
Vds
type
Vgs
type * ( V(g) - V(s)
Vdsi
type * ( V(di) - V(si
)
55
begin
Vgdraw)
Vgsi
=
dir
1;
end
b egin
Vgs
type
V(s) - V(d)
);
V(g) - V(d)
);
V(si
(
type
*
Vds
*
else
*
60
Vgsraw;
65
Vdsi
=
type
Vgsi
=
Vgdraw;
dir
=
) - V(di) );
-1;
end
/Parasitic element definition
70
Rs
RsO/W;
Rd =Rs;
77
7
s-terminal resistance [ohms]
d-terminal resistance [ohms]
/For symmetric source and drain Rd
75
phit
nphit
$vt (Tjun);
=
77
Rs.
Thermal voltage , kT/q [V]
nO * phit;
Product of n and phit [used as one variable]
/
aphit = alpha * phit ;
Product of alpha and phit [used as one variable]
80
eVgO
= exp(( Vgsi -
(VtO-0.5*aphit))/
158
( aphit ));
//
Compute eVg factor from uncorrected intrinsic Vgs
= 1.0/
FF0
Qref
Cinv *
2.0 * nphit;
Vdsat = vsat*Lgdr//mu;
Fsat
Vdsi/Vdsat /(pow((1+pow(Vds/Vdsat
etas
(Vgsi-(VtO -0.5*aphit *FFO)) /(2.0* nphit)
etad
90
1.0 + eVgO );
if
=
, beta)) ,I.0/ beta));
(Vgsi -(Vdsat*Fsat+Vt0 -0.5* aphit *FFO)) /(2.0* nphit);
<= 'LARGE-VALUE)
(etas
Qis = Qref * ln(
begin
1.0 + exp(etas)
)
85
(
end
else begin
Qis
95
= Qref * etas;
end
if (etad <= 'LARGE-VALUE)
Qid = Qref
/7
*
begin
ln( 1.0 + exp(etad)
);
Compute charge w/ uncorrected intrinsic Vgs for use
later on in charge partitioning
100
end
else
begin
Qid = Qref
*
etad;
end
105
Fvsat = (Qis-Qid) /(Cinv*Vdsat) /(pow((1+pow (( Qis-Qid) /(Cinv*
Vdsat) ,beta)) ,1/beta))
/Total
drain current
Id = W*vsat*(Qis+Qid)/2.0*Fvsat;
159
110
//Sub- c i r c u it
initialization
I(di, si)
<+
type
I(ddi)
<+
( V(d) - V(di)
I(si ,s)
<+
( V(si) - V(s) )/ Rs;
* dir * Id
)/ Rd;
end
115
endmodule
C.2
Technology Library for MoS 2 Device Layout
(
layerDefinitions
(
techLayers
(
Abbreviation
Layer#
( default
0
default
(
Mesa
1
MES
( Gate
2
G
(
3
Cont
( Pads
4
PAD
( Vial
5
VI
(AUX1
6
AXI
( ATY9
7
A Y9
Contact
)
5
LayerName
10
)
)I
;techLayers
PurposeName
( layout
)
Purpose#
1
Abbreviation
lyo
; techPurposes
20
;( LayerName
Purpose
160
)
techLayerPurposePriorities(
)
(
15
)
(
techPurposes
25
)
( default
( Mesa
drawing
( Gate
drawing
(
drawing
drawing
Contact
( Pads
drawing
( Vial
drawing
(AUXi
drawing
(AUX2
drawing
; techLayerPurposePriorities
30
(
techDisplays
LayerName
Vis
35
40
Sel
Purpose
Con2ChgLy
Packet
DrgEnbl
(
Mesa
drawing
pinkSlashl
t t t t t)
(
(
Gate
drawing
limebackSlash
t t t t t)
Contact
drawing
bluebackSlash
t t t t t)
( Pads
drawing
grayDot3
t t t t t)
(
(
(
Vial
drawing
redbackSlash
t t t t t)
AUX1
drawing
brownSlashl
t t t t t)
AUX2
drawing
yellowSlashl
t t t t t)
) ; techDisplays
)
Valid
)
(
; layerDefinitions
161
162
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