ANALYSIS OF A DUAL MODE
FORWARD/FLYBACK CONVERTER
by
Thomas Raymond Zaloum
SUBMITTED IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE
DEGREES OF
BACHELOR OF SCIENCE
and
MASTER OF SCIENCE
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
June, 1982
Thomas Raymond Zaloum, 1982
The author hereby grants to MIT permission to reproduce and to
distribute copies of this thesis document in whole or in part.
Signature redacted
Signature of Auth r
Signature
Certified by
//
TApartment of Electrical Engineering and
redactedomputer Science, May 14, 1982
-7
Signature redacted
<Si gnature redacted
Accepted by
John G. Kassakian
Thesis Supervisor
John N. Park
rY.
Supervisor
.7L-uprio
Arthur C. Smith
Chairman, Departmental Committee on Graduate Students
Archives
.ir:/22
i
c~rit~g~S
ANALYSIS OF A DUAL MODE
FORWARD/FLYBACK CONVERTER
by
Thomas Raymond Zaloum
Submitted to the Department of Electrical Engineering
and Computer Science on May 14, 1982 in partial
fulfillment of the requirements for the Degrees of
Master of Science in Electric Engineering and
Bachelor of Science in Electrical Engineering
ABSTRACT
A single transistor dc-dc converter that combines both forward and flyback action is
presented. The resulting circuit is ohmically isolated and can operate over a wide range of.
input-to-output voltage ratios. An analysis of the circuit indicates that the forward and
flyback portions of the circuit interact to produce three distinct regions of operation. With
the design information presented, the circuit can be tailored to utilize the desirable characteristics of either converter action for a specific application. The dynamics of the dual.
mode circuit are modeled by means of the state-space averaging technique.
Also
described is the testing of an ac-dc regulator that takes advantage of the wide operating
range of the dual mode converter to operate off the ac line with only a small input filter.
Thesis Supervisor:
Title:
Dr. John G. Kassakian
Associate Professor of Electrical Engineering
ii
ACKNOWLEDGMENT
The author would like to thank the General Electric Company, Corporate Research
and Development, for providing the opportunity to undertake this thesis. In particular, I
thank Dr. James W.A. Wilson, manager of the Power Circuits and Systems Branch, for
his encouragement and support. Great thanks go to Dr. John N. Park for his guidance on
this project throughout my stay at GE.
I also appreciate the assistance of Professor John Kassakian of MIT in completing the
final thesis.
iii
TABLE OF CONTENTS
Chapter
Page
1
INTRODUCTION ...................................................
1
2
PRIOR TECHNOLOGY ..............................................
4
3
CIRCUIT OPERATION ..............................................
3.1 O verview ........................................................
3.2 Basic Relations ...........................................
3.3 R egion 1.........................................................
3.4 R egion 2 .........................................................
3.5 R egion 3.........................................................
3.6 Normalized V-I Characteristics .....................................
3.7 Device Ratings ...................................................
3.8 Effects of Non-Ideal Elements ......................................
3.9 Summ ary ........................................................
10
10
11
15
17
20
22
26
30
32
4
SMALL SIGNAL ANALYSIS .........................................
4.1 Overview ........................................................
4.2 Region 1: State-Space Analysis .....................................
4.3 Region2: State-Space Analysis .....................................
4.4 Region 3: State-Space Analysis .....................................
4.5 Summ ary ........................................................
33
33
33
42
49
50
5
EXPERIMENTAL WORK ............................................
5.1 Description of the Breadboard......................................
5.2 Presentation of Steady-State Results .................................
5.3 Sum mary ........................................................
53
53
63
69
6
CLOSED-LOOP TESTING ...........................................
6.1 Overview ........................................................
6.2 Basic Tests.......................................................
6.3 Line Operation ...................................................
76
76
76
84
7
CONCLUSIONS.....................................................
91
REFERENCES ......................................................
94
iv
GLOSSARY OF TERMS
D
fraction of switching period that transistor conducts
D'
fraction of switching period transistor is off
decay interval of flyback current in Region 1
82
decay interval of forward current in Region 2
fs
switching frequency
iL
forward contribution to output current
i'L
flyback contribution to output current
in
magnetizing inductance current
io
output current
LM
magnetizing inductance
Ls
forward smoothing inductor
N,
forward winding turns ratio
N2
flyback winding turns ratio
RL
load resistance
T
switching period
Vs
source voltage
VSE
effective source voltage
VO
output voltage
Example of Nomenclature
iL = iL (t)
instantaneous current (total variable)
IL
average current (dc component)
iLmax
maximum of iL during T
iL min
minimum of iL during T
ILN
normalized average current
1
small signal perturbation
L
v
LIST OF FIGURES
Figure
Page
1
Typical ac-dc converter .................................................................................
3
2
Linear and switched mode converters ...............................
3
3
Essence of dc-dc regulator.......................................
3
4
Non-isolated single transistor switching topologies .................................
5
5
Isolated single transistor switching topologies ............................................
7
6
Transformer clamp reset method...................................
7
7
Forward/flyback converter.......................................
9
8
Equivalent circuit for forward/flyback converter .....................................
12
9
Definition of the duty cycle .....................................
12
10
Continuous and discontinuous mode inductor currents .............................
12
11
D versus V---V-- -- -- ---.............
-....
....... ...... ..........................................
14
12
Current waveforms for regions of operation ..............................................
14
13
Flyback current in Region 1 ......................................................................
18
14
Forward current in Region 1 .....................................................................
15
Instantaneous output current in Region 1 ......---------...........................
18
16
Forward current Region 2.............................................................
21
17
Flyback current Region 2 .............................................
21
18
Output current Region 2 -------...
21
vi
------------------------.......................................
.
18
LIST OF FIGURES (Cont'd)
Page
Figure
19
O utput current : Region 3 ..........................................................................
21
20
V-I characteristic for forward circuit ...........................................................
25
21
V-I characteristic for flyback circuit ..........................................................
25
22
D efinitions of device stresses .......................................................................
28
23
Comparison of unfiltered output currents ...................................................
29
24
Circuit model with some parasitic elements ................................................
31
25
Switching states: Region 1 ..........................................................................
35
26
Root locus: Region 1 .........................................................
39
27
C anonical circuit m odel .................................................................................
41
28
Circuit model for dual mode converter : Region 1 .....................................
41
29
Switching states : Region 2 ...........................................................................
44
30
R oot locus : R egion 2 ..................................................................................
48
31
Transition at Region 1 - Region 2 boundary ...............................................
51
32
Incremental block diagram of regulator .......................................................
52
33
Output capacitor current at rated load ..........................................................
59
34
Cross section of "EC" core for inductor construction ...............................
62
35
Model of transformer including leakage inductance ...................................
62
vii
.............
LIST OF FIGURES (Cont'd)
Figure
Page
36
Snubber configuration ...................................................................................
62
37
Power circuit components ..........................................................-----
64
38
D ual m ode converter breadboard .................................................................
39
SG 1525 block diagram ..................................................................................
40
O pen-loop drive circuit ...............................................................................
41
Forward and flyback currents : rated load ....................................................
70
42
Output current and voltage : rated load ................................................
70
43
Transistor turn-off waveform s .....................................................................
71
44
Prim ary current .............................................................................................
71
45
Forward and flyback current : Vo = 2.5 volts ............................................
72
46
Transistor voltage and current : Vo = 2.5 volts .........................................
72
47
Forward, flyback currents, transistor voltage boundary case ......................
73
48
Output current and voltage : Region 2 ........................................................
73
49
Forward and flyback currents : Region 2 .....................................................
74
50
Forward and flyback currents : Region 3 .....................................................
74
51
Experimental D versus Vo/ Vs plot ..............................................................
75
52
SG1525 error amplifier ................................................................
78
viii
66
..
66
LIST OF FIGURES (Cont'd)
Page
Figure
53
Uncom pensated SG1525 transfer plot ..........................................................
78
54
Uncompensated loop - transmission : Region 1 .........................................
79
55
Representative uncompensated loop transmission : Region 2 ............
80
56
C om pensation param eters .............................................................................
81
57
Response to reference step : Region 1 (slow compensation) ..................
83
58
Response to reference step : Region 1 (fast compensation) .......................
83
59
Response to Vs step : Region 1 (slow compensation) ................................
85
60
Response to Vs step : Region 2 (slow compensation) ................................
85
61
Response to Vs step : Region 1 (fast compensation) ................................
86
62
A C line connection ........................................................................................
87
63
Illustration of input im pedance ....................................................................
. 87
64
Source and output voltages : C, = 60.F , Vref = 1.75V .......................
89
65
Source and output voltages : C, = 60pF , Vref = 5.0V .............................
89
66
Source and output voltages : C, = 20tF , Vref = 3.OV .............................
90
67
Modulation of duty cycle (high ripple source) ...........................................
90
ix
LIST OF TABLES
Page
Table
9
1
Comparison of various switching converter topologies .....................
2
Comparison of peak device stresses......................................
27
3
Idealized circuit component values ......................................
55
4
N om inal turns ratios ..................................................
56
5
Peak stresses for Region 1 operation.....................................
57
x
Chapter 1
INTRODUCTION
There are many applications for regulated dc sources. These range from low voltage
supplies for logic circuits to high voltage supplies for cathode ray tubes. Since most commercially distributed power is ac, such sources are ultimately ac-dc converters. A change
in the voltage level may be accomplished before any rectification by a transformer, or
after, in a dc-dc stage.
A commonly used configuration employs a dc-dc regulator which automatically compensates for possible variations in the source voltage. Typically, three stages are involved:
an input filter, the regulator, and an output filter (Figure 1). The input filter rectifies the
ac line and generally provides a low ripple source to the regulator. The regulator converts
that source to the required dc level, acting as a dc-dc transformer. The output filter attenuates any harmonics that may be generated by the action of the regulator.
The regulator can either be of the linear type or one designed to operate in a switched
mode (Figure 2). In each case, the variable element represented by S can be achieved
with a transistor. Either circuit becomes a regulator when the output voltage is fed back
and compared to a reference, the difference determining the drive signal D (Figure 3).
A major problem with the linear regulator is that its efficiency is no better than the
output/input voltage ratio. Improving this efficiency becomes especially difficult when either voltage is required to vary significantly. Also, the linear regulator can only convert to
a lower voltage level, which is not a constraint for the general switching converter.
Switching regulators use time-averaging to effect the dc-dc transformation. With the proper inductive energy storage, step-down, step-up, or both are possible.
Since switched
mode supplies do not inherently waste energy (although there are inevitable losses), they
1
are preferable when efficiency is a concern.
This efficiency comes at the cost of greater
filtering requirements, as compared to a linear supply.
The scope of this thesis is confined to the switched mode circuits. The work began
with a proposed, but undeveloped, new topology.
In the next chapter, the potential
benefits of this circuit over previous ones are indicated. Following that, a detailed analysis
quantifies the improvement.
A breadboard of the circuit was constructed and evaluated
and the results are presented.
2
ac
REGULATOR
FIT
Figure 1.
Vo (dc)
VFLTER
Typical ac-dc converter
S
S
D
4
+
D
VS
RL
RL
Vr
Vo
LINEAR
Figure 2.
SWITCHED
Linear and switched mode converters
V-
-- Vo
CONVERTER
F EEDBACK
LCONTROL
(FEED FORWARD, IF USED)
VREF
Figure 3.
Essence of dc-dc regulator
3
V0
Chapter 2
PRIOR TECHNOLOGY
The intended application of a power supply generally determines what parameters
(size, cost, weight, reliability, etc) are most carefully controlled in its design. These dominant parameters, along with the electrical specifications, will determine the approach taken. In regulated supplies where high efficiency is desired, the dc-dc switching converter is
well suited. Within this category, the designer still has several choices. Each of the various types of high frequency dc-dc converters has its own distinct advantages and disadvantages for each application. Often, a compromise is necessary because no single converter topology incorporates all the desired characteristics.
The standard single transistor switching topologies are the buck (forward), the boost,
and the buck/boost (flyback) circuits (Figure 4).1 As the name implies, the transistor in
each of these circuits operates as a switch, ideally being either fully on or fully off. The
duty cycle D represents the percentage of time the switch is closed. This controls the ratio of charging time to discharging time for the inductor. Since the average voltage on the
inductor must be zero in the steady state, the ratio Vol Vs is thus constrained by D. Notice that in the buck and boost converters, there is a period when energy flows directly
from the source to the load, while in the flyback circuit the charging interval and the
discharging interval do not overlap.
If ohmic isolation and step-down capability are required, which is true of the majority
of line operated dc supplies, the choice narrows to the isolated forward or flyback circuits
(Figure 5). Note that the isolated flyback converter (Figure 5b) requires only one magnetic component since the transformer's magnetizing inductance serves as the energy
storage element. The forward converter (Figure 5a) uses a separate transformer.
4
D
VS
Vo
(a) FORWARD (BUCK) CONVERTER
VS
,,Vo
D
(b) BOOST CONVERTER
D
Vs
T
+
V0
(c) FLYBACK (BUCK/BOOST) CONVERTER
Figure 4.
Non-isolated single transistor switching topologies
5
The pulsed dc voltage applied to the primaries of these transformers has a non-zero
average value. Precautions must be taken to ensure that the flux level is reset by the end
of each switching period to prevent saturation of the core material. In the flyback circuit,
this is inherently accomplished as the magnetizing energy is transferred to the load during
the transistor's off period. The forward circuit, on the other hand, requires a separate energy recovery network. In Figure 5a, this is shown as a third winding which returns energy to the source through a diode, during the "off" interval.
This is the traditional
method and can be implemented with N 2 = 1 or with the ratio optimized to some design
goal (such as reducing device stresses).
The transformer clamp (Figure 6) resets the transformer with a constant voltage,,independent of source voltage. 2 This can reduce the peak stress on the transistor, particularly when the input voltage is subject to large variation. However, unless there is some
use for the auxiliary supply created, the efficiency of this connection is jeopardized. Ideally, this energy should be transferred to the load, which is desirable for both efficiency and
device utilization.
The previous discussion of the transformer saturation problem makes the flyback converter look especially desirable for isolated supplies.
However, other factors force
compromises in circuit selection. Table 1 summarizes characteristics of the various topologies. Note that if the turns ratio of the transformer does not equal unity in the isolated
circuits, the input-output voltage relations must be suitably scaled.
The flyback converter, which is capable of either buck (VO < Vs) or boost (Vo > Vs)
operation, can tolerate a wide range of source voltages for a given output. This reduces
the requirements for the input filter (stage 1 of Figure 1), providing the feedback circuit is
fast enough to follow and suppress the effect of the input ripple on the output voltage.
This advantage of the flyback circuit comes at the expense of increased device stress, as
6
+
+
D
Vs
V0
1:N 2:N 1
a) ISOLATED FORWARD CONVERTER WITH RESET WINDING
Vs
DI
D
FI
1:N
--
b) ISOLATED FLYBACK CONVERTER
Figure 5.
Isolated single transistor switching topologies
Vs
TRANSFORMER CLAMP RESET METHOD
Figure 6.
Transformer clamp reset method
7
Vo
It can be readily seen, however, that while
will be detailed in the following chapter.
energy can flow directly from the source to the load when the switch (transistor) is closed
in the forward converter, in the flyback circuit all energy must first be stored in the inductor for transfer during the "off" interval.
This causes the peak device stresses to be
higher in the flyback circuit.
A circuit that combines direct energy transfer with a wide operating range would have
advantages over a forward or flyback converter alone. Such a circuit is possible.
If
Figures 5a and 5b are compared, it can be seen that the reset network of the isolated forward converter is identical to a flyback connection, except for where the stored energy is
delivered. Additionally, note that the transformer clamp network (Figure 6) is a flyback
connection to an auxiliary load, regulated by the zener diode. However, there is a constant
potential available elsewhere in the circuit: the regulated output. Continuing this path to
its conclusion leads to the dual mode forward/flyback converter (Figure 7).
The dual mode circuit can be viewed as two converters operating in parallel, from the
same source and into the same load. The flyback circuit serves as the reset mechanism of
the isolated forward converter. Since both modes supply load current and are forced to
have the same duty cycle (D), they are not independent. This interaction makes a completely new analysis of the circuit necessary. Fortunately, the standard switching converter analysis techniques can be readily applied. 3 '4 The next two chapters detail the steady
state and ac small signal operation of the dual mode converter.
8
Table I
COMPARISON OF VARIOUS SWITCHING
CONVERTER TOPOLOGIES
Reset Problem
Circuit
t
VO
I
Input Current
Output Current
I
If Isolated
Forward
0 < V 0 < Vs
Discontinuous
Continuous
Flyback
Unrestricted
Discontinuous
Discontinuous
No
Boost
VO > VS
Continuous
Discontinuous
Yes
Yes
N2
0
Vs
N1
Figure 7.
Forward/flyback converter
9
V0
Chapter 3
CIRCUIT OPERATION
3.1 Overview
The steady state operating conditions of the dual mode converter are detailed in the
following pages.
The basic constraining relations are derived by assuming continuous
periodic currents in the two inductors. These relations indicate the existence of three distinct regions of operation, each of which are presented in detail.
To provide a graphic display of how each mode responds to variation in the load
current, output voltage versus output current characteristics are presented. These quantities are normalized to the component values and operating conditions so that dimensionless axes can be used. Finally, a table of device ratings for the dual mode, forward, and
flyback converters is presented. The benefits of the new circuit, as compared to the single
mode topologies, are indicated.
To avoid confusion, a consistent language for referring to various aspects of the circuit
has been adopted. When making a distinction between the flyback and forward portions
of the circuit, the words "circuit" or "converter" are used, e.g., forward circuit or forward converter. The word "mode" is used to denote the distinction between continuous
and discontinuous inductor currents. The operating point is defined to be within certain
"regions of operation." Either or both the forward or flyback converters may be in continuous or discontinuous conduction mode, depending on the region of operation. Both
continuous and discontinuous inductor currents may exist at a given operating point,
hence the name "dual mode."
10
3.2 Basic Relations
An equivalent circuit for the dual mode forward/flyback converter represents the
transformer by a set of ideal turns ratios and a magnetizing inductance (Figure 8). A real
transformer also has loss elements and leakage inductance. While these may have observable effect on an actual circuit, they do not alter the basic operation and would introduce
unnecessary complication at this point. To derive the basic operating regions, it will be assumed that there are no losses; i.e., ideal diodes and R, = 0. The results of this assumption are assessed after the basic analysis.
The circuit is considered in steady state when the various voltages and currents are
periodic at the switching frequency (Figure 9): i(T) = i(0). This periodicity condition at
the two inductors requires zero net volt-secs per switching cycle. Assuming continuous
inductor current:
T
f
vL (tdt = 0 or VL,,,D
-
VLOf (0-D)
where VL is the voltage across the inductor. Applying this to the magnetizing inductance:
VsD
=
VO D -
N2
yielding
DN2
( a)
-DVs
(a
V0
VO(b)
VO + N 2 Vs
Similarly, at the forward smoothing inductor Ls:
(N 1 Vs -
VO) D =- (1-D) VO
yielding
VO - DN1 Vs
(2a)
D -
(2b)
0
NVs
11
These are the standard relations for flyback and forward converters, respectively, operating separately in the continuous conduction mode (Figure 10).
However, the con-
straints on the two converters are simultaneously in effect, since they have the same
Vs, V0 , and D.
LL
1:N2:N1
Ls
- - RC
IL
---
m
I
VsLm
it)
+
D
LRL
DRIVE
Vo
co-_
J
SIGNAL|
Figure 8.
Equivalent circuit for forward/flyback converter
DRIVE
SIGNALSWITCHING
FREQUENCY = fs=
T
CYCLE = D =-.
SlDUTY
T
0
DT
Figure 9.
D' = 1-D =of
T
10 t
T
Definition of the duty cycle
L
-
L
DT
T
t
DT
a) CONTINUOUS MODE
Figure 10.
(D + d)T T
b) DISCONTINUOUS MODE
Continuous and discontinuous mode inductor currents
12
The plots of D vs. Vo/ Vs for Equations lb and 2b, as shown in Figure 11, have one
point of intersection (other than D = 0).
This is the only voltage ratio, for a given
transformer, for which both inductor currents can be continuous and periodic. For each
converter, operation below its constraint line (smaller D) corresponds to discontinuous
conduction.
Operation above the constraint line corresponds to increasing average
current, and thus is not a steady state condition. For this reason, the operating point
must be on or below the lower of the two curves, as indicated by the dotted path on Figure 11. The expected current waveforms for the three regions defined in Figure 11 are
shown in Figure 12.
The switching action of the power circuit determines the ripple of the inductor current,
but not necessarily its dc component. It is the load impedance that determines the average value of the current in the continuous conduction mode. Only in discontinuous conduction is the amplitude of the inductor current determined by the switching circuit. That
is, in a normal single mode circuit, the duty cycle is dependent only on Vo in continuous
conduction, but on both Vo and Io when the inductor current becomes discontinuous.
The load condition for the dual mode converter is:
10- -- = IL + 'L
RL
(3)
The average flyback current and the average forward current sum to the output current
(though not instantaneously). An interesting aspect of the dual mode circuit is that the
duty cycle is determined by the continuous mode, and thus is independent of Io, despite
the existence of the discontinuous mode. This is true providing that the load is sufficient
(I great enough) to sustain continuous conduction. Since the continuous mode determines the duty cycle, it will be considered the dominant mode. Thus, in Region 1 the
forward converter dominates, while in Regions 2 and 3, the flyback converter is dominant. It should be noted that Figure 11 shows the case N1 > N 2. If N 1 < N 2 , the
13
D
A4
1
(1) FLYBACK CONSTRAINT
(2) FORWARD CONSTRAINT
(2)
(1)
.5
,1
10
I
I
l-
_
Vo/Vs
N1
N2
2
)
(N -N
0
Figure 11.
D versus V0/Vs
A.
iL
im
/
Region 1
t
iL
Region 2
0
t
t
4
___
__
__ __ ___ __ __ __ __
t.
1
Region 3
t
Figure 12.
Current waveforms for regions of operation
14
flyback converter would always be dominant. The contribution of the forward converter
would be small and the benefit of its continuous output current significantly reduced.
At a given operating point, the circuit's behavior follows this sequence:
1.
Vo/ Vs determines the region of operation and the dominant converter
2.
The dominant converter determines D.
3.
D determines the contribution of the discontinuous mode to the output current.
4.
The remaining output current (defined by Equation 3) determines the contribution
of the continuous mode current.
Following this sequence, quantitative relations among the circuit and load parameters
can be determined for each region.
3.3 Region 1
In this region the forward converter operates in continuous conduction mode and
determines the duty cycle D by Equation 2b. The forward current is fixed by:
IL = 10 - IL
Thus the flyback current must first be evaluated. Referring to Figure 13:
VsDT
LM
""Lm
Since the waveform is triangular, the average IM over the conduction period (D + 8 1) is:
iMmax -
_____
IM -
2
VsDT
=maVD
2
LM
(5)
Instantaneously, during the "off" period
l'L (t) -
(6)
N2
and the conduction interval of i4 is 81, thus the average flyback contribution to I is
VsDT
2- Lm
15
8
1
N2
The decay interval 81 can be determined from the zero net volt-secs constraint that must
still hold at L11 :
V0
VsD = 81
(8)
N2
which, with substitution for D from (2b), yields:
N2
81
NI
=
--
(9)
which is a constant for a given circuit. Using (2b) and (9) in (7) yields
I L =,
VsDT
2NILM
V0 T
T
2NLM
(10)
which shows that for a given VO and fs the total flyback contribution is constant. This
would be expected, since the energy stored in the magnetizing inductance during to,, is
proportional to (VsD), which is held constant by the forward condition (2a).
Finally, from (3) and (10) the total forward contribution can be fixed.
Vo
IL - RL
V
2N2LM
(11)
As Vs changes (with the operating point remaining in Region 1) D must vary to hold VO
constant, but the two average currents IL and Ii remain constant. There are limitations
on this, which are determined by considering the instantaneous currents iL t) and I (t).
The flyback current iL (t) has been shown to be triangular in shape. The forward
current iL ()
will have the form shown in Figure 14. The difference between the ex-
tremum, from Ai =
j
v L (t) dt is:
L0
AL==
(N 1 Vs - VO) DT
Ls
TVOD'
Ls
(12)
Thus the maximum and minimum values of iL (t) are respectively:
iLmax = IL +
16
TV 0 D'
2 Ls
2S
(13a)
'Lni
=
IL
-
(13b)
TVD
ULs
To maintain continuous conduction, the average current must be great enough to
maintain 'L
>
0.
This is the same condition that any forward converter faces, the
difference here is that IL is reduced by the flyback current (eq. 11), which increases the
minimum load. The load condition is:
10 > TV+
2
N'LM
Ls
(13c)
The instantaneous output current is shown in Figure 15.
10 ma
i0 .
Lmax
==
+
iL mi
'ILmax
LI
014a)
b
As D is increased, the operating point approaches Region 2. Equation 9 indicated that
the decay period for the flyback current, 81, was constant. Clearly, 81 T must be less than
the tiff period (1-D)T. Evaluation of this boundary shows that it is in fact the same condition that leads to the intersection point at Vo/ Vs - N 1- N 2 in Figure 11. According to
the model pursued thus far, both the flyback and forward converters are in continuous
conduction at this point. Since neither current's magnitude is directly constrained, the
distribution of the load current between the two is undefined. As D is further increased,
moving the operating point into Region 2, the forward circuit drops into discontinuous
conduction and the current distribution is again constrained.
3.4 Region 2
The analysis for this region parallels that for Region 1. The flyback converter will
operate in the continuous mode and thus determine the duty cycle by Equation lb. The
flyback current is fixed by (Figure 8):
I = I0 -
17
IL
iM(t)A
M max
DT
(D+ d 1)T
ON PERIOD
DT
=
d 1T
=
DECAY PERIOD
D'T
=
OFF PERIOD
T
a) MAGNETIZING CURRENT
i'L( t)
I
DT
N.
(D+ 6 1)T
T
b) OUTPUT COMPONENT OF MAGNETIZING CURRENT
Figure 13.
Flyback current in Region 1
II
L
SAI
ImIaxI
"
t )A
IL
I
il-min
DT
Figure 1 4.
A iL
T
Forward current in Region 1
o max
i0 min
DT
Figure 15.
(D+
d1)T
T
Instantaneous output current in Region 1
18
First evaluate the forward current; refer to Figure 16 and from i
1
DTV
L dt:
L0
L~
Vo DT/Ls=8 2 VoT/Ls
=[N1Vs -
(15)
The average over the full period is
IL
=
(16)
+ 82)/2
+(D
iL
Equation 15 with (ib) can be solved for 82, yielding
82 -
N,
N 2 + VO/ VS
or
D + 8 21 = DN1 VS
I
(17)
VO
Note that unlike Region 1, the decay interval is dependent on Vol Vs.
It is a max-
imum at Vol Vs = N 1 - N 2, where 82 - N2/N1 - 1-D at the intersection point, and the
When Vo/ Vs - N1 , 82 - 0 and the forward
forward current just becomes continuous.
converter ceases contributing, because its effective source voltage is less than VO. Figure 11 displays these boundaries. From (15) and (17) it can be seen that for a given
.
VO, iL a is a maximum at Vo/ VS - N 1 - N 2 and diminishes to zero at Vo/ Vs - N 1
The maximum peak value
N2 V 0 T
Max iL
(18)
LN 1
=
From (ib) and (17):
(D + 8 2)
N
N1
(19)
N2 + VO/ VS
and (15), (16) and (17):
IL
VO T
2Ls
(N 1 - Vo/VS)N 1
Vo VO
(N 2 + V/ Vs) 2
Note that as (Vo/ VS) approaches (NI - N 2),
IL -
N2
N
(20)
VO T
0
N 1 2 2Ls
which is the condition
defined by (13b), proving that the magnitude of this current is continuous across the
boundary point. From (3) and (6): (Figure 17)
19
I
N2
_N
(22)
DVsT
(23)
=iL
ita
(21)
L,,v
1
Mmax =
N2IL
(1-D)
DVsT
2 LM
(24a)
N2IL
(1-D)
D2 VS T
(24b)
Mmin =
LM
,Ij
D Vs T
+ D T(25a)
(1-D)
2N 2 La
max =
,Li
____
in
II=
(1-D)
DVs T
2N2LM
The condition that continuous conduction is possible is immin > 0.
A stand-alone
flyback converter faces the same constraint, while in this case IM is reduced by the
reflected forward contribution, 1L (Equation 20).
This increases the minimum load
current for continuous conduction. The output current for Region 2 is shown in Figure 18.
3.5 Region 3
In this region, the dual mode circuit reduces to a simple flyback converter, because the
source voltage is too low for the forward converter to operate. The forward contribution
is zero, thus
The
iL W)
previously
L
derived
II - Io
relations for Region 2
(26)
hold
with
the
substitution
0.
I =
N 210
1-D)
The output current is shown in Figure 19 (which is also the flyback current
20
(27)
'L).
IitM
DT = ON PERIOD
6 2T = DECAY PERIOD
iL-max
(I-D)T = D'T = OFF PERIOD
;;;zDT
Figure 16.
max-
(D + 6 2)T T
*
L
t
Forward current: Region 2
max
Lmin
M
iM min--
_____________________
-.--.
DT
~
+
l'L
T
Figure 17.
DT
Flyback current: Region 2
ioA
O max
L max+L
7
max'
Lmax
Loo
DT (D + 6 2)T T
Figure 18.
iL(t) - io(t)
IL =
Output current: Region 2
L
10
DT
Figure 19.
T
Output current: Region 3
21
t
T
t
3.6 Normalized V-I Characteristics
While the D vs. Vo/ Vs sketch (Figure 11) is useful in determining the operating point
as a function of voltage, it does not convey the circuit's response to the load condition.
For this purpose, normalized V-I characteristics can be derived. The output current, on
the horizontal axis, is normalized to the quantity I
=
VSE
TIL.
Since two inductors
(Ls and Lm) which face different effective source voltages VSE equal to (N1 Vs and Vs,
respectively) are involved, the dual mode behavior is most easily shown with two separate
characteristics, one for the forward circuit and one for the flyback. The output voltage,
on the vertical axis, is normalized to NI Vs for both plots, so that a given operating point
corresponds to the same vertical position on both Figures 20 and 21. To avoid confusion,
these characteristics are for the specific value of N2/Ni - 0.7, which fixes the duty cycle
at the intersection point to D = 0.3. The individual characteristics are drawn as a function of the parameter D.
Each sketch has four major parts.
1)
an area corresponding to continuous conduction, where the current is not constrained
by the duty cycle,
2)
a boundary where the current is just barely continuous,
3)
an area where the current is discontinuous, to the left of the boundary, and
4)
a constraint line within the discontinuous area, imposed by the operation of the dominant (continuous conduction) converter.
1) The continuous conduction area is indicated by the horizontal lines on both the forward and flyback characteristics.
2) To derive the boundary (IN) line (dashed) for each converter
a) For theforward circuit, set Equation 13b to zero:
22
iL= = IL - TVOD'/2Ls = 0
Since the forward current is still continuous, Equation 2b applies, yielding
IL LS
Ni TVs
V (-VN)
2
where VN = Vo/Ni Vs. As Figure 19 shows, I*LN
=
(28)
0 at
Nv =
0 and VV
=
1.
b) For theflyback circuit, set Equation 25b to zero:
1
,IL
Lmin =
DVs T
(-D)
0
2N2LM
Since the flyback current (M) is still continuous, Equation lb applies, yielding
N2
N
Ni
ILN2LM
TIs
ILN
(N 2
2
21 + VNI
(29)
Ni
which is zero only at VN=0 (Figure 21).
3) In the discontinuous area, the current is constrained by the duty cycle:
a) For the forward converter for ILN <
'LN
Equations 15 and 16 apply:
ILLs
ILN
NiV S
II
VN
-
1i
(30)
b) For the Flyback Converter for ILN <iO
Equations 7 and 8 apply:
,
ILN2LM
TVs
_
N2
N,
D2
VN
2
(31)
4a) To find the particular locus of points for operation in Region 2, substitute the duty
cycle constraint of the flyback mode Equation 16.
23
ILN =
32
=
V\(1 2- V\)
(2
-
2 V\ + N2
This is the dotted line in Figure 19. Notice that it intersects the normal boundary line
(dashed) at the dual mode point V' = ( 1 - N2/N 1 ) as required.
4b) To find the particular locus of points for operation in Region 1, substitute the
duty cycle constraint of the forward mode
,
Equation 2b.
(33)
(2N 1 )
This is the dotted (straight) line in Figure 20. Notice that it intersects the normal boundIiN = N 2 VN/
ary (dashed) at the dual mode point, VN = 1-N/N 1
.
+22
The path of the circuit's operating point can now be traced out as any parameter
varies. Refer to Figures 11, 20, and 21 and assume VN is swept from a minimum to a
maximum. Operation begins towards the left of Figure 11, in Region 1. This corresponds
to a flyback current on the dotted line in Figure 21 with the remainder of the load current
supplied by the forward converter, operating on the horizontal characteristics in Figure 20.
As VN increases, the flyback contribution increases as the intersection point is reached.
At this point, the current sharing is unconstrained until VN increases further. The two
converters trade roles, the forward current on the dotted line of Figure 20 while the
flyback circuit picks up the remaining load current, operating on the horizontal characteristics of Figure 21. As VN becomes greater than unity, the forward action ceases, as indicated by the vertical line at ILN=O on Figure 20. This condition corresponds to Region 3.
24
1.2
1.1
VN
1.0
9
W
8
0
D =.5
7
C-
5
<
0=4
o
4
z
D=.2
.2
0
0
D=.1
I
I
.2
.3
ILN
.5
.5
.4
ILLS
=
N1 TVs
Figure 20.
V-I characteristic for forward circuit
-N
1.7
1.6
1.5
D=.7
1.4
D=.65
1.3
VN
1.2
1.1
D=.6
0
1.0
0
.9
0
I-
.8
D=.5
.7
z
.6
D=.4
.5
.4
D=.2
.3
.2
D=.3
D=.1
4~
.1
)
0
.1
I
.2
I
I
I
.3
N 2 1 LLM
,
TV
Figure 21.
V-I characteristic for flyback circuit
25
I
I.5
.4
.5
3.7 Device Ratings
The peak values of the various voltages and currents which appear on the circuit elements are listed in Table II for the dual mode, the forward, and the flyback converters.
These parameters are defined in Figure 22. So that a reasonable comparison can be made,
all three converters are assumed to be operating in a step down condition and the dual
mode converter is in its Region 1 of operation.
The dual mode converter has a lower V-I requirement on its switching device for two
main reasons. The peak off-state voltage is reduced (as compared to the isolated forward
converter) because the energy recovery network clamps the transformer secondary to VO,
rather than Vs.
The current is reduced because the magnetizing energy supplies load
current, reducing the forward contribution IL. In the form shown in Table II, it is clear
that the transistor current over and above the reflected load current (ION,) is reduced by
a factor of two. As the table shows, this does not impose a penalty in diode stress. The
output capacitance required to achieve a given voltage ripple will be increased somewhat,
but this will still be much less than required by a flyback converter (because of its discontinuous output current.) Table II does not list expressions for CO because more insight is
gained from a graphical comparison. Figure 23 illustrates the currents that CO must filter
in each case.
Depending on the application, the forward and flyback contributions in the dual mode
converter can be adjusted to best suit the governing conditions. Thus far, the dual mode
converter has been described analytically. In later chapters, the correlation of theory and
experimental results will be shown, including a numerical version of Table II for a typical
application.
26
Table II
COMPARISON OF PEAK DEVICE STRESSES
Dual Mode
VQ
Vs + VO/N 2
IQ
IoN1+ TVo/2NILm
VDR 1
Forward
Flyback
Vs(l+l/N
2
ION1 + TVO/NlLm
Io(N 2 +
/01VS)
N1
VF)- VF
VF)- VF
S
VsNI- VF
VSNI- VF
VDR 3
VO+ VSN2
Vs(1+ N 2
)
VDR 2
TVO
<IL>
Vs+ Vo/ N 2
(
N1
-(VO+
N2
Isolated
)
Parameter
Isolated
I0
2N? L,
Notes:
1) Vo< Ni Vs
2) VF is diode forward drop, assumed zero except for
VDR'S
3) Assume low ripple of continuous currents, i.e., A iL « IL
to simplify equations.
27
V 0 +N 2 VS
Io(N 2+
/01Vs)
-
+ VDR3
VDR1
+
-
N2
+ VN
Vs
VO
VDR2
1
N1
Co
+VQ
VDR 3
-
+
a) ISOLATED FORWARD CONVERTER
N
S1
Vs
VO
V0
-
-
+
VDR3
+
b) FLYBACK CONVERTER
N2
0
-
VDR1
+
Vs
+
10
+
N1
VDR2
c) FORWARD/FLYBACK CONVERTER
Figure 22.
Definitions of device stresses
28
C
Vo
i0 (t)
10
t
T
a) DUAL MODE CONVERTER (REGION 1)
io (t)
-
10
T
-t
b) FORWARD CONVERTER
io (t)
10 -------
T
c) FLYBACK CONVERTER
Figure 23.
Comparison of unfiltered output currents
29
3.8 Effects of Non-Ideal Elements
The basic operating relations have been shown for an ideal circuit. A physical circuit
will differ due to the existence of resistive losses, leakage inductance, and stray capacitance (Figure 24). The effects of losses in the various legs of the circuit can be accounted
for by the inclusion of suitable terms in the relations already developed. For example, the
diode "on" state voltage drops (VF) are easily added to the duty cycle constraints for the
two converters (Equations 1 and 2). From VL, D - VL,,1-D):
(1-D) ( VO+ VF)
AtLM
At Ls
VsD =N
(N1 Vs -
With the substitution of VOF -
2
VF)D - (1-D) (Vo+VF)
VO -
VO + VF for VO, the result is identical to that of Sec-
tion 3.1. Figure 11 is still valid, if the plot is considered to be D versus VoEI VS. For
high voltage outputs (VO >> VF) the change will not be significant. For a 5 volt supply,
however, a VF of 0.6 V would cause a 12% deviation in the effective output voltage.
Resistance in the secondary circuits will also cause the dual mode behavior to deviate
from the simplified description. Figure 24 illustrates one way of modeling parasitic resistances in the outputs of the forward and flyback portions of the circuit. It can be seen
that R, and Rp will add current-dependent terms to the above volt-seconds equalities at
Ls and Lm. This contrasts with the ideal behavior where the duty cycle is independent of
the output current, given continuous conduction in the dominant converter.
Two effects can be predicted without a detailed mathematical analysis. Parasitic resistance in the output of either converter will cause it to "see" a greater output voltage.
This will shift its D versus Vo/ Vs constraint to the left (assuming the axes are unchanged). If the effect is greater for the forward converter, the intersection of the two
constraints will occur at a lower Vo/ Vs. If the flyback converter has a greater shift, the
30
LI
D3
vs LM
S
Lm
V6
LI
D1
LS
e
RP
ESR
ESL
C
-
D2
Figure 24.
Circuit model with some parasitic elements
31
RL
intersection will move to the right, to greater Vo/ Vs. A second effect is that the current
distribution (between the forward and flyback portions of the circuit) will be constrained
at that intersection point, because of the existence of the current-dependent terms. This
behavior was demonstrated with the breadboard circuit, as shown in Chapter 5.
The inevitable transformer leakage inductance will contain energy that produces voltage peaks when the switching device is turned off. Depending on the components used,
some means of protective snubbing may be required. Also, stray capacitance may interact
with this parasitic inductance to produce oscillatory behavior during switching, although
this was not a problem.
One last significant non-ideality is related to the output capacitor. The effective series
inductance (ESL) and effective series resistance (ESR) of the capacitor will place constraints on its selection other than its capacitance and current rating. The ESR and ESL
will increase the output voltge ripple as compared to an ideal capacitor. This is especially
noticeable for discontinuous output currents. These and other parasitic effects are not
peculiar to the dual mode circuit, and thus are not further addressed here.
3.9 Summary
This chapter has presented the steady state operation of the dual mode converter, both
graphically and mathematically. Much detail has been shown, which supports the fundamental consequences of dual mode operation. This detail may at times tend to obscure
the basic results, however.
The most important aspect is the interaction of the two
modes, which thus defines the regions of operation (Figures 11, 12). Once this is accepted, mathematical detail follows directly. The method of depicting the operating point on
the normalized V-I characteristics (Figures 20, 21) is also important. This is a concise way
of showing how the two modes react to the load condition. An understanding of these
concepts is necessary before proceeding to the small signal analysis which follows.
32
Chapter 4
SMALL SIGNAL ANALYSIS
4.1 Overview
The dual mode forward/flyback converter has been analyzed using the state-space
averaging techniques of Middlebrook and C'k.5 These techniques provide detailed predictions for the transient behavior of the switching circuit which are used to achieve closedloop regulated operation. The analysis method represents each state of the switching circuit by an appropriate matrix of equations, the coefficients of which are averaged (weighted by the period each is in effect) to yield a single steady state representation. The application of standard perturbation and linearization techniques yields a transfer function
representation of the circuit. A circuit model is readily obtainable from these equations.
As a check, the circuit model can also be derived directly by equivalent circuit manipulations.
The dual mode circuit, in addition to presenting a new topology, poses the additional
problem of having several distinct regions of operation where different constraints are in
effect. The solution is a separate analysis for each region which provides a root locus not
only as a function of loop gain, but as a function of operating point as well.
4.2 Region 1:
State-Space Analysis
The dual mode circuit has three states (circuit configurations), not two as in the simple
buck converter. Three state variables will be used, the output voltage and the two inductor currents. The magnetizing current is discontinuous, which will require substituting its
average value as the state variable. 6
The basic equations are:
x =
A x + bvs
33
(34)
A = DAI + D 2 A 2 + D 3A 3
where
(35a)
b = Dbi + D 2 b 2 + D 3 b3 (35b)
d - D + d => Transistor ON Period
and
d2= D 2 + d 2 => Flyback conduction period
d3 = D 3 + d 2 => Forward only period
An
is the coefficient matrix for the n"' state. As indicated by the duty cycle expressions,
each total variable consists of a dc component and a small signal perturbation (indicated
by the carat
'^').
In the steady state, x = 0, yielding:
X = -A~
1
bVs
(36)
Perturbing and linearizing (34) provides:
X
= Ax + biVs + d [(A 1 - A3)
+ d 2 (A 2 - A)
x
+ (bi- b 3) vsj
(37)
+ (b 2 - b 3) vs
x
as the small signal relation.
The circuit configurations for each of the three states are shown in Figure 25. The
state variable matrix is
IL
x -ml(37b)
Evaluating the A. and b,, and applying equations 35a and 35b:
A=
D
0-D2
0
0
0
0
--
D2
1
-1
N2 C
C
RC
N2LM
-1
LS
Lm
b=
DN1
LS
(38)
0
34
1:N1
v
+
,
,
+
LM
Ls
IM
C
vo
RL
a) STATE 1: "ON" INTERVAL
1:N 2
L
1M
LM
C
VO
IT
Ls
RL
b) STATE 2: FLYBACK CONDUCTION PERIOD
vo
C
RL
Ls
iL
c) STATE 3: FORWARD ONLY PERIOD
Figure 25.
Switching states: Region 1
35
A*
There are additional constraints to consider due to the discontinuous nature of i1. In
state 3, jn
0. Therefore,
-
-i
dt
( T) - im(0)
-TII
0
(39)
which prevents iM from being used as a state variable in the normal sense.
Although a perturbation of the instantaneous current iM(t) may exist, the discrete
derivative of Equation (39) will always be zero. To remedy this situation, the iM state
variable is replaced by its average, defined as
1
1
M
Mm
=
2
vsdT
-L
2LM
(40)
Note that this is the average over the conduction interval of iM, which is (D + D 2) T, not
the switching period T. Since the state variable defined in this way depends on the value
of the current at one point (IMAX), its derivative over the period T is in fact zero (the
average for a given period being constant throughout that period).
If an attempt is made to evaluate the steady state condition (Equation 36), it is found
that the |Al - 0, indicating no closed form solution. Solving 0 - A X + b V, explicitly,
and rearranging, yields:
(41)
VO = DNI Vs
SI
+ IL(42)
N2
RL
D2 -
-Ni
(43)
which are the same relations found in the preceding chapter. Matrix Equation (36) could
not be solved directly because IM and IL cannot be independently determined, as was
found previously.
36
4.2.1 Perturbation
Applying Equation (37) is straightforward, yielding:
dt
+ D
-
N 2L
LV
0 L
v
Vs d
+
-
D2
-
diut =
--
V
N2LM
22
d
(44)
A
dt
dvo
dt
+
Ls
DN1
vs
V5N 1
+
diL
A
(45)
+-
1
(46)
N
2
N 2C
N2C2 d
RLC C
From (39), (44) can be set to zero and solved for the perturbation in the flyback conducD2
+
-
iL ~
tion period (d2):
d2
-D2
vo+
N 2D
N 2 Vs
S
V0
From (40), 'M can be resolved in terms of the other small signal quantities.
i=
VO
V
(47)
Since
iM(v, d, T, LM):
IM
-
aVS
-
VS
+
d
ad
(48)
assuming Lm is time invariant and the frequency is constant. Since (40) must also hold
for unperturbed operation:
vsd
IM = VsD I
(49)
V's v.+
I MV
(50)
Evaluating (48) with (49) provides:
Dd d
Now, with substitution of (47) and (50) into (45) and (46), the system can be reduced to
two state variables, iL and v. After collecting terms and simplifying, the result is reasonably tractable.
37
diL
dt diL
dfvc
dt
_
NIs
DN 1
0
1
1S
1
C
Re 1
2Ls
+L
[L+
IL
21M
1
A
L
L
+
V
d
2 Ijf
NICV
(51)
N 1 CD
where Rei = RL 11 Rj and R i is the apparent load impedance as seen by the flyback circuit:
,
VO
L
Solving (51) for IL and
0
VO N 2 '
(52)
2NLM
T
IM D2
:
S+
IL_
_
L
s2LsC+s
21
N1CReiCJ
NDVs
2 sIML
+11
(53)
N1DVs
V0
io
-- , --
from which the transfer functions
(D' + Vsd)
d
vs
etc. are readily available. For example, with
use of (5) to replace If:
VsN 1
-
+ S
NL
1
=
(54)
d s 2LsC +
s
+ 1+
This is the same result achieved for a forward converter, with two exceptions: the
effective load impedance is reduced from RL to RL 11 R 1', and a zero is added by the action of the flyback connection.
Note that if Lm - oo (no magnetizing current), (54)
reduces to the forward only case. As flyback action increases, the zero moves nearer to
the origin, and transfer function (54) is not a function of D, so the singularities do not
move as VO is changed by varying the duty cycle. Figure 26 illustrates the behavior of the
singularities, as the operating point is changed with a fixed circuit and as the circuit is
changed for increasing flyback action.
38
Ca)
Xl
X-POLE
O-ZERO
X
a)
vo SINGULARITIES FIXED FOR ANY OPERATING POINT
a
WITHIN REGION 1.
A
/
-
~jw
wn
I
I
I
%If
'4
b) MOVEMENT OF SINGULARITIES AS CIRCUIT IS ALTERED
FOR INCREASED FLYBACK CURRENT IN REGION 1.
Figure 26.
Root locus: Region 1
39
4.2.2 Canonical Circuit Model
Middlebrook and Cnk have established a canonical circuit model for representing any
switching converter input-output model. This circuit is shown in Figure 27, with the
effective output filter network, H,(s), represented by an L-C section. The actual form of
H,(s) will depend on the switching circuit modeled. The elements of the canonical circuit
model for a specific converter can be derived from the transfer function representation of
the switching circuit. This involves expressing the input-output properties of the circuit
with an input current-output voltage two-port representation.
The canonical circuit model was derived for the dual mode converter (Region 1 operation), with the result shown in Figure 28. The effective output filter of the dual mode circuit has the transfer function:
TLS
l+s NM+s____
H,(s) -
2L5
L
s 2 LsC+s --
Rei
L
+1
s2 LC+s -
Re
(55)
+1
This function can be realized with a dependent current source as shown in Figure 28. Notice also the added resistor at the primary of the transformer. This represents the added
load that the magnetizing inductance places on the source. This does not represent a loss,
because the power into that resistance equals that power provided by the current source in
the secondary circuit. These two elements represent the flyback circuit as added to a forward converter.
The canonical circuit model can also be obtained by equivalent circuit manipulations.
The multi-state switching circuit is represented by a continuous, averaged circuit model
whose parameters are then perturbed and linearized. This approach was also used for the
dual mode converter operating in Region 1, yielding the circuit of Figure 28 as before.
40
Re
Le
e(s)a
+
~s)8
.
V,
--
L -------
CONTROL FUNCTION
IDEAL DC-DC
TRANSFORMATION
EFFECTIVE FILTER
NETWORK H*(s)
++
Figure 27.
I
Canonical circuit model
I
I
Vs
-d
V__+Ni_
L
(2va-v0 )
___'__
R
D2N1
R'
1:DN 1
Figure 28.
Circuit model for dual mode converter: Region 1
41
v
4.3 Region 2:
State-Space Analysis
The state-space averaging technique was applied in Region 2 in the same way as in Region 1. The basic equations (34) to (37) still apply. Once again, there are three states, illustrated in Figure 29.
Evaluating the A, and b, and applying Equations (35a) and (35b) yields:
A=
0
0
ND'
0
0
(D+D 2 )
LS
(1-D)
(D+D 2)
N 2C
C
N2Lm
(56a)
-1
RLC
D
LM
b -
Ls
0
(56b)
Because iL is discontinuous, there is the additional constraint:
diL
--- = 0
dt
(57)
As before, the state variable iL is replaced by its average, defined as:
iL.z~
dT(Njvs-vo)
2L
=
2
2LS
iL =
from Equation (15).
(58a)
This is the average forward current over its conduction interval,
(D+D 2) T. Note that IL as used in Chapter 3 is the average over the full period T. To
avoid having two meanings for one variable, the dc equivalent for (58) will be called IA:
IA
DT(N1 Vs- VO)
2LS
(58b)
such that
IL - (D + D 2 ) IA
(58c)
This problem did not arise in the Region 1 analysis because two distinct variables, I; (the
42
flyback load contribution) and IM (the magnetizing inductor current), already existed.
If (36) is evaluated to determine the steady state response, it is found that JAI - 0,
again indicating no closed solution. Solved explicitly, (36) yields:
VO = DN 2 Vs/(1-D)
(59)
(l-D)IM
VO
+ (D+D2)IA - -N2
RL
(60)
D2
N1Vs-Vo
(61)
N,
N2Vs+Vo
These are the same relations found previously, with D 2 being the same as
82
of sec-
tion 3.3. It should be kept in mind that the discontinuous forward current contributes to
1o
during both states 1 and 2, unlike the flyback current of Region 1, which only contrib-
utes during state 2 (compare Equations (42) and (60)).
43
Ls
LM
RL
iM
-+
C
U
_________
I
1:N 1
a) STATE 1: "ON" INTERVAL
L
CI
+
VS
iM
LMu
I
0
1:N 2
V0
RL
b) STATE 2: FORWARD CONDUCTION INTERVAL
C
i
RL
M
Lm
1:N 2
c) STATE 3: FLYBACK ONLY PERIOD
Figure 29.
Switching states: Region 2
44
4.3.1 Perturbation
Evaluating the small signal relation (37) with A and b (56) provides:
D'
N2C
lM+
i +
)
(N1 Vs-VO)
+
LS
(D+D 2
IL
C
1
Vo +
-
d -c
V
-
LM
vs
+
v
(62)
+
DNI
2
Vs+Vo/N 2
LM
)
at
DV
i,
vL+
N2Lu
-(D+D
Ls
diL
d^o
dt
-(-D)
.
dit
dt
Ls
L-fl/N2)
RC
CC
.d+--d
2
IL
(63)
(64)
From the constraint (57), (63) can be set to zero and solved for d 2, the perturbation in
the forward current decay interval:
-(D+D
2)
DN 1
0VO
+
Vs
N1Vs
(65)
+
d2"
=
From (58), 'L can be resolved in terms of the remaining small signal quantities. Since
iL = iL Gs, Vo, d, T, Ls, N 1 ):
8V
Vs
+
A
aL
(66)
-
IL
8vV
assuming T, Ls, N, are time invariant. From the total variable and steady state expressions, (58a) and (58b) respectively:
*
IL
d(Nivs-vo)
(67)
D(NIVs-Vo)
Evaluating (66) with (67) provides:
N1 Vs- VO
V-
45
IA
NVsV
IA
+ -DDod
-
NIIA
IL = N
(68)
Now, with substitution of (65) and (68) into (62) and (64), the system can be reduced
The result is:
to two state variables, ij and v.
D
VO
DN 2 L4
L,
vs + I
- O
-v
R 2C
R3 C
-D'
dt
=r,
N2Luf
0
S
Re 2 C
N2C
dt
+
1
-1
,
dig
(69)
and
where Re 2 = RL 11 R
R2=
2Ls
T
(N2
2
(70a)
D'N1
Note the correspondence to Equation (52) in the Region 1 analysis. Here, the effective
circuit elements are a function of the operating point, as is the case in a flyback converter.
--
1
1
N 1DT
R2
:2Ls
1
RsRL
2D'
N2
D N1
TD'N1
---
2LSN2 I
D
N2
(70b)
- DI
2D ' + 1
(70c)
Solving (69) for IM and
1
s 2 LeC + S
(s+
1
Re2C
DN2
where
D2 C
DN2C
Le
Re 2
N2
s
D'2H D'R 2
+Le
R2
x
+1
C
Re2C DD '2
+
DD'
Le -
46
N2LM
,
lIMo
D
N2
N2
D'2R 3
(71a)
DLe
R3
(71b)
Although they are not as simple as those for Region 1, the various transfer functions for
Region 2 are derivable from (71).
If the forward action (the discontinuous mode in this region) is removed, NJ is
effectively zero, yielding R' = R 2 = oo, R 3 = Re2 - RL . In that case, the matrix equation (71) reduces to that derived 2 for a flyback only converter, which serves as a reassuring check.
The response of the output voltage to a perturbation in duty cycle is:
VO
--
VOI
DLe
TD
1 - s
3
-(
2)
ds2LeC + s -- +1
Re
I
which indicates a complex pole pair in the left half plane and a real zero in the right half
plane. For fixed circuit elements, the singularities move as the operating point is varied.
As D is increased, Le increases, which not only moves the poles nearer the origin but also
increases their damping factor.
It also tends to move the zero towards the origin (not
counting the effect on R 3). This is the usual result for a flyback converter, but here there
is an additional effect. As D increases, the forward action is decreased, which causes Re2
to increase and R 3 to decrease (both approaching R). This decreases the damping factor
but at the same time continues to move the zero nearer the origin. Consideration of typical parameter values indicates that the net effect is to increase the damping as D is increased. Figure 30a illustrates this behavior. If the circuit is altered to increase forward
action at any operating point (by varying NJ, N 2 , Ls, etc.) the singularities move as shown
in Figure 30b.
It has been shown that the dynamics of the dual mode converter are determined by
different elements, depending on which basic converter is dominant. This indicates that a
47
X-POLE
0-ZERO
/X
X
A
a) MOVEMENT OF v2 SINGULARITIES AS D IS INCREASED
WITH FIXED CIRCUIT ELEMENTS.
jCL
wn
1
U
a
~4h
b) EFFECT OF INCREASING FORWARD CONTRIBUTION AT
GIVEN OPERATING POINT BY VARYING CIRCUIT ELEMENTS.
Figure 30.
Root locus: Region 2
48
discontinuity in the locations of the singularities may exist as the transition between Regions 1 and 2 is made.
When the two linearized models for Regions 1 and 2, Equa-
tions (53) and (71) respectively, are taken in the limit as D approaches f - N2/NI (the
boundary point), they are not the same, and it is not expected that they would be. This is
because operating conditions that exist as the boundary is approached from each side are
different, and Figure 31 illustrates this point. A transition period exists during which both
the forward and flyback circuits are equally dominant. A state-space analysis for this condition (dc component of duty cycle = D fixed) shows that the singularities move from
one boundary condition to another as a function of the change in the two average
currents, IL and Ij. The closed loop analysis in Chapter 6 was done using the two systems of Equations (53) and (71).
4.4 Region 3:
State-Space Analysis
The Region 3 state-space-derived model stems directly from the Region 2 model, since
it is the special case, iL (t)
0. In fact, the Region 2 model should become the Region 3
model as Vo/ V, approaches N (the 2-3 boundary) and as IL becomes zero. As this condition is reached, DID' - NI/N 2, from (59). At this point,
R 3 - RL
R_2
1
N1
N1
(73a)
[2LTD
52
(73b)
This causes the Equation (71) to reduce to the flyback only case, with the exception that
Re2
RL since R2 has not become infinite. This is because a small signal forward
current, IL, is still possible, according to (68). Thus, it is necessary to recognize that R'
and R 2 are infinite for the Region 3 model.
Realizing this, the result is:
49
S+
e
S2LC+sLe
1
R2C
D2
VS
2
+DN
RL
Is+
DNSC
,2
+
VO
__
RLC
D'
N2 C
DD
1 1
ii-I
DD'
2
+
N
'2 2
D 2RL
sDLe 1
RL
Vd(
which is the expected result for a flyback converter. This has a -
d
response to change in
D, as illustrated in Figure 30a.
4.5 Summary
The net result of the state-space analysis is the linearized model for each region of
operation represented by the small signal transfer functions. These are used to determine
the closed-loop behavior for a system of the form shown in Figure 32.
The closed-loop transfer functions shown in this figure depend not only on the switching circuit's dynamics, as just determined, but also on the dynamics of the circuit that
completes the control loop. The controller converts an error signal (e - Vref - vo) to a
duty cycle d, which is pulse width modulation (PWM). The purpose of the control analysis is to ensure that the regulator has both sufficient stability and speed of response. This
requires adjusting the dc gain and dynamics of the controller to properly compensate the
loop's gain. Since the means for doing this depends on the control hardware used, the
closed-loop analysis will be demonstrated using the breadboard circuit described in the following chapter.
50
I
I
a)
b)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i
I-
I
I
I
I
I
I
I
c)
I
I
I
I
I
I
DT
I
I
I
I
T
0a - IL +
I
2I
=
I
I
I
I
DT
T
I
CONSTANT
D' - N2,N1
a) BOUNDARY OF REGION 1 MODEL AS D -
1-N2/N
1
1-N2 /N
1
b) TRANSITION
c) BOUNDARY OF REGION 2 MODEL AS D
Figure 31.
Transition at Region 1 - Region 2 boundary
51
-Y
G= a
GVd = v
Vref = REFERENCE VOLTAGE
d
e = vref - vo
.
Gvs =
vs
Linearized Model: V0 = Gvs vs + Gvd d
vs
GGvd
de
+
V0
Gde
LOOP TRANSMISSION: Gde Gvd
CLOSED LOOP RESPONSE:
vol
v
Gvs
CL
1 + GdeGvd
A
vo
reflCL
Figure 32.
1 + GdeGvd
Incremental block diagram of regulator
52
Vref
Chapter 5
EXPERIMENTAL WORK
5.1 Description of the Breadboard
A breadboard of the dual mode converter was constructed to verify the analysis of the
preceding chapters. This breadboard was intended to be a test fixture rather than an optimized circuit design. It was decided to have the breadboard simulate a computer logic
supply, with a 5 volt output at a power rating of 100 watts. This is a realistic size which
does not severely limit the choice of components.
For initial testing, the circuit was operated strictly as a dc-dc converter, with the input
voltage supplied by a laboratory dc supply.
The design input voltage would be that
achieved with a rectified and filtered ac source (170 volts peak nominal). The nature of
the dual mode converter enables the operating point to be placed in any one of the three
regions desired. Since the breadboard would be operating at a small Vo/ Vs (==.03), it was
appropriate to design for Region 1 operation (forward dominant). This enabled all three
operating regions to be traversed as the supply voltage was reduced from its nominal
value (assuming D is adjusted to hold Vo constant).
As noted in Section 3.2, the component values determine the distribution of the load
current between the forward and flyback converters. Equations 10 and 11 show that the
average forward and flyback currents are fixed for a given Vo anywhere in Region 1.
An analysis was undertaken to find the optimum distribution, based on minimizing total magnetic energy storage to reduce component size. This analysis was not conclusive,
however, because such a criterion adversely affects other circuit parameters (such as filtering requirements). Since this was a breadboard, a logical choice was to allow the two converters to share the load current approximately equally at the maximum load of 20 amps.
53
That is:
IL = IL
1
0
-
o =
Vol R L
at VO = 5 volts.
Component values were first calculated using the design equations of Chapter 3, which
assume a lossless circuit. These values are listed in Table III, which also shows the design
criteria. Next, the effect of semiconductor and inductor losses was considered, which increases the required primary current for a given output. The nominal turns ratios, NJ and
N 2 , were adjusted accordingly. Since the actual construction of the magnetic elements
influences these calculations, their design was carried on in parallel with the determination
of the nominal component values. This was an iterative process, which produced the
nominal turns ratios shown in Table IV. These are the actual wire turns ratios. Effective
turns ratios are also presented which indicate how data from the breadboard is expected to
correlate with the analysis of Chapter 3. These were obtained by considering the effects
of non-ideal diodes, as detailed in Section 3.8, which alter the effective secondary voltages.
The anticipated voltages and currents are listed in Table V. The components for the
breadboard were chosen on the basis of these peak stresses.
A power MOSFET was
selected for the switching element for two main reasons. In the first place, these devices
have low switching losses, a desirable characteristic for a 25 kHz breadboard. 7 Secondly,
the required drive circuitry is simplified, in comparison to bipolar devices, enabling the
power circuit to be interfaced easily with a control circuit.
The particular device used was an International Rectifier IRF 350. This device is rated
at 400 volts, peak, and 11 amperes, average. These values comfortably encompass the VQ
and iQ stresses (225 volts, 1 A avg) of Table V, and the device was on hand in quantity
when the breadboard was constructed; both desirable factors when a new power circuit topology is first tested.
54
Table III
IDEALIZED CIRCUIT COMPONENT VALUES
Design Criteria:
25 kHz
fs
sec
T
-
40
Vo
=
5 volts
1
Vsmax
=
20 amps
170 volts
-
Dmin
-
0.20 (at Vsmax)
Vsmin
-
100 volts (Regions 1, 2, boundary)
I'L
10 amps ( Region 1)
A iL
2 amps
Equation
Parameter
Value
Ni
1/6.8
2a
N2
1/12.3
9
81
.62
Ls
90 sH
12
Lm
580 sH
10
55
2b and Fig. 11
Table IV
NOMINAL TURNS RATIOS
Nominal
Effective
N,
1/6.0
1/7.5
N2
1/9.0
1/11.2
81
.67
.67
56
Table V
PEAK STRESSES FOR REGION 1 OPERATION
Parameter
Peak Value
Units
VO
5
V
Vs
170
V
I0
20
A
9.4
A
10.6
A
VQ
225
V
iQ
3.9
A
1
8.4
V
V DR 2
27.4
V
V DR 3
22.6
V
iD 1
12.0
A
(avg: 9.6 A)
1
D2
12.0
A
(avg: 4.6 A)
D3
26.5
A
(avg: 8.2 A)
38.3
A
(avg: 20.0 A)
18.3
A
(rms: 8.8A)
P DR
ic
57
Design Choices
(avg: 1.0 A)
It should be noted that the IRF350 is not as over-rated for the application as the above
current levels indicate. The peak stresses listed in Table V are for operation at the design
levels of Table III: specifically, for V, = 170 volts. Since the breadboard was used to
demonstrate the various regions of dual mode operation, the supply voltage was varied to
a point as low as one tenth of this nominal value. For a constant power output, this
corresponds to a maximum average current requirement of 10 A for the switching device.
Thus, the ruggedness of the IRF350 was an asset for the wide range of conditions under
which the breadboard was actually run.
The rectifiers used in the breadboard were Motorola IN5828 high power Schottky devices.
These are rated at 15 A average forward current with a peak reverse bias of
40 volts. Schottky rectifiers have the advantage of lower on-state voltage drop (VF) and
faster switching than conventional (silicon junction), high-power diodes.
The required output capacitance was first estimated by relating the output voltage ripple to the integral of the current to be filtered. Figure 33 indicates this area on the i0 (t)
waveform.
S
i dt
Assuming a peak-to-peak output voltage ripple of 50mV, (75) yielded CO = 3.2mF for the
io (t) specified by the design criteria (Table III).
Upon investigating available capacitors that satisfy the rms current requirement, however, it was found that ESR and ESL would be significant factors. Because C, must carry
a peak current of 18 amps, for example, an ESR as low as 2.8mfl would still produce a
voltage ripple as large as the 50mV allowed in the capacitance calculation. The effect of
ESL is not as easy to quantify since the rate of rise of the flyback current pulse is not
known before testing; nevertheless it q.uickly becomes clear why it is difficult to achieve
low output voltage ripple with converters that have discontinuous output currents.
58
i 0 (t)
38.3
20A ---
10
11.8
Ii
____________
T
DT
t
ic(t)
18.3
I
icmax
=
18.3A
U ~
t
-8.2
mwmmm
0
Figure 33.
0(t) - io(t) - 10 = io(t)- 20
Output capacitor current at rated load
59
icrms = 8.8A
For the purposes of the breadboard circuit a Mepco Electra 86F150 capacitor was used.
This component has a 17.0 mF capacitance rating and a nominal ESR of 16.9mfl. It has a
rms current rating of 7.4 A at 120 Hz and 85*C.
The forward smoothing inductor was specifically designed and constructed for the
breadboard. It is wound on a ferrite EC core manufactured by Ferroxcube Corporation.
The desired inductance was achieved by using a gapped central leg (under the winding)
and choosing the number of turns accordingly (Figure 34).
The initial transformer design also used a centrally gapped EC core, with the three
windings arranged concentrically over the gap to reduce leakage inductance. An air gap
dominates the total reluctance of the flux path, thus making the inductance (inversely)
proportional to gap length, rather than to total path length. A smaller gap increases the
magnetizing inductance, thus reducing the magnetizing current, as shown by Equation (4), which is repeated below.
VsDT
Lm
iM
(4)
For the dual mode converter, the transformer was designed to yield 600 MH of magnetizing inductance, as seen at the primary (source winding).
Initial operation of the breadboard indicated that coupling between the primary and
flyback secondary was insufficient. Ideally, when the transistor turns off, all the energy
Lmi 2!max, should be coupled to the
stored in the transformer, represented by ET -
flyback.secondary such that:
LM
ET
-
2N 2 2
r2
1 Lmax
(76)
However, any energy stored in leakage inductance at the primary cannot be removed via
the secondary (Figure 35). When the primary is open-circuited, this uncoupled energy
60
causes a voltage spike to appear at the primary terminals, thus adding to the voltage across
the transistor.
Because this problem was anticipated, a snubber circuit was placed across
the MOSFET before initial operation (Figure 36).
The uncoupled energy stored in the primary can be modeled as E, =
L
,ax This
2 LQ'maxTi
energy must be absorbed by the snubbing circuit at turnoff. Therefore:
1
2
L
i2
= I
2
IQmax
,1 2
sQ
( 7
(77)
The snubber limits the peak transistor voltage, but this energy is dissipated in R, when
the transistor turns back on and vQ is nearly zero. For this particular circuit, the snubber
was sized entirely in order to limit the peak voltage stress rather than to diminish the
switching dissipation (a vQ) in the MOSFET.
The voltage levels seen with the original
transformer indicated that the problem should be addressed by reducing the uncoupled
energy rather than by dissipating it in a snubber.
The uncoupled energy was reduced in two ways. First, to minimize inductance in the
primary circuit outside the transformer, the breadboard was physically reconfigured to
shorten all lead lengths and minimize the area of any current loops. This had a small but
observable effect on the switching behavior of the circuit.
Second, a new transformer
design was used, with special emphasis on improving the coupling between the primary
and reset (flyback) windings.
A major obstacle to such a design is that the large winding ratio involved (==10:1)
makes it difficult to get the windings physically close. Windings with a ratio near 1:1 can
be wound bifilarly (a two wire wrap, one from each winding) which minimizes leakage inductance but at the expense of interwinding capacitance.
After considering various winding techniques, a ready-made solution was found. A
transformer designed by William McMurray of General Electric 8 for a transformer-coupled
61
AIR GAP
WINDING
CORE
Figure 34.
L 11
Cross section of "EC" core for inductor construction
1:N 2
LM - MAGNETIZING
INDUCTANCE
-1 1,L 12 - LEAKAGE
INDUCTANCE
LM
(FORWARD WINDING NOT SHOWN FOR CLARITY)
Figure 35.
Model of transformer including leakage inductance
s 250 0
A 11R
.01 pF
Figure 36.
Snubber configuration
62
VQ
flyback inverter had the desired properties.
This unique design utilizes four layers of
copper sheet (the secondary) interleaved with four primary layers, each containing nine
turns of copper braid. The resultant ratio is 36:4 so that N 2 = 1/9.
The purpose of the
copper sheet is to spread out the winding with fewer turns so that it has the same effective
surface area as the other winding.
A prototype of this transformer was found and
modified for use in the dual mode circuit by the addition of another secondary (for the
forward converter) consisting of an outer wrap of six turns of copper braid. This yielded
N, - 6/36 - 1/6.
The gapping was changed to provide the desired magnetizing induc-
tance of Lm = 600y H. Replacing the original transformer with this design cut the voltage
overshoot (above the clamping level,
Vs + VO/N 2) in half, with the same size snubber.
All the data in the second half of this chapter was taken from this improved version of
the breadboard.
The schematic for the power circuit is shown in Figure 37. Figure 38 shows the actual
breadboard.
The details of the instrumentation are provided in the following section,
along with the results of the dc input testing. The drive signal for the MOSFET, vGS, was
initially supplied by a laboratory pulse generator set for 25 kHz output with adjustable
duty cycle.
This was later replaced by a single integrated PWM chip which enabled a
current limit shutdown circuit to be easily implemented.
Chapter 6 describes how the
closed loop control was achieved with these components, first with adjustable (dc) Vs and
VREF,
and later-for line operation-with low and high (==100 V) input ripple.
5.2 Presentation of Steady-State Results
The gate signal for the IRF350 in the power circuit (Figure 37) was provided by a Silicon General SG1525 Pulse Width Modulator.
shown in Figure 39.
A block diagram for this 16 pin DIP is
For non-regulated operation, a dc voltage applied directly to the
63
Lm = 600g H
IN5828
4
IN5828
90/. H
36
6
VS
IN5828
T167Fr1 5 0
6
D
IRF350
G
.1I
S
+251
VO
250i1
A115D
.01/ F
VSHUNT
Figure 37.
Figure 38.
Power circuit components
Dual mode converter breadboard
64
compensation terminal modulates the duty cycle. The complete open-loop drive circuit is
shown in Figure 40. This includes the instantaneous current limit with manual shutdown
and reset controls.
For the low ripple dc input case, a Systron Donner HR160-3C power supply was used
to provide Vs. By adjusting VS and D (via the voltage applied at the SG1525) any point
on the D versus Vo/ Vs plot could be reached.
The various waveforms were displayed
and photographed on a Tektronix 7854 Oscilloscope with Waveform Calculator.
The
waveform calculator quickly provides valuable numerical data from stored waveforms.
Tektronix P6302 current probes with AM503 amplifiers acquired the currents. This system can measure up to 25A (dc) before saturation of the probe occurs. When larger
currents were encountered, the probe was used in conjunction with a small current
transformer at the lead under investigation.
Figure 41 shows the flyback and forward currents for full rated output (20 amps into
5 volts) for V, = 160 Vdc. The output current (before the output capacitor) and voltage
are shown in Figure 42. The form of the currents indicates Region 1 operation.
Note
that the output voltage ripple, 220 mV p-p, is larger than would be expected given the capacitance used, due to the ESR and ESL of C0 , as previously stated. A small bypass capacitor across Co was used to reduce the high frequency impedance of the output
capacitance.
From these waveforms, certain effective circuit parameters can -be quickly deduced.
The flyback current decay interval, 81 = .70, was virtually constant for all Region 1 operation, as succeeding waveforms will illustrate. The predicted value of 81 from the analysis
of Chapter 3 was N2/N, = .67. The average flyback current, IL = 6.7A, was less than
the predicted value of 9.4 A, but calculations using the design equation for I
(Equa-
tion 10) indicate that a larger effective forward turns ratio, NI, or a larger magnetizing in-
65
VC
OSC OUTPUT
SYNC34
PT
A
6OUTPUT
OSCILLA TOR
CLOCK
CTS
DISCHARGE 71
+G
1525 OUTPUT
STAGE
INV INPUTT
N.I.
INPUT
COMPENSATION
SOPT-STA-T
SOFT-TARTCIRCUITRY
-VIN
UMT
REFERENCE
REGULATOR
5
GVRE
GAIOUNO
Figure 39.
SG1525 block diagram (Source: Silicon General 1980 Product Catalog)
+15
SG1525
+5
IN4608
3k
150f
GATE
IN4608
OMP A
2N2222
18v
IN6277
1+
OFF
15
ON-+VSHNT
1k
51Op F
-
10k
1k
+5
.7v
Figure 40.
SHUTDOWN
(PIN 9 SG1525)
+
L1
Open-loop drive circuit
66
ductance, L,, would account for this.
Figure 43 shows a close-up of the transistor voltage and current at turn-off. It can be
seen that the actual dissipation within the transistor is small. The switching loss takes
place almost entirely with the snubber (as noted previously, the snubber was sized for
protection against over-voltage). The total primary current, as measured with the shunt
in the current limit circuit, is shown in Figure 44. Since the source voltage is constant,
the total power into the circuit is simply Vs times the average input current, I,:
Pi,, - (160 volts) (.87 A) - 139 W.
The load power is VOI = 100 W, so the efficiency n is found to be .72. This compares
favorably
with
other switching supplies,
although
refinement
could
produce
an
improvement.
To illustrate the traversal of the various regions of operation, the source voltage was
decreased, while the duty cycle was adjusted to maintain the output voltage constant. This
was done for VO = 2.5 volts, so as not to over-stress the circuit's components, since the
input current must rise as the input voltage falls.
Figure 45 illustrates the outputs of the two converters for the case Vs = 160 V. Note
that as Equation 10 indicated, the flyback current, IL, is essentially halved as VO is
halved, such that IL supplies the remainder of the load current (compare Figures 41 and
45). Also note that although the duty cycle has been cut in half, 81 has remained constant. The transistor voltage and current waveforms are shown in Figure 46. The vQ
waveform illustrates the overshoot due to parasitic inductance in the primary circuit. This
is followed by the interval during which vQ is clamped by the flyback secondary to
Vs + VO/N 2. This evaluates to 182 volts for the conditions of Figure 46. When the 81
interval ends, D 3 turns off and vQ reduces to just Vs - 160 volts as shown.
The next four figures illustrate the effect of maintaining VO as Vs is reduced. This
67
corresponds to moving from left to right on Figure 10. Figure 47 shows the boundary
case where 81 = D. Beyond this point, the magnetizing current is continuous. As Vs is
further reduced, Region 2 is entered, and there the output current is dominated by the
flyback current, as shown in Figure 48.
Figure 49 illustrates the discontinuous nature of the forward current in Region 2. In
the breadboard circuit, Ls was sized for low ripple in the forward current, so IL is naturally quite small when iL is discontinuous. Decreasing Vs to N, VO causes the forward converter
to
cease
operating
completely,
as
shown
in
Figure 50.
In
this
case,
I'L - 10 = 10A, and the circuit behaves like a simple flyback converter.
As Vs was varied from 160 volts down to 17 volts, the duty cycle D required to maintain VO
=
2.5 V was recorded at many points. This information is contained in the D
versus Vo/ Vs plot in Figure 51. This figure also shows the predicted relationship (Figure 11) for the effective turns ratios used in the breadboard. It can be seen that the two
curves are in very close agreement for lower values of Vo/ Vs (Region 1 operation). The
boundary point (between forward or flyback-dominated operation) occurs at the expected
duty cycle, but a greater than expected D was required at every point in Regions 2 and 3.
This can be attributed to the fact that losses increase as the circuit is forced to operate
from a lower source voltage. When the flyback current pulses are of shorter duration and
higher amplitude, the average current remains the same, but the rms value increases.
Since losses tend to increase with rms current, the efficiency is decreased.
5.3 Summary
In this chapter, it has been shown that the breadboard of the dual mode circuit
demonstrates the behavior predicted in Chapter 3. Most importantly, the existence of
three distinct regions of operation has been confirmed. The flyback current decay period,
81, was found to be constant within Region 1 as expected. The flyback secondary clamps
68
the transistor voltage during tOFF, but uncoupled magnetic energy causes a voltage peak
when the primary circuit is opened.
The waveforms, along with the D versus Vol Vs plot (Figure 51), show that the dominant (continuous) converter determines the duty cycle. This is important because it was
a basic assumption used in the small signal analysis (Chapter 4) which was used to achieve
closed-loop control. The description of the closed-loop experiments follow.
69
10 Asec/div
IL = 6.7A
0 -10
IL= 13.3A
0 -*
Top:
i
10 A/div
Vs = 160 V
Bottom:
iL
10 A/div
Vo = 5.0 V
Figure 41.
Forward and flyback currents: rated load
10 psec/div
10
0---0-
Avo
0
Figure 42.
=
Top:
10
10 A/div
Bottom:
vo
2 V/div
Output current and voltage: rated load
70
20.0 A
=
220 mV
100 nsec/div
VQ
iQ
Q
0
--
Figure 43.
iQ
1 A/div
vQ
50 V/div
Transistor turn-off waveforms
10 pisec/div
10 = .87 A
'Prms
0 --_b
ip 1 A/div
Figure 44.
Primary current
71
= 1.67 A
10 ysec/div
IL = 6.8 A
r
4-*IL = 3.2 A
o
--
0
Figure 45.
Top:
iL
5 A/div
V, = 160 V
Bottom:
iL
5 A/div
V, = 2.5 V
Forward and flyback current: Vo = 2.5 volts
0
-
5 psec/div
0
-
IQ = .21 A
Figure 46.
Top:
IQ
1 A/di v
Vs = 160 V
Bottom:
V0
50 V/di v
VO = 2.5 V
Transistor voltage an d current: VO = 2.5 volts
72
10 ysec/div
0 -*-
Boundary
Case
0
-0
-
0
Figure 47.
Top:
V
50 V/div
Middle:
iL
5 A/div
Bottom:
iL
5 A/div
Vs = 77 V
Vo = 2.5 V
Forward, flyback currents, transistor voltage boundary case
OPW 2
VZR -1
DSW
3
2
10 ysec/div
10 = 10.0 A
0
Irms = 11.11 A
-*
-
0
Top:
io
5 A/div
Vs = 60 V
Bottom:
V0
1 V/div
Vo = 2.5 V
Figure 48.
Output current and voltage: Region 2
73
10 ysec/div
Top:
IL
10
Bottom:
iL
0.5 A/div
Figure 49.
A/div
Vs = 30 V
VO = 2.5 V
Forward and flyback currents: Region 2
10 psec/div
IL = 10 A
IL
Top:
il
20 A/div
Bottom:
iL
1 A/div
Figure 50.
Forward
V, = 17.7 V
VO = 2.5 V
and flyback currents: Region 3
74
0A
FIGURE 50
.9
.8
.7
.6
D
,-
.5 --
.4
.3
PREDICTED
ACTUAL
.2
V
1
2
3
4
5
6
7
8
9
10
Vx/V, X 102
Figure 51.
Experimental D versus VO/Vs plot
75
11
12
13
Chapter 6
CLOSED-LOOP DESIGN AND TESTING
6.1 Overview
This chapter presents frequency response plots based on the state-space analysis of
Chapter 4 and on a model for the SG1525's error amplifier. The cascade of these systems
is the loop transmission of the regulator circuit. A simple compensation scheme, based
on the form of this response, was implemented.
To demonstrate the regulating action, the response of the output voltage to step
changes in either reference voltage or source voltage is presented. The final test consists
of the line-operated regulator with high ripple input.
6.2 Basic Tests
As Figure 32 illustrates, the loop transmission of the regulator depends on the dynamics of both the power circuit and the controller. In Chapter 4, small signal transfer functions were derived for the power circuit in each of its regions of operation. It must be
kept in mind that these are valid only at frequencies well below the switching frequency of
the circuit due to the nature of the state-state averaged model. The control circuit was
designed for satisfactory operation in two different applications. In the simpler case, the
dual mode converter is operated from a low ripple source of dc and required to maintain
the output voltage at a level specified by a reference. Since Vo/ Vs is essentially constant,
the operating point is either fixed, or it varies slowly as the reference voltage is adjusted.
The compensation is chosen to produce the desired stability and speed of response over a
suitable range of operating points.
In the more interesting case, the wide operating range of the dual mode converter is
put to use by operating from a rectified ac source that is only mildly filtered. For opera76
tion from a 60 Hz line, the fundamental component of the input ripple is at 120 Hz.
Ideally, since many switching periods occur during an input cycle, the regulator can maintain a low ripple output by modulating the duty cycle in response to the varying source
voltage. This brings up questions of input versus output energy storage, which will be
discussed with the experimental results.
The SG1525 Pulse Width Modulator's error amplifier can be modeled by the circuit
shown in Figure 52, which results in an uncompensated transfer function dominated by a
single pole at 400 Hz. 9 The open loop dc gain is 1037 which, when multiplied by the duty
cycle to error voltage transformation ratio of .33, yields the Bode plot shown in Figure 53.
This is the Gd, transfer function. When cascaded with the Region 1 output voltage to
duty cycle transfer function (Grd) of the breadboard, the loop transmission depicted in
.
Figure 51 results. Note that as Equation 54 indicated, the dc value of Gyd equals VsN1
For operation from a rectified and filtered ac line, Vs is appropriately chosen as 170 volts,
which was the design voltage used in Chapter 5. In Region 2, the transfer function varies
with the operating point, as Figure 28a illustrates. The Bode plot (Figure 55) depicts this
function at a typical point in Region 2. Note that Figures 54 and 55 (for Regions 1 and 2
respectively) are very similar in the area of crossover (magnitude = 1). The uncompensated loop transmission predicts an unstable circuit because of the lack of phase margin.
It should be noted that the switching frequency of the breadboard, 25 kHz = 105.2
rad/sec, is very close to the predicted crossover point of the uncompensated circuit.
The shape of the Bode plot suggests a lead network (a zero followed by a pole) as an
appropriate compensation network. 10 The form of the compensation network is shown in
Figure 56. This is a relatively simple compensation scheme, yet it successfully demonstrates the use of the dual mode converter in both the low and high input ripple cases.
The resulting responses for two different sets of compensation parameters, differing in
77
C --- - 4
7 MfI
Ve
56P F
+
+
10 Ve
Figure 52.
10
5
SG1525 error amplifier
r-
e(s) - ERROR AMP OPEN LOOP
104
ON&
103
e(s)1
102
101
10 0 L
10 0
101
Figure 53.
102
103
w
I
I
104
105
Uncompensated SG1525 transfer plot
78
I
106
105
Gd eGvd = - LT
104
REGION 1 UNCOMPENSATED
(CALCIULATED VALUES)
1o3
LT
I
102
10'
100
0
1
3
2
4
1
5
I
w
6
-1000
0
-180*
-200*
-300*
Figure 54.
Uncompensated loop - transmission: Region 1
79
7
- LT = GdeGvd
105
REGION 2 UNCOMPENSATED
104
I
LT
ASYMTOTIC A PPROXIMATION
103
102
101
100
00
100
i
i
10'
102
i
103
I
S104
105
106
-1000
-
1800
-200*
-300*
Figure 55.
Representative uncompensated loop transmission: Region 2
80
w
1
C
10
7M6
Rc
56pF
l+
0
cc
RESULTING SINGULARITIES
S
~1
7Mi -Cc
1
S
S
(Cc >> 56pF, RC << 7Mfl)
Pole
Zero
11
RC-56pF
Pole
IGdeI
Decreasing RC
Increasing InceaiC\
nc
1
7Mfl-Cc
H1
1
Rc-56pF
1
7MO -56pF
Figure 56.
Compensation parameters
81
stability versus speed, are presented below.
It can be seen that increasing the compensation capacitor C, lowers the error
amplifier's pole which shifts the crossover to a lower frequency. However, this affects the
circuit's ability to suppress the effects of large input ripple. As Figure 32 illustrated,
-SI
-s
(77)
1 + GdeGy.
V C. L.
It is therefore desirable to maintain as large a loop transmission as possible at the frequency of the source ripple - 120 Hz = 750 rad/sec in this case. This leaves only two decades of frequency for the magnitude to reach unity if crossover is to occur sufficiently
below the switching frequency for stable operation. This effect became apparent during
experimental testing of compensation parameters and indicates the desirability of operating circuits with high ripple inputs of higher switching frequencies.
The first application of the regulator, as a true dc-dc converter tied to a reference, was
straightforward to implement. Using Rc
=
1kf and C, - 1 MF, the response to a step
change in reference voltage is shown in Figure 57. The width of the output voltage trace
is due to the compression of the switching frequency ripple. If Cc is reduced to .05 MF
(which increases the loop transmission at all frequencies), the response shown in Figure 58 is obtained. As expected, the total damping of the circuit has been decreased, as
evidenced by the larger peak overshoot. Also, the frequency of this oscillation has increased. Note that the responses to positive and negative step changes are different. The
fastest response the control circuit can make to a decrease in Vref is to turn the drive signal off completely for several switching periods, in which case the time constant of the
output filter determines the initial response.
To observe the response of the regulator to a step change in source voltage, a high
82
2 msec/div
Vs = 80 volts
Figure 57.
Top:
vo
100 mV/div
Vo = 1 volt
Bottom:
vref
100 mV/div
Vref = 1 volt
Response to reference step: Region 1 (slow compensation)
2 msec/div
Vs = 80 volts
Figure 58.
Top:
vo
100 mV/div
VO = 1 volt
Bottom:
vref
100 mV/div
Vref = 1 volt
Response to reference step: Region 1 (fast compensation)
83
power square wave source (prepared by Gene Johnson of GE) was placed in series with
the dc laboratory supply. Comparisons of Region 1 versus Region 2 response for both
slow and fast compensation were conducted.
Figure 59 shows the result of applying a
6 volt step on a source voltage of 80 volts with the reference fixed at 2 volts. The high
frequency ripple has been removed to reveal the response to the source step, which is
quite small. If the source voltage is reduced to 40 volts, the response then becomes that
of Region 2, as shown in Figure 60. It is apparent that the output voltage transient is
much larger in this region, which is consistent with Equation 77. The function G, for
Region 2 contains a zero which increases the high frequency gain, while that for Region 1
does not.
Increasing the mid-band gain by moving the first compensation pole to higher frequency (the fast compensation) decreases the output transient as evidenced by Figure 61. This
corresponds to increasing the denominator of Equation 77. It was found that the Region 2 response was not stable over its full range of operating points with this fast compensation, because of movement of the singularities with the voltage swing.
6.3 Line Operation
The line-operated testing was conducted using the connection shown in Figure 62.
The smaller the value of C,, the greater the swing in voltage applied to the source terminals of the regulator. This voltage swing is also a function of the load power, of course.
If we neglect for a moment the energy storage capability of the converter's output filter,
we note that the regulator tries to draw constant power from its source. This causes the
source to see the regulator as a negative impedance, since the source current increases as
the source voltage decreases. However, this is an incremental impedance, since the large
scale Vs/Is is positive, as shown in Figure 63.
Figure 64 shows the source and output voltage waveforms for the case C = 60 yF,
84
80 V
-
2 msec/div
Vref = 2 V
2 V
-*
Figure 59.
Top:
vs
5 V/div
Bottom:
vo
20 mV/div
Response to Vs step: Region 1 (slow compensation)
2 msec/div
40 V
-0
Vret = 2 V
-
2 V
Figure 60.
Top:
vs
5 V/div
Bottom:
vo
20 mV/div
Response to Vs step: Region 2 (slow compensation)
85
80 V
-
2 msec/div
Vref = 2 V
2 V
-*
Figure 61.
Top:
vs
5 V/div
Bottom:
vo
20 mV/div
Response to Vs step: Region 1 (fast compensation)
86
*
-F
110 VAC
Figure 62.
C.
vs
TO
REGULATOR
AC line connection
is
VsIs =P in = CONSTANT
'SLOPE = INCREMENTAL IMPEDANCE
SLOPE =
LARGE SIGNAL
IMPEDANCE
vs
Figure 63.
Illustration of input impedance
87
V,f = 1.75 volts. These waveforms and those following use the fast (higher midband
gain) compensation described above. In Figure 64, the operating point remains entirely
within Range 1, and there are no noticeable anomalies in the output voltage waveform.
In Figure 65, the output voltage has been increased to the rated value of 5 volts,
which increases the source voltage ripple to 60 volts. Some oscillation becomes apparent
in the output voltage following the cusp of the source waveform where Region 2 is entered. This is due to the compromise necessary in choosing a fixed compensation for the
full operating range.
However, fixed compensation is simple, and experimentation
showed that it can be optimized toward some desired response.
Decreasing C to 20 gF increases the source ripple to 90 volts when V, = 3 volts, as
shown in Figure 66. Since the maximum Vo/ Vs is greater in this case than in Figure 65,
Region 2 is not as deeply entered. There is a 50 mV bump in vo in response to the steplike change in v, at its minimum. This property of the source voltage waveform is the
main obstacle to achieving an unperturbed output waveform.
Figure 67 illustrates the
modulation of the primary current pulse during this high ripple operation. This was measured using the shunt of the current limiting circuit.
This chapter has demonstrated the successful closed-loop control of the forward/
flyback converter. Since conclusions on these results are conclusions on the entire thesis,
they are presented in the final chapter.
88
2 msec/div
0
--
Figure 64.
Top:
vO
500 mV/div
Bottom:
vs
50 V/div
Source and output voltages:
Ci = 60pF, Vref = 1.75V
2 msec/div
0 --
0-
Figure 65.
Top:
vO
2 V/div
Bottom:
vs
50 V/div
Source and output voltages: Ci = 60sF, Vref = 5.OV
89
2 msec/div
Figure 66.
Top:
vO
500 mV/div
Bottom:
v.
50 V/div
Sc urce and output voltages: Ci = 20/sF, Vref = 3.OV
2 ysec/div
Primary Current 100 mA/div
Figure 67.
Modulation of duty cycle (high ripple source)
90
Chapter 7
CONCLUSIONS AND SUGGESTIONS FOR FURTHER RESEARCH
The dual mode behavior of the forward/flyback converter has been successfully
demonstrated.
The flyback converter accomplishes the reset function for the isolation
transformer so that no additional reset circuitry is required.
Furthermore, since the
transformer magnetizing energy is supplied to load, the utilization of the switching transistor is improved. In Chapter 5, it was shown that the dual mode converter does behave
according to the three region model developed in Chapter 3. Using this information, circuit elements can be chosen to place the operating point as desired for given input/output
conditions.
The dual mode converter has characteristics which offer operational advantages for
some applications when compared to either the forward or flyback converter taken alone.
For example, placement of the operating point in Region 1, where forward action dominates, produces a minimum requirement for the output filter by maintaining a continuous
load current, while still maintaining the reset benefits of the flyback circuit. This is essentially the case for a large percentage of time when the converter is fed from a high ripple
input. When necessary, however, the flyback converter can dominate and maintain the
output voltage outside the range that would be obtainable with the forward circuit alone.
This occurs during the minimum of the source voltage waveform with high ripple input
operation.
The ability to tolerate a large source voltage ripple permits a large reduction in input
filter capacitance. The effect of such operation on the smoothness of the output voltage
waveform depends on the feedback control circuit used. The control system used with
the breadboard was based on the small signal model developed using state-space averaging
91
techniques. Using a simple, fixed, single variable feedback network, the dual mode converter was line-operated with input ripple exceeding one-half the peak input voltage. The
output voltage ripple resulting from this low frequency (120 Hz) perturbation was found
to be less than that produced by the 25 kHz switching action.
For higher performance (faster response, wider operating range), the feedback network could be improved in several ways. Full state variable feedback would permit the
system's poles to be placed as desired by appropriately chosen gains at a given operating
point. This would require a novel approach for the dual mode converter since (as demonstrated in Chapter 4) the effective state variable set is dependent on the operating region.
Operation over a wide range of input voltages really requires that the feedback path be
a function of the operating point. Since the source voltage, and thus the operating point,
is a periodic function of time, this requires that any feedback gains be time-varying. This
would permit keeping the closed-loop poles in fixed locations. This technique has been
introduced by Schecht.11 Time-varying feedback gains were used in the control loop of a
line-interfaced inverter to compensate for the power circuit's time-dependent response.
Such an approach appears applicable to the control problem of the high ripple input, dual
mode converter, but it has not yet been attempted. One possibility, rather than a continuously varying gain approach, would be a control circuit that senses the change in operating
region and responds with a different compensation strategy.
It was noted in Chapter 5, in the discussion of the breadboard design and results, that
the large step-down ratio of the flyback winding made it difficult to achieve good coupling.
The resulting uncoupled energy created a voltage problem at transistor turn-off. The very
large input/output voltage ratio of the breadboard (170/5) is probably a "worst case" condition. The dual mode converter would function well in a step-down condition where the
output voltage was approximately one-half the source voltage, which would ease the
92
transformer winding problem.
Examples of such applications would include line-operated
battery chargers for telephone systems or electric vehicles. The battery-charging application could use the wide operating range of the dual mode converter to virtually eliminate
filter capacitance.
A battery can provide a voltage source load without additional capaci-
tance, while the input filter can be drastically reduced by using high ripple input operation.
The reduction of input filter capacitance can significantly improve the ac mains power factor, which is an additional benefit.
Many properties of the dual mode forward/flyback converter have been presented.
The breadboard circuit has demonstrated the basic principles of operation for a hypothetical low voltage application.
Further development of this converter should include the
design and testing of circuits which exploit the basic understanding gained thus far to produce systems optimized to their applications. Once understood, the dual mode circuit becomes a practical alternative to currently used dc-dc switching topologies.
93
REFERENCES
(1)
R. Severns, "Switchmode Converter Topologies - Make Them Work for You," Application Bulletin A035, Intersil, Inc., 1980
(2)
S. Hayes, "A Design Technique for Optimizing Power Device Utilization in FeedForward Converters," Powercon 8, Session F
(3)
A.I. Pressman, Switching and Linear Power Supply, Power Converter Design, Hayden,
1977
(4)
C. Van Velthooven, "Properties of DC-DC Converters for Switched Mode Power
Supplies," N.V. Phillips Application Note No. 472, Eindhoven, 18 March 1975
(5)
R.D. Middlebrook and S. C(1k, "A General Unified Approach to Modeling Switching
Converter Power Stages," IEEE PESC, 1976 Record, pp. 18-34
(6)
S. C6k and R.D. Middlebrook, "A General Unified Approach to Modeling Switching
DC-to-DC Converters in Discontinuous Conduction Mode," IEEE PESC, 1977
Record, pp. 36-57
(7)
S.R. Westbrook, The Switching Behavior of the Power MOSFET, MIT Master's Thesis,
1980
(8)
W.McMurray, "Selection of Snubbers and Clamps to Optimize the Design of
Transistor Switching Converters," IEEE Transactions on Industry Applications, Vol.
IA - 16, No. 4, July/August 1980
94
(9)
S. Dendinger, "Designing with the SG1525/1527 Series of Pulse Width Modulators," Silicon General, Inc. Application Notes - SG1525/1527, 1980
(10) J.K. Roberge, OperationalAmpfiers: Theory and Practice, John Wiley and Sons, 1975
(11) M. Schlecht, "Time-Varying
Feedback Gains for Power Circuits with Active
Waveshaping," IEEE PESC, 1981 Record, pp.52-59
95