18-447
Computer Architecture
Lecture 18: Caches, Caches, Caches
Prof. Onur Mutlu
Carnegie Mellon University
Spring 2015, 2/27/2015
Assignment and Exam Reminders
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Lab 4: Due March 6
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Control flow and branch prediction
Lab 5: Due March 22
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Data cache
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HW 4: March 18
Exam: March 20
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Advice: Finish the labs early
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You have almost a month for Lab 5
Advice: Manage your time well
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Agenda for the Rest of 447
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The memory hierarchy
Caches, caches, more caches (high locality, high bandwidth)
Virtualizing the memory hierarchy
Main memory: DRAM
Main memory control, scheduling
Memory latency tolerance techniques
Non-volatile memory
Multiprocessors
Coherence and consistency
Interconnection networks
Multi-core issues
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Readings for Today and Next Lecture
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Memory Hierarchy and Caches
Required
n  Cache chapters from P&H: 5.1-5.3
n  Memory/cache chapters from Hamacher+: 8.1-8.7
Required + Review:
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Wilkes, “Slave Memories and Dynamic Storage Allocation,” IEEE
Trans. On Electronic Computers, 1965.
Qureshi et al., “A Case for MLP-Aware Cache Replacement,“
ISCA 2006.
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Review: Caching Basics
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Caches are structures that exploit locality of reference in
memory
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Temporal locality
Spatial locality
They can be constructed in many ways
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Can exploit either temporal or spatial locality or both
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Review: Caching Basics
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Block (line): Unit of storage in the cache
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Memory is logically divided into cache blocks that map to
locations in the cache
When data referenced
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HIT: If in cache, use cached data instead of accessing memory
MISS: If not in cache, bring block into cache
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Maybe have to kick something else out to do it
Some important cache design decisions
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Placement: where and how to place/find a block in cache?
Replacement: what data to remove to make room in cache?
Granularity of management: large, small, uniform blocks?
Write policy: what do we do about writes?
Instructions/data: Do we treat them separately?
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Cache Abstraction and Metrics
Address
Tag Store
Data Store
(is the address
in the cache?
+ bookkeeping)
(stores
memory
blocks)
Hit/miss?
Data
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Cache hit rate = (# hits) / (# hits + # misses) = (# hits) / (# accesses)
Average memory access time (AMAT)
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= ( hit-rate * hit-latency ) + ( miss-rate * miss-latency )
Aside: Can reducing AMAT reduce performance?
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A Basic Hardware Cache Design
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We will start with a basic hardware cache design
Then, we will examine a multitude of ideas to make it
better
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Blocks and Addressing the Cache
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Memory is logically divided into fixed-size blocks
Each block maps to a location in the cache, determined by
the index bits in the address
tag index byte in block
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used to index into the tag and data stores
2b
3 bits 3 bits
8-bit address
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Cache access:
1) index into the tag and data stores with index bits in address
2) check valid bit in tag store
3) compare tag bits in address with the stored tag in tag store
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If a block is in the cache (cache hit), the stored tag should be
valid and match the tag of the block
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Direct-Mapped Cache: Placement and Access
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Assume byte-addressable memory:
256 bytes, 8-byte blocks à 32 blocks
Assume cache: 64 bytes, 8 blocks
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tag
Direct-mapped: A block can go to only one location
index
byte in block
Tag store
3 bits 3 bits
2b
Data store
Address
V
tag
=?
q
MUX
byte in block
Hit?
Data
Addresses with same index contend for the same location
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Cause conflict misses
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Direct-Mapped Caches
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Direct-mapped cache: Two blocks in memory that map to
the same index in the cache cannot be present in the cache
at the same time
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One index à one entry
Can lead to 0% hit rate if more than one block accessed in
an interleaved manner map to the same index
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Assume addresses A and B have the same index bits but
different tag bits
A, B, A, B, A, B, A, B, … à conflict in the cache index
All accesses are conflict misses
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Set Associativity
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Addresses 0 and 8 always conflict in direct mapped cache
Instead of having one column of 8, have 2 columns of 4 blocks
Tag store
Data store
SET
V
tag
tag
V
=?
=?
Logic
Address
tag
3b
index
byte in block
2 bits 3 bits
MUX
MUX
byte in block
Hit?
Key idea: Associative memory within the set
+ Accommodates conflicts better (fewer conflict misses)
-- More complex, slower access, larger tag store
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Higher Associativity
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4-way
Tag store
=?
=?
=?
Logic
=?
Hit?
Data store
MUX
MUX
byte in block
+ Likelihood of conflict misses even lower
-- More tag comparators and wider data mux; larger tags
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Full Associativity
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Fully associative cache
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A block can be placed in any cache location
Tag store
=?
=?
=?
=?
=?
=?
=?
=?
Logic
Hit?
Data store
MUX
MUX
byte in block
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Associativity (and Tradeoffs)
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Degree of associativity: How many blocks can map to the
same index (or set)?
Higher associativity
++ Higher hit rate
-- Slower cache access time (hit latency and data access latency)
-- More expensive hardware (morehitcomparators)
rate
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Diminishing returns from higher
associativity
associativity
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Issues in Set-Associative Caches
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Think of each block in a set having a “priority”
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Key issue: How do you determine/adjust block priorities?
There are three key decisions in a set:
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Where to insert the incoming block, whether or not to insert the block
Promotion: What happens to priorities on a cache hit?
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Insertion, promotion, eviction (replacement)
Insertion: What happens to priorities on a cache fill?
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Indicating how important it is to keep the block in the cache
Whether and how to change block priority
Eviction/replacement: What happens to priorities on a cache
miss?
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Which block to evict and how to adjust priorities
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Eviction/Replacement Policy
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Which block in the set to replace on a cache miss?
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Any invalid block first
If all are valid, consult the replacement policy
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Random
FIFO
Least recently used (how to implement?)
Not most recently used
Least frequently used?
Least costly to re-fetch?
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Why would memory accesses have different cost?
Hybrid replacement policies
Optimal replacement policy?
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Implementing LRU
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Idea: Evict the least recently accessed block
Problem: Need to keep track of access ordering of blocks
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Question: 2-way set associative cache:
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What do you need to implement LRU perfectly?
Question: 4-way set associative cache:
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What do you need to implement LRU perfectly?
How many different orderings possible for the 4 blocks in the
set?
How many bits needed to encode the LRU order of a block?
What is the logic needed to determine the LRU victim?
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Approximations of LRU
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Most modern processors do not implement “true LRU” (also
called “perfect LRU”) in highly-associative caches
Why?
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True LRU is complex
LRU is an approximation to predict locality anyway (i.e., not
the best possible cache management policy)
Examples:
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Not MRU (not most recently used)
Hierarchical LRU: divide the 4-way set into 2-way “groups”,
track the MRU group and the MRU way in each group
Victim-NextVictim Replacement: Only keep track of the victim
and the next victim
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Hierarchical LRU (not MRU)
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Divide a set into multiple groups
Keep track of only the MRU group
Keep track of only the MRU block in each group
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On replacement, select victim as:
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A not-MRU block in one of the not-MRU groups (randomly pick
one of such blocks/groups)
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Hierarchical LRU (not MRU) Example
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Hierarchical LRU (not MRU) Example
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Hierarchical LRU (not MRU): Questions
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16-way cache
2 8-way groups
What is an access pattern that performs worse than true
LRU?
What is an access pattern that performs better than true
LRU?
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Victim/Next-Victim Policy
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Only 2 blocks’ status tracked in each set:
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On a cache miss
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victim (V), next victim (NV)
all other blocks denoted as (O) – Ordinary block
Replace V
Demote NV to V
Randomly pick an O block as NV
On a cache hit to V
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Demote NV to V
Randomly pick an O block as NV
Turn V to O
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Victim/Next-Victim Policy (II)
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On a cache hit to NV
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Randomly pick an O block as NV
Turn NV to O
On a cache hit to O
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Do nothing
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Victim/Next-Victim Example
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Cache Replacement Policy: LRU or Random
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LRU vs. Random: Which one is better?
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Example: 4-way cache, cyclic references to A, B, C, D, E
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Set thrashing: When the “program working set” in a set is
larger than set associativity
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Random replacement policy is better when thrashing occurs
In practice:
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0% hit rate with LRU policy
Depends on workload
Average hit rate of LRU and Random are similar
Best of both Worlds: Hybrid of LRU and Random
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How to choose between the two? Set sampling
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See Qureshi et al., “A Case for MLP-Aware Cache Replacement,“
ISCA 2006.
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What Is the Optimal Replacement Policy?
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Belady’s OPT
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Replace the block that is going to be referenced furthest in the
future by the program
Belady, “A study of replacement algorithms for a virtualstorage computer,” IBM Systems Journal, 1966.
How do we implement this? Simulate?
Is this optimal for minimizing miss rate?
Is this optimal for minimizing execution time?
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No. Cache miss latency/cost varies from block to block!
Two reasons: Remote vs. local caches and miss overlapping
Qureshi et al. “A Case for MLP-Aware Cache Replacement,“
ISCA 2006.
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Aside: Cache versus Page Replacement
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Physical memory (DRAM) is a cache for disk
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Usually managed by system software via the virtual memory
subsystem
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Page replacement is similar to cache replacement
Page table is the “tag store” for physical memory data store
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What is the difference?
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Required speed of access to cache vs. physical memory
Number of blocks in a cache vs. physical memory
“Tolerable” amount of time to find a replacement candidate
(disk versus memory access latency)
Role of hardware versus software
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What’s In A Tag Store Entry?
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Valid bit
Tag
Replacement policy bits
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Dirty bit?
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Write back vs. write through caches
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Handling Writes (I)
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When do we write the modified data in a cache to the next level?
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q
Write through: At the time the write happens
Write back: When the block is evicted
Write-back
+ Can consolidate multiple writes to the same block before eviction
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Potentially saves bandwidth between cache levels + saves energy
-- Need a bit in the tag store indicating the block is “dirty/modified”
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Write-through
+ Simpler
+ All levels are up to date. Consistency: Simpler cache coherence because
no need to check lower-level caches
-- More bandwidth intensive; no coalescing of writes
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Handling Writes (II)
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Do we allocate a cache block on a write miss?
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Allocate on write miss: Yes
No-allocate on write miss: No
Allocate on write miss
+ Can consolidate writes instead of writing each of them
individually to next level
+ Simpler because write misses can be treated the same way as
read misses
-- Requires (?) transfer of the whole cache block
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No-allocate
+ Conserves cache space if locality of writes is low (potentially
better cache hit rate)
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Handling Writes (III)
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What if the processor writes to an entire block over a small
amount of time?
Is there any need to bring the block into the cache from
memory in the first place?
Ditto for a portion of the block, i.e., subblock
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E.g., 4 bytes out of 64 bytes
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Sectored Caches
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Idea: Divide a block into subblocks (or sectors)
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Have separate valid and dirty bits for each sector
When is this useful? (Think writes…)
++ No need to transfer the entire cache block into the cache
(A write simply validates and updates a subblock)
++ More freedom in transferring subblocks into the cache (a
cache block does not need to be in the cache fully)
(How many subblocks do you transfer on a read?)
-- More complex design
-- May not exploit spatial locality fully when used for reads
v d subblock v d subblock
v d subblock
tag
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Instruction vs. Data Caches
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Separate or Unified?
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Unified:
+ Dynamic sharing of cache space: no overprovisioning that
might happen with static partitioning (i.e., split I and D
caches)
-- Instructions and data can thrash each other (i.e., no
guaranteed space for either)
-- I and D are accessed in different places in the pipeline. Where
do we place the unified cache for fast access?
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First level caches are almost always split
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Mainly for the last reason above
Second and higher levels are almost always unified
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Multi-level Caching in a Pipelined Design
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First-level caches (instruction and data)
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Second-level caches
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Decisions very much affected by cycle time
Small, lower associativity
Tag store and data store accessed in parallel
Decisions need to balance hit rate and access latency
Usually large and highly associative; latency not as important
Tag store and data store accessed serially
Serial vs. Parallel access of levels
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Serial: Second level cache accessed only if first-level misses
Second level does not see the same accesses as the first
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First level acts as a filter (filters some temporal and spatial locality)
Management policies are therefore different
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Cache Performance
Cache Parameters vs. Miss/Hit Rate
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Cache size
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Block size
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Associativity
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Replacement policy
Insertion/Placement policy
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Cache Size
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Cache size: total data (not including tag) capacity
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Too large a cache adversely affects hit and miss latency
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smaller is faster => bigger is slower
access time may degrade critical path
Too small a cache
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bigger can exploit temporal locality better
not ALWAYS better
doesn’t exploit temporal locality well
useful data replaced often
Working set: the whole set of data
the executing application references
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Within a time interval
hit rate
“working set”
size
cache size
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Block Size
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Block size is the data that is associated with an address tag
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not necessarily the unit of transfer between hierarchies
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Sub-blocking: A block divided into multiple pieces (each with V bit)
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Too small blocks
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Can improve “write” performance
hit rate
don’t exploit spatial locality well
have larger tag overhead
Too large blocks
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too few total # of blocks à less
temporal locality exploitation
waste of cache space and bandwidth/energy
if spatial locality is not high
block
size
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Large Blocks: Critical-Word and Subblocking
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Large cache blocks can take a long time to fill into the cache
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fill cache line critical word first
restart cache access before complete fill
Large cache blocks can waste bus bandwidth
q
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divide a block into subblocks
associate separate valid bits for each subblock
When is this useful?
v d subblock v d subblock
v d subblock
tag
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Associativity
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How many blocks can map to the same index (or set)?
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Larger associativity
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lower miss rate, less variation among programs
diminishing returns, higher hit latency
hit rate
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Smaller associativity
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q
lower cost
lower hit latency
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Especially important for L1 caches
Power of 2 associativity required?
associativity
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Classification of Cache Misses
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Compulsory miss
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q
n
Capacity miss
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first reference to an address (block) always results in a miss
subsequent references should hit unless the cache block is
displaced for the reasons below
cache is too small to hold everything needed
defined as the misses that would occur even in a fully-associative
cache (with optimal replacement) of the same capacity
Conflict miss
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defined as any miss that is neither a compulsory nor a capacity
miss
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How to Reduce Each Miss Type
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Compulsory
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Caching cannot help
Prefetching
Conflict
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More associativity
Other ways to get more associativity without making the
cache associative
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Victim cache
Hashing
Software hints?
Capacity
q
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Utilize cache space better: keep blocks that will be referenced
Software management: divide working set such that each
“phase” fits in cache
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Improving Cache “Performance”
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Remember
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Average memory access time (AMAT)
= ( hit-rate * hit-latency ) + ( miss-rate * miss-latency )
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Reducing miss rate
q
Caveat: reducing miss rate can reduce performance if more
costly-to-refetch blocks are evicted
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Reducing miss latency/cost
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Reducing hit latency/cost
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Improving Basic Cache Performance
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Reducing miss rate
q
q
More associativity
Alternatives/enhancements to associativity
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q
q
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Victim caches, hashing, pseudo-associativity, skewed associativity
Better replacement/insertion policies
Software approaches
Reducing miss latency/cost
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q
q
q
q
q
Multi-level caches
Critical word first
Subblocking/sectoring
Better replacement/insertion policies
Non-blocking caches (multiple cache misses in parallel)
Multiple accesses per cycle
Software approaches
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