Lab 3
Digital Systems Laboratory
ECE230L – Spring 2011
Lab 3: Universal NAND
Objectives:
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•
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Copy existing schematic from another project into current project.
Create and use a symbol.
Implement basic logic gates (AND, OR and NOT) from NAND gates.
Verify DeMorgan’s theorem via simulation
Implement logic circuit using only NAND gates.
Lab Details:
Part 1 – NAND only equals circuit
Objective: Learn to copy schematics from other projects, create symbols from schematics, and make
instances of newly created symbols.
a.
b.
c.
d.
e.
f.
Copy equals schematic from lab 0 tutorial into lab3 project
Create a symbol for equals.sch. (equals_basic.sch equals_basic.sym)
Create new schematic (equals_nand.sch); include in report
Create symbol (equals_nand.sym)
Create new schematic and drag in instances of the previously created symbols; include in report
Attach inputs A and B to both symbols, and supply separate outputs for each symbol.
Create test bench and verify that the outputs are equal; include in report
Deliverables: Schematic for NAND only version of equals. Top level schematic that includes instances of
equals and equals_nand symbols, and accompanying test bench waveform.
Part 2 – Basic logic gates from NAND gates
Using only NAND gates, create:
a. An AND gate (and_nand.sch and and_nand.sym)
b. An OR gate (or_nand.sch and or_nand.sym)
c. A NOT gate (not_nand.sch and not_nand.sym)
Create a new equals circuit that is implemented with these new versions of AND, OR and NOT.
Create a new symbol for this equals implementation and add this new version of equals to Part 1.e
schematic and Part 1.f test bench.
Deliverables: Schematic for each logic gate created above (and_nand.sch, or_nand.sch, not_nand.sch)
Part 3 – DeMorgan’s equations
Show that a + b = ab
Boise State University
Electrical and Computer Engineering Department
(simulate and build on proto-board)
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Lab 3
Digital Systems Laboratory
ECE230L – Spring 2011
Show that a  b = a + b
(simulate only)
Deliverables: Schematics and waveforms
Part 4 - NAND only implementation of f (a, b, c) = abc + abc + abc
Re-do lab 2 to find the minimal solution, then implement with only NAND gates. It should only take one
7400 chip to implement this design.
Design a circuit that implements the following function:
f (a, b, c) = abc + abc + abc
You will basically be repeating the steps you went through in Labs 0 and 1, including appropriate unit
naming and internal signal truth table verification in simulation.
Deliverables: Check-off, design work, truth tables, reduced algebraic expression, schematic waveform,
discussion.
Deliverables:
Check-off:
TA to check off your completed circuit for Part 4 by end of lab period (11:55 AM)
Submission:
Due by Midnight Thursday 2/3/2011
Email:
To: ece230lreport@gmail.com
cc: your team partner
Subject: Lab3_TeamX report (X is your team no.)
Attachment: Lab3_TeamX.zip (contents as listed below)
Attachment:
(must be zip format – no others accepted)
Contents of zip file:
1. Report File: \Lab3_TeamX_Report.pdf
Report Content
(create in Microsoft Word using template provided)
Items as specified in each part
After report has been created in Word, create a pdf and then zip.
Boise State University
Electrical and Computer Engineering Department
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