June 21, 2007
Lev Uvarov
CCB Interface
The CCB interface provides the SP with timing and trigger control signals distributed by
the Clock and Control Board (CCB) over the backplane [i]. The backplane counts as many as 34
signal lines coming in and going out of the SP. Table 1 arranges backplane signals into four
Groups. All GTLP lines are active LOW (negative bus logic).
Table 1: SP CCB Interface Signals.
Signal
Lines
Direction
Type
Clock Group
Logic
Duration
Usage
CCB_CLK
2
IN
Point-to-point
LVDS
40MHz
Used
CCB_CLK_EN
1
IN
Bussed
GTLP
Pulse, n counts
Connected, but not used
GTLP
Level
Used
Subtotal
3
Fast Control Group
CCB_CMD [5..0]
6
IN
Bussed
CCB_CMD_STR
1
IN
Bussed
GTLP
25ns
Used
CCB_L1ACC
1
IN
Bussed
GTLP
25ns+ECL FP
Used
CCB_RDY
1
IN
Bussed
GTLP
Static level
Used
SP_L1REQ (former SP_RSVD[3])
1
OUT
Bussed
GTLP
25ns
Used
CCB_ECRES
1
IN
Bussed
GTLP
25ns
Connected, but not used
CCB_BCRES
1
IN
Bussed
GTLP
25ns
Connected, but not used
CCB_BX0
1
IN
Bussed
GTLP
25ns+ECL FP
Connected, but not used
CCB_L1RES (former CCB_RSVD[3])
1
IN
Bussed
GTLP
Level
Connected, but not used
CCB_DAT [7..0]
8
IN
Bussed
GTLP
Level
Connected, but not used
CCB_DAT_STR
1
IN
Bussed
GTLP
25ns
Connected, but not used
Subtotal
21
Reload Group
CCB_SP_HRES
1
IN
Bussed
GTLP
400ns
Used
SP_CFG_DONE
1
OUT
Point-to-Point
GTLP
Level
Used
Subtotal
2
Reserved Group
CCB_RSVD [2..0]1
3
IN
Bussed
GTLP
25ns
Connected, but not used
SP_RSVD [2..0]
3
OUT
Bussed
GTLP
25ns
Connected, but not used
Subtotal
Total
8
34
The Clock Group includes differential clock and clock enable lines. The SP uses the
CCB_CLK signal as a reference for its on-board QPLL. The 40 MHz QPLL output after deskewing drives each of the SP FPGAs. The 80 MHz QPLL output delivers a reference clock to
GTX_CLK pins of the TLK2501 serializers / deserializers. The SP ignores the CCB_CLK_EN
signal.
The Fast Control Group includes a CCB_RDY status line, TTCrx command and data
busses with strobes, and a few TTCrx signals, decoded by the CCB. The Fast Control Group
signals are valid when and only when the CCB_RDY is LOW. The SP uses neither decoded
TTCrx signals, nor CCB data.
1
CCB_RSVD3 is assigned for CCB_L1RES – L1 Reset signal resets L1 buffers and resynchronizes optical links.
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June 21, 2007
Lev Uvarov
The Reload Group includes a CCB_SP_HRES (Hard Reset) signal for reconfiguration of
the SP FPGAs and a SP_CFG_DONE (Configuration Done) status line that the SP returns to the
CCB.
The Reserved Group is not used.
The VME_FPGA delivers fast control signals to every SP FPGA via a 6-bit Fast Control
(FC) bus. Table 2 sets correspondence between the FC and CCB signals.
Table 2: Correspondence between CCB commands and SP Internal Fast Control Bus Signals
TTCvi /
TTCci
Broadcast
command
Dedicated Lines
CCB Command Description
CCB Backplane
Signal or Command
Code
L1 Accept
ccb_l1acc
L1 Accept
ccb_l1acc
L1 Accept
ccb_l1acc
Internal
Condition
Unconditional
If enabled by
VM/MA/CSR_TFC
If enabled by
VM/MA/CSR_SFC
If enabled by
VM/MA/CSR_TFC
If enabled by
VM/MA/CSR_SFC
If enabled by
VM/MA/CSR_TFC
If enabled by
VM/MA/CSR_SFC
If enabled by
VM/MA/CSR_SFC
If enabled by
VM/MA/CSR_SFC
Fast Control Bus
Command Code
fc_cmd[5] or FC_L1ACC
fc_cmd[4] or FC_TFRUN
fc_cmd[3] or FC_SFRUN
Inject Test Pattern into MPC
ccb_cmd[5:0]=0x2F
or CCB_TPSP
ccb_cmd[5:0]=0x2F
or CCB_TPSP
ccb_cmd[5:0]=0x01
or CCB_BC0
ccb_cmd[5:0]=0x01
or CCB_BC0
ccb_cmd[5:0]=0x24
or CCB_TPTMB
ccb_cmd[5:0]=0x30
or CCB_TPMPC
No command / Idle state
ccb_cmd[5:0]=0x00
or CCB_NOCMD
0x00
Unconditional
Bunch Crossing Zero Mark (BC0)
ccb_cmd[5:0]=0x01
or CCB_BC0
0x04
Unconditional
fc_cmd[2:0]=0x0
or FC_NOCMD
fc_cmd[2:0]=0x1
or FC_BC0
Orbit Counter Reset (OC0)
also resets valid pattern counters
ReSync (former L1Reset)
resynchronizes MPC fiber links,
resets readout buffers,
does not reset Event Counters
ccb_cmd[5:0]=0x02
or CCB_OCRES
0x08
Unconditional
fc_cmd[2:0]=0x2
or FC_OCRES
ccb_cmd[5:0]=0x03
or CCB_L1RES
0x0C
Unconditional
fc_cmd[2:0]=0x3
or FC_RSYNC
Event Counter Reset (EC0)
CCB_ECRES
0x02
Unconditional
fc_cmd[2:0]=0x4
or FC_ECRES
Start Data Taking (not used)
ccb_cmd[5:0]=0x06
or CCB_L1STT
0x18
Unconditional
fc_cmd[2:0]=0x5
or FC_L1STT
Stop Data Taking (not used)
ccb_cmd[5:0]=0x07
or CCB_L1STP
0x1C
Unconditional
fc_cmd[2:0]=0x6
or FC_L1STP
Inject Test Pattern into SP
Inject Test Pattern into SP
Bunch Crossing Zero Mark
Bunch Crossing Zero Mark
Inject Test Pattern into TMB
0xBC
0xBC
0x04
0x04
0x90
0xC0
fc_cmd[4] or FC_TFRUN
fc_cmd[3] or FC_SFRUN
fc_cmd[4] or FC_TFRUN
fc_cmd[3] or FC_SFRUN
fc_cmd[3] or FC_SFRUN
fc_cmd[3] or FC_SFRUN
Encoded Commands
fc_cmd[2:0]=0x7
or FC_VME
SP is under VME control
Note. The SP should be under CCB control: VM/MA/CSR_FCC[8] = 0, for CCB
commands to be passed to the internal Fast Control Bus.
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Lev Uvarov
L1A_FSMs have been eliminated from all FPGAs, and all CSR_FCC registers have been
modified accordingly. If configured to listen to CCB signals, the SP follows a “Free Running”
approach: its track-finding logic is active all the time. The SP also collects and pushes readout
data to DDU whenever it gets L1 Accept signal.
It is assumed that the GMT/GT logic eventually makes a decision on the validity of
SP/MS trigger-path data based on the SP status being reported over the FMM output. It is also
assumed the TTC sends L1 Accepts only when the SP reports being in a Ready state.
The SP reports being in a Disconnected state (all LEDs are ON), if it is under VME
control, otherwise it reports status as described in
http://www.phys.ufl.edu/~uvarov/SP05/LU-SP2DDU_Event_Record_Structure_4d2.pdf
VM/MA/CSR_FCC[8] = 1 setting enables VME access to DAT_LP, DAT_GP,
DAT_DT, and DAT_GE registers in the Front FPGAs and DAT_ETA, DAT_FTR and
CSR_SCC registers in the SP FPGA. Otherwise VME access to the above registers is disabled as
a fool-proof measure against changing essential SP parameters “on the fly”.
Front Panel LED
Table 3: Front Panel LEDs, Top to Bottom
LED Label
LED Color
NO LOCK
VME
DTRUN
L1ACC
RED
YELLOW
YELLOW
YELLOW
TRACK
YELLOW
BSY
RDY
WOF
OSY
RED
GREEN
RED
RED
MExx
YELLOW
Description
When ON indicates that on-board QPLL lost lock to the TTC clock
Flashes on every VME command addressed to the SP and terminated with DTACK
When ON indicates SP is under CCB control
Flashes on every FC_L1ACC sent to the Fast Control Bus; see Table 1
Flashes on every L1R, which may be sent to the backplane, if enabled; see Table 1 and
VM/ACT_FCC, VM/CSR_FCC and SP/CSR_REQ registers description
Visualizes signal on Busy FMM output
Visualizes signal on Ready FMM output
Visualizes signal on Warning Overflow FMM output
Visualizes signal on Out of Sync FMM output
When DIMMED indicates the Optical Receiver Carrier Detect signal in ON,
Flashes on every Valid Pattern occurence in the input data stream
xx stands for 1A, 1B, 1C, 1D, 1E, 1F, 2A, 2B, 2C, 3A, 3B, 3C, 4A, 4B, and 4C muons
CSR_FCC – Fast Control Configuration / Status
VME FPGA
This read/write register sets the SP fast control modes and shows the status of the
L1Accept control state machine. The FCM bit switches the source of fast control commands,
which could be either from the local VME interface (default on power-up), or from the CCB
over the TF crate backplane. The FCL bit controls the source for the internal FC_L1ACC signal.
The source can be either a backplane CCB_L1ACC signal (default), or a fake signal, generated
on every FC_SFRUN to facilitate debugging of the readout logic. The feature is used for
validation of the readout process in the SP. The FCLCT bit controls if Local Charged Triggers
(LCT) from the SP_FPGA are being sent to the backplane. The LCT is defines as Mode > 0 for
the SP core output.
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June 21, 2007
Lev Uvarov
Table 4: CSR_FCC Data Format for VME_FPGA
D15
RDY
X
D14
BSY
X
D13
OSY
X
D12
WOF
X
D11
0
X
D10
0
X
D9
0
X
D8
FCM
FCM
D7
0
X
D6
0
X
D5
D4
FCL FCLCT
FCL FCLCT
D3
0
X
D2
0
X
D1
0
X
D0
0
X
Acc
R
W
Here:
− X – Don’t care bit;
− RDY = 1 – FMM state machine is in a Ready state;
− BSY = 1 – FMM state machine is in a Busy state;
− OSY = 1 – FMM state machine is in a Out-of-Synch state;
− WOF = 1 – FMM state machine is in a Warning-OverFlow state;
− FCM = 0 / 1 (default) – Fast Control Mode set to CCB / VME (default);
− FCL = 0 (default) / 1 – CCB/VME_L1ACC (default) / FC_SFRUN is a source for the
FC_L1ACC signal, see the CSR_SFC register description for details on FC_SFRUN.
− FCLCT = 0 (default) /1 – disable (default) / enable Local Charge Trigger.
Front FPGA, SP FPGA and DDU FPGA
In the Front FPGA, SP FPGA or DDU FPGA this read-only register returns current state
of the L1Acept Finite State Machine and FMM Finite State Machine.
Table 5: CSR_FCC Data Format for FRONT_FPGA, SP_FPGA and DDU_FPGA
D15
RDY
X
D14
BSY
X
D13
OSY
X
D12
WOF
X
D11
0
X
D10
0
X
D9
0
X
D8
0
X
D7
0
X
D6
0
X
D5
0
X
D4
0
X
D3
0
X
Here:
− X – Don’t care bit;
− RDY = 1 – FMM state machine is in a Ready state;
− BSY = 1 – FMM state machine is in a Busy state;
− OSY = 1 – FMM state machine is in a Out-of-Synch state;
− WOF = 1 – FMM state machine is in a Warning-OverFlow state.
[i] CCB'2004 Specification. Version 3.3, 09/01/2006
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D2
0
X
D1
0
X
D0
0
X
Acc
R
W