January 22, 2010
Lev Uvarov
Added Registers
Table 1: Register Address Field Format for Non Privileged Data Access
RA,
hex
Register
Label
Description
SP
Valid CA / Valid MA
DD
Fx
VM
Page
Data Register Group
0x70
DAT_HLC
Halo Track Counter
M1/M2/M3
-
-
-
1
Control/Status Register Group Update
CSR_SCC = 0x46 – SP05 Core Configuration
RW: SP / MA
This read/write register keeps the SP05 core configuration options. The register is protected
against accidental accesses: in order to get VME access to this register the SP05 should be set to
the VME fast control mode.
Please note that the register format changes with every core release.
Table 2: CSR_SCC / SP Data Format for 100122 and later versions (Core Version #2)
D15
X
0
D14
D13
X
X
0
0
Not Used
D12
X
0
D11
D10
X
X
1
0
Core Version
D9
D8
PRE1 PRE0
PRE1 PRE0
Pre-Trigger
D7
DTE
DTE
D6
D5
D4
WPHI HDL1 HDL0
WPHI HDL1 HDL0
Mode Control
D3
D2
X
X
0
0
Not Used
D1
D0 CYCL
BXA1 BXA0
W
BXA1 BXA0
R
BXA [1:0]
Here:
−
−
−
−
−
X – Don’t care bit;
PRE [1:0] = 1, 2 (default), 3 – Pre-Trigger control;
DTE = 0 (default) / 1 – disable (default) / enable Drift Tube data inputs to SP05 Core;
WPHI = 0 (default) / 1 – enable Wider Phi extrapolation;
HDL [1:0] = 0 (default), 1, 2, 3 – Halo Trigger Delay = additional latency of 0, 1, 2, 3
for Halo Triggers; applies to output 3 only;
− BXA [1:0] = 0, 1, 2 (default) – Bunch Crossing Analyzer history control.
Table 3: CSR_SCC / SP Data Format for 090601 and later (but earlier than 100122) versions (Core Version
#2)
D15
X
0
D14
D13
X
X
0
0
Not Used
D12
X
0
D11
D10
X
X
1
0
Core Version
D9
D8
PRE1 PRE0
PRE1 PRE0
Pre-Trigger
D7
DTE
DTE
D6
D5
D4
WPHI HDL1 HDL0
WPHI HDL1 HDL0
Mode Control
D3
D2
X
X
0
0
Not Used
D1
D0 CYCL
BXA1 BXA0
W
BXA1 BXA0
R
BXA [1:0]
Here:
−
−
−
−
−
X – Don’t care bit;
PRE [1:0] = 1, 2 (default), 3 – Pre-Trigger control;
DTE = 0 (default) / 1 – disable (default) / enable Drift Tube data inputs to SP05 Core;
WPHI = 0 (default) / 1 – enable Wider Phi extrapolation;
HDL [1:0] = 0 (default), 1, 2, 3 – Halo Trigger Delay = additional latency of 0, 0, 1, 2
for Halo Triggers; applies to output 3 only;
− BXA [1:0] = 0, 1, 2 (default) – Bunch Crossing Analyzer history control.
1 of 3
January 22, 2010
Lev Uvarov
Table 4: CSR_SCC / SP Data Format for 080514 and later (but earlier than 090601) versions (Core Version
#1 with +4 bx latency)
D15
D14
X
X
0
0
Not Used
D13
D12
HDL1 HDL0
HDL1 HDL0
Halo Delay
D11
D10
X
X
0
1
Core Version
D9
D8
PRE1 PRE0
PRE1 PRE0
Pre-Trigger
D7
DTE
DTE
D6
D5
D4
X
Q2EN Q1EN
0
Q2EN Q1EN
Mode Control
D3
D2
X
X
0
0
Not Used
D1
D0 CYCL
BXA1 BXA0
W
BXA1 BXA0
R
BXA [1:0]
Here:
− X – Don’t care bit for;
− HDL [1:0] = 0 (default), 1, 2, 3 – Halo Trigger Delay = additional latency of 0, 0, 1, 2
for Halo Triggers; applies to output 3 only.
− PRE [1:0] = 1, 2 (default), 3 – Pre-Trigger control;
− DTE = 0 (default) / 1 – disable (default) / enable Drift Tube data inputs to SP05 Core;
− Q1EN = 0 (default) / 1 – disable (default) / enable processing stubs with Quality = 1;
− Q2EN = 0 (default) / 1 – disable (default) / enable processing stubs with Quality = 2;
− BXA [1:0] = 0, 1, 2 (default) – Bunch Crossing Analyzer history control.
Table 5: CSR_SCC / SP Data Format for 080408 and later (but earlier than 080514) versions (Core Version
#1 with +5 bx latency)
D15
X
0
D14
D13
X
X
0
0
Not Used
D12
X
0
D11
D10
X
X
0
1
Core Version
D9
D8
PRE1 PRE0
PRE1 PRE0
Pre-Trigger
D7
DTE
DTE
D6
D5
D4
X
Q4EN Q3EN
0
Q4EN Q3EN
Mode Control
D3
D2
X
X
0
0
Not Used
D1
D0 CYCL
BXA1 BXA0
W
BXA1 BXA0
R
BXA [1:0]
Here:
−
−
−
−
−
−
X – Don’t care bit;
PRE [1:0] = 1, 2 (default), 3 – Pre-Trigger control;
DTE = 0 (default) / 1 – disable (default) / enable Drift Tube data inputs to SP05 Core;
Q3EN = 0 (default) / 1 – disable (default) / enable processing stubs with Quality = 3;
Q4EN = 0 (default) / 1 – disable (default) / enable processing stubs with Quality = 4;
BXA [1:0] = 0, 1, 2 (default) – Bunch Crossing Analyzer history control.
Table 6: CSR_SCC / SP Data Format for earlier than 080514 versions (Core Version #0)
D15
X
0
D14
X
0
D13
X
0
D12
D11
X
X
0
0
Not Used
D10
X
0
D9
X
0
D8
DTE
DTE
D7
D6
X
X
0
0
Not Used
D5
D4
Q4EN Q3EN
Q4EN Q3EN
Mode Control
D3
X
0
D2
D1
X
X
0
0
Not Used
D0
BXE
BXE
BXA
CYCL
W
R
Here:
−
−
−
−
−
X – Don’t care bit;
DTE = 0 (default) / 1 – disable (default) / enable Drift Tube data inputs to SP05 Core;
Q3EN = 0 (default) / 1 – disable (default) / enable processing stubs with Quality = 3;
Q4EN = 0 (default) / 1 – disable (default) / enable processing stubs with Quality = 4;
BXE = 0 (default) / 1 – disable (default) / enable Bunch Crossing Analyzer (BXA).
2 of 3
January 22, 2010
Lev Uvarov
Data Register Group Update
DAT_HLC = 0x70 – Halo Track Counter
R: SP / [M1|M2|M3]
This read-only register is intended to monitor halo track rate for core outputs by counting the
number of tracks with Mode = 15. The counter control follows that of the DAT_VPC register: it
can be reset with either FC_ECRES command or ACT_LCR / VPR command.
An internal 42-bit binary counter is read out in a floating point format as VPM * 2VPP.
Table 7: DAT_HLC / SP Data Format for 100122 and later versions
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
HLM10 HLM9 HLM8 HLM7 HLM6 HLM5 HLM4 HLM3 HLM2 HLM1 HLM0 HLP4
Mantissa [10:0]
Here:
−
−
HLM [10:0] = 0…2047 - Mantissa;
HLP [4:0] = 0…31 – Power of 2.
3 of 3
D3
D2
D1
HLP3 HLP2 HLP1
Power [4:0]
D0 CYCL
HLP0
R