Status of the Level-1 CSC Trigger
D.Acosta
University of Florida
CMS Week, September 2000
1
Darin Acosta
Outline
It works!
Successful test this year of prototypes for all system
components
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Software works
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Perfect agreement between CSC Track-Finder and ORCA
Tuning of trigger primitives and PT assignment finalized
It’s compact
Current technology makes a one crate CSC Track-Finder
possible in the near future
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All this is going into the TDR
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Latest simulation plots shown
CMS Week, September 2000
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Darin Acosta
Tests of Current Prototypes
In preparation of the Level-1 TDR, all trigger
prototypes must be tested by end of September
è
è
è
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Sector Processor:
Sector Receiver:
Muon Port Card:
Clock and Control Board:
Channel-Link backplane:
UFlorida
UCLA
Rice
Rice
UFlorida
All boards were completed in July
Crate tests of the boards followed and are on-going
è
Have shifted from single board tests to integration tests
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Darin Acosta
Level-1 Trigger Architecture
From DT
Track-Finder
(Vienna)
12 Sector
Processors
MB1
DT TF
1 Muon Sorter
SP
ME4
OPTICAL
(Vienna)
ME2-ME3
To Global
Muon
Trigger
ME1
SR
Muon Port
Cards
PC
3µ / port card
(Rice)
MS
SP
36 Sector
Receivers
3µ / sector
(UCLA)
(Florida)
12 sectors
4µ
(Rice)
GMT
4µ
From DT
8µ
Track-Finder
RPC
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Darin Acosta
Muon Track-Finding
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è
è
è
è
CSC system divided into 12 sectors (6 per endcap)
Link trigger primitives into 3D tracks
Select best 3 tracks per sector
Assign pT, ϕ, and η using data from up to 3 stations
Send 4 highest quality candidates to Global L1
θ
ϕ
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Darin Acosta
Track-Finding Logic in Sector Processor
Extrapolation
Units
E1 – E2
Bunch
Crossing
Analyzer
From Backplane
BXA
EU1-2
Track
Assembler
Units
TAU1
Final
Sorter
EU1-3
EU2-3
TAU2
FSU
EU2-4
EU3-4
TAU3
Assignment
Unit
EU
MB1-2
AU
E2 – E4
FIFO
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MUX
Darin Acosta
To Front
panel
Sector Processor Prototype
Final Selection Unit
Extrapolation Units
XCV150BG352
XCV400BG560
12 layers
10K vias
17 FPGAs
12 SRAMs
25 buffers
Assignment Units Track Assemblers Bunch Crossing
256k x 16 SRAM
XCV50BG256 &
Analyzer
2M x 8 SRAM
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XCV50BG256
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Darin Acosta
Sector Receiver Prototype
Optical Receivers
and HP Glinks
SRAM LUTs
Front FPGAs
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Back FPGAs
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Darin Acosta
Port Card Prototype
Rice
Optical Receivers
and HP Glinks
Sorter FPGA
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Darin Acosta
Track-Finder Crate Test
SP SR CCB
Bit3
VME
Interface
Custom
backplane
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Darin Acosta
UF Test Software on Win95
JAVA GUI to call
command line programs
Should be portable to UNIX
Programs to load FPGAs and LUTs
through Bit3 VME interface
(JTAG runs at 25 MHz on board)
CMS Week, September 2000
Test software and subset of ORCA
simulation to compare hardware
and simulation results
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Darin Acosta
Test Results: Sector Processor
All logic works flawlessly with 100% agreement with
ORCA simulation
Single step mode and 40 MHz dynamic test mode
p FIFOs on input and output hold 256 events
è Each subprocessor separately verified (extrapolation,
track assembly, final sorting, PT assignment)
è Input was 180K single muon events, 60K triple muon
events, generated from CMSIM
è Usual bug fixes to software and firmware took place
p We improved the PT precision after construction!
è Same software used to validate tests is now in ORCA
simulation, and methods to generate hardware LUTs are
included in the package
è
Overall latency is 15 b.x. (w/o Channel-Link)
Dynamic tests of front logic determined that maximum
clock frequency is 63 MHz
è Therefore, already can reduce latency to 14 b.x.
è
CMS Week, September 2000
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Darin Acosta
Test Results: MPC & Sector Receiver
Muon Port Card:
Plug-in mezzanine card (with low profile connectors) for
sorter FPGA works
è Dynamic test of sorter logic with random input data works
è Optical communication to Sector Receiver verified by
oscilloscope, and dynamic test planned for this week
è
Sector Receiver:
Static and (recently) dynamic tests of FPGA and LUTs
verified using random input data
è Bugs in firmware and UCLA software had to be fixed
è Dynamic test from the back of one SR (through
ChannelLink backplane) to SP verified with UF software in
August
è
Dynamic test of complete system (MPC+SR+SP)
scheduled for mid-October
Merge of UF, UCLA, Rice test software on-going
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Darin Acosta
Lessons from Construction & Tests
It is possible to work with ball-grid arrays (BGAs)
on large 9U VME boards
It is possible to remove and replace BGAs
è
è
SR and SP had chips replaced (FPGA and buffers)
Some difficulty with fine pitch BGA (0.8mm)
Not all board assembly companies are equal!
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Had to switch companies for re-working of boards
National Channel Link chips fail when connected to
Xilinx Virtex I/O pins
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è
è
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Sector Receiver had many chips die
Probably related to over/undershoot
Slow risetime configuration of Virtex I/O pin is okay
Connection to buffer chips is okay
TI Channel-Link chips may be more tolerant
CMS Week, September 2000
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Darin Acosta
Future: A Compact Muon Trigger
Current technology will allow us to merge all 17
FPGAs of prototype Sector Processor into just one:
è
è
Xilinx Virtex XCV2000E (~2.5M gates) available now
or Virtex 2, available soon
This opens the possibility of merging the Sector
Processor and Sector Receivers onto a single board
Would allow for a single crate Track-Finder (currently 6)
è Reduces latency
è No Channel-Link connection between SR and SP
è No cable to Muon Sorter
è Would allow communication between sectors (through
backplane) to cancel ghost tracks at boundaries
è Under investigation by Florida
è
Depends on new optical link technology to reduce
connections from peripheral crate
è
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1.6 Gbit links with 80 MHz clock
Under investigation by Rice
CMS Week, September 2000
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Darin Acosta
Optical Connection for MPC→SR/SP
MPC
Optical modules
1.6 Gbits/s
Transceiver:
Lucent 1417K4A
Or
Infineon
V23818-N15-L17
FPGA
120
@40MHz
FRONT
FPGA
40Bits
@80MHz
40Bits
@80MHz
Data
Compression
(factor 3)
SR/SP
120
@40MHz
Data
Decompression
(factor 3)
SER/DES Chips
TLK2501
From
Texas Instruments
• Completely tested by Texas Instruments
(optical modules + ser/des chips only)
• 15 connections per SR/SP module (3 connections x 5 MPC)
• Low power consumption:
2.2W MPC (3 links)
11W SR/SP (15 links)
• Latency ~ 0.5Bx for Tx and 1.5Bx for Rx
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Darin Acosta
Possible Board Layout
Preliminary layout of SR/SP module (2.5Gb/s link option)
Small Form
Factor
Transceivers
Deserializer
Chips
Front
FPGAs
Memory
Look-up
Tables
From MPC
(chamber 4)
VME
Interface
Sector
Processor
FPGA
chip
From MPC
(chamber 3)
From Clock
and Control
Board
From MPC
(chamber 2)
To Muon
Sorter
From MPC
(chamber
1B)
Ptassignment
LUTs
From MPC
(chamber 1A)
From / To
Barrel
•
•
•
•
•
CMS Week, September 2000
Low power consumption: ~ 38.5W per 9U VME card
Latency: ~ 15Bx
SP structure is fully programmable
Cost reduction: 1 SR/SP module instead of 3 SR and 1 SP
1 SR/SP module per 60° sector
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Darin Acosta
Possible Crate Layout
SR SR SR SR SR SR
/ / / / / /
SP SP SP SP SP SP
CCB/MS
CCB/MS Card
(CCB +
Muon Sorter)
BIT3 Controller
Track-Finder crate (1.6 Gbits/s optical links)
SR SR SR SR SR SR
/ / / / / /
SP SP SP SP SP SP
SR/SP Card
(3 Sector Receivers +
Sector Processor)
(60° sector)
From MPC
(chamber 4)
From MPC
(chamber 3)
From
TTC
From MPC
(chamber 2)
From MPC
(chamber 1B)
To
Global Trigger
From MPC
(chamber 1A)
From / To
Barrel
•
•
•
•
Total latency: ~ 20Bx (from input of SR/SP card to output of CCB/MS card)
Power consumption: ~ 500W per crate
17 optical connections per SR/SP card (15 - from endcap, 2 – from/to barrel)
Custom backplane for SR/SPs < > CCB/MS connection
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Darin Acosta
Possible Latency Savings
Description
Bx
Description
Bx
SR optical receiving and
synchronization
SR Front FPGAs and Lookups
2
2
2
SR/SP optical receiving and
synchronization
SR/SP Front FPGAs and Lookups
SR to SP Channel Link
transmission over short backplane
SP processing
4
-
-
3
15
SP processing
10
SP to Muon Sorter transmission
over 5m cable
Muon Sorter processing
2.5
SP to Muon Sorter transmission
over short backplane
Muon Sorter processing
2
Muon Sorter to GMT transmission
over 11m cable
3.5
5
Muon Sorter to GMT transmission
over 11m cable
Total 34
3.5
Total 23.5
Prototype 1 (current)
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Prototype 2 (merged)
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Darin Acosta
Future Plans: Backplane
Recently discovered that Channel Link chips have
unacceptably long latency (~3.5 clocks)
è
è
Rice, UCLA, UF have verified this
e.g. SR → SP test had 4 clock delay
Need a replacement technology ASAP for peripheral
crate and Track-Finder crate backplanes
è
Or run Channel Link at 80 MHz as Bristol group?
Florida proposal is to use GTLP at 80 MHz
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è
è
è
Doubled frequency achieves 2× signal reduction
(vs. 3× from Channel-Link)
Can be bussed.
No differential signals (fewer traces)
Can be driven by Virtex I/O directly,
or buffers by Fairchild and TI
Prototype backplane will be tested in the next 2
months by Florida
CMS Week, September 2000
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Darin Acosta
ALCT2000-384 Prototype (UCLA)
Algorithm:
Wire
group
number
Efficiency:
n+2
n+1
n
n-1
n-2
99.9
99.85
99.8
99.75
99.7
abcdef
layer
99.65
99.6
99.55
99.5
99.45
ALCT99 Efficiency
ME1/a
ME1/1
ME1/2
ME1/3
ME2/1
ME3/1
ME4/1
ME2/2
ME3/2
ME4/2
Channel-Links to SCSI
output connectors
Circuit
board:
Concentrator FPGA
96-ch ALCT FPGAs
Delay/ buffer ASICs
Input
connectors
Analog section: Pulser, AFEB
power and control
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Darin Acosta
ALCT2000 Tests
Feb production
Bench testing done by end of March, internal test muon patterns
Tested on chamber since end of April
ALCT2000-384
under test
CMS Week, September 2000
Test pattern
injector and checker
(CLCT99-mod)
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Muon patterns
found & verified
Darin Acosta
State of the Simulation
CSC Track-Finder hardware and software agree
perfectly, so what’s the problem?
Many “knobs” to tune in the trigger
PT assignment ⇒ affects PT resolution
Trigger cuts ⇒ affect efficiency
Moreover, the Track-Finder is only as good as its
input
Good PT resolution in the endcap requires positions
calculated to ~1mm from L1 trigger primitives
Any systematic offset in φ that is different from station
to station induces an offset in ∆φ
A systematic increase in ∆φ causes PT to be reconstructed
too low, a systematic decrease causes PT to be too high
Causes an asymmetry between µ+ and µ-
CMS Week, September 2000
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Darin Acosta
Improvements to Track-Finder
PT assignment has been re-tuned on CMSIM118 and
parameterized by a set of functions
This offers flexibility:
PT binning may be changed
50% or 90% thresholds (or anything else) can be used
Look-up table contents are still based on integers like
hardware
Contents computed dynamically
Precision of input data to PT LUT was increased even
after Sector Processor prototype was built
Slight design change was possible
May be able to increase precision even more in future HW
prototypes using more SRAM
All SW and HW algorithms tested and agree!
Modifications made to ORCA to match prototype exactly,
and all LUTs used by HW generated from ORCA code
CMS Week, September 2000
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Darin Acosta
Improvements to Trigger Primitives
Several offsets to φ positions found and fixed:
Local offsets between reported track segment and hits
~0.5 mrad shift because left of bin (not center of bin)
was being reported
Global offsets from sector boundary between station 1
and stations 2—4
~1.5 mrad shift because chambers are aligned 2.5
strips into active area (because of chamber overlap)
Time offsets discovered in BX assignment which give
artificially low track segment efficiency
Need to “time-in” the software!
Should have timing simulation to better match true
performance of trigger primitives
This still needs to be fixed
CMS Week, September 2000
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Darin Acosta
Benchmark Performance
L1 PT resolution is not 20%
for 100 GeV muons in the
endcap! Would need 100µ
µm
position resolution.
3-station PT measurement
is 20% only for PT<10 GeV
σ( 1/Ptrec - 1/Ptgen )/( 1/Ptgen )
Don’t expect miracles!
1
0.9
Pt = 5 GeV
Pt = 50 GeV
Pt = 10 GeV
Pt = 100 GeV
0.8
0.7
ME1/3
ME1/2
ME1/1
MB1
0.6
0.5
0.4
0.3
0.2
But, the L1 rate does not
come from poorly
measured 100 GeV muons,
but from poorly measured
3 GeV ones!
CMS Week, September 2000
0.1
MB1 / ME1 / ME2
0
0.8
1
1.2
1.4
1.6
1.8
2
2.2
CMS IN 1999/026
CMSIM based study
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Darin Acosta
2.4
ηrec
Summary
Prototypes of all CSC L1 Trigger components
constructed and tested (except CSC Sorter)
First feasible Track-Finder design built and working
Another round of prototypes are expected in order
to reduce overall latency
Might have a single crate Track-Finder solution
Target date is mid-2002
Production to start mid-2003
ORCA simulation being tuned
No insurmountable problems anticipated to get a
reasonable simulation of CSC performance
CMS Week, September 2000
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Darin Acosta