Status of the Track-Finder
D.Acosta
University of Florida
HW Tests
Future Plans
EMU Meeting, Spetember 2000
1
Darin Acosta
Tests of Current Prototypes
In preparation of the Level-1 TDR, all trigger
prototypes must be tested by end of September
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Sector Processor:
Sector Receiver:
Muon Port Card:
Clock and Control Board:
ChannelLink backplane:
UFlorida
UCLA
Rice
Rice
UFlorida
All boards were completed in July
Crate tests of the boards (the TriDAS “testbeam”)
followed and are still on-going
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Have shifted from single board tests to integration tests
EMU Meeting, Spetember 2000
2
Darin Acosta
Level-1 Trigger Architecture
From DT
Track-Finder
(Vienna)
12 Sector
Processors
MB1
DT TF
1 Muon Sorter
SP
ME4
OPTICAL
(Vienna)
ME2-ME3
To Global
Muon
Trigger
ME1
SR
Muon Port
Cards
PC
3µ / port card
(Rice)
MS
SP
36 Sector
Receivers
3µ / sector
(UCLA)
(Florida)
12 sectors
4µ
(Rice)
GMT
4µ
From DT
8µ
Track-Finder
RPC
EMU Meeting, Spetember 2000
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Darin Acosta
Muon Track-Finding
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CSC system divided into 12 sectors (6 per endcap)
Link trigger primitives into 3D tracks
Select best 3 tracks per sector
Assign pT, ϕ, and η using data from up to 3 stations
Send 4 highest quality candidates to Global L1
θ
ϕ
EMU Meeting, Spetember 2000
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Darin Acosta
Track-Finding Logic in Sector Processor
Extrapolation
Units
E1 – E2
Bunch
Crossing
Analyzer
From Backplane
BXA
EU1-2
Track
Assembler
Units
TAU1
Final
Sorter
EU1-3
EU2-3
TAU2
FSU
EU2-4
EU3-4
TAU3
Assignment
Unit
EU
MB1-2
AU
E2 – E4
FIFO
EMU Meeting, Spetember 2000
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MUX
Darin Acosta
To Front
panel
Sector Processor Prototype
Final Selection Unit
Extrapolation Units
XCV150BG352
XCV400BG560
12 layers
10K vias
Assignment Units Track Assemblers Bunch Crossing
256k x 16 SRAM
XCV50BG256 &
Analyzer
2M x 8 SRAM
EMU Meeting, Spetember 2000
XCV50BG256
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Darin Acosta
Sector Receiver Prototype
Optical Receivers
and HP Glinks
SRAM LUTs
Front FPGAs
EMU Meeting, Spetember 2000
Back FPGAs
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Darin Acosta
Track-Finder Crate Test
SP SR CCB
Bit3
VME
Interface
Custom
backplane
EMU Meeting, Spetember 2000
8
Darin Acosta
UF Test Software on Win95
JAVA GUI to call
command line programs
Should be portable to UNIX
programs to load FPGAs and LUTs
through Bit3 VME interface
(JTAG runs at 25 MHz on board)
EMU Meeting, Spetember 2000
Test software and subset of ORCA
simulation to compare hardware
and simulation results
9
Darin Acosta
Test Results: Sector Processor
Front half of logic (Extrapolation, Track Assembly)
works flawlessly with 100% agreement with ORCA
simulation
180K single muon events, 60K triple muon events,
generated from CMSIM
è Usual bug fixes to software and firmware took place
è
Dynamic tests of front logic determined that
maximum clock frequency is 63 MHz
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FIFOs on input and output hold 256 events
Back half of logic is currently under test
Sorter logic and PT assignment seem to be working
correctly – a few discrepancies under investigation
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Overall latency is 15 b.x. (w/o ChannelLink)
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Already can reduce to 14 b.x.
EMU Meeting, Spetember 2000
10
Darin Acosta
Test Results: MPC & Sector Receiver
Muon Port Card:
Plug-in mezzanine card (with low profile connectors) for
sorter FPGA works
è Basic sorter logic verified
è Optical communication to Sector Receiver verified
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Sector Receiver:
Static tests of FPGA and LUTs verified
è Dynamic test from Back FPGAs of one SR (through
ChannelLink backplane) to SP verified with UF software
è Dynamic test of SR logic still on-going using UCLA
software
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Dynamic test of complete system planned
Merge of UF and UCLA software required
EMU Meeting, Spetember 2000
11
Darin Acosta
Lessons from Construction & Tests
It is possible to work with ball-grid arrays (BGAs)
on large 9U VME boards
It is possible to remove and replace BGAs
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SR and SP each had one chip replaced
Not all board assembly companies are equal!
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Conquest in Orlando is out
Bat PC in San Jose is in
Channel Link chips fail when connected to Xilinx
Virtex I/O pins
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Sector Receiver had many chips die
Probably related to over/undershoot
Slow risetime configuration of Virtex I/O pin is okay
Connection to buffer chips is okay
And… opinions on software outweighed all opinions on
hardware!
EMU Meeting, Spetember 2000
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Darin Acosta
Future Plans: SR/SP
Current technology will allow us to merge all 17
FPGAs of prototype Sector Processor into just one:
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Xilinx Virtex XCV2000E (~2.5M gates) available now
or Virtex 2, available soon
This opens the possibility of merging the Sector
Processor and Sector Receivers onto a single board
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Would allow for a single crate Track-Finder (currently 6)
Reduces latency
No Channel Link connection between SR and SP
No cable to Muon Sorter
Depends on new optical link technology to reduce
connections from peripheral crate
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2.5 Gbit links or parallel optical cables
EMU Meeting, Spetember 2000
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Darin Acosta
Optical Solution 1
MPC
Optical modules
2.5Gbits/s
Transceiver:
Lucent 1417K4A
Or
Infineon
V23818-N15-L17
FPGA
FRONT
FPGA
40Bits
@120MHz
40Bits
@120MHz
Data
Compression
(factor 3)
SR/SP
120
@40MHz
Data
Decompression
(factor 3)
SER/DES Chips
TLK2501
From
Texas Instruments
• 1 Optical Connection per each track segment
• Completely tested by Texas Instruments
(optical modules + ser/des chips only)
• 15 connections per SR/SP module (3 connections x 5 MPC)
• Low power consumption:
2.2W MPC (3 links)
11W SR/SP (15 links)
• Latency ~ 0.5Bx for Tx and 1.5Bx for Rx
EMU Meeting, Spetember 2000
14
Darin Acosta
Optical Solution 2
12-channel optical link
up to 1.6Gbits/s
per channel
MPC
Infineon
V23814/15-U1306
Transmitter
Receiver
FPGA
FRONT
FPGA
40Bits
@120MHz
40Bits
@120MHz
Data
Compression
(factor 3)
SR/SP
SER/DES Chips
4-channel
Motorola MC92600
Or
8-channel
PMC-Sierra PM8351
120
@40MHz
Data
Decompression
(factor 3)
• 1 Optical Connection per each MPC
• 5 connections per SR/SP module (1 connection x 5 MPC)
• Low power consumption:
2W MPC (1 link) and 9W SR/SP (5 links)
• Latency ~ 1Bx for Tx and 2Bx for Rx
• LVDS to PECL conversion must be tested
EMU Meeting, Spetember 2000
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Darin Acosta
Possible Board Layout
Preliminary layout of SR/SP module (2.5Gb/s link option)
Small Form
Factor
Transceivers
Deserializer
Chips
Front
FPGAs
Memory
Look-up
Tables
From MPC
(chamber 4)
VME
Interface
Sector
Processor
FPGA
chip
From MPC
(chamber 3)
From Clock
and Control
Board
From MPC
(chamber 2)
To Muon
Sorter
From MPC
(chamber
1B)
Ptassignment
LUTs
From MPC
(chamber 1A)
From / To
Barrel
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•
•
•
•
Low power consumption: ~ 38.5W per 9U VME card
Latency: ~ 15Bx
SP structure is fully programmable
Cost reduction: 1 SR/SP module instead of 3 SR and 1 SP
1 SR/SP module per 60° sector
EMU Meeting, Spetember 2000
16
Darin Acosta
Possible Crate Layout
Track-Finder crate (2.5Gbits/s optical links)
SR SR SR SR SR SR
/ / / / / /
SP SP SP SP SP SP
CCB/MS
(CCB +
Muon Sorter)
BIT3 Controller
CCB/MS Card
SR SR SR SR SR SR
/ / / / / /
SP SP SP SP SP SP
SR/SP Card
(3 Sector Receivers +
Sector Processor)
(60° sector)
From MPC
(chamber 4)
From MPC
(chamber 3)
From
From MPC
(chamber 2)
TTC
From MPC
(chamber 1B)
To
From MPC
(chamber 1A)
Global Trigger
From / To
Barrel
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Total latency: ~ 20Bx (from input of SR/SP card to output of CCB/MS card)
Power consumption: ~ 500W per crate
17 optical connections per SR/SP card (15 - from endcap, 2 – from/to barrel)
Custom backplane for SR/SPs < > CCB/MS connection
EMU Meeting, Spetember 2000
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Darin Acosta
Possible Latency Savings
Description
Bx
Description
Bx
SR optical receiving and
synchronization
SR Front FPGAs and Lookups
2
2
2
SR/SP optical receiving and
synchronization
SR/SP Front FPGAs and Lookups
SR to SP Channel Link
transmission over short backplane
SP processing
4
-
-
3
15
SP processing
10
SP to Muon Sorter transmission
over 5m cable
Muon Sorter processing
2.5
SP to Muon Sorter transmission
over short backplane
Muon Sorter processing
2
Muon Sorter to GMT transmission
over 11m cable
3.5
5
Muon Sorter to GMT transmission
over 11m cable
Total 34
3.5
Total 23.5
Prototype 1 (current)
EMU Meeting, Spetember 2000
3
Prototype 2 (merged)
18
Darin Acosta
Future Plans: Backplane
Recently discovered that Channel Link chips have
unacceptably long latency (~3.5 clocks)
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Rice, UCLA, UF have verified this
e.g. SR → SP test had 4 clock delay
Need a replacement technology ASAP for peripheral
crate and Track-Finder crate backplanes
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Or run Channel Link at 80 MHz as Bristol group?
UF proposal (Madorsky) is to use GTLP at 80 MHz
Doubled frequency achieves 2× signal reduction (vs. 3×
from ChannelLink)
è Can be bussed.
è No differential signals (fewer traces)
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Prototype backplane will be tested in the next 3
months
EMU Meeting, Spetember 2000
19
Darin Acosta