LECTURE SUPPLEMENT #02
Two Port And Basic
Amplifier Networks
Dr. John Choma
Professor of Electrical Engineering
University of Southern California
Ming Hsieh Department of Electrical Engineering
University Park: Mail Code: 0271
Los Angeles, California 90089–0271
213–740–4692 [USC Office]
213–740–8677 [USC Fax]
818–384–1552 [Cell]
johnc@usc.edu
PRELUDE:
In this first chapter, we introduce the four fundamental architectures of analog linear signal
processing; namely, the transconductance amplifier, the voltage amplifier, the current amplifier,
and the transresistance amplifier. In their idealized realizations, these four basic building blocks
of analog electronics behave electrically and respectively as a voltage controlled current source,
a voltage controlled voltage source, a current controlled current source, and a current controlled
voltage source. You undoubtedly grappled with these so-called dependent sources in your first
course on linear circuits and were probably puzzled -at least initially- by their intended purpose
in circuit technology. In this chapter, you will learn that these dependent generators are
indispensable branch element tools for first order modeling of analog electronic circuits. Using
these idealized dependent voltage and current generators, we shall develop general modeling
strategies and mathematical techniques for analyzing analog electronic networks that contain
one or more of the aforementioned four fundamental cells. We shall then couch these analyses in
forms that encourage a realistic and meaningful assessment of network properties and
characteristics. In the process of this development, we expose the student to several of the
performance metrics that commonly bracket the performance of analog circuits.
August 2009/January 2011
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
1.1.0. INTRODUCTION
As we launch our foray into the world of electronic circuit design, you should be mindful of a few basic principles and facts. The first of these principles is that circuit design, and
especially the design of analog circuits, which process applied input voltages or currents as a
continuous function of time, is rarely perceived as a standalone discipline. Instead, it is a discipline sculpted to support system technologies. Commercial, military, and space sciences
consumers do not buy circuits. Instead, these consumers purchase and exploit electronic systems
whose desired input to output (I/O) functionality is determined by the manner in which the circuits that are embedded within each subsystem of these systems are designed, manufactured, and
interconnected. The upshot of this basic fact is that circuit design cannot be meaningfully
accomplished without awareness and at least a basic understanding of the operation of the system
for which the design venture is targeted. Thus, for example, an amplifier required of a cell telephone is designed differently than is an apparently similar amplifier destined for use in a medical
monitoring device.
The second fact underpinning the task of realizing an electronic circuit is that analog
design is challenging because it does not mirror the straightforward problem of solving for the n
unknown variables in a system whose characteristics are mathematically defined by n independent equations. Two circumstances complicate this issue. The first is that our ability to write n
independent mathematical equations for a circuit presumes that we know a priori the actual circuit deemed suitable for the design venture at hand. But design entails, virtually as the first step
subsequent to system definition, the ability to stipulate candidate circuit topologies that we feel
can satisfy the I/O performance objectives of a subsystem within the system whose practical
realization is the fundamental engineering objective. For example, amplification of the applied
input signal may be required of a specific block within the considered system. But what kind of
amplifier shall we use? To answer this question, we must investigate if the input terminals of the
amplifier are driven by a high impedance current source or a low impedance voltage source, and
we must learn if the amplifier is to drive a low or a high impedance load. We must also be aware
of the maximum and minimum amplitudes anticipated of the input signal, for this information
assists us with respect to achieving a suitable range of I/O linearity that is consistent with the
power dissipation budget allotted to the circuit charged to our responsibility. Another piece of
information we need in order to solve the design puzzle relates to the frequency spectrum implicit to the information associated with the applied input signal. Do the frequencies associated
with the input signal lie within a narrow band centered about a single, so-called carrier, frequency or are these frequencies dispersed over a broad passband? These and other questions
must be resolved before we can choose the type of amplifier topology that should be exploited
and the specific design constraints we must invoke on the selected amplifier.
Upon resolving the circuit topology appropriate to the design task, the most typical design problem we will encounter is the quandary of having more specifications that must be satisfied or more variables that need to be determined than there are independent equations that can
be written. Our ninth grade algebra teacher taught us that an algebraic problem for which the
number of unknowns does not equal the number of available independent equations has no
unique solution. You might therefore blame your algebra instructors for the simple fact that
unique design solutions are rare and indeed, many solutions are generally possible. Although we
naturally view this non-uniqueness of design solutions as exasperating, it offers us a singular
opportunity to demonstrate our engineering creativity with respect to identifying optimal solutions for the application that confronts us. The best of these viable design solutions, in the sense
Ming Hsieh Department of Electrical Engineering
- 90 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
of developing reliable electronic networks that can be manufactured cost-effectively to meet target specifications, are rarely forged by trial and error design strategies. Instead, optimal designs
derive from the fruits of fundamental phenomenological understanding. The task that necessarily precedes our understanding of electronic engineering complexities is the conduct of thorough
and physically understandable mathematical analyses, likely supported by computer-based
simulations, which insightfully highlight both the attributes and the limitations of the alternative
circuit architectures we have identified. This insightful understanding is promoted by analytical
disclosures −often premised on arguably reasonable approximations− that we can interpret creatively and explain lucidly in terms of known physical laws, basic circuit and system concepts,
and tractable mathematics. We are therefore moved to suspect that in a design environment,
computational precision is not the core objective of circuit analyses. A realistically approximated result yielding design insights has far more design value than does an exact solution
whose complicated nature obscures an insightful understanding of circuit dynamics. Stated succinctly, we are not paid the big bucks merely to extol algebraic elegance or other forms of
mathematical acumen. Rather, we are paid to deliver expert opinions of competing circuit
architectures and consistent design excellence. In view of this fundamental fact of engineering
life, we can argue that the engineering design task does not end when we formulate mathematical
predilections of circuit responses. In a sense, our design task commences with the mathematical
delineation of these responses, for we are then challenged to couch our solutions into forms that
insightfully illuminate circuit attributes, as well as shortfalls, thereby enabling the prospects of
rendering intelligent and creative design solutions.
Modern electronic systems, such as cellular telephones, MP3 players, medical monitoring devices, and global positioning satellite (GPS) navigation equipment, are comprised of suitably interconnected mixed signal integrated circuit chips. Mixed signal circuits are integrated circuits whose operation simultaneously exploits analog and digital signal processing. Digital circuits dominate the commercial, military, and spacecraft electronic system landscape because
they offer flexible functionality at reasonable power dissipation levels. Although operating
flexibility and associated programmable versatility may require digital cells containing thousands, if not millions, of transistors, modern semiconductor device technologies operating at low
power levels allow for the realization of these cells within impressively small integrated circuit
surface areas. But analog, or continuous time, circuits, whose necessity is absolute because of
the analog nature of the practical world in which electronic systems communicate, arguably consume the most design time despite the fact that they utilize far fewer active devices than do their
digital counterparts. One reason for this disproportionate level of design effort is the increased
system functionality and operating performance continually demanded by consumers. These demands predispose design challenges in that analog networks utilized at the input front end of a
system must process input signals with widely divergent amplitudes, frequencies, and other key
metrics. A similar statement can be proffered for the analog circuits used at the output system
port. A second reason underlying significant analog design time is that unlike digital technologies, analog technologies have yet to gravitate to a standard cell design methodology. We shall
learn that the broad diversity of decisions that must commonly be made in an analog circuit design exercise contributes to this lack of a standard cell methodology. While the venerable operational amplifier, or op-amp, is a notable standard cell exception in analog circuit technology, the
operational utility of most op-amps is largely limited to relatively low signal frequencies. Unlike
the gates, read only memories, random access memories and other switching circuits pervasive
of digital design initiatives, we are therefore compelled to live with the fact that there are no
standard analog cells and associated design rules for radio frequency amplifiers, impedance
Ming Hsieh Department of Electrical Engineering
- 91 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
converters, oscillators, filters, and other high performance analog electronic modules. The good
news about the lack of standard cells is that electrical engineers who master analog design skills
are not likely to be replaced by computers and relevant design software. Accordingly, analog
designers are in constant industrial demand even when recessions plague general business economies.
As we suggested in the Prelude to this chapter, most of the amplification circuits and all
of the linear analog electronic networks deployed in electronic systems are made up of four
fundamental architectures. The most commonly encountered of these four fundamental circuit
types is the transconductance amplifier, or more generically, the transadmittance amplifier,
which emulates an ideal voltage controlled current source, or “gmV generator,” in the vernacular
of electrical engineering shop talk. The three other basic circuits are the voltage amplifier, which
ideally behaves as a voltage controlled voltage source, the current amplifier, which approximates
a current controlled current source, and the transresistance, or transimpedance, amplifier, which
emulates a current controlled voltage source. For example and subject to the constraint of low
signal frequency processing, the op-amp is an excellent approximation of an ideal voltage controlled voltage source. In this first chapter, we focus on the idealized and practical characteristics of these four fundamental electronic configurations. We launch the investigation of general
amplifier configurations by developing two port network theories as a means of studying the
behavior of these amplifier modules and other linear circuits in terms of only the volt-ampere
characteristics observable at their extrinsic terminals.
1.2.0. LINEAR TWO PORT NETWORKS
We generally desire the output current or voltage response of an amplifier to be linearly
related to the applied input voltage or current. When I/O linearity prevails, we are assured that
the frequency spectrum of the output voltage or current response replicates the frequency content
of the applied input signal. This assurance stems from the fact that neither a linear system nor a
linear circuit is capable of producing output frequencies that differ from those implicit to the input excitation. In other words, the output response of a linear system or circuit to an input signal
can be only an amplitude-scaled and invariably time delayed version of the applied input. The
delay to which we refer and about which we shall have far more to say later derives from the
simple fact that a physically realizable network presents unavoidable electrical baggage in the
form of energy storage elements (parasitic capacitances and/or inductances). Since capacitances
cannot respond instantaneously to applied voltages and inductances are incapable of processing
currents instantly, a network requires time to respond to and process input signal excitations.
But the core concept you should take home here is that after all transients manifested by the sudden application of an input signal have subsided, which typifies so-called steady state operation,
the frequency content of the output response of a linear network is identical to the observed frequency spectrum of its input. Thus, a linear amplifier does not distort the input signal in the
sense of creating an output frequency spectrum that differs from that of the input signal. In a stereo system, for example, linearity is a crucial design objective for we wish to hear only that
information that is burned on the compact disk we are playing. We do not wish the stereo system to generate any frequencies on its own for to do so amounts to contaminating the input signal and the information we ultimately wish to hear. Wouldn’t you be annoyed if your stereo
made Mick Jagger sound like Frank Sinatra?
Ming Hsieh Department of Electrical Engineering
- 92 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
Vaa
Unfortunately, we shall learn that achieving I/O linearity in electronic circuits is a
challenging undertaking because the transistors embedded within each of the four basic amplifier
blocks have a propensity toward delivering inherently nonlinear volt-ampere, or V-I, characteristics. We know from basic circuit theory that it takes only one nonlinear branch element in a circuit that is otherwise comprised of linear branch elements to render an I/O response nonlinear.
Accordingly, strictly linear I/O relationships can never be guaranteed in practical amplifiers. But
electronic circuits earmarked for linear signal processing applications can be conditioned to deliver approximately linear I/O transfer and impedance characteristics through the implementation
of appropriate biasing. The key to this requisite biasing is the availability of one or more network ports, or pair of terminals to which static voltages are applied to force nominally linear
operation for at least a suitably constrained range of input signal amplitudes. These biasing
terminals may or may not be coincident with the signal input and signal output ports. Later in
our travels, we shall deal with the design of electronic network biasing modules that ensure
nominally linear operation of all nonlinear elements embedded within the network so that linear
I/O signal processing can be emulated satisfactorily.
+
+
vi(t)
−
vs(t)
−
2
Vbb
+
Vaa
Zl
4
ibb(t)
(a).
+
IoQ
Electronic
Network
2
+
vo(t)
−
Electronic
Network
−
+
ViQ
−
io(t) 3
−
Zs
IaaQ
1 IiQ
−
Zs
+
iaa(t)
1 ii(t)
IbbQ
3
+
VoQ
−
+
Zl
vs(t)
−
4
Zs
1 iis(t)
+
vis(t)
−
2
Zin
iaas(t)
ios(t) 3
Linear Model
Of Electronic
Network
ibbs(t)
+
vos(t)
−
Zl
4
Zout
−
Vbb
+
(b).
(c).
Figure (1.1). (a). A general electronic network whose input signal port is formed of terminal pair [1-2] and whose
output load port is established by terminal pair [3-4]. An additional pair of ports, to which static
voltages Vaa and Vbb are respectively applied, is provided for biasing purposes. (b). The network in
(a), with the input signal source set to zero. The two power supply voltages, Vaa and Vbb, establish
the quiescent operating conditions for the network. (c). The linear model of the network in (a),
assuming that the power supply voltages, Vaa and Vbb, manifest I/O linearity with respect to the applied input signal, vs(t). With the power supply voltages short circuited to ground, the input signal
voltage, vs(t), is applied to forge signal-induced perturbations in the quiescent voltages and currents
of all ports. The metrics, Zin and Zout, respectively symbolize the input and output impedances under
actual load and source termination conditions.
In the electronic network abstraction of Figure (1.1a), the biasing to which the preceding paragraph speaks is implemented by the two indicated power supply voltages, Vaa and Vbb,
which conduct currents iaa(t) and ibb(t), respectively. In other network embodiments, we may
Ming Hsieh Department of Electrical Engineering
- 93 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
find that only one of these two supply voltages, which are often realized as simple batteries, is
required. The static voltage sources are presumed ideal so that their Thévenin impedances,
which are not shown in the diagram, are zero. A signal voltage, vs(t), whose Thévenin impedance is Zs and whose average value is zero, is applied across the network input port formed of
terminal pair [1-2]. In response to these applied signal and biasing voltages, an output voltage,
vo(t), is established across load impedance Zl, which terminates the output port comprised of
terminal pair [3-4]. Corresponding to this output port voltage, current io(t) is conducted by the
load impedance.
All responses of unconditionally stable electronic networks are time variant if we presume that the input signal varies with time. But after the transients associated with switching on
the power supply voltages have died, as they ultimately will in stable networks, the resultant
steady state responses to the two indicated biasing voltages are constant voltages and currents
that collectively define the standby or quiescent operating conditions of the network. In other
words, these constant voltages and currents are the electrical responses we observe as we hang
out waiting for the input signal to be applied. Since we presume an input signal having zero
average value, vs(t) contributes nothing to the quiescent state of the network. Thus, when signal
vs(t) is null, which leaves static excitations Vaa and Vbb as the lone energy sources applied to the
considered network, the resultant I/O port voltages and currents are their quiescent values, ViQ,
VoQ, IiQ, and IoQ. As we indicate in Figure (1.1b), the power supply currents assume their respective standby values, IaaQ and IbbQ, which combine to deliver a static network power dissipation of
(VaaIaaQ + VbbIbbQ). The numerical values of these standby variables depend, not only on supply
voltages Vaa and Vbb, but also on relevant parameters implicit to the invariably nonlinear static VI characteristics of the active devices we use within the network. The nonlinear nature pervading
the interrelationships of these static variables demands that we determine their values through
prudently combining approximate nonlinear manual analyses with thoughtfully executed circuit
simulations.
With Vaa and Vbb sustained at their required biasing levels, we can rationalize that the
impact of an applied input signal, vs(t), is a time domain change in the quiescent values of all
branch currents and node voltages that are manifested in the network prior to the application of
vs(t). A necessary condition underpinning approximate I/O signal response linearity is that we
implement network biasing in such a way that the quiescent, or Q-point, values of all network
branch currents and node voltages forged with vs(t) = 0 be made independent of all signalinduced changes incurred by nonzero vs(t). If we are successful in this endeavor, we can lean on
classic superposition theory to determine the signal-induced components of all network responses. In particular, we can deduce the numerical values of all quiescent branch variables by
analyzing the considered network under the standby condition of vs(t) = 0. Because the quiescent variables of active devices are nonlinearly intertwined, this exercise invariably entails a
nonlinear analysis for which first order manual computations need to be supported and confirmed by computer-aided simulations that exploit accurate models of the transistors we choose
to utilize. Upon discerning all quiescent branch variables in the circuit, we can then mathematically examine the effects of the signal voltage by setting the power supply voltages to zero. If
linearity indeed prevails because of our clever biasing strategy, the nature of this secondary
analysis should entail an exclusively linear circuit investigation. A subtle implication of this second computational step is that the circuit transistors, which are inherently nonlinear beasts, must
be supplanted by suitable linear equivalent circuits, or linear models, that ensure a realistic
superposition strategy.
Ming Hsieh Department of Electrical Engineering
- 94 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
We can expand on the preceding discourse by noting that if the quiescent voltages and
currents of the considered network are independent of the responses produced by the signal, vs(t),
applied to the network input port, the variables indicated in Figure (1.1a) can be expressed in
terms of those delineated in Figures (1.1b) and (1.1c) in accordance with
vo (t) = VoQ + vos (t)
,
(1-1)
io (t) = I oQ + ios (t)
vi (t) = ViQ + vis (t)
ii (t) = IiQ + iis (t)
,
(1-2)
and
iaa (t) = I aaQ + iaas (t)
ibb (t) = I bbQ + ibbs (t)
.
(1-3)
In the preceding three disclosures, the appended subscript, “s,” signifies a voltage or current signal change incurred about a corresponding quiescent current or voltage as an exclusive result of
the signal source that energizes the input port. For example, ios(t) in (1-1) is the positive or negative current variation, [io(t) – IoQ], in net output port current about the quiescent value of this port
current. Our previously acknowledged clever biasing ensures that this current change does not
influence the quiescent current, IoQ, (or any other quiescent current or voltage in the considered
network) and that it is identically zero when the input signal, vs(t), is null. Indeed, these stipulations are foundational to the use of superposition theory, which is mirrored by (1-1) through (13).
In addition to ensuring that quiescent network variables are independent of the signal
components of these variables, our biasing subcircuit must also guarantee nominally linear
interrelationships among all perturbed voltage and current components. With reference to the
output port current perturbations, [io(t) – IoQ], which we introduced in the preceding paragraph,
the linearity requirement implies that [io(t) – IoQ] = gvis(t), where the proportionality factor, g, is
a constant, independent of vis(t). We further note that parameter g must have conductance units
so that the gods of dimensional consistency are appeased. Again by way of example, we cannot
expect vo(t) in (1-1) to be a linear function of vi(t) in (1-2). The reason for this misfortune is that
voltage VoQ is likely to be nonlinearly related to ViQ because the inherently nonlinear transistors
that we use in the network render these two quiescent variables nonlinear functions of the power
supply voltages that energize the network. But since the power supplies are constant voltages,
VoQ and ViQ should be constant (at least at a fixed circuit operating temperature). The ability of
the network in Figure (1.1) to process input signals linearly within the foregoing constraints
mandates that the adopted biasing scheme assure the linear dependence of vos(t) on vis(t) and indeed, on every other signal component of every branch current and node voltage in the network.
Thus, we expect (actually, we demand) that the signal current flowing in the seventeenth branch
of the network is linearly proportional to vis(t), to vos(t), to the signal voltage established with respect to ground at the twenty-eighth circuit node, and to the signal current conducted by the fiftythird network branch.
In due time, we shall appreciate the foregoing biasing assignment as a nontrivial exercise requiring the satisfaction of a pivotally important operating requirement. Specifically, the
biasing we decide to implement must be such that for all operating conditions, every active device embedded in the subject network is forced to operate in a reasonably linear region of its
static volt-ampere characteristic curves. This stipulation implies that the implicitly nonlinear
Ming Hsieh Department of Electrical Engineering
- 95 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
static (or “DC”) V-I characteristics of all utilized devices must exhibit well defined, albeit constricted, regions over which their observed static currents relate to their corresponding static device voltages in a reasonably linear fashion. It is fortuitous that metal oxide semiconductor field
effect transistors (MOSFETs) and bipolar junction transistors (BJTs), which are the focus of this
text, do indeed exhibit such quasi-linear operating regions. The quasi linearity requirement
speaks to meaningfully representing the static V-I characteristics of a transistor within our network by a Taylor series developed for the immediate neighborhood of the quiescent operating
point at which we choose to operate the transistor. If the characteristic curves exhibit reasonable
linearity at and near the operating point, the second and all higher order derivatives of the device
Taylor series expansion approach zero. We see that the immediate result of this mathematical
behavior is a Taylor series that approximates a device V-I characteristic in the immediate
neighborhood of the operating point with a series that is truncated after its linear term. We can
presumably ensure that the excursions in device currents and voltages remain within the region
over which the linearized Taylor series has been formulated by constraining the amplitude of the
applied input to a correspondingly small value. The constraint on input signal amplitude is why
linear analysis of analog electronics is commonly referred to as small signal analysis.
Let’s take the foregoing linearization scenario a step further. We learned in our first
circuits course that the analysis of a linear circuit produces a system of linear equations that define the equilibrium state of the circuit undergoing study. By “equilibrium state,” we refer to the
node voltage and/or branch current solutions that satisfy the system of equations for prescribed
independent variables, which are the applied input currents and voltages. It seems only reasonable then that if we can express the characteristics of a device by linear equations that we deem
to be sufficiently accurate for constrained values of device voltages and currents, we should be
able to produce a linear circuit whose equilibrium conditions are defined by the linear equations
we have contrived. This exercise is the essence of device modeling. In particular, we shall term
the equivalent circuit we contrive as a small signal model since its validity is limited to only a
suitably confined portion of the characteristics curves of the device we are examining. Given
that the model we deduce from the linearized Taylor series expansion of the device volt-ampere
characteristic pertains to only the immediate neighborhood of the quiescent point at which the
device operates, we naturally expect that the branch parameters of the equivalent circuit we
configure are dependent on the operating point. This is to say that different operating points may
imply different V-I characteristic slopes at the Q-point, which in turn are likely to modify relevant branch parameters in the small signal model.
We hereby suggest that suitably designed biasing serves to linearize an electronic network in the immediate neighborhood of its quiescent operating point. This linearization allows
the exploitation of classic superposition theory with respect to the problems of calculating both
quiescent and dynamic branch voltages, branch currents, and node voltages. Figure (1.1b)
dramatizes this contention by depicting quiescent network variables as deriving from the conditions of zero applied signal and, of course, nonzero power supply voltages. Implicit to this circuit structure is the presumption that the ultimately applied input signal does not affect any of the
standby electrical variables of the network.
Figure (1.1c) is the second part of the superposition game we are playing in that it
mathematically nulls the power supply voltages and applies the input signal to a linear model of
the considered electronic network. The solutions arising from our analysis of this model are the
signal-induced changes of branch and node variables about respective Q-points. Since these
changes are linearly interrelated, we understand that the indicated linearized network is a circuit
Ming Hsieh Department of Electrical Engineering
- 96 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
containing only linear resistors, linear capacitors, linear inductors, and/or linear current controlled or voltage controlled dependent sources. We should expect the topology of this model to
differ from that of the original electronic network in Figure (1.1a) because its mathematical relevance is limited to only a determination of signal-induced changes in network variables about
their Q-points. In other words, the linearized structure is “equivalent” to the original electronic
configuration only insofar as the delineation of signal-induced changes in I/O port variables
about specified operating points is concerned.
In concert with the foregoing discussion, we offer Figure (1.2) as a simplified version
of the configurations of Figure (1.1). We understand that Figure (1.2) reflects only a linearized
model of the original two port electronic network and therefore, it can give no information about
the quiescent branch variables of the network. Indeed, the parameters within the model of Figure
(1.2) rely on known quiescent conditions. In other words, we cannot construct the linearized
model without knowing the network Q-point. The reason for this important fact is that the
parameters of the model we construct are functionally related to the equations we formulated as
linearized Taylor series expansions of device V-I characteristics about specified operating points.
Because of an exclusive focus on linear I/O transfer and impedance properties, the power supply
ports appearing in Figure (1.1) are omitted. Moreover, we herewith drop the time domain notation with respect to signal source and all network electrical variables in favor of more convenient
peak, root mean square, or phasor designations. As in Figure (1.1), the input port is formed by
the terminal pair, [1–2], while the output port is the terminal pair, [3–4]. No energy sources are
contained within the two port network, which implies that if any energy storage elements are
embedded therein, zero state conditions apply; that is, all capacitors are initially uncharged, and
all inductors conduct zero current initially. We see that energy is therefore applied to the linear
two port system at only its input port. In Figure (1.2a), we represent this signal energy by a
Thévenin equivalent circuit comprised of the signal source voltage, Vs, and its internal series
impedance, Zs. Alternatively, the applied energy can be modeled by Thévenin’s technological
cousin, Norton, where to keep things legal and moral, the Norton, or short circuit, equivalent input current, Is, is
I2 3
1 I1
+
Zs
Vs
−
+
V1
−
Linear Model
Of Electronic
Network
+
V2
−
2
Zl
4
(a).
1 I1
Is
Zs
+
V1
−
I2
Linear Model
Of Electronic
Network
2
3
+
V2
−
Zl
4
(b).
Figure (1.2). (a). A linear model of a two port network excited at its input
port by a signal source whose Thévenin voltage is Vs and whose
Thévenin impedance is Zs. (b). The system in (a) with the signal source modeled by its Norton equivalent circuit.
I s = Vs Z s .
(1-4)
Because of the input signal excitation, we show a voltage, V1, established across the input port, a
current, I1, flowing into this port, a current, I2 flowing into the output port, and a voltage, V2,
Ming Hsieh Department of Electrical Engineering
- 97 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
developed across the output port. Obviously, current I2 and voltage V2 are constrained by Ohm;
namely,
I 2 = - V2 Zl .
(1-5)
It is important that we understand that voltage V1 is the signal or phasor representation of the
voltage vis(t) in Figure (1.1c), while current I1 is the phasor representation of current iis(t) in the
same figure. Similarly, voltage V2 is in one to one correspondence with vos(t) in Figure (1.1c),
and current I2 corresponds to ios(t).
For any linear two port system, we can quantify the input and output impedance or
admittance and the I/O transadmittance, voltage gain, current gain, or transimpedance in terms of
model parameters we deduce strictly from measurements performed at both the input and output
ports. Interestingly, these impedance, admittance, and transfer metrics can be quantified even if
the circuit architecture implicit to the two port configuration of Figure (1.2) is unknown,
inaccessible, or simply too intricate for a traditional circuit analyses based on the classic
Kirchhoff laws. Such a situation materializes, for example, if the two port network under
investigation is an op-amp for which the manufacturer has not provided a detailed schematic diagram. The upshot of the matter is that if we find that jumping into the linear two port box to play
circuit analysis is impossible, impractical, or simply too intellectually traumatic, we can determine the aforementioned performance indices from only two equilibrium equations that we can
formulate. One of these equations focuses on the input port, where the source energy, source
impedance, and the input port variables, V1 and I1, reside, while the other addresses the output
port, where the load impedance and the output port variables, V2 and I2, prevail. Since only two
equations in the four variables, V1, I1, V2, and I2, can be written without diving into the box, the
formulation of a unique network solution requires that two of these four port variables be viewed
as independent and the remaining two be interpreted as dependent variables. A viable solution
also requires that V2 and I2 abide by Ohm’s law applied to the load termination, while V1 and I1
must be constrained by the source excitation and source impedance. The selection of the
independent and dependent variable sets is arbitrary, subject to the proviso that the corresponding two port model parameters that define the electrical properties of the network can be
meaningfully defined and measured.
1.2.1. SHORT CIRCUIT y-PARAMETERS
If we bookmark the input port and output port voltages, V1 and V2, respectively, as
independent variables in the generalized network of Figure (1.2), the linear two port model we
resultantly formulate is termed the short circuit admittance parameter, or simply y-parameter,
equivalent circuit. Designating voltages V1 and V2 as the independent variables of our model or
equivalent circuit leaves us no choice but to view the input port current, I1, and the output port
current, I2, as the corresponding dependent variables in our analytical strategy. Since the voltampere characteristics of the two port network model undergoing scrutiny are rendered nominally linear because of our biasing efforts and our presumption of only sufficiently small, signalinduced changes about respective Q-point levels, each of its dependent variables is a linear
superposition of the effects of each of its independent variables. This observation gives rise to
input and output port relationships of the algebraic form,
I1 = y11V1 + y12V2
,
(1-6)
I 2 = y21V1 + y22V2
Ming Hsieh Department of Electrical Engineering
- 98 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
where the yij are constants, independent of voltages V1 and V2, and have units of admittance (siemens or mhos). Equation (1-6) can be expressed compactly in matrix form as
y12 ⎤ ⎡V1 ⎤
⎡I ⎤
⎡y
(1-7)
I = ⎢ 1 ⎥ = ⎢ 11
⎥ ⎢ ⎥ = YV .
⎣I2 ⎦
⎣ y21 y22 ⎦ ⎣V2 ⎦
Although the short circuit admittance parameters, yij in (1-6) and (1-7), are independent of the
signal voltages, V1 and V2, and the signal currents, I1 and I2, it is important for us to respect the
fact that they are a function of the quiescent network I/O variables at which the linear analysis is
undertaken. Stated more precisely, the yij characterize the nominally linear volt-ampere properties of the two port electronic network undergoing study in only the immediate neighborhoods of
predetermined input and output quiescent operating points. Therefore, in practical electronic networks we must be mindful that the linear superposition relationships in (1-6) and (1-7) are
meaningful only for sufficiently small values of the independent voltage variables, V1 and V2.
I2 3
1 I1
+
V1
−
Linear Model
Of Electronic
Network
2
+
V2
−
4
1 I1
+
V1
−
I2
1/y11
y12V2
y21V1
2
1/y22
3
+
V2
−
4
Figure (1.3). The short circuit admittance, or y-parameter, equivalent circuit of a linear two port network. All of the
admittance parameters, yij, are in units of mhos.
Recall our assertion to the effect that the analysis of linear circuits produces a linear
system of equations, and conversely, a set of linear equations corresponds to the existence of a
linear network. In the case of (1-6) and (1-7), the y-parameter model of the linear two port network in Figure (1.2) is the topological structure shown in Figure (1.3). We must understand two
pivotal issues about this model. The first of these issues is that the individual yij appearing in the
model can be chosen to ensure that the model delivers accurate volt-ampere relationships at both
its input and output ports. No circuit solutions, accurate or otherwise, can be delivered with respect to internal branch currents and node voltages because despite analytical accuracy at the I/O
ports, the topology of the equivalent circuit almost certainly does not reflect the physical
phenomenology taking place within the original network. This contention asserts little more than
the obvious fact that if we were to jump into the network box, we would not see a simple branch
admittance shunting a controlled current source connected across both the input and output ports.
In short, the model is not physically sound, but it is a behaviorally correct electrical structure that
delivers accurate electrical relationships at the input and output ports for suitably small input signals. The second issue is that the model in Figure (1.3) mirrors what we presumably learned in
our first circuits course. In particular, we were taught that any port of a linear circuit can be
modeled by either a Thévenin or a Norton equivalent circuit. To this end, recall that the
Thévenin and Norton models for a simple one port are cast in terms of independent electrical network variables. We see in Figure (1.3) that the input and output port models reflect Norton
Ming Hsieh Department of Electrical Engineering
- 99 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
equivalent circuits of these ports. Specifically, the Norton dependent generator, y21V1, shunting
the output port and the Norton input port current, y12V2, are respectively proportional to the variables, V1 and V2, which are the independent electrical variables in the y-parameter formulation of
the two port network model. Both of these controlled sources are shunted by admittances, which
we can take as implying that in general, the I/O ports of linear networks can be modeled by nonideal current sources, albeit non-ideal controlled current sources.
Measurement procedures for the admittance parameters derive directly from (1-6) or (17). For example, if the output port signal voltage, V2, is clamped to zero, which corresponds to
the short circuited output port depicted in the linearized system of Figure (1.4a),
I
y11 = 1
V1 V =0
2
.
(1-8)
I2
y21 =
V1 V =0
1 I1 = y11 V1
+
−
+
V1
−
2
I2 = y21 V1 3
Linear Model
Of Electronic
Network
(a).
Short
Circuit
+
V1 = 0
−
2
4
I2 = y22 V2 3
Linear Model
Of Electronic
Network
(b).
+
V2
−
4
+
−
Ideal Test
Voltage Source
1 I1 = y12 V2
+
V2 = 0
−
Short
Circuit
Ideal Test
Voltage Source
2
Figure (1.4). (a). Measurement of the short circuit admittance parameters, y11 and y21.
(b). Measurement of the short circuit admittance parameters, y22 and y12.
It follows that y11 is the short circuit (meaning that the output port is a short circuit) input admittance of the two port undergoing examination, while y21 designates the forward short circuit
transadmittance. Thus, y11 is a particular value of the network input admittance; specifically, y11
is the input admittance under the special case of a short circuited termination imposed on the network output port. On the other hand, y21, which is commonly called the short circuit forward
transadmittance of a linear two port network, is a measure of the forward gain of the network in
that it stipulates a value for the output port current corresponding to a given input port voltage.
In view of the fact that a short circuited load termination is conducive to maximal output port
current, y21 can be viewed as defining the maximum possible forward transadmittance.
Before proceeding further, it is crucial that we understand that the foregoing “short circuit” nomenclature invoked at the network output port applies only to signal conditions. In
particular, an output short circuit in the present context implies only a null output signal; that is,
vos(t) = 0. From (1-1), this constraint means that the output voltage in the actual network (as opposed to the linearized model of the network) is, in general, nonzero and held fixed at its quiescent level, VoQ. A simple way of establishing such a fixed voltage is to connect a capacitor directly across the output port. If this capacitor is sufficiently large to approximate a short circuit
Ming Hsieh Department of Electrical Engineering
- 100 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
for the signal frequency associated with the test signal source applied at the network input port, it
charges to voltage VoQ while simultaneously sustaining vos(t) = 0. The imposed capacitor sustains the requisite constant output voltage without drawing steady state biasing current from the
network under test, thereby allowing for a y-parameter characterization under true quiescent
operating conditions.
With V1 = 0, which reflects the short circuited input port diagrammed in Figure (1.4b),
(1-6) yields
I
y22 = 2
V2 V =0
1
(1-9)
.
I1
y12 =
V2 V =0
1
As in the case of the output port, the short circuit signal requirement, V1 = 0, corresponds only to
the condition, vis(t) = 0, in (1-2) or equivalently, vi(t) = ViQ. Parameter y22 is the short circuit
(meaning that the input port is short circuited) output admittance of the considered network. It is
the actual output admittance observed under the special case of a short circuit imposed at the input port. On the other hand, the parameter, y12, is termed the reverse transadmittance, or the yparameter feedback factor, of a two port network. It is literally the maximum possible reverse
transadmittance since the condition, V1 = 0, imparts a short circuit termination at the input port.
A two port network, and particularly an active two port network, is naturally thought of
as a system capable of delivering very large y21 so that maximal output signal is generated in response to input port excitation. But a portion of the output response can be returned, or fed back,
to the input port because of the electrical nature of the devices implicit to the linear network and
the manner in which the elements of said network are interconnected and laid out. Feedback can
also be manifested by the electrical nature of the package in which the electronic circuit is
embedded. Feedback can be an undesirable phenomenon, as in the case of packaging anomalies
and when bipolar and MOS technology transistors are operated at high signal frequencies. It can
also be a specific design objective, as when feedback paths are appended around active subcircuits to condition overall circuit response. Regardless of the source of network feedback,
parameter y12 is its measure in a y-parameter assessment of the I/O performance of a linear network.
An alternative interpretation of y12 is that of an isolation factor between output and input ports. To this end, y12 = 0 reflects perfect isolation, which implies that the voltages and currents evidenced at the input port are not affected by electrical phenomena prevailing at the output
port. On the other hand, large y12 infers poor isolation, or significant crosstalk, from the output
port to the input port. In an attempt to clarify these assertions, return to (1-6) to solve for the ratio, I1/V1, which is literally the driving point (meaning with actual load incident across the network output port) input admittance of the subject network. In particular,
I1
⎛V ⎞
= y11 + y12 ⎜ 2 ⎟ .
(1-10)
V1
⎝ V1 ⎠
In this expression, the ratio, V2/V1, of independent network variables is the forward voltage transfer ratio, or voltage gain, between the input port and the output port of the circuit undergoing
examination. For fixed input voltage V1, this gain is certainly influenced by the load termination,
across which the output port voltage, V2, is established. For example, a short circuited load
necessarily renders V2 = 0, whereby (1-10) confirms a driving point input admittance that is
Ming Hsieh Department of Electrical Engineering
- 101 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
identical to y11, which is dependent on only internal network parameters and assuredly independent of output port electrical variables. But the same admittance result, I1/V1 = y11, is manifested
by y12 = 0. Evidently, y12 = 0 decouples, or isolates, the output and input ports in the sense that
the input port does not respond to any output port voltage changes induced by load fluctuations,
parasitic signal coupling, or other electrical phenomena.
In an electronic system, it is generally advantageous to achieve |y21| >> |y12|; that is,
the magnitude of the maximum possible forward transadmittance is desirably much larger than
the magnitude of the maximum possible reverse, or feedback, transadmittance. This design
objective is clearly satisfied when the I/O ports are perfectly isolated, in which case the subject
two port becomes known as a unilateral network. The term, “unilateral,” refers to an ability of a
network to transmit signal between I/O ports in only one direction; in this case, from the input
port to the output port. A passive network, on the other hand, has y21 = y12. Any linear network
for which y21 = y12 is said to be bilateral, which means that signal can be propagated from input
to output ports as well as it can be transmitted in the reverse direction, from output to input ports.
All passive linear networks, which are structures whose topologies are comprised exclusively of
electrical interconnections of linear resistors, linear capacitors, and/or linear inductors, are bilateral structures. On the other hand, the electrical behavior of certain types of electronic
configurations closely approximates that of a unilateral network.
1.2.1.1. Alternative y-Parameter Model
It is possible to contrive an interesting alternative to the y-parameter equivalent circuit
of Figure (1.3) −one that underscores the significance of parameter y12 as an intrinsic feedback
metric− for the frequently encountered presence of a common terminal between the input and
output ports. The resultant three terminal two port network, which is commonly referenced as a
π-network model, is the structure offered in Figure (1.5a). This π-type model derives from writing (1-6) in the form,
I1 = y11V1 + y12V2 = ( y11 + y12 )V1 − y12 (V1 − V2 )
.
(1-11)
I 2 = y21V1 + y22V2 = ( y21 − y12 )V1 + ( y22 + y12 )V2 − y12 (V2 − V1 )
1 I1
I2
Linear Model
Of Electronic
Network
+
V1
−
3
+
V2
−
4
2
(a).
1 I1
+
V1
−
2
I2
1/yr
1/yi
yf V 1
(b).
1/yo
3
1 I1
+
V2
−
+
V1
−
4
2
I2
1/yr
1/yi
1/yo
(c).
3
+
V2
−
4
Figure (1.5). (a). Three terminal linear two port network. Observe that nodes 2 and 4 are common to one another.
(b). Alternative π-type form of a y-parameter equivalent circuit for a three terminal, linear two port
network. (c). The model of (b) for the special case of a bilateral, three terminal linear network.
Upon introduction of the ancillary admittances,
Ming Hsieh Department of Electrical Engineering
- 102 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
yi y11 + y12
yr − y12
y f y21 − y12
J. Choma
,
(1-12)
yo y22 + y12
we observe (1-11) to be expressible as
I1 = yi V1 + yr (V1 - V2 )
(1-13)
.
I 2 = y f V1 + yo V2 + yr (V2 - V1 )
which are the equilibrium port equations for the alternative model in Figure (1.5b). Note therein
that parameter yr, which is little more than the negative of y-parameter y12, appears as a feedback
element coupling the output port to the input port. Of course, the model element, yr, is fully
capable of transmitting signal from the input port to the output port. This capability is the reason
underlying an effective forward transadmittance, yf, which is the original forward transadmittance, y21, modified algebraically by an amount, (−y12 = yr). To the extent that |y21| >> |y12|, the
forward transmission through the circuit feedback element pales in comparison to the forward
transmission effected by the controlled generator, yfV1. For a bilateral network, yf in (1-12) is
zero by virtue of the fact that y21 = y12. Accordingly, the model in Figure (1.5b) collapses to the
configuration appearing in Figure (1.5c).
EXAMPLE #1.1:
Determine the short circuit admittance parameters, yij, and the π-model admittance
parameters, yi, yo, yr, and yf, for the linear, bilateral circuit given in Figure (1.6).
1 I1
+
V1
−
Za
Zb
Zc
2
I2
3
+
V2
−
4
Figure (1.6). The simple bilateral two port network addressed in Example (1.1).
SOLUTION #1.1:
Short
Circuit
The determination of the admittance parameters, y11 and y21, requires that a short circuit be
imposed across the output port of the subject network, as diagrammed in Figure (1.7a).
Recalling (1-8), an inspection of the diagram in Figure (1.7a) reveals
I2 3
I2 3
1 I1
1 I1
Za
Zb
Za
Zb
+
+
Zc
Zc
V1
V2
−
−
2
Short
Circuit
(1).
4
2
(a).
4
(b).
Figure (1.7). (a). Equivalent circuit pertinent to the evaluation of the admittance parameters, y11 and y21,
for the network in Figure (1.6). (b). Equivalent circuit pertinent to the evaluation of the
admittance parameters, y22 and y12, for the network in Figure (1.6).
Ming Hsieh Department of Electrical Engineering
- 103 -
USC Viterbi School of Engineering
Lecture Supplement #2
y11 =
Two-Port & Basic Amplifier Networks
J. Choma
I1
1
,
=
V1 V =0
Za + Zb Zc
2
(E1-1)
⎞
⎛ Zc ⎞ ⎛
I2
I
I
1
= 2× 1
= −⎜
⎟
⎟ ⎜⎜
V1 V =0
I1 V1 V =0
Z b + Z c ⎠ ⎝ Z a + Z b Z c ⎠⎟
⎝
2
2
Zc
.
= −
Z a Zb + Za Zc + Zb Z c
(E1-2)
while
y21 =
(2).
Parameters y22 and y12 require the imposition of a short circuit at the input port. Figure (1.7b) is therefore applicable and by (1-9),
I
1
(E1-3)
y22 = 2
,
=
V2 V =0
Zb + Za Zc
1
and
y12 =
(3).
⎞
⎛ Zc ⎞ ⎛
I1
I
I
1
= 1× 2
= −⎜
⎟⎟
⎟ ⎜⎜
V2 V =0
I 2 V2 V =0
⎝ Za + Zc ⎠ ⎝ Zb + Z a Z c ⎠
1
1
Zc
.
= −
Z a Zb + Z a Z c + Zb Z c
(E1-4)
With reference to (1-12), the subsidiary admittance parameters are found to be
Zb
Zb
yi = y11 + y12 =
=
( Zb + Zc ) ( Za + Zb Zc ) Za Zb + Za Zc + Zb Zc
yr = − y12 =
Zc
Za Zb + Za Zc + Zb Zc
. (E1-5)
y f = y21 − y12 = 0
yo = y22 + y12 =
COMMENTS:
Za
Za
=
( Za + Zc ) ( Zb + Za Zc ) Za Zb + Za Zc + Zb Zc
The network addressed in this example is passive and therefore, it is a
bilateral entity. Therefore, it is hardly surprising that parameters y12 and
y21 are identical, whence an effective forward transadmittance, yf, of zero.
An inspection of the network in Figure (1.6) suggests immediately that
impedance Zc functions as the feedback vehicle for coupling the voltampere characteristics of the output port to those of the input port. For
example, if Zc = 0, voltage V1 is simply ZaI1, which is independent of
output variables V2 and I2. Similarly, with Zc = 0, V2 = ZbI2, which is
independent of input port variables. Thus, the no feedback condition
arising from a short circuited impedance, Zc, serves to isolate the input
and output ports of the network. Note that among the four short circuit
admittance parameters, only parameter y12 vanishes when Zc = 0.
Accordingly, and as might have been expected, Zc = 0 achieves the zero
feedback condition typified by null y12, and hence, null yr.
Ming Hsieh Department of Electrical Engineering
- 104 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
EXAMPLE #1.2:
Two port models and parameters are most utilitarian when they are applied to linear
equivalent circuits of active networks, such as amplifiers. To this end, consider the circuit in Figure (1.8), which diagrams an approximate linear model of an amplifier realized in MOSFET technology. Determine the short circuit admittance parameters of this
model, the alternative admittance parameters, and the model implied by the alternative
admittance metrics.
C2
V1
V
+
−
C1
I2
V2
gmV
R
gmV + sC1V
Figure (1.8). The non-bilateral, active two port network addressed in Example (1.1).
SOLUTION #1.2:
(1).
Figure (1.9a) depicts the network of Figure (1.8) under the condition of a short circuited output port. In view of the fact that resistance R must conduct a current of (gm + sC1)V, as is
indicated in the diagram, the input port voltage, V1, is necessarily related to voltage V. In
turn, voltage V functions as the controlling variable for the controlled current source, gmV.
From Figure (1.9a),
V1 = V + V ( gm + sC1 ) R ,
(E2-1)
whence
V1
(E2-2)
V =
,
(1 + gm R )(1 + sRC x )
with the understanding that the effective capacitance, Cx, is given by
C1
(E2-3)
Cx =
.
1 + gm R
(2).
In order to compute the short circuit admittance parameters, y11 and y21, a short circuit must
be imposed across the network output port, as is diagrammed in Figure (1.9a). Since the input port current, I1, satisfies
I1 = sC1V + sC2V ,
(E2-4)
the use of (E2-2) results in
sC x
I1
= sC2 +
.
V1 V =0
1 + sRC x
2
On the other hand, the output port current, I2, is
I 2 = gmV − sC2V ,
whence (E2-2) delivers
y11 =
Ming Hsieh Department of Electrical Engineering
- 105 -
(E2-5)
(E2-6)
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
gx
I2
=
− sC2 ,
V1 V =0
1 + sRC x
2
where the effective forward transconductance at low signal frequencies is
gm
gx =
.
1 + gm R
y21 =
C2
gmV
C1
−
V2 = 0
V1 = 0
Short
Circuit
V
+
(E2-8)
C2
Short
Circuit
V1
I2
(E2-7)
V
I2
+
−
gmV
C1
R
R
gmV + sC1V
gmV + sC 1V
(a).
(b).
C2
V1
V
+
−
C1
V2
I2
C2
V1
V2
gmV
Cx =
C1
1 + gm R
R
R
gm
gx =
1 + gm R
Cx
I2
V2
gxV1
1 + sRCx
(c).
Figure (1.9). (a). Equivalent circuit pertinent to the evaluation of the admittance parameters, y11 and y21,
for the network in Figure (1.8). (b). Equivalent circuit pertinent to the evaluation of the
admittance parameters, y22 and y12, for the network in Figure (1.8). (c). Alternative two
port equivalent circuit of the original network in Figure (1.8).
(3).
Admittance parameters y22 and y12 derive from an analysis of the model offered in Figure
(1.9b), which is the original network of Figure (1.8) with a short circuit imposed across the
network input port. Since (E2-2) is a general relationship applicable for any input or output
port termination, V1 = 0 remands control voltage V to zero. Accordingly, the short circuit
value of the output port current is simply I2 = sC2V2, thereby implying a purely capacitive
short circuit output admittance of
I2
= sC2 .
(E2-9)
V2 V =0
1
Moreover, the input port current, I1, with V1, and therefore V, equal to zero is I1 = −sC2V2,
whence a purely capacitive feedback transadmittance of
y22 =
y12 =
(4).
I1
= −sC2 .
V2 V =0
1
(E2-10)
Appealing to (1-12),
Ming Hsieh Department of Electrical Engineering
- 106 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
yi = y11 + y12 =
J. Choma
sC x
1
=
1 + sRC x
R + 1 sC x
yr = − y12 = sC2
.
gx
y f = y21 − y12 =
1 + sRC x
(E2-11)
yo = y22 + y12 = 0
Referring to the generalized admittance parameter circuit model shown in Figure (1.5a), the
last result postures Figure (1.9c) as a valid equivalent circuit for the network of Figure (1.8).
COMMENTS:
It should be noted that the controlled source in the original network is directly proportional to the intrinsic branch voltage, V, which portends no
immediate analytical significance. In contrast, the controlled source at
the output port of the equivalent circuit deduced as the structure in Figure (1.9c) is directly proportional to the input port voltage, V1, whose
value is ultimately determined as a function of the nature and strength of
the applied input signal.
Apart from its analytical convenience, the subject transformation of the
controlled output port generator reveals at least two interesting network
characteristics that are not immediately transparent in the original network. First, observe that the effective forward transconductance at low
frequencies is gx, which is reduced from the original value of gm by the
potentially significant factor, (1 + gmR). In other words, the effective
forward transconductance, which is a measure of the achievable input
port to output port gain of the amplifier modeled by the architecture in
Figure (1.8), is substantively attenuated, or degenerated, by the indicated
presence of resistance R. Second, note that the magnitude of the effective transconductance is reduced further at high signal frequencies owing
to the time constant, RCx. Fortunately, capacitance Cx is smaller than the
original input port capacitance, C1, by a factor of (1 + gmR), but nonetheless, the magnitude of effective forward transconductance is unavoidably
reduced for appreciable high frequencies. In effect, the ability of the
original network to supply gain over a broad frequency passband is
compromised by intrinsic network capacitance and specifically, the time
constant established by this capacitance.
1.2.1.2. Parameter Measurement
A parametric measurement complication arises when the two port network undergoing
investigation is an active system, which inherently requires biasing to ensure reasonably linear
driving point impedance and transfer characteristics. Unfortunately, the action of physically
short circuiting either the input port or the output port is likely to upset requisite biasing. But on
the assumption that the test voltage sources appearing in Figure (1.4) are sinusoids having zero
average value, we can circumvent the biasing quandary by approximating a short circuit with a
sufficiently large capacitance. In other types of two port characterizations that may require open
circuited ports, we choose a sufficiently large inductance to emulate an open circuit for signal
conditions, without upsetting biasing constraints.
Figure (1.10) portrays practical modifications to the y-parameter measurement strategy.
Because the source and load impedances, Zs and Zl, may play a role in the biasing of the network,
a branch impedance equal to the source impedance at the input port and a branch impedance
Ming Hsieh Department of Electrical Engineering
- 107 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
Vaa
equal to the load impedance connection at the output port are sustained. We should stress that at
the lowest test frequency of interest in Figure (1.10a), the capacitance serving as a “dummy” output port short circuit presents a branch impedance that is significantly smaller than the net resistance it effectively shunts. Since capacitors behave as open circuits at zero frequency, this
dummy shunt is transparent to any output port biasing conditions. Similarly, the capacitance we
incorporate to emulate an input port short circuit in Figure (1.10b) establishes a branch impedance that is substantially smaller than the resistance it effectively shunts. We see then that the
capacitances we deploy to emulate signal short circuits at both the input and the output ports of a
linearized two port network must be large enough so that there respective inverse time constants
are significantly smaller than the lowest test frequency of interest.
Ideal Test
Voltage Source
+
1 I1 = y11 V1
+
V1
−
I2 = y21 V1 3
Linear Model
Of Electronic
Network
2
+
V2 ≅ 0
−
Large
−
−
+
Zs
Zl
4
−
+
Vaa
Vbb
(a).
−
+
Large
Zs
+
V1≅ 0
−
Linear Model
Of Electronic
Network
2
+
V2
−
4
Zl
+
−
Ideal Test
Voltage Source
I2 = y22 V2 3
1 I1 = y11 V2
−
Vbb
(b).
+
Figure (1.10). (a). Practical measurement strategy for admittance parameters y11 and y21 for an electronic network that requires input and output port biasing to sustain acceptable linearity. (b). Practical
measurement strategy for admittance parameters y22 and y12 for an electronic network.
Unfortunately, the simple measurement methodology we have postured in the preceding paragraph proves effective only when the two port network under test is earmarked for relatively low frequency signal processing, such as that typified by audio or video applications. For
broadband systems spanning frequencies through several gigahertz, and for all other circuit and
system functions that require match terminated source and/or load impedances, the electronic
subcircuits embedded within the two port network become fussy under short or open circuited
port terminations. The manifestations potentially incurred by inappropriately terminating the I/O
ports of broadbanded networks are severe I/O nonlinearities, poor transient responses in the
Ming Hsieh Department of Electrical Engineering
- 108 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
senses of severe underdamping and/or long settling times, or even free running oscillations. The
seriousness of the problem at hand forces an abandonment of a direct y-parameter characterization of such networks in favor of indirect measurement methods that do not require short circuited or open circuited network ports. To this end, the most commonly used characterization
tool is a model predicated on the network scattering parameters[1].
1.2.1.3. Ideal Transconductor
The π-model equivalent circuit shown in Figure (1.5b) expedites a convenient definition of an ideal transconductance amplifier, or transconductor. In particular, an ideal
transconductor is an electronic network whose relevant admittance parameters are yi = yr = yo =
0, and yf = Gm, where Gm is a frequency invariant constant known as the effective forward
transconductance of the amplifier. It follows that for all signal frequencies and source and load
terminations, an ideal transconductor provides infinitely large input impedance to an applied signal source and infinitely large output impedance to an arbitrary load termination. Because no
intrinsic feedback is manifested, we see that the output port of an ideal transconductor is perfectly isolated from the input port, which is to say that load impedances exert no effect on the
input impedance. Because of this no feedback, infinite input impedance, and infinitely large output impedance conditions, we further understand that an ideal transconductance amplifier delivers an output port current that is directly proportional to the input port voltage via a frequency
invariant, conductance proportionality, Gm. In short, an ideal transconductor behaves as the voltage controlled current source that you likely thought was a useless academic beast in your first
circuits course.
Figure (1.11a) offers the circuit schematic symbol of an ideal transconductor, together
with its electrical equivalent circuit. Note therein that the input port voltage is applied to the
non-inverting transconductor input terminal, which is symbolized by the “+” sign adjacent to the
terminal. Transconductors can be designed with negative forward transconductance, meaning
that the output port current flows from the network output port, as opposed to into the output
port. Rather than deal with the awkwardness of negative transconductance, we assign a new
symbolic schematic designation to a phase inverted transconductor, as we portray in Figure
(1.11b). In this revised designation, we observe that the input port voltage is now incident with
the inverting (denoted by “−”) input terminal.
I2
I1
I1
+
+
I2
+
Gm
V1
V1
−
GmV1
−
−
(a).
+
V1
−
I1
−
G
+ m
+
V1
−
I2
I1
I2
GmV1
(b).
Ming Hsieh Department of Electrical Engineering
- 109 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
Figure (1.11). (a). Schematic symbol and equivalent circuit for an ideal transconductor.
Note that the input port voltage is applied to the non-inverting input terminal, which is denoted by the indicated “+” sign. (b). Schematic symbol
and equivalent circuit for a phase inverting ideal transconductor. Observe
that the input port voltage is now applied to the inverting input terminal,
which is denoted by the indicated “−” sign. Note that in both cases, the
output port signal current, I2, is I2 = GmV1.
Idealized electrical elements of any type are little more than mathematical artifacts, and
the transconductor is no exception to this philosophical tidbit. Practical transconductors are burdened with finite, and generally capacitive, input impedance, finite and similarly capacitive output impedance, a frequency variant forward transadmittance, as opposed to a real number
transconductance, and the possibility of potentially significant internal feedback. We shall learn
that these second order effects can often be rendered negligible in specific design tasks so that
the idealized form of a transconductor comprises a convenient tool for executing a meaningful
first order performance assessment of many electronic systems.
Ix
+
+
Vx
−
0
+
G
− m
GmVx
Vx
Ix
Vx
1
Gm
−
Vc
(a).
(b).
Figure (1.12). (a). Transconductor interconnected to function as a two terminal linear resistance. (b). The equivalent circuit of the structure in (a). The resistance presented by the transconductor
architecture is 1/Gm, where transconductance Gm is controllable through the static voltage, Vc.
An especially useful attribute of most practical transconductors is that they can be designed to achieve a forward transconductance whose value is adjustable as a monotonic function
of a static voltage or current applied to a control port that we have not delineated in Figure
(1.11). This control voltage or current, which is separate and apart from the biasing required for
acceptable I/O linearity, allows for fine tuning monolithic circuit responses in the face of
processing vagaries, device modeling uncertainties, and the effects of parasitics forged by circuit
layout. As an example of the utility of a voltage controlled transconductance, let us examine the
simple circuit of Figure (1.12a), which depicts a non-inverting transconductor whose input and
output terminals are connected together. While biasing is not explicitly depicted in this diagram,
a static voltage, Vc, is shown as applied to an available control port to allow for transconductance
adjustment, or tuning. We can determine the resistance, say R, established from the transconductor output terminal to ground by exploiting a symbolic ohmmeter to squirt a small and arbitrary
current Ix, into the output port of the network. This current manifests the indicated terminal voltage, Vx, so that the desired resistance, R, is simply the voltage to current ratio, Vx/Ix, which keeps
George Ohm off our backs Since voltage Vx is simultaneously applied to the transconductor input port, the current, I2 conducted by the network output port is necessarily GmVx. It follows that
the “ohmmeter” current, Ix, must be Ix = GmVx, thereby implying a net resistance, R, of R = Vx/Ix
= 1/Gm, as we dutifully suggest by Figure (1.12b). In view of the fact that control voltage Vc is
Ming Hsieh Department of Electrical Engineering
- 110 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
used to adjust the numerical value of transconductance Gm, we have effectively realized an electronic potentiometer.
EXAMPLE #1.3:
Simple amplifiers can be realized with transconductors without resorting to the use of
passive resistances in the signal path of the circuit. In most MOSFET technology processes, avoiding passive resistances affords design advantages that we shall address later.
To this end, consider the network in Figure (1.13a), which utilizes two transconductor
elements for which the transconductances of each are controlled by separate static voltages, Vc1 and Vc2. A capacitance, C is appended across the output port of the amplifier.
This capacitance might very well absorb the output and input port capacitances of a
practical realization of the second transconductor, as well as the output port capacitance
of the first transconductor. Develop expressions for the voltage gain function, Av(s) =
Vo/Vs, the zero frequency value, Av(0), of this gain, and the 3-dB bandwidth, B, afforded
by the network. Discuss the performance ramifications of control voltages Vc1 and Vc2.
Vs
Vo
+
G
− 1
+
G
− 2
Vc1
C
Vc2
(a).
Vs
G1Vs
0
+
G
− 1
G 1V s
0
+
G
− 2
Vc1
Vo
G 2V o
C
G 1V s + G 2 V o
Vc2
(b).
Vs
0
+
G
− 1
G 1V s
Vo
1
G2
C
Vc1
(c).
Figure (1.13). (a). An amplifier formed of two transconductors. Capacitance
C represents the sum of the load, second transconductor input
port and output port, and first transconductor output port
Ming Hsieh Department of Electrical Engineering
- 111 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
capacitances. (b). The circuit of (a) with key branch currents
expressly delineated. (c). The circuit of (a) with the second
transconductor supplanted by the resistance, 1/G2, which it
establishes across the output port of the amplifier.
SOLUTION #1.3:
(1).
We can tackle this problem in at least two different ways. The first way entails, as is delineated in Figure (1.13b), the identification of the branch currents supported by the architecture.
To this end, we note that the current flowing into the output port of the first transconductor
(G1) is G1Vs. Since the output voltage, Vo, is simultaneously incident with the input port of
the second transconductor (G2), a current of G2Vo must flow into the output port of this
transconductor. Because the input port currents of ideal transconductor amplifiers are zero,
the indicated current, G1Vs, must be supplied by the short circuit that connects the output port
to the input port of the second transconductor. Consequently, we conclude a current flowing
through the capacitance, C, which is the sum, (G1Vs + G2Vo). If Kirchhoff is to be placated,
the resultant signal output voltage is
G V + G2Vo
(E3-1)
Vo = − 1 s
.
sC
Upon solving this expression for voltage Vo, the voltage gain, Av(s), derives directly as
V
G G
Av (s) = o = − 1 2 .
(E3-2)
sC
Vs
1+
G2
(2).
The second problem solving strategy relies on our ability to recognize that the interconnection of the second transconductor is tantamount to the realization of a two terminal resistance, 1/G2, which terminates the output port to ground. Accordingly, the original network
in Figure (1.13a) collapses to the topology appearing in Figure (1.13c). An inspection of the
latter circuit diagram readily leads to
G1Vs
(E3-3)
Vo = −
,
G2 + sC
which obviously produces the gain result in (E3-2).
(3).
The gain of an amplifier as a function of signal frequency is ordinarily extracted from steady
state observations of the amplifier output port response to an applied sinusoidal input signal;
that is, voltage Vs is a fixed amplitude sinusoid whose frequency is varied over the amplifier
passband. For this steady state sinusoidal excitation, the Laplace variable, s, can be supplanted by jω, where we understand that ω represents the radial signal frequency of the applied input signal. It follows that in the sinusoidal steady state, (E3-2) becomes
G1 G2
Av (jω ) = −
.
(E3-4)
jωC
1+
G2
Clearly, the gain at zero frequency (ω = 0, which is equivalent to s = j0 = 0) is
G
Av (0) = − 1 .
G2
(E3-5)
On the other hand, the 3-dB bandwidth, B, (in units of radians -per- second) is the value of
signal frequency ω, such that the gain magnitude is a factor of root two smaller than the
magnitude of the zero frequency gain. It should be noted that the decibel value of root two is
Decibel Value Of 2 = 20 log10 2 = 3.01,
(E3-6)
Ming Hsieh Department of Electrical Engineering
- 112 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
which approximates 3 for small values of 1. Thus, a factor of root two below the magnitude
of the zero frequency voltage gain is a gain that is very nearly 3 decibels smaller than the
decibel value of the zero frequency gain magnitude. From (E3-4),
Av (jB ) = −
G1 G2
G1 G2
=
=
jBC
jBC
1+
1+
G2
G2
G1 G2
=
G1 G2
(E3-7)
.
2
2
⎛ BC ⎞
1+⎜
⎟
⎝ G2 ⎠
An inspection of the last result reveals a 3-dB bandwidth of
G
B = 2 .
(E3-8)
C
We note that (E3-8) and (E3-5) enable writing (E3-2) in the generalized form
V
Av (0)
G G
Av (s) = o = − 1 2 =
,
(E3-9)
sC
s
Vs
1+
1+
G2
B
which suggests that the inverse of the coefficient of the s-term in a monic representation of
the characteristic polynomial of a single time constant network is indeed the 3-dB bandwidth
of the network.
COMMENTS:
Although forthcoming chapters provide far more definitive information
about the frequency response of linear networks, this example serves to
introduce you to a few of the metrics commonly used to assess frequency
domain performance. First, we observe that the zero frequency gain is
the gain that would be obtained if capacitance C were zero. We
substantiate his contention by multiplying both sides of (E3-1) by (sC)
and then setting C = 0, which we recognize as an equivalence to an open
circuited load capacitance. Second, we observe that the quoted zero frequency gain cannot be sustained from DC to daylight because the capacitance, which directly shunts the amplifier output port, behaves progressively more as a branch short circuit as the signal frequency is increased.
This short circuit behavior mirrors the well-known fact that voltages
across capacitances cannot change instantaneously in response to rapidly
changing (high frequency) signals. At the 3-dB bandwidth, which is the
frequency at which the impedance of the capacitance matches the resistance said capacitance effectively faces in the network at hand, the voltage gain is a factor of root two below the gain magnitude observed at
zero frequency. Equivalently, the 3-dB bandwidth is the signal frequency at which the signal power gain, which is related to the square of
voltage gain, is one-half the power gain achieved at zero, or at least at
very low, frequencies.
The transconductor realization of the amplifier addressed herewith is
sufficiently creative to allow gain and bandwidth to be controlled
independently. For example, a change in transconductance G1 through
an appropriate change in control voltage Vc1 alters the zero frequency
gain without affecting the 3-dB bandwidth. On the other hand and for
the manually dexterous, a change in G2, coupled with an identical change
in G1, via the application of suitable control voltages, Vc1 and Vc2, perturbs the 3-dB bandwidth without influencing the low frequency gain.
Ming Hsieh Department of Electrical Engineering
- 113 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
1.2.2. OPEN CIRCUIT z-PARAMETERS
The fallout of an arbitrary selection of input port voltage V1 and output port voltage V2
as the independent variables of a linear two port system is the y-parameter network model we
formulated as Figure (1.3). Obviously, numerous choices are available for independent variable
selection, and each such selection results in different modeling architectures, This assertion
synergizes with an earlier contention as to the non-uniqueness of electronic circuit models. For
example, consider the use of the input port current, I1, and the output port current, I2, as
independent electrical variables in the system of Figure (1.2). The upshot of this selection is the
defining volt-ampere matrix relationship,
ÈV1 ˘
È z11 z12 ˘ È I1 ˘
(1-14)
ÍV ˙ = Í z
˙Í ˙ ,
Î 2˚
Î 21 z22 ˚ Î I 2 ˚
where the zij are the open circuit impedance parameters, or z–parameters of the network. The
equivalent circuit implied by (1-14) is given in Figure (1.14) and, in contrast to the Norton port
representations implicit to the y-parameter model, it exploits Thévenin’s theorem at both the input and output ports.
I2 3
1 I1
+
V1
−
Linear Model
Of Electronic
Network
+
V2
−
4
2
1 I1
+
V1
−
z11
+
+
z12 I2
−
z22
z21 I1
−
I2
3
+
V2
−
4
2
Figure (1.14). The open circuit impedance, or z-parameter, equivalent circuit of a linear two port network. All of the
impedance parameters, zij, are in units of ohms.
The designation of the z–parameters as open circuit impedances follows from the
parametric measurement strategy that we can easily deduce from (1-14). In particular,
V
z11 = 1
I1 I = 0
2
(1-15)
,
V2
z21 =
I1 I = 0
2
whence z11 is the open circuit (meaning an open circuited output port) input impedance of the linear two port network, while z21 is seen as the open circuit transimpedance of the two port system.
Thus, parameter z11 is the driving point input impedance of a linear two port network under the
special case of an open circuited load termination at the output port. Moreover, z21 represents the
maximum possible forward transimpedance in that the model voltage source, z21I1, associated
with this parameter drives an open circuited load. Analogously,
Ming Hsieh Department of Electrical Engineering
- 114 -
USC Viterbi School of Engineering
Lecture Supplement #2
z12 =
Two-Port & Basic Amplifier Networks
J. Choma
V1
I2 I =0
1
(1-16)
.
V2
z22 =
I2 I =0
1
Accordingly, we conclude that z12 is the feedback transimpedance under the condition of an open
circuited input port, and z22 is the driving point output impedance measured under the same open
circuited input port constraint.
Recall that if the individual ports of a linear two port network share a common terminal, the basic y-parameter model can be collapsed to a π-type network architecture. Analogously, the z-parameter model of a common terminal two port network can be reduced to the teetype structure offered in Figure (1.15b). The subsidiary impedance parameters, zi, zf, zr, and zo,
in the tee model derive from (1-14), which we can couch as
1 I1
+
V1
−
3
I2
Linear Model
Of Electronic
Network
+
V2
−
4
2
(a).
1 I1
+
V1
−
zf I 1
+ I2
3
1 I1
zr
+
V2
−
+
V1
−
(b).
4
2
zi
2
−
zo
zi
zo
I2
3
zr
+
V2
−
(c).
4
Figure (1.15). (a). Three terminal linear two port network. Observe that nodes 2 and 4 are common to one
another. (b). Alternative tee-type form of a z-parameter equivalent circuit for a three terminal, linear two port network. (c). The model of (b) for the special case of a bilateral, three
terminal linear network.
V1 = ( z11 − z12 ) I1 + z12 ( I1 + I 2 )
.
V2 = ( z21 − z12 ) I1 + ( z22 − z12 ) I 2 + z12 ( I1 + I 2 )
Letting
zi = z11 − z12
z f = z21 − z12
zr = z12
,
(1-17)
(1-18)
zo = z22 − z12
(1-17) becomes
V1 = zi I1 + zr ( I1 + I 2 )
(1-19)
,
V2 = z f I1 + zo I 2 + zr ( I1 + I 2 )
which leads immediately to the model in Figure (1.15b). For the case of a bilateral network for
which open circuit feedforward signal transmission is equal to open circuit feedback signal
Ming Hsieh Department of Electrical Engineering
- 115 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
transfer, z21 = z12, whence zf = 0. The tee-type model for a bilateral network is resultantly the
circuit in Figure (1.15b).
1.2.2.1. Ideal Transresistor
An ideal transconductor is an amplifier that delivers an output port signal current that is
directly proportional to input port voltage, regardless of source or load terminations. In contrast,
an ideal transresistance amplifier, or transresistor, supplies an output port voltage that is directly proportional to its input port current, independent of source and load terminations. If we
return to the model in Figure (1.15b), we can easily deduce that an ideal transresistor has zi = zr
= zo = 0, while sustaining a forward transimpedance, zf, that equals a real number, say Rm, which
is independent of signal frequency. Accordingly, and as depicted in Figure (1.16), the ideal
transresistance amplifier projects no feedback from its output to input ports. Additionally, it postures a short circuited input port that enables an input port current, I1, which is independent of the
signal source impedance. Finally, the output port of an ideal transresistor functions as an ideal
voltage source supporting an output port voltage, V2, which is directly proportional to the input
port current and is independent of load terminations incident with the output port.
+
V1
−
I1
+
R
− m
I2
V2
I1
+
V1
−
I2
+
V2
Rm I1
−
Figure (1.16). Schematic symbol and equivalent circuit for an ideal transresistance amplifier.
EXAMPLE #1.4:
Let us take Figure (1.17a) as the low frequency, linear equivalent circuit of a given
transresistance amplifier. In terms of the circuit parameters implicit to this model,
evaluate the open circuit impedance parameters, as well as the tee-equivalent impedance
parameters. Draw the tee-type model for the special case of very largeβ, where β is the
indicated gain of the controlled current source embedded in the model.
SOLUTION #1.4:
(1).
We show in Figure (1.17b) the model of Figure (1.17a) for the special case of an open circuited output port (I2 = 0). Pertinent branch currents are indicated in the latter structure and
in particular, observe that the control current, I, for the current controlled current source, βI,
is I = I1 − βI,
I1
(E4-1)
I =
.
β+1
Thus, the input port voltage, V1, is
⎛ I ⎞
(E4-2)
V1 = R1 I1 + R2 I = R1 I 1 + R2 ⎜ 1 ⎟ ,
⎝ β + 1⎠
from which we obtain an open circuit input impedance given by
z11 =
V1
R2
.
= R1 +
I 1 I =0
β+1
2
Ming Hsieh Department of Electrical Engineering
(E4-3)
- 116 -
USC Viterbi School of Engineering
Lecture Supplement #2
V1
I1
Two-Port & Basic Amplifier Networks
R1
Rf
I2
R2
V2
V1
I1
R1
βI
0
R2
V2
βI
I
(a).
V1
Rf
βI
I
0
J. Choma
(b).
Rf I2−βI
R1
I2
V2
V1
I1
R1
I2
V2
−
R2
I=I1
βI
I
RfI1
+
(d).
(c).
Figure (1.17). (a). Linear equivalent circuit of a transresistance amplifier. (b). The circuit of (a) with the
output port open circuited. (c). The circuit of (a) with the input port open circuited. (d).
Tee-equivalent model of the equivalent circuit in (a) under the special case of very large β.
Similarly, the output port voltage, V2, satisfies
I1
,
V2 = − R f βI + R2 I = − βR f − R2
β+1
which produces a forward transimpedance of
(
z21 =
(2).
)
⎛ β ⎞
V2
R2
.
= −⎜
⎟Rf +
I 1 I =0
β + 1⎠
β+1
⎝
2
(E4-4)
(E4-5)
The applicable circuit diagram and key branch currents pertinent to an open circuited input
port (I1 = 0) is the topology appearing in Figure (1.17c). Note now that the control current,
I, is given by I = I2 − βI, which yields
I2
(E4-6)
I =
.
β+1
The corresponding output port voltage, V2, is, using (E4-6),
⎛ R f + R2 ⎞
(E4-7)
V2 = R f ( I 2 − βI ) + R2 I = ⎜
⎟ I2 .
⎝ β+1 ⎠
Clearly, the open circuit output impedance abides by
R f + R2
V
z22 = 2
.
=
(E4-8)
I 2 I =0
β+1
1
Since
R2 I 2
,
β+1
the feedback transimpedance is
V1 = R1 ( 0 ) + R2 I =
z12 =
(E4-9)
V1
R2
.
=
I 2 I =0
β+1
1
Ming Hsieh Department of Electrical Engineering
(E4-10)
- 117 -
USC Viterbi School of Engineering
Lecture Supplement #2
(3).
Two-Port & Basic Amplifier Networks
J. Choma
The subsidiary impedance parameters for the tee-equivalent model derive from the preceding
results and (1-18). In particular,
zi = z11 − z12 = R1
⎛ β ⎞
z f = z21 − z12 = − ⎜
⎟Rf
⎝ β + 1⎠
R2
zr = z12 =
β+1
Rf
zo = z22 − z12 =
β+1
.
(E4-11)
For very large β, the preceding results become
zi = z11 − z12 = R1
z f = z21 − z12 ≈ − R f
zr = z12 ≈ 0
,
(E4-12)
zo = z22 − z12 ≈ 0
The latter equations give rise to the simplified equivalent circuit in Figure (1.17d).
COMMENTS:
Aside from demonstrating the analytical techniques underlying the
computation of the open circuit impedance parameters, this example
highlights the utility of the z-parameters in circuit design ventures.
Specifically, the z-parameters and their subsidiary tee-type impedance
counterparts render transparent the fact that the circuit model in Figure
(1.17a) emulates ideal transresistance action only if parameter β is suitably large. To be sure, large β does not reduce parameter zi to its desirable null value, but because zi is an element that is in series with the input
port, it can presumably be absorbed into the Thévenin impedance of the
ultimately applied signal source.
1.2.2.2. z-Parameter Relationship To y-Parameters
A potentially confusing aspect of the preceding disclosures is that two models for a linear two port network have now been formulated. The short circuit admittance parameters model
both network ports by Norton equivalent circuits that feature current sources controlled by input
and output port voltages. On the other hand, the open circuit impedance parameters exploit
Thévenin equivalent input and output port circuits whose voltage sources are controlled by
independent port currents. Analytical chaos ensues if the y-parameter model and the z-parameter
model of the same linear network do not deliver identical input and output port responses to applied signal excitations. We can avoid such chaos only if the y-parameters and the z-parameters
of the same network are unambiguously related to one another in a manner that is consistent with
the equilibrium volt-ampere relationships prevailing at both network ports. In short, for given
source excitation at the input port and load termination at the output port of a linear network, the
y-parameter model and the z-parameter model of the subject network must deliver identical port
voltage and port current responses to the same signal excitations.
In a linear network, such as the one abstracted in Figure (1.2), the volt-ampere port
equilibrium relationships expressed in terms of z-parameters are stipulated by (1-14). On the
other hand, (1-7) defines these unique relationships in terms of the y-parameters of the network.
But from (1-7),
Ming Hsieh Department of Electrical Engineering
- 118 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
−1
⎡V1 ⎤
⎡ y11 y12 ⎤ ⎡ I1 ⎤
(1-20)
⎢V ⎥ = ⎢ y
⎥ ⎢ ⎥,
⎣ 2⎦
⎣ 21 y22 ⎦ ⎣ I 2 ⎦
which is precisely the form of (1-14). In other words, the matrix of z-parameters is little more
than the inverse of the matrix of corresponding y-parameters. Specifically,
y
1
z11 = 22 =
y y
Δy
y11 − 12 21
y22
z22 =
y11
1
=
y y
Δy
y22 − 12 21
y11
,
(1-21)
y
y12
z12 = − 12 = −
Δy
y11 y22 − y12 y21
y
y21
z21 = − 21 = −
Δy
y11 y22 − y12 y21
where
Δy = y11 y22 − y12 y21
(1-22)
symbolizes the determinant of the y-parameter matrix. Similarly, the matrix of y-parameters is
the inverse of the corresponding matrix of z-parameters.
But if two different models yield identical response results to identical input signals, we
can naturally question the logic underlying the use of different two port network models. In
other words, why must we learn about two models when, in fact, each of the two models delivers
identical I/O port responses? One answer to this query is that depending on the architecture
undergoing investigation, one set of parameters may be more easily evaluated or meaningfully
interpreted than another set. But a clue as to the dominant reason for adopting multiple model
representations is provided by (1-21). In particular, if the determinant, Δy, of the matrix of short
circuit admittance parameters is zero, the matrix is said to be singular, and the open circuit
impedance parameters, zij, cannot be determined. In other words, the z-parameters of a network
whose matrix of y-parameters is singular do not exist, thereby leaving us with little choice now
but to adopt a y-parameter basis for the analysis of interest. Conversely, if the z-parameter matrix of a linear two port network is singular, the y-parameters do not exist, thereby forcing us to
exploit a z-parameter representation of the network before us.
Somewhat paradoxically, matrix singularity in the course of circuit analysis is commonly the byproduct of approximations invoked to simplify the network at hand. For example,
consider the idealized transresistor model of Figure (1.16), which is the upshot of invoking the
simplification, z11 = z12 = z22 = 0 on a generalized z-parameter model of a transresistance amplifier. The matric relationship of this idealized two port structure is
⎡ 0 0 ⎤ ⎡ I1 ⎤
⎡V1 ⎤
(1-23)
⎥⎢ ⎥ ,
⎢V ⎥ = ⎢ R
⎣ 2⎦
⎣ m 0⎦ ⎣ I2 ⎦
for which the determinant, Δz, of the square matrix on the right hand side is zero. Thus, the yparameters of the ideal transresistance amplifier cannot be determined. The disbelievers of the
singularity dilemma are hereby challenged to determine the y-parameters of the model in Figure
(1.16). They are additionally reminded that the Thévenin equivalent circuit of a current source
Ming Hsieh Department of Electrical Engineering
- 119 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
approximated as an idealized branch element does not exist, nor does the Norton equivalent circuit of an ideal, zero series resistance, voltage source.
1.2.3. HYBRID h-PARAMETERS
If we arbitrarily select the input port current, I1, and the output port voltage, V2, as the
independent variables of a linear network, an h-parameter representation abiding by the generalized volt-ampere characteristic,
⎡V1 ⎤
⎡ h11 h12 ⎤ ⎡ I1 ⎤
(1-24)
⎢ I ⎥ = ⎢h
⎥⎢ ⎥ ,
⎣ 2⎦
⎣ 21 h22 ⎦ ⎣V2 ⎦
results. The parameters, hij, are referred to as hybrid h-parameters, or simply h-parameters,
where the adjective, “hybrid,” highlights the fact that the individual hij do not have the same
physical units. Specifically,
V
h11 = 1
(1-25)
I1 V =0
2
is in units of ohms in that it is the impedance established at the network input port under the
condition of a short circuited output port. In contrast,
I
h22 = 2
(1-26)
V2 I =0
1
has units of siemens (or mhos) as it symbolizes the admittance prevailing at the network output
port under the condition of an open circuited input port. In contrast to h11 and h22, both h21 and
h12 are dimensionless metrics. From (1-24),
I
h21 = 2
(1-27)
I1 V =0
2
is the short circuit, and therefore maximum, current gain of the network, while
V
h12 = 1
V2 I =0
(1-28)
1
monitors internal network feedback as a reverse open circuit voltage transfer function. The
equivalent circuit inferred by (1-24), which we submit as Figure (1.18), is seen to utilize
Thévenin’s theorem at the input port and Norton’s theorem at the output port.
I2 3
1 I1
+
V1
−
Linear Model
Of Electronic
Network
4
2
1 I1
+
V1
−
h11
+
V2
−
I2
+
h12 V2
−
h21 I1 1/h22
3
+
V2
−
4
2
Figure (1.18). The hybrid h-parameter equivalent circuit of a linear two port network. Parameter h11 is in units of
Ming Hsieh Department of Electrical Engineering
- 120 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
ohms, h22 has dimensional units of siemens, and
both h12 and h21 are dimensionless parameters.
The h-parameter equivalent circuit is the third modeling option available for linear circuit analysis. As in the case of requisite analytical relationships between the y- and z-parameters
of a linear network, analytical propriety mandates that these h-parameters be related to both the
y- and z-parameters. In the case of the y-parameters introduced in (1-6),
V
1
h11 = 1
.
=
(1-29)
I1 V =0
y11
2
This relationship is hardly astonishing news in light of our understanding that y11 is the short circuit input admittance, while h11 designates the short circuit input impedance. For parameter h21,
I
y
h21 = 2
= 21 ,
(1-30)
I1 V =0
y11
2
which confirms that the measure of forward gain, h21, is directly proportional to the counterpart
y-parameter forward gain metric, y21. Indeed, we may assert that hybrid parameter h21 is simply
y-parameter y21 normalized to y-parameter y11. This alternative interpretation serves to confirm
the dimensionless nature of h21. Returning to (1-6),
Δy
I
y y
(1-31)
,
h22 = 2
= y22 − 12 21 =
y11
V2 I =0
y11
1
and finally,
V1
y
= − 12 .
(1-32)
V2 I =0
y11
1
Recalling that an implicit property of a bilateral network is y21 = y12, we observe from (1-30) and
(1-32) that a bilateral network requires forward and reverse transmission hybrid h-parameters
satisfying h21 = −h12.
h12 =
The h-parameter model allows for a convenient definition of an ideal current amplifier,
whose circuit schematic symbol and electrical model are given in Figure (1.19). In particular, an
ideal current amplifier has h11 = 0 and h12 = 0, which combine to imply a short circuited input
port for all load terminations. Moreover h22 = 0 in an ideal current amplifier. In concert with h12
= 0, h22 = 0 fashions an infinitely large output impedance that is independent of input port
dynamics. Finally, h21 = αm, where αm, a real number that we can identify as the current gain of
the amplifier, is independent of signal frequency. In summary and with reference to Figure
(1.19), the terminal volt-ampere characteristics of an ideal current amplifier are given by
+
V1
−
I1
+
α
− m
I2
V2
I1
+
V1
−
I2
V2
αm I1
Figure (1.19). Schematic symbol and equivalent circuit for an ideal current amplifier.
⎡0
⎡V1 ⎤
⎢ I ⎥ = ⎢α
⎣ 2⎦
⎣ m
0 ⎤ ⎡ I1 ⎤
.
0 ⎥⎦ ⎢⎣V2 ⎥⎦
Ming Hsieh Department of Electrical Engineering
(1-33)
- 121 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
The current amplifier in either its idealized or non-ideal forms is commonly exploited
in circuit applications as a current buffer, which is often referred to as a cascode. We shall find
that current buffering is advantageous when a high impedance signal source is coupled to a load
of comparably large impedance. As an illustration of the utility of current buffering, consider
Figure (1.20a), which depicts a signal current source, Is, whose shunt resistance is Rs, is directly
coupled to a load resistance of Rl. The resultant signal transmitted to the load is the current I2,
which obviously derives from
I2
Is
I1
Rs
Rl
Is
Rs
−
α
+ m
I2
Rl
(a).
(b).
I1
Is
I2
αm I1
Rs
Rl
(c).
Figure (1.20). (a). A signal current, Is, whose Thévenin resistance is Rs, is coupled to a resistive
load of value Rl. (b). The circuit of (a) modified by the insertion of a current
buffer between the signal source and the load termination. (c). The equivalent circuit of the system in (b), assuming that the current buffer approximates the electrical characteristics an ideal current amplifier.
Rs
I2
.
=
(1-34)
Is
Rs + Rl
If Rl << Rs, we surmise an efficient source to load coupling in the sense that the signal current
suffers little attenuation caused by the direct coupling. But if Rl is comparable to, or even greater
than, Rs, a significant percentage of the signal current is lost during its source to load transmission. In the latter event, a current buffer inserted between the source and load, as diagrammed in
Figure (1.20b) proves effective. We observe that the signal is applied to the inverting input
terminal of the current amplifier. Resultantly, the pertinent equivalent circuit is the model in
Figure (1.20c) for which I1 = −Is, and I2 = −αmI1 = αmIs, whence I2/Is = αm. The idealized nature of the current amplifier in this example renders the current transfer function, I2/Is, unlike the
form of (1-34), independent of both source and load resistances. Moreover, if the amplifier is
designed to deliver a port current gain, αm, of one, the load and signal source currents are identical.
1.2.4. HYBRID g-PARAMETERS
The independent and dependent electrical variable sets used to define the hybrid gparameters are the converse of those used in conjunction with the hybrid h-parameters. Specifically, the independent variables for g-parameter modeling are the input port voltage, V1, and the
output port current, I2, thereby rendering the input port current, I1, and the output port voltage,
Ming Hsieh Department of Electrical Engineering
- 122 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
V2, dependent electrical quantities. Accordingly, the port equilibrium relationships assume the
form
⎡ I1 ⎤
⎡ g11 g12 ⎤ ⎡V1 ⎤
(1-35)
⎢V ⎥ = ⎢ g
⎥⎢ ⎥ ,
⎣ 2⎦
⎣ 21 g 22 ⎦ ⎣ I 2 ⎦
and by comparison with (1-24),
−1
⎡ g11 g12 ⎤
⎡ h11 h12 ⎤
(1-36)
=
⎢g
⎥
⎢h
⎥ .
⎣ 21 g 22 ⎦
⎣ 21 h22 ⎦
Like the hybrid h-parameters, the g-parameters have mixed dimensions. In particular, g11 has
units of conductance, g22 is a resistive quantity, and g21 and g12, which respectively measure
feedforward and feedback within the network undergoing study, are dimensionless metrics. Figure (1.21) is the electrical equivalent circuit evoked by (1-35). In further analogy to h-parameters, a bilateral network has g12 = −g21, just as it has h12 = −h21 if h-parameters are adopted as
the modeling vehicle.
I2 3
1 I1
+
V1
−
Linear Model
Of Electronic
Network
+
V2
−
4
2
1 I1
+
V1
−
+
1/g11
g12 I2
g22
g21 V1
−
I2
3
+
V2
−
4
2
Figure (1.21). The hybrid g-parameter equivalent circuit of a linear two port network. Parameter g11 is in units of
siemens, g22 has units of ohms, and both g12 and
g21 are dimensionless parameters.
Although the g-parameters are used less often than are the h- and y-parameters when
arbitrary linear two port networks are modeled for circuit analysis purposes, they are suitable for
the modeling of an ideal voltage amplifier, for which the ubiquitous operational amplifier is a
pragmatic approximation. Formally, an ideal voltage amplifier, which is illustrated symbolically
in Figure (1.22), delivers null g11 and g12. These constraints dictate an infinitely large driving
point input impedance that is independent of load terminations imposed at the output port.
Additionally, g22 = 0, which along with g12 = 0, guarantees a zero output impedance that is
oblivious to source impedance. Finally, g21 = μm, where parameter μm, which is termed the open
circuit voltage gain of the subject amplifier, is a constant that is independent of signal frequency.
The ideal operational amplifier takes the concept of an ideal voltage amplifier a step further by
ascribing an infinitely large value to the open circuit voltage gain; that is, μm = ∞.
Ming Hsieh Department of Electrical Engineering
- 123 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
I1
+
V1
−
+
μ
− m
I2
J. Choma
I1
V2
I2
+
+
V1
−
V2
μmV1
−
Figure (1.22). Schematic symbol and equivalent circuit of an ideal voltage amplifier.
EXAMPLE #1.5:
Figure (1.23a) diagrams a low frequency, small signal equivalent circuit of a voltage
amplifier that exploits feedback via the resistance, R2. Let R1 = 22 KΩ, and R2 = 3 KΩ.
Assume an amplifier output resistance, ro, of 300 Ω, and an amplifier open circuit voltage gain, Ao, of 250. Derive general expressions for, and numerically evaluate, the four
g-parameters, gij, of the feedback amplifier.
I1
V1
I2
+
V
−
V2
A oV
R1
+
−
R2
(a).
I1
I2 = 0
+
V
−
AoV
R1
−
+
I1
V2
I2
+
V1 = 0
V1
V
−
AoV
R1
−
V2
+
R2
R2
(b).
(c).
Figure (1.23). (a). Linear equivalent circuit of the amplifier studied in Example #1.5. (b). The circuit of
(a) with an open circuit imposed at the output port to facilitate the computation of gparameters g11 and g21. (c). The circuit of (a) with a short circuit imposed at the input
port to calculate parameters g22 and g12.
SOLUTION #1.5:
(1).
Figure (1.23b) is the original circuit of Figure (1.23a) but with an open circuit delineated at
the output port. Because of this open circuit, we see that the only current conducted by resistance R2 is the input port current, I1. It follows that
Ming Hsieh Department of Electrical Engineering
- 124 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
I1
1
=
= 40 μS .
V1 I =0
R1 + R2
2
Since I2 = 0 delivers V1 = (R1 + R2)I1 and V2 = −AoV + R2I1 = −(AoR1 − R2)I1,
Ao R1 − R2
⎡V
V
I ⎤
g 21 = 2
= ⎢ 2 × 1⎥
= −
= − 219.88 volts/volt .
V1 I =0
I1 V1 ⎦
R1 + R2
⎣
=
I
0
2
2
g11 =
(2).
(E5-1)
(E5-2)
The circuit for computing g-parameters g12 and g22 is given in Figure (1.23c), which is the
structure of Figure (1.23a) with a short circuit imposed at its input port. With V1 = 0,
0 = ( R1 + R2 )I1 + R2 I 2 ,
(E5-3)
which leads immediately to
I1
R2
= −
= 120 mA/amp .
I 2 V =0
R1 + R2
1
Continuing with V1 = 0,
V2 = ro I 2 − AoV + R2 ( I1 + I 2 ) = ( ro + R2 )I 2 − ( Ao R1 − R2 )I1 .
With the help of (E5-4), we find that
g12 =
g 22 =
COMMENTS:
(E5-4)
(E5-5)
V2
= ro + ( Ao + 1 )( R1 R2 ) = 662.94 KΩ .
I 2 V =0
1
(E5-6)
In the heat of a detailed analysis, it is only human to incur mathematical
errors. While errors plague all humanity, engineers who customarily
commit them while assuming the responsibility for the design of reliable
and reproducible circuits destined for fabrication in inordinately expensive fabrication processes are banished to deserted islands divorced of
electronic components. It is therefore prudent to check and re-check
analyses and concomitant calculations and even to adopt simple validation procedures that test the propriety of relevant results. For example, if
Ao were zero in Figure (1.23b) (it likely can never be zero, but nevertheless, one of the many kudos of engineering academe is that nothing hinders the mathematical stipulation of a null gain), the resistance seen looking into the output port under the condition of a short circuited input port
is easily seen to be
ro + ( R1 R2 ) .
Referring to (E5-6), note that g22, which is indeed the short circuit output
resistance of the considered amplifier model, collapses to the quoted result if Ao = 0. This affirmation does not guarantee the correctness (E56), but a result that differs from reasonable expectations implies the presence of at least one error. At a minimum, a disparity between expectation and reality certainly warrants a reconsideration of the solution tack
adopted. An additional check is afforded by the observation that Ao = 0
reduces the network at hand to a passive, and therefore bilateral,
architecture. From (E5-2) and (E5-4), observe that Ao = 0 gives rise to
g12 = −g21, as expected.
1.2.5. MODEL SELECTION
The preceding subsections of material confirm that we can deploy as many as four
types of equivalent circuits to model the terminal volt-ampere characteristics of an electronic netMing Hsieh Department of Electrical Engineering
- 125 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
work that has been biased to ensure nominally linear processing of an applied input signal. Of
course, the number of choices may be less than four if one or more of the parametric matrices is
singular. For example, if the z-parameter matrix is singular, y-parameters do not exist and similarly, a singular g-parameter matrix precludes the exploitation of the hybrid h-parameters. But if
all four parameter sets subsist, questions naturally arise as to which of the four equivalent circuits
should be utilized in a given application. The somewhat cavalier answer is that the choice is
fundamentally immaterial because the interrelationship of all four sets of two port parameters
guarantees analytical consistency. From a practical perspective, however, a prudent modeling
choice can forestall profanity on the part of the individual confronted with a daunting analysis
problem.
The y-parameter and g-parameter equivalent circuits represent the input port of a linear
network by Norton equivalent circuits. Accordingly, y-parameters and g-parameters work
particularly well for networks whose input ports are driven by a signal current source, which is
otherwise referred to as a high impedance source. Moreover, y-parameters function best in
transimpedance amplifiers, which feature a low output impedance to facilitate the delivery of an
output voltage response that is nominally independent of the load termination. The requisite low
output impedance of a transimpedance unit is supported by the admittance, y22, which shunts the
output port of a y-parameter model and therefore reduces the achievable output impedance. On
the other hand, g-parameters work famously in current amplifiers. These amplifiers offer high
output impedance so that the output current, which is proportional to input current, can be delivered efficiently to a load termination. The presence of series impedance g22 at the output port of
a g-parameter model for a current amplifier hints at the possibility of realizing large output
impedance.
The h-parameter and z-parameter models feature Thévenin equivalent circuits at their
input ports. They are therefore most serviceable in linear networks whose input ports are driven
by voltage signals, which are commonly referenced as simply low impedance sources. Voltage
amplifiers, whose output ports are designed to offer low impedances so that their voltage responses can be transferred efficiently to a load termination, are best modeled by h-parameters.
As in the case of y22, h22 shunts the output port of an h-parameter model to reduce the observable
output impedance of a linear network. If for no other reason, the process of elimination suggests
the utility of z-parameter models in transadmittance applications. Like g22, the series impedance
presence of z22 at the output port of a z-parameter model bolsters the network output impedance.
Of course, high output impedance in a transadmittance amplifier facilitates a current response
that is nominally invariant with the load termination.
1.2.6. FEEDBACK ARCHITECTURES
We shall ultimately learn that many practical amplifiers exploit feedback applied externally to active devices and their subcircuits to achieve target performance specifications in a
predictable and reproducible fashion. This externally applied feedback supplements the internal
feedback (as measured by y12, z12, h12, or g12) invariably established within the two port subcircuits whose electrical interconnections comprise the amplifier topology earmarked for designoriented investigation. In these cases, the decision as to which of the four basic models should
be adopted is often made in terms of the external feedback circuit architecture, independent of
the nature of the source signal. Just as there are four basic models on which we can predicate an
electronic circuit analysis, there are only four fundamental feedback topologies, which suggests
that each feedback form has a preferred model embodiment.
Ming Hsieh Department of Electrical Engineering
- 126 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
1.2.6.1. Shunt-Shunt Feedback
When the input port of an extrinsic feedback network is connected in shunt with the input port of a base amplifier and when the output port of the same feedback subcircuit is in parallel with the output port of the base unit, the resultant circuit architecture is cleverly referred to as
shunt-shunt feedback. The shunting nature of the feedback subcircuit at both network ports
gives rise to potentially low input and output impedances. Since a low input impedance allows
for convenient processing of an applied current signal and low output impedance facilitates the
delivery of a voltage response to a load termination, the shunt-shunt feedback amplifier functions
optimally as a transimpedance amplifier (or transresistance amplifier if only low signal frequencies are addressed). This is to say that shunt-shunt feedback supports transimpedance signal
processing in the sense that the achieved transimpedance is approximately independent of the
source and load impedances.
I1b
+
V1
−
+
Zs
I1
−
Vs
−
Zs
I2a
I2
3
+
V2
4
(a).
1 I1
+
V1
−
Zl
−
-Circuit (a)-
2
+
−
Linear Model
Of Base
Amplifier
V1
−
+
V2
-Circuit (b)I1a
1
+
Vs
I2b
Linear Model
Of Feedback
Network
I2
1
y11b
1
y11a
y12bV2
2
y21aV1
1
y22a
1
y22b
3
+
V2
−
Zl
4
(b).
Figure (1.24). (a). System level abstraction of a shunt-shunt feedback amplifier. The base amplifier
has y-parameters yija, while the feedback circuit is characterized by admittance parameters of yijb. The entire network has y-parameters, yij = yija + yijb. (b). Approximate
equivalent circuit of the feedback architecture in (a). The model ignores feedback in the
base amplifier and feedforward in the feedback network.
The shunt-shunt feedback architecture in question is diagrammed in Figure (1.24a),
where the basic amplifier, which may or may not exude significant internal feedback, is labeled
as the “a” network. In a clarion demonstration of analytical creativity, the feedback component
is referenced as the “b” network. In practice, terminals 2 and 4 can be common with one another
and even grounded, but in the interest of generality, we shall sustain electrical independence of
the subject two terminals. Because of the shunt-shunt interconnection of the feedback subcircuit
with the two network ports, the I/O ports of both subcircuits support the same signal input port
voltage, V1, and the same signal output port voltage, V2. But the net signal input port current, I1,
which must be supplied by the signal source comprised of Thévenin voltage Vs and Thévenin
impedance Zs, is the sum of the currents, I1a and I1b, which respectively flow into the input ports
Ming Hsieh Department of Electrical Engineering
- 127 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
of the base amplifier and the feedback structure. Similarly, the net output port current conducted
by the load impedance, Zl, is necessarily the sum of the indicated output port currents, I2a and I2b.
Since the input ports of both the base amplifier and the feedback network support the
same signal voltage, V1, and the respective output ports share an identical signal voltage, V2, yparameter models, which invoke input and output port voltages as independent circuit variables,
are analytically expedient in shunt-shunt architectures. This contention stems from the following
straightforward analysis, which we begin by writing for the base amplifier,
⎡ I1a ⎤
⎡ y11a y12a ⎤ ⎡V1 ⎤
(1-37)
⎢I ⎥ = ⎢ y
⎥⎢ ⎥ ,
⎣ 2a ⎦
⎣ 21a y22a ⎦ ⎣V2 ⎦
while for the feedback subcircuit,
⎡ I1b ⎤
⎡ y11b y12b ⎤ ⎡V1 ⎤
(1-38)
=
⎢I ⎥
⎢y
⎥⎢ ⎥ ,
⎣ 2b ⎦
⎣ 21b y22b ⎦ ⎣V2 ⎦
where the appended subscripts, “a” and “b,” obviously refer to the base and feedback units,
respectively. Since
⎡ I1a ⎤
⎡ I1b ⎤
⎡ I1a + I1b ⎤
⎡ I1 ⎤
(1-39)
⎢I ⎥ = ⎢I ⎥ + ⎢I ⎥ = ⎢I + I ⎥ ,
2b ⎦
⎣ 2⎦
⎣ 2a ⎦
⎣ 2b ⎦
⎣ 2a
it follows that the two port equilibrium equations for the entire feedback interconnection are
⎡ ( y11a + y11b ) ( y12a + y12b ) ⎤ ⎡V1 ⎤
⎡ I1 ⎤
⎡ y11 y12 ⎤ ⎡V1 ⎤
(1-40)
⎥⎢ ⎥ ⎢
⎢ I ⎥ = ⎢( y
⎥ ⎢V ⎥ ,
y
y
y
+
+
V
y
y
)
(
)
21a
21b
22a
22b
2
21
22
2
⎣ 2⎦
⎣
⎦
⎣
⎦
⎣
⎦
⎣
⎦
which highlights the elegant mathematical simplicity of the overall y-parameter matrix. It is
important to understand that such simplicity is enabled solely because voltage V1 is common to
both base and feedback input ports, while voltage V2 is common to both output ports. We can
conclude, therefore, that the short circuit admittance parameters, yij, of the overall shunt-shunt
feedback system are sums of the corresponding parameters, yija and yijb, for the “a” and “b” structures.
In typical shunt-shunt feedback realizations, the magnitude of the feedforward
transadmittance, y21a, of the base amplifier is much larger than is the magnitude of the feedforward transadmittance, y21b, of the feedback component. Since the “21” two port parameter is a
measure of forward gain, y21a >> y21b simply affirms the presumption that most of the I/O gain is
supplied by the base amplifier. Such an operating circumstance is particularly true if the feedback structure is formed of a passive, bilateral network for which a forward gain exceeding one
is inherently impossible. With the possible exception of the very high signal frequencies that
challenge the performance capabilities of the base amplifier, feedback in the base amplifier, as
monitored by |y12a|, is commonly much smaller than |y12b| if for no other reason than the “b”
network is expressly appended to ensure substantial signal conditioning feedback over the frequency passband of the entire amplifier. The last two statements articulate the fundamental goal
of appending the indicated “b” network expressly for feedback with hopefully minimal feedforward. But the incorporated feedback does load the input and output ports of the amplifier so that
in general, no conclusions can be drawn about the relative values of |y11a| and |y11b| and |y22a| and
|y22b|. As a result of these observations, (1-40) can be approximated as
y12b
⎡( y11a + y11b )
⎤ ⎡V1 ⎤
⎡ I1 ⎤
(1-41)
⎥⎢ ⎥ .
⎢I ⎥ ≈ ⎢
y
y
y
+
V
(
)
21a
22a
22b
2
⎣ 2⎦
⎣
⎦
⎣
⎦
Ming Hsieh Department of Electrical Engineering
- 128 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
The immediate implication of the preceding expression is the equivalent circuit diagrammed in Figure (1.24b). An interesting feature of this model is the additional impedance,
1/y11b, imposed across the input port of the base amplifier, as well as the impedance, 1/y22b, appended in shunt with the output port. As such, the model unambiguously accounts for the loading effects of the feedback subcircuit on both the input and output ports of the base amplifier. To
the extent that feedback intrinsic to the base amplifier can be tacitly ignored, y12b, which derives
exclusively from the characteristics of the feedback subcircuit, appears as the feedback factor for
the entire amplifier. And if feedforward through the feedback subcircuit is negligible in
comparison to the feedforward afforded by the base amplifier, y21a, which is precipitated exclusively by the base amplifier, is the lone feedforward parameter of the structure.
1.2.6.2. Series-Series Feedback
I1 1
Zs
+
V1a
−
+
+
V1
−
Vs
−
3
kiI1
Linear Model
Of Base
Amplifier
-Circuit (a)-
I1b
1 I1
+
+
Vs
V1
−
koI2 −
+
V2
−
+
V1b
Linear Model
Of Feedback
Network
+
V2b
−
-Circuit (b)-
−
z11a
+
Zl
4
(a).
z22a
+
z21aI1
koz12b I2
−
−
kiz11b
koz22b
−
2
+
V2a
I2b
2
Zs
I2
I2
3
+
V2
Zl
−
(b).
4
Figure (1.25). (a). System level abstraction of a series-series feedback amplifier. The base amplifier has z-parameters zija, while the feedback circuit is characterized by open circuit
impedance parameters of zijb. (b). Approximate equivalent circuit of the feedback
architecture in (a). The model ignores feedback within the base amplifier and
feedforward incurred by the feedback network.
A series connection of both the input and output ports of a base amplifier and an external feedback subcircuit, as is depicted in Figure (1.25a), is known as a series-series feedback
amplifier. As we highlighted in the shunt-shunt architecture, terminals 2 and 4 can be electrically incident with one another. The indicated topological structure encourages high input and
output impedances, which makes the series-series architecture most suitable for transadmittance
amplification. These I/O impedances are potentially large expressly because the input and output
port voltages, V1 and V2, of the overall configuration is respectively the sum of the input and outMing Hsieh Department of Electrical Engineering
- 129 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
put port voltages of the amplifier and feedback unit; that is, and with reference to the subject figure,
⎡V1a ⎤
⎡V1b ⎤
⎡V1a + V1b ⎤
⎡V1 ⎤
(1-42)
⎢V ⎥ = ⎢V ⎥ + ⎢V ⎥ = ⎢V + V ⎥ .
2b ⎦
⎣ 2⎦
⎣ 2a ⎦
⎣ 2b ⎦
⎣ 2a
On the other hand, the net input port current, I1, which the signal source supplies, routes through
the input ports of both the amplifier and the feedback structure. But in some two port networks,
and particularly in two port, three terminal models of active devices and amplifier blocks, we
shall find that the input port current does not simply circulate around the loop formed by the two
terminals of the port. Instead, some of this current may be diverted to the output port. For this
reason, the diagram in Figure (1.25a) depicts an amplifier input port current of I1 and a return
input port current of kiI1, which flows as current I1b into the input port of the feedback circuit.
The same logic allows a return current of koI2 at the amplifier output terminal, where it is noted
that I2b = koI2. Thus,
I1b = ki I1
(1-43)
I 2b = ko I 2
and to keep Kirchhoff happy, ki and ko are factors (possibly frequency variant factors) that satisfy
(1-44)
( 1 − ki ) I 1 + ( 1 − ko ) I 2 = 0 .
Strictly speaking, (1-43) implies that the respective input and output ports are no longer in series
with one another but nonetheless, the architecture is unwaveringly referred to as a series-series
feedback configuration.
The Thévenin nature, and thus series electrical temperament, of the input and output
ports in a z-parameter equivalent circuit is a clue that z-parameters, which adopt port currents as
independent variables, might be profitably exploited in series-series feedback systems. To this
end, we write
⎡V1a ⎤
⎡ z11a z12a ⎤ ⎡ I 1 ⎤
(1-45)
⎢V ⎥ = ⎢ z
⎥⎢ ⎥ ,
⎣ 2a ⎦
⎣ 21a z22a ⎦ ⎣ I 2 ⎦
for the base amplifier, and
ko z12b ⎤ ⎡ I 1 ⎤
⎡V1b ⎤
⎡ z11b z12b ⎤ ⎡ I1b ⎤
⎡k z
(1-46)
= ⎢ i 11b
⎢V ⎥ = ⎢ z
⎥
⎢
⎥
⎥⎢ ⎥ ,
⎣ 2b ⎦
⎣ 21b z22b ⎦ ⎣ I 2b ⎦
⎣ ki z21b ko z22b ⎦ ⎣ I 2 ⎦
for the feedback subcircuit, where (1-43) has been applied. The substitution of the last two results into (1-42) readily delivers
⎡ ( z11a + ki z11b ) ( z12a + ko z12b ) ⎤ ⎡ I1 ⎤
⎡V1 ⎤
=
(1-47)
⎥⎢ ⎥ ,
⎢
⎢V ⎥
⎣ 2⎦
⎣( z21a + ki z21b ) ( z22a + ko z22b ) ⎦ ⎣ I 2 ⎦
which suggests immediately that the entire structure in Figure (1.25a) can be represented by a zparameter model whose open circuit impedances subscribe to
⎡ ( z11a + ki z11b ) ( z12a + ko z12b ) ⎤
⎡ z11 z12 ⎤
=
(1-48)
⎥.
⎢
⎢z
⎥
⎣ 21 z22 ⎦
⎣( z21a + ki z21b ) ( z22a + ko z22b ) ⎦
As indicated in conjunction with the shunt-shunt feedback architecture, the feedback
associated with the entire structure is likely to be dominated by the feedback implicit to the feedback subcircuit; that is, |z12a| << |koz12b|. Moreover, overall feedforward, on which the net forward gain is dependent, is dominated by the base amplifier so that |z21a| >> |kiz21b|. Under these
circumstances, (1-48) implies the ability to model the linear characteristics of the series-series
Ming Hsieh Department of Electrical Engineering
- 130 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
feedback architecture by the equivalent circuit given in Figure (1.25b). Observe the branch
impedance, kiz11b, in the loop associated with the input port of the amplifier and the appearance
of a branch impedance, koz22b, in series with the output port loop. These elements suggest that
series-series feedback is likely to increase both the input and output impedances of the base
amplifier. Since high impedance input ports accept voltage signals with minimal attenuation and
high output port impedances efficiently transfer current responses to load terminations, the series-series feedback amplifier is best suited for transadmittance signal processing.
1.2.6.3. Series-Shunt Feedback
The third type of feedback system is the series-shunt architecture depicted in Figure
(1.26a). As we can garner from the architecture nomenclature, the input ports of the base amplifier and the feedback topology are electrically connected in series with one another, thereby
encouraging high input impedance. Moreover, the output ports of these networks are connected
in parallel with one another, which manifests potentially low output impedance. Accordingly,
the series-shunt feedback architecture is well suited for voltage amplifier applications.
In Figure (1.26a), the net input port current, I1, supplied by the signal source flows
through the input port of the base amplifier and thence on into the input port of the feedback
structure. As is the case with the input port of the base amplifier deployed in series-series feedback, the input port current returned by the present base amplifier is kiI1. Accordingly, (1-43)
remains applicable for current I1b, which is conducted by the input port of the feedback subcircuit. The overall output port situation is simpler in that the overall voltage response, V2, developed across the load termination is sustained across the output ports of both the base amplifier
and feedback structures.
The currents flowing in the input ports of both the base amplifier and the feedback
structure are proportional to the net input current, I1, while the respective output port voltages are
identical to signal voltage, V2. These facts are a clue that h-parameter modeling, which invokes
net input port current and net output port voltage as independent electrical variables is optimal
for the series-shunt feedback architecture. Specifically, the h-parameter equivalent circuit projects a Thévenin type (series) input port representation and a Norton type (shunt) output port
description. From Figure (1.26),
⎡V1a ⎤
⎡V1b ⎤
⎡V1a + V1b ⎤
⎡V1 ⎤
(1-49)
⎢I ⎥ = ⎢I ⎥ + ⎢I ⎥ = ⎢I + I ⎥ .
2b ⎦
⎣ 2⎦
⎣ 2a ⎦
⎣ 2b ⎦
⎣ 2a
Moreover,
⎡V1a ⎤
⎡ h11a h12a ⎤ ⎡ I1 ⎤
⎢ I ⎥ = ⎢h
⎥⎢ ⎥ ,
⎣ 2a ⎦
⎣ 21a h22a ⎦ ⎣V2 ⎦
for the base amplifier, while for the feedback unit,
⎡V1b ⎤
⎡ ki h11b h12b ⎤ ⎡ I1 ⎤
⎢ I ⎥ = ⎢k h
⎥⎢ ⎥ .
⎣ 2b ⎦
⎣ i 21b h22b ⎦ ⎣V2 ⎦
It follows that
⎡ ( h11a + ki h11b ) ( h12a + h12b ) ⎤ ⎡ I1 ⎤
⎡V1 ⎤
⎥⎢ ⎥ ,
⎢ I ⎥ = ⎢( h
k
h
h
h
+
+
)
(
)
21a
i
21b
22a
22b
⎣ 2⎦
⎣
⎦ ⎣V2 ⎦
Ming Hsieh Department of Electrical Engineering
- 131 -
(1-50)
(1-51)
(1-52)
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
I1 1
Zs
+
V1
−
Vs
−
kiI1
Linear Model
Of Base
Amplifier
1 I1
+
V1b
Linear Model
Of Feedback
Network
−
-Circuit (b)-
+
+
Vs
V1
h11a
+
V2
−
Zl
4
(a).
I2
+
−
h21 aI1
−
3
+
h12b V2
kih11b
−
−
I2b
I1b
I2
+
V2
-Circuit (a)-
2
Zs
3
I2a
+
V1a
−
+
J. Choma
1
h22a
1
h22b
V2
Zl
−
2
4
(b).
Figure (1.26). (a). System level abstraction of a series-shunt feedback amplifier. The base amplifier has h-parameters hija, while the feedback circuit is characterized by hybrid hparameters of hijb. (b). Approximate equivalent circuit of the feedback architecture
in (a). The model ignores feedback within the base amplifier and feedforward incurred by the feedback network.
where it is understood that the effective matrix of h-parameters for the series-shunt feedback
amplifier is
⎡ ( h + ki h11b ) ( h12a + h12b ) ⎤
⎡ h11 h12 ⎤
= ⎢ 11a
(1-53)
⎥.
⎢h
⎥
⎣ 21 h22 ⎦
⎣( h21a + ki h21b ) ( h22a + h22b ) ⎦
If, as is typically the case, feedforward through the base amplifier prevails over the
feedforward characteristic of the feedback subcircuit and if intrinsic feedback within the base
amplifier is negligible, (1-53) gives rise to the approximate equivalent circuit shown in Figure
(1.26b). The appearance of the element, kih11b, as a branch impedance in series with the input
port of the series-series interconnection encourages high input impedance. On the other hand,
the shunting action of the impedance, 1/h22b, across the output port diminishes the achievable
output impedance. It follows that the series-series feedback amplifier enjoys utility in applications for which a specified voltage gain is targeted to be nominally independent of source and
load terminations.
Ming Hsieh Department of Electrical Engineering
- 132 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
1.2.6.4. Shunt-Series Feedback
3
I1a
Linear Model
Of Base
Amplifier
+
V1
−
I1 1
Zs
+
-Circuit (a)I1b
+
V1
Vs
−
−
2
Zs
koI2 −
V1
+
V2b
-Circuit (b)-
−
−
g22a
g21aV1
1
1
g11a
kog12 bI2
−
kog22b
−
Zl
4
(a).
+
g11b
+
V2
−
Linear Model
Of Feedback
Network
1 I1
+
Vs
+
V2a
I2b
+
I2
I2
3
+
V2
Zl
−
2
4
(b).
Figure (1.27). (a). A shunt-series feedback amplifier. The base amplifier has g-parameters gija, while
the corresponding feedback circuit parameters are gijb. (b). Approximate equivalent circuit of the feedback architecture in (a). The model presumes negligible feedback in the
base amplifier and negligible feedforward through the feedback network.
It is hardly rocket science to surmise now that the final feedback form warranting
consideration is the shunt-series feedback amplifier, whose topology appears in Figure (1.27a).
In this topology, the input ports of the base amplifier and feedback unit are electrically in parallel, while their output ports are connected in series. Consequently, low input and high output
impedances are fashioned by this interconnection, which is therefore tailor made for current
amplification. As in the case of series-series feedback, the amplifier return current at the output
port is adjusted by a factor of ko.
The hybrid g-parameters are best suited for modeling the system at hand. The analysis
proceeds along lines analogous to those invoked on the series-shunt structure. The reader is
encouraged to confirm that the hybrid g-parameter volt-ampere relationships of the overall shuntseries network derive from
⎡ ( g11a + g11b ) ( g12a + ko g12b ) ⎤ ⎡V1 ⎤
⎡ I1 ⎤
=
(1-54)
⎥⎢ ⎥ .
⎢
⎢ ⎥
⎣V2 ⎦
⎣( g 21a + g 21b ) ( g 22a + ko g 22b ) ⎦ ⎣ I 2 ⎦
The corresponding approximate equivalent circuit is given as Figure (1.27b). This model, like its
predecessors, is premised on the presumptions of negligible feedback internal to the base amplifier and negligible feedforward through the feedback subcircuit.
Ming Hsieh Department of Electrical Engineering
- 133 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
1.3.0. ANALYSIS OF LINEARIZED ACTIVE NETWORKS
The four two port models allow for unambiguous transfer function and I/O impedance
characterizations of any linear two port network in terms of parameters extracted from observable voltage and current responses at the network ports. These models are the fundamental tools
that expedite a computationally efficient and insightful analysis of electronic systems. They are
especially germane to those electronic systems whose intrinsic circuit topologies are either unknown or too complicated for straightforward circuit analyses predicated on the traditional
Kirchhoff laws.
1.3.1. ANALYSIS VIA y-PARAMETERS
Recalling Figure (1.2a), the y-parameter equivalent circuit at a known quiescent operating point imposed on the electronic system of Figure (1.1a) is the topology given in Figure
(1.28). Because y-parameter equivalent circuits exploit a Norton topology for their input port, it
is convenient to represent the signal source as a Norton equivalent structure. In this Norton
representation, the short circuit signal current is Is, and the presumably large shunt impedance is
Zs. Our inspection of the subject model reveals
y21V1
V2 = −
(1-55)
y22 + Yl
and
(1-56)
I s = ( y11 + Ys )V1 + y12V2 ,
where Yl = 1/Zl and Ys = 1/Zs symbolize the admittances of the load and source impedances,
respectively. If we insert (1-55) into (1-56), we obtain
y12 y21V1
I s = ( y11 + Ys )V1 −
,
(1-57)
y22 + Yl
1 I1
Is
Zs
+
V1
−
I2
Linear Model
Of Electronic
Network
2
3
+
V2
−
4
1 I1
Is
+
V1
−
Zs
Yin
Zl
I2
1/y11
y12 V2 y21V1
2
1/y22
3
+
V2
−
4
Zl
Yout
Figure (1.28). The y-parameter equivalent circuit for a linear model of an electronic network. The electronic network is suitable for transimpedance signal processing. The applied input signal
is represented as an independent current source because of the Norton nature of the yparameter input port model.
which captures the equilibrium condition by which the load admittance, Yl, affects the value of
the signal source current, Is, that is required to sustain a given input port voltage, V1. The
combination of (1-57) and (1-55) delivers a system transimpedance, Zfs = V2/Is, of
Ming Hsieh Department of Electrical Engineering
- 134 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
y21
( y11 + Ys )( y22 + Yl )
(1-58)
=
Z fs .
y12 y21
Is
1−
( y11 + Ys )( y22 + Yl )
Obviously, we can convert this transimpedance, which is the ratio of the independent output port
variable to the signal source current that activates the input port, to a transadmittance, voltage
gain, or current gain by noting that I2 = −YlV2 and by recognizing that the Norton source current
is related to its Thévenin source voltage, say Vs, by Is = YsVs.
−
V2
1.3.1.1. Transfer Function And Gain Metrics
The algebraic sloppiness of the gain expression in (1-58) hardly fosters engineering
confidence, and it certainly does not lend itself toward forging design insights relevant to the dynamic behavior of the system undergoing investigation. But a more constructive format begins
to emerge from the substitution,
y21
(1-59)
Z fo = −
,
( y11 + Ys )( y22 + Yl )
whereupon (1-58) becomes the significantly simpler equation,
V
Z fo
Z fs 2 =
.
(1-60)
Is
1 + y12 Z fo
The last result is equivalent to the algebraic relationship,
V2 = Z fo ( I s − y12V2 ) ,
Is
+
Σ
Is − y12V2
Zfo
(1-61)
V2
−
y12V2
y12
Figure (1.29). Signal flow representation of the I/O transfer characteristics
for the circuit in Figure (1.24). The diagram highlights the
feedback, as manifested by parameter y12, inherent to the
subject circuit.
which maps into the block, or signal flow, diagram we provide in Figure (1.29). The block diagram is a conceptually useful design-oriented analysis tool in that it enables an engineering
perspective to be ascribed to the various model and algebraic parameters introduced in the
foregoing gain derivation. For example, the y-parameter, y12, is clearly portrayed in Figure
(1.29) as a feedback metric in that a current, y12V2, which is obviously proportional to the output
response, V2, is returned directly to the input port where it is algebraically summed with the signal source current. The summing action is accomplished merely through Kirchhoff’s current law
(KCL) applied to the input port node. We note that the resultant current difference signal, (Is −
y12V2), which is commonly referred to as the error signal in a feedback network, must have a
magnitude that is smaller than that of the prevailing signal current, Is, for otherwise, V2 is unbounded as a direct result of the prevailing feedback. This latter contention is intimately related
Ming Hsieh Department of Electrical Engineering
- 135 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
to the problem of ensuring electronic network stability, about which far more is proffered in due
course. When the magnitude of the error signal is smaller than the magnitude of the applied input signal source (current Is in this case), we say that negative feedback prevails in the subject
feedback network.
Our further study of the block diagram at hand divulges that a closed loop path from the
input port to the output port and back to the input port is established by the blocks labeled Zfo and
y12. This closed loop encourages referencing the transimpedance, Zfs, in (1-60) as the closed loop
(transimpedance) gain of the electronic network. In other words, the closed loop gain is the actual transimpedance achieved when the effects of all model elements in the system, including the
feedback vehicle, are absorbed into the circuit analysis venture. The loop is broken, or opened,
when the feedback factor is set to zero, whence the transimpedance reduces to Zfs = Zfo. Since
y12 = 0 effectively breaks the closed loop we have uncovered, Zfo is known as the open loop gain
of the network undergoing investigation. In effect, the open loop gain of an electronic network is
the ratio of the output port response to the error signal. Moreover, Zfo happens to be the effective
overall gain of the network for the special case of null feedback. Of course, the loop can be
opened by setting Zfo to zero. But such action comprises engineering foolishness in that Zfo = 0
severs the signal path from input to output ports and therefore precludes the possibility of any
nonzero I/O gain.
The aforementioned closed loop path forged by the open loop gain block and the feedback factor block manifests a net loop gain, Ty(Ys, Yl), given by
y12 y21
(1-62)
T y (Ys ,Yl ) = y12 Z fo = −
,
( y11 + Ys )( y22 + Yl )
where subscript “y” reminds us that we have adopted y-parameters for the circuit analysis.
Moreover, the functional dependence on the source admittance, Ys, and load admittance, Yl,
incorporated into the loop gain notation derives from the dependence of the open loop gain on
these admittance terminations. A related metric, Fy(Ys, Yl), which is known as the return difference of the network undergoing study, is simply the ratio of the open loop gain to the closed loop
gain. Thus, the return difference is the factor by which the open and closed loop gains differ owing to the presence of feedback. We observe that the loop gain is zero and the return difference
is one when no feedback is embedded into the network. Recalling (1-60),
V
Z fo
Z fo
Z fo
Z fs 2 =
=
=
,
(1-63)
Is
1 + y12 Z fo
1 + Ty (Ys , Yl )
Fy (Ys , Yl )
where
Fy (Ys , Yl ) Z fo
Z fs
≡ 1 + T y (Ys , Yl ) .
(1-64)
One immediately evident attribute of the return difference function is that in principle,
it elegantly conveys the necessary condition underlying system stability. In particular, the return
difference is a function of frequency and thus, the Laplace operator, “s,” because of the nature of
the source and load terminations and energy storage implicit to the base amplifier and feedback
subcircuits. As such, the roots of Fy(Ys, Yl), which are the poles of the I/O closed loop transimpedance, must lie in the left half s-plane; that is, the real parts of all of these roots must be negative numbers. The assurance of only left half plane poles guarantees that time domain responses
to any type of input signal excitation remain forever bounded. As interjected earlier, stability
fans are asked to await a forthcoming chapter for relevant design requirements and details.
Ming Hsieh Department of Electrical Engineering
- 136 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
Return to (1-63) or (1-60) and consider the case of a stable system in which the magnitude of the loop gain is far greater than unity; that is, |Ty(Ys, Yl)| = |y12Zfo| >> 1. Under this
condition, the closed loop transimpedance reduces to the magnificently simple disclosure,
V
1
(1-65)
Z fs = 2
≈
.
Is
y12
|y12 Z fo |>>1
In other words, a very large loop gain in a stable electronic network modeled by y-parameters
produces a closed loop transimpedance that depends on only the feedback factor, y12. This result
contrasts sharply with (1-60), which with the help of (1-59), shows a closed loop transimpedance
that is dependent on six parameters.
The result advanced by (1-65) is interesting from at last three perspectives that are pivotal to the task of insightfully formulating meaningful design guidelines. First, the gain in (1-65)
is independent of source and load terminations, thereby rendering the given network suitable for
a broad variety of general system applications. Second, the closed loop gain is invariant with the
open loop gain in (1-59), which implies that the y-parameters, y11, y21, and y22, are nominally
irrelevant with respect to the closed loop performance of the amplifier. Processing and
manufacturing vagaries, operating temperature changes, parasitic uncertainties associated with
circuit layout and/or device modeling, and other engineering problems invariably alter the measured values of one or more of these admittance parameters. But for very large loop gain systems,
these potentially significant parametric shifts have essentially no impact on the observable closed
loop performance predicted by (1-65). To the extent that parameter y12 can be rendered
independent of the quiescent operating point of the network, standby voltage or current fluctuations incurred by poorly regulated static supplies, temperature variations, or even excessive signal strengths applied to the open loop component of the system, we can conclude that the closed
loop gain is accurately predictable and reliably reproducible.
The elimination, or at least circumvention, of the effects of the foregoing environmental
issues is a fundamental objective of all circuit design endeavors. Such prudent design results in
circuits that can be produced to meet stipulated performance specifications reliably and
reproducibly. The design issue here is transparent. In particular, Zfs in (1-65) depends on one
parameter, while the general expression for Zfs in (1-60) is a function of six parameters (source
and load admittances included). One parameter can arguably be controlled easier than can six. It
follows that an electronic circuit whose I/O transfer characteristics abide by (1-65) is robust in
the sense of its relative insensitivity to the deleterious ramifications of design, manufacturing,
and both engineering and environmental uncertainties.
The third interesting perspective fostered by (1-65) is that on the reasonable presumption of a design goal that nurtures a greater than unity magnitude of closed loop gain, the magnitude of the feedback parameter, y12, must be correspondingly smaller than one siemen (or mho).
But since (1-65) requires |y12Zfo| >> 1, this feedback factor limitation implies that the magnitude
of the open loop gain, Zfo, must be very large. We note that while Zfo is indeed a function of five
parameters, the numerical values of most or all of which may be difficult to predict and control
precisely, it is not necessary that Zfo be obligated to a particular numerical value; instead, it simply must exude a sufficiently large magnitude that satisfies the inequality, |y12Zfo| >> 1. Thus,
the requisite design tack is to ensure that very large loop gain be achieved for worst case operating circumstances. We deduce from (1-65) that |y12Zfo| >> 1 must therefore be satisfied for the
smallest estimated magnitude of the forward gain metric, y21, and the largest anticipated magnitudes of the admittances, y11, y22, Ys, and Yl.
Ming Hsieh Department of Electrical Engineering
- 137 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
Engineers are invariably prone to adopting extreme analytical measures as a prelude to
simplified design. One example of this professional affliction is that they often capitalize on the
large loop gain stipulation that generates (1-65) as an expression for an approximate closed loop
gain by adopting the measure of an infinitely large magnitude, |Zfo|, of open loop gain. If, in
fact, |Zfo| = ∞, but the network output response, V2 is nonetheless finite, we see that (1-65) forces
an approximate null value to the error signal input to the open loop component of the amplifier.
But if we carefully scrutinize the model of Figure (1.28), we conclude that Is = y12V2 if and only
if the input port signal voltage, V1, is reduced to zero. Accordingly, the tacit presumption of an
infinitely large open loop gain as a means of establishing an infinitely large loop gain in the electronic network of Figure (1.28) translates to a virtual short circuit at the network input port.
While infinitely large open loop gain is hardly reflective of engineering pragmatics, its
mathematical implication can often be exploited gainfully to arrive quickly at a first order
analytical estimate of the closed loop performance of a potentially complex electronic system.
You have likely witnessed this simplified analytical state when you have dealt with negative
feedback applied around operational amplifiers. To this end and assuming that the incorporated
feedback establishes a very large loop gain, recall that the presumption of a virtual ground at the
op-amp input port led directly and straightforwardly to an analytical expression of the overall
closed loop gain of the entire network.
1.3.1.2. Circuit Interpretation of the Loop Gain
The gain around a circuit loop, or loop gain, is a critically important circuit metric in
that it effectively measures the quality of a feedback system in at least the senses of closed loop
network stability and the desensitization of the closed loop gain with respect to open loop
parametric uncertainties. As is demonstrated in the following subsection, the loop gain is even
critically important to the problems of determining the input and output impedances of a feedback network. Accordingly, a clear understanding of the manner in which a given circuit forges
its loop gain is vital for innovative and creative circuit design. In order to examine this loop gain
from an engineering perspective, return to the block diagram of Figure (1.29) and consider the
case of zero input signal; in this case, Is = 0. The output voltage response, V2, obviously vanishes in the absence of source excitation. A non-vanishing response in the face of zero input signal is indicative of either an unstable system (at least one closed loop pole lies in the right half
plane) or a system whose designer is a viable candidate for Nobel distinction in that said system
produces output signal energy despite the absence of applied input energy. With Is sustained at
zero, let the loop be broken between the output port and the feedback network input port. The
input port to the feedback subcircuit normally accepts a voltage input as per Figure (1.29) but in
this broken loop case, allow an independent and phase-inverted test voltage signal, say −Vtest, to
be applied to the feedback subcircuit, as indicated in Figure (1.30a). The resultant response of
the feedback block is −y12Vtest, and with Is = 0, the error signal applied to the open loop component of the system is merely +y12Vtest. It follows that this input excitation manifests an output,
V2, of +y12ZfoVtest, whence the gain, V2/Vtest, around the entire modified network loop is seen to
be y12Zfo. From (1-62), this voltage gain is precisely the loop gain of the original feedback network. It is important to comprehend the product, y12Zfo, as signifying the gain around the entire
network loop, for the response evaluated under the special test condition is extracted at the same
node to which the phase-inverted test signal is applied.
Ming Hsieh Department of Electrical Engineering
- 138 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
+
Is
=0
Σ
+y12Vtest
J. Choma
Zfo
V2
= y12 ZfoVtest
y12
−Vtest
−
−y12Vtest
(a).
V2
y12 y21
= −
Vtest
( y11 + Ys )( y 22 + Yl )
1 I1
Zs
+
V1
−
I2
1/y11
y12 Vtest y21V1
2
1/y22
3
+
V2
−
Zl
4
(b).
Figure (1.30). (a). The block diagram of Figure (1.29) with the feedback loop broken
and a test voltage signal, −Vtest, inserted at the input port of the feedback subcircuit. (b). The y-parameter equivalent circuit of the system
captured in (a). Note that the direction of the feedback controlled
source is reversed to reflect the test condition of an input signal, −Vtest,
applied to the input port of the feedback unit.
With Is = 0 and with an input signal, −Vtest, applied to the input port of the feedback
unit, the y-parameter equivalent circuit drawn in Figure (1.28) becomes the network shown In
Figure (1.30b). In this representation, we reverse the polarity of the original feedback current,
y12V2, to account for the test condition input, −Vtest, applied to the feedback subcircuit. Note further that the revised model reflects no feedback presence and that an effective input signal,
y12Vtest, is applied to the amplifier input port in a fashion that mirrors the application of the original signal source, Is. But since no feedback prevails herewith, the input of y12Vtest is effectively
applied to the input port of the open loop component of the feedback architecture. A straightforward circuit analysis predicated on the subject model reveals a voltage ratio, V2/Vtest, that is
identical to the loop gain function appearing on the far right hand side of (1-62). It is important
to remember that the y-parameters, yij, embedded in this test model are the net admittance
parameters of the entire feedback circuit and not just the parameters of the base amplifier.
1.3.1.3. Input And Output Admittances
In addition to quantifying the transfer function of a linear network, the loop gain introduced in the preceding subsection plays a pivotal role in the determination of the driving point
admittances of the network. The driving point input admittance is the input admittance “seen”
by the entire signal source (inclusive of the source admittance) with the output port terminated in
the actual load impedance. Similarly, the driving point output admittance is the admittance
effectively shunting the terminating load impedance, with the signal source supplanted by its
internal impedance. The model pertinent to an evaluation of the input admittance is shown in
Figure (1.31a), while its output admittance counterpart appears in Figure (1.31b). In the former
case, the signal source comprised of the shunt interconnection of current Is and admittance Ys is
replaced by an ideal independent current source, Ix. This independent current manifests a
Ming Hsieh Department of Electrical Engineering
- 139 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
terminal voltage, Vx, in disassociated reference polarity to Ix, so that the desired input admittance
is the current to voltage ratio, Ix/Vx. In effect, a mathematical ohmmeter is incident with the input port, divorced of the signal source circuit. An analogous “ohmmeter” supplants the load
admittance, Yl in Figure (1.31b), where it should be noted that the signal source is represented by
its original shunting impedance, Zs.
1 I1
+
Vx
−
Ix
+
V1
−
Yin
2
1/y11
1/y22
y12 V2 y21V1
+
V1
−
2
y12 V2 y21V1
(b).
Zl
4
I2
1/y11
+
V2
−
(a).
1 I1
Zs
3
I2
1/y22
3
+
V2
−
4
+
Vx
−
Ix
Yout
Figure (1.31). (a). The y-parameter model pertinent to computing the driving point input admittance of
the electronic network in Figure (1.24). (b). The y-parameter model pertinent to computing the driving point output admittance of the electronic network in Figure (1.24).
The driving point input admittance has all but been determined by (1-57). Comparing
Figure (1.31a) with Figure (1.28), the only differences are (1) the source admittance is set to zero
(equivalent to infinitely large source impedance Zs), (2) current Is is replaced by the “ohmmeter”
current, Ix, and (3) voltages V1 and Vx both represent potentials developed across the input port.
Thus, the driving point input admittance, Yin, is
⎡
⎤
I
I
y y
y12 y21
= y11 − 12 21 = y11 ⎢1 −
Yin = x = s
(1-66)
⎥.
Vx
Vs Y =0
y22 + Yl
y11 ( y22 + Yl ) ⎦
⎣
s
While authors, and particularly authors who are university professors, never commit errors, it is
nonetheless prudent to validate (1-66) for at least one special case. In particular, observe as expected that Yin collapses to y11 (the short circuit input admittance) if the load admittance, Yl, is
infinitely large, which is tantamount to a short circuited load impedance.
An especially useful form of (1-66) evolves from the use of (1-62). To wit,
I
Yin = x = y11 ⎡⎣1 + T y (0,Yl ) ⎤⎦ ,
(1-67)
Vx
where Ty(0, Yl) is the originally computed loop gain, Ty(Ys, Yl), evaluated under the condition of
Ys = 0. This result reveals several interesting properties of the transimpedance amplifier. First,
parameter y11, in addition to symbolizing the short circuit input admittance of the amplifier, can
be viewed as the open loop input admittance for with y12 = 0, whence Ty(0, Yl) = 0. Resultantly,
we can interpret the driving point input admittance predicted by (1-67) as the closed loop input
admittance. Second, the driving point input admittance of a stable transimpedance feedback
amplifier is likely to be bolstered by feedback. This admittance enhancement is especially pronounced if the amplifier is designed to deliver an I/O transimpedance that approximates the inverse of the feedback parameter, y12. In such a case, a very large loop gain is mandated and since
|Ty(0, Yl)| is larger than |Ty(Ys, Yl)| owing to the inverse dependence of the loop gain on source
Ming Hsieh Department of Electrical Engineering
- 140 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
admittance, Yin is potentially significantly larger than is its open loop counterpart. This situation
is good news for in a transimpedance amplifier, low and even ideally zero, driving point input
impedance is desired to promote an input port signal current that is virtually identical to the applied signal source current.
Returning to Figure (1.31) KCL applied to the output port of the model in Figure
(1.31b) gives
I x = y22Vx + y21V1 ,
(1-68)
where
y V
V1 = − 12 x
(1-69)
y11 + Ys
and we have made use of the fact that the output port voltage, V2, is identical to the “ohmmeter”
voltage, Vx. Subsequent to substituting (1-69) into (1-68), the driving point, or closed loop, output admittance, Yout, is found to be
⎡
⎤
I
y y
y12 y21
Yout = x = y22 − 12 21 = y22 ⎢1 −
(1-70)
⎥.
Vx
y11 + Ys
y22 ( y11 + Ys ) ⎦
⎣
Appealing to (1-62) once again,
I
Yout = x = y22 ⎡⎣1 + T y (Ys ,0 ) ⎤⎦ ,
(1-71)
Vx
where Ty(Ys, 0) is the loop gain, Ty(Ys, Yl), evaluated for Yl = 0. The similarity between this last
result and (1-67) for the input admittance is indisputable. It is therefore hardly surprising that the
commentary offered with respect to the input admittance function applies to the output admittance as well. In brief, y22 represents the open loop output admittance, which is likely to be
appreciably enhanced in a transimpedance unit by the feedback embedded therein.
EXAMPLE #1.6:
Figure (1.32) is a low frequency model of a single transistor amplifier that incorporates
a feedback resistance identified as Rf. Although the amplifier is fundamentally a
transimpedance unit, the closed loop transfer function of interest herewith is the voltage
gain, V2/Vs. To this end, derive general expressions for the open loop voltage gain, loop
gain, and closed loop voltage gain. Also, give general expressions for the open loop and
closed loop input and output driving point resistances, Rin and Rout, respectively, of the
feedback amplifier. Numerically evaluate all of the foregoing metrics for Rs = 300 Ω, ri
= 4 KΩ, Rf = 2.7 KΩ, ro = 40 KΩ, Rl = 5 KΩ and finally, β = 150 amps/amp.
Rin
V1
I1
Rs
+
Rout
Rf
I2
V2
I
ri
βI
ro
Rl
Vs
−
Ming Hsieh Department of Electrical Engineering
- 141 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
Figure (1.32). Linearized low frequency model of the transimpedance
amplifier considered in Example #1.6. Feedback is
implemented in the form of the resistance, Rf.
SOLUTION #1.6:
(1).
Figure (1.33a) redraws the schematic diagram of Figure (1.32) to highlight the connection of
resistance Rf as a feedback branch connected in shunt-shunt with the base amplifier. Although Rf is merely a conventional two terminal resistance, it can nonetheless be viewed as a
two port network in that its connection to the input port of the base amplifier shares the
ground node of said amplifier. A similar statement can be proffered about its connection to
the output port. If we adopt the notation advanced by (1-38), it is readily apparent that for
the resistive feedback circuit,
I
I
1
(E6-1)
y11b = 1b
=
≡ y22b = 2b
V1 V =0
Rf
V2 V =0
2
1
and
I 1b
I
1
= −
≡ y21b = 2b
.
V2 V =0
Rf
V1 V =0
1
2
Obviously, y12b ≡ y21b because of the passivity of the feedback resistance.
y12b =
(2).
(E6-2)
The base amplifier in Figure (1.33a) delivers
I
1
y11a = 1a
=
,
V1 V =0
ri
(E6-3)
and recognizing that with V2 = 0, I2 = βI = βV1/ri,
I
β
y21a = 2a
=
.
V1 V =0
ri
(E6-4)
2
2
Continuing while noting that the controlling current, I, for the dependent generator, βI, is
identical to the input port current, I1a, of the base amplifier,
I
1
(E6-5)
y22a = 2a
=
,
V2 V =0
ro
1
and
I1a
(E6-6)
= 0.
V2 V =0
1
The last result confirms that the base amplifier boasts no internal feedback.
Before proceeding further with the solution to this problem, a few sidebars may prove to be
instructive. In particular, (E6-1) through (E6-6) can be substituted into (1-40), and the resultant equations can be written out, albeit on scratch paper. An inspection of these port
equilibrium relationships suggests that the original circuit is electrically identical to the
network offered in Figure (1.33b). Although the latter circuit is not especially inviting from
a sheer circuit analysis perspective, it does underscore elegantly the various ramifications of
appending resistive feedback in shunt-shunt connection to a base amplifier.
(a). Observe that resistance Rf appears in shunt with both the input and output ports of the
base amplifier, thereby suggesting that the appended feedback resistor exacerbates the
impedance loading imposed on these ports. Clearly, too small of a resistance causes
diminished voltage gain because the input and output ports ultimately begin to resemble
a short circuit in the limit of extremely small Rf.
y12a =
Ming Hsieh Department of Electrical Engineering
- 142 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
Rf
I1b
V1
I2b
I1a
I1
J. Choma
I2a
I2
V2
I
Rs
ri
+
βI
ro
Rl
Vs
−
(a).
V1
I2
I1
I
Rs
Rf
+
Vs
−
V2
ri
V2
Rf
βI
V1
Rf
ro
Rf
Rl
Rout
Rin
(b).
Figure (1.33). (a). The amplifier model of Figure (1.32) with resistance Rf relocated to confirm its
function as shunt-shunt feedback with the base amplifier. (b). Alternative model to
the structure in (a), which expressly delineates the effects that feedback resistance Rf
exerts on the base amplifier.
(b). Note that a controlled current source of value V1/Rf is manifested directly across the
controlled source, βI, at the output port of the overall system. The βI source models
feedforward through the base amplifier from its input port to its output port. On the
other hand, the source, V1/Rf, accounts for feedforward through the resistive feedback
element. In other words, the potential difference, (V1−V2), developed across Rf encourages a portion of the base amplifier input port current to bleed to the output port through
Rf. This bleeding is in a direction to incur a clockwise current flow through the load
resistance, which is the reason that the polarity of the subject controlled source is opposite to that of βI. Once again, too small of a resistance value, Rf, is undesirable, this
time from the viewpoint of incurring parasitic signal feedforward. If comparable to the
feedforward current of base amplifier, this undesirable feedforward through the feedback element compromises the overall gain of the network.
(c). The fundamental purpose of installing Rf is to provide feedback from the amplifier output port to its input port. To this end, the generator, V2/Rf, which is intimate with the
y12V2 controlled source in a y-parameter model, appears across the amplifier input port
as a current proportional to the output port voltage. The subject current source flows
upward, as opposed to the conventional downward flow of y12V2 because y12b, which in
this case is identical to y12, is the negative of 1/Rf.
(d). The final sidebar statement may be perceived by the reader as academic chicanery. But
it does not reflect “fudging” and is indeed a lesson that must be learned now! In
particular, and despite the clearly feedback countenance of resistance Rf and even a
small body of literature to the contrary, the evaluation or computation of open loop metrics for the amplifier at hand does not mean that Rf is physically removed. To remove Rf
is to neglect the effects of its I/O port loading, as well as its parasitic feedforward.
Ming Hsieh Department of Electrical Engineering
- 143 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
Open loop computations herewith mean only that the feedback factor, y12, in the y12V2
generator is set to zero. Specifically, the generator, V2/Rf, and only that generator, is set
to zero in the course of open loop circuit assessments. In other words, “open loop” allows for the removal of only the output port to input port feedback factor, and assuredly
not the other aforementioned ramifications of feedback. Of course, it can be argued that
for suitably large Rf, loading and parasitic feedforward are negligible. In this case, and
only in this special case, open loop circumstances can be adequately approximated
through a disconnection of the feedback resistance.
(3).
Continuing now with the problem at hand, the results of the first two steps of the solution
tack combine with (1-40) to deliver the short circuit admittance parameters of the overall
network. Specifically,
1
1
1
+
=
y11 = y11a + y11b =
,
(E6-7)
ri R f
ri R f
y12 = y11a + y11b = −
y21 = y21a + y21b =
1
,
Rf
(E6-8)
r ⎞
β
1
β⎛
−
= ⎜1 − i ⎟ ,
ri
Rf
ri ⎜⎝
βR f ⎟⎠
(E6-9)
and
y22 = y22a + y22b =
(4).
1
1
1
+
=
.
ro R f
ro R f
Using (1-59) and the preceding disclosures, the open loop transimpedance is
⎛
r ⎞ ⎛ R f Rs ⎞
⎟ r R R ,
Z fo = − β ⎜ 1 − i ⎟ ⎜
(E6-11)
⎜
⎟⎜ R R + r ⎟ o f l
βR
f
f
s
i
⎝
⎠⎝
⎠
which is clearly and correctly a function of the feedback resistance. This open loop metric
represents the zero feedback factor value of the ratio of the output port voltage, V2, to the
Norton equivalent signal source current, which is Vs/Rs. Accordingly, the open loop voltage
gain, say Avo, is
(
Avo =
(5).
(E6-10)
⎛
r
= − β ⎜1 − i
⎜
Rs
βR f
⎝
Z fo
)
⎞ ⎛ R f ⎞ ⎛ ro R f Rl ⎞
⎟ = − 52.58 volts/volt .
⎟⎜
⎟⎜
⎟⎜
⎟
⎠ ⎝ R f + ri ⎠ ⎜⎝ ri R f + Rs ⎟⎠
(E6-12)
From (1-62) and (E6-11), the loop gain evaluated in terms of admittance parameters is
⎛
r ⎞ ⎛ Rs ⎞ ⎛ ro R f Rl ⎞
⎜
⎟ = 5.84 ,
T y ( Gs ,Gl ) = y12 Z fo = β ⎜ 1 − i ⎟ ⎜
(E6-13)
⎜
⎟ ⎝ Rs + ri ⎟⎠ ⎜ ri Rs + R f ⎟
βR
f
⎝
⎠
⎝
⎠
which is hardly large by most conventional standards. For future use, the zero source
conductance and zero load conductance values of the loop gain are computed here as
⎛
r ⎞ ⎛ ro R f Rl ⎞
⎟ = 83.74 ,
T y ( 0,Gl ) = β ⎜ 1 − i ⎟ ⎜
(E6-14)
⎜
⎟
⎜
⎟
βR
r
R
+
R
f ⎠⎝ i s
f ⎠
⎝
and
⎛
⎞
r ⎞ ⎛ Rs ⎞ ⎛ ro R f
T y ( Gs ,0 ) = β ⎜ 1 − i ⎟ ⎜
(E6-15)
⎜
⎟ = 8.80 .
⎟
⎜
⎟ ⎝ Rs + ri ⎠ ⎜ ri Rs + R f ⎟
βR
f
⎝
⎠
⎝
⎠
Ming Hsieh Department of Electrical Engineering
- 144 -
USC Viterbi School of Engineering
Lecture Supplement #2
(6).
Two-Port & Basic Amplifier Networks
J. Choma
Equation (1-63) stipulates the closed loop transimpedance of the shunt-shunt feedback
amplifier. It follows that the closed loop voltage gain, Av, is
Z fo Rs
Avo
Av =
=
= − 7.68 volts/volt ,
(E6-16)
1 + T y ( Gs , Gl )
1 + T y ( Gs , Gl )
where Zfo is given by (E6-11) and the loop gain, Ty(Gs, Gl), is the expression in (E6-13).
(7).
The open loop input admittance (conductance) is simply y11. Thus, the corresponding open
loop input resistance, say Rino, is
1
(E6-17)
Rino =
= ri R f = 1.61 KΩ .
y11
Equation (1-67) defines the closed loop driving point input admittance (conductance), the inverse of which is the closed loop driving point input resistance, Rin. Consequently and with
the help of the preceding result and (E6-14),
Rino
Rin =
= 19.02 Ω .
(E6-18)
1 + T y ( 0, Gl )
The open loop output conductance is y22, whence an open loop output resistance, say Routo, of
1
(E6-19)
Routo =
= ro R f = 2.53 KΩ .
y22
This result, (E6-15), and (1-71), leads to a closed loop driving point output resistance, Rout,
of
Routo
Rout =
= 258.16 Ω .
(E6-20)
1 + T y ( Gs , 0 )
COMMENTS:
Although we can argue that the circuit in Figure (1.32) is not so complicated that the gain and impedance levels could not be determined by
conventional Kirchhoff methods, applying the feedback concepts introduced in Section (1.2.6.1) has several advantages. First, the separation of
the feedback subcircuit, which in this case is a simple two-terminal resistance, from the base amplifier facilitates the evaluation of the short circuit admittance parameters for the overall network. Second, the
identification of such feedback circuit metrics as open loop gain, loop
gain, and so forth renders the fruits of analytical endeavors more
understandable. For example, the loop gain in (E6-13) is not very large,
which immediately teaches that the overall gain of the network is not
maximally desensitized to changes in various network element values.
The subject expression also shows that larger loop gains can be obtained
for larger load resistance, Rl, larger source resistance, Rs, and so forth.
It should be interjected that if the loop gain were to be made very large,
(E6-13) and (E6-16) verify an approximate closed loop gain, Av, of
−Rf/Rs, which is reminiscent of stereotypical operational amplifier cells
with a feedback resistance appended between its output and inverting input terminals. If this large loop gain assumption is invoked a priori, the
closed loop gain estimate is −9 volts/volt, whose magnitude differs from
the true gain magnitude computed in (E6-16) by slightly more than 17%.
The example computations suggest that the amplifier at hand is a far better transimpedance unit than it is a voltage amplifier, which functions
best when its input impedance is large and its output impedance is small.
To wit, a driving point input resistance of about 19 ohms means that the
Ming Hsieh Department of Electrical Engineering
- 145 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
net input current is essentially the Norton source current for most high
impedance sources. But for typical voltage sources, such a low input
resistance spawns significant attenuation, dependent on the signal source
resistance, of the applied voltage signal at the amplifier input port. The
output resistance of slightly under 260 ohms does not imply a great output voltage port, but it can reasonably drive load terminations whose
resistances are at least a few thousand ohms.
1.3.2. ANALYSIS VIA z-PARAMETERS
The z-parameter equivalent circuit at a given quiescent operating point imposed on the
electronic system of Figure (1.1a) is the topology submitted as Figure (1.34a). Because zparameter equivalent circuits exploit a Thévenin input port topology, the signal source is represented in a Thévenin format. An inspection of the figure at hand advances the output port
relationship,
z I
I 2 = − 21 1 ,
(1-72)
z22 + Z l
as well as the input port expression,
(1-73)
Vs = ( z11 + Z s ) I1 + z12 I 2 .
The combination of (1-72) into (1-73) generates
⎡
⎤
z z I
z12 z21
Vs = ( z11 + Z s ) I1 − 12 21 1 = ( z11 + Z s ) ⎢1 −
(1-74)
⎥ I1 .
+
+
z22 + Z l
z
Z
z
Z
(
)(
)
11
s
22
l ⎦
⎣
Substituting the solution for current I1 in (1-74) into (1-72) gives an I/O transadmittance, say Yfs,
which is effectively the closed loop transadmittance of the active network, of
z21
( z11 + Z s )( z22 + Z l )
I
(1-75)
Y fs = 2 = −
.
z12 z21
Vs
1−
( z11 + Z s )( z22 + Z l )
Under an open loop circumstance, which is defined by z12 = 0, the transadmittance in
(1-75) is simply the numerator on the right hand side of this relationship. Accordingly, the open
loop transadmittance, Yfo, is
z21
(1-76)
= −
.
Y fo = Y fs
z12 =0
( z11 + Z s )( z22 + Z l )
It follows that (1-75) is expressible as
Y fo
I
(1-77)
Y fs = 2 =
,
Vs
1 + z12Y fo
whose mathematical form is identical to that of the transimpedance expression of (1-60). Indeed,
replacing all z-parameters by their corresponding y-parameters and further replacing source and
load impedances by their respective admittances renders (1-76) identical to (1-59) and (1-75) the
same as (1-58). This similarity of expressions applies equally well to the loop gain metric, which
for z-parameters is
z12 z21
(1-78)
Tz ( Z s , Z l ) = z12Y fo = −
.
( z11 + Z s )( z22 + Zl )
Thus
Ming Hsieh Department of Electrical Engineering
- 146 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
+
Zs
Vs
−
1 I1
+
V1
−
J. Choma
3
I2
Linear Model
Of Electronic
Network
+
V2
−
2
+
1 I1
Zs
+
V1
−
Vs
−
Zin
Zl
4
z11
+
z22
+
z12 I2
−
I2
3
+
V2
−
z21 I1
−
2
4
Zl
Zout
(a).
Zs
1 I1
+
V1
−
z11
−
z22
+
z12 Itest
+
2
z21 I1
−
I2
3
+
V2
−
Zl
4
(b).
Figure (1.34). (a). The z-parameter equivalent circuit for a linear model of an electronic network. The
electronic network is designed to provide transadmittance signal processing. The applied
input signal is represented as an independent voltage source because of the Thévenin nature of the z-parameter input port model. (b). The equivalent circuit pertinent to the
computation of the z-parameter loop gain, Tz(Zs, Zl) = I2/Itest.
Y fo
Y fo
I2
=
=
.
Vs
1 + z12Y fo
1 + Tz ( Z s , Z l )
For large loop gain, which is tantamount to satisfying the inequality, |z12Yfo| >> 1,
1
≈
.
Y fs
z12Y fo >>1
z12
Y fs =
(1-79)
(1-80)
As in the case of the transimpedance amplifier, the loop gain in (1-78) can be computed
directly from the equivalent circuit. In the case of open circuit impedance parameters, the output
response is taken as the output current, I2. With the input signal Vs, set to zero, a test current signal, Itest, is therefore conceptually applied to the feedback subcircuit, with the result that the
applicable equivalent circuit is the structure in Figure (1.34b). An inspection of this circuit attests to
I2
I
I
z12 z21
(1-81)
= 1 × 2 = −
,
I test
I test I1
( z11 + Z s )( z22 + Z l )
which is indeed the loop gain stipulated in (1-78).
The driving point input and output impedances, Zin and Zout, can be found with the help
of Figure (1.35), where each impedance is computed as the “ohmmeter” voltage to current ratio,
Vx/Ix. In the case of Figure (1.35a), the driving point input impedance, Zin, derives directly from
(1-74) upon recognizing that Vx/Ix in Figure (1.35a) is identical to Vs/Is in (1-74), provided that Zs
is set to zero. In particular,
Ming Hsieh Department of Electrical Engineering
- 147 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
1 I1
Ix
+
Vx
−
+
V1
−
Zin
Zs
z11
+
V1
−
z22
+
z12 I2
−
2
1 I1
+
J. Choma
I2
+
V2
−
z21 I1
−
2
+
z22
+
z12 I2
−
Zl
4
(a).
z11
3
z21 I1
−
(b).
I2
3
+
V2
−
4
+
Vx
−
Ix
Zout
Figure (1.35). (a). The z-parameter model for computing the driving point input admittance of the transimpedance amplifier in Figure (1.34). (b). The z-parameter equivalent circuit pertinent to
computing the driving point output admittance of the subject electronic network.
⎡
⎤
Vx
z12 z21
= z11 ⎢1 −
(1-82)
⎥ = z11 ⎡⎣1 + Tz (0, Z l ) ⎤⎦ ,
Ix
z11 ( z22 + Z l ) ⎦
⎣
where (1-78) is invoked. Just as admittance parameter y11 represents the open loop input admittance of a transimpedance amplifier, we can view z11 as the open loop input impedance of a
transadmittance amplifier. If the transadmittance configuration is designed to achieve large loop
gain for desensitizing the closed loop transadmittance with respect to parameter and source/load
impedance shifts, the resultant driving point input impedance is potentially very large because
the modified loop gain, Tz(0, Zl), is even larger than the actual loop gain. This large input impedance is a laudable attribute for an input port that is to be voltage-driven.
Zin =
In the model in Figure (1.35b),
Vx = z22 I x + z21I1 ,
(1-83)
with
z12 I x
.
(1-84)
z11 + Z s
Upon inserting (1-84) into (1-83), the closed loop driving point output impedance is found as
⎡
⎤
V
z12 z21
Zout = x = z22 ⎢1 −
(1-85)
⎥ = z22 ⎡⎣1 + Tz ( Z s , 0 ) ⎤⎦ ,
Ix
z22 ( z11 + Z s ) ⎦
⎣
where z22 symbolizes the open loop driving point output impedance. Like Zin, Zout can be very
large, which is advantageous from the standpoint of delivering the output current response of a
transadmittance amplifier to an arbitrary external load termination.
I1 = −
1.3.3. ANALYSIS VIA h-PARAMETERS
A voltage amplifier requires high input impedance and low output impedance for maximal operating efficiency in the sense of establishing a voltage gain that is nominally independent
of source and load terminations. The h-parameters work well for modeling the linear
characteristics of such amplifiers and to this end, we submit Figure (1.36a). The analysis
underpinning the definition of voltage gain and I/O impedances mirrors the analyses undertaken
with respect to short circuit admittance and open circuit impedance parameters. Moreover, the
Ming Hsieh Department of Electrical Engineering
- 148 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
relevant results emulate the mathematical forms encountered in preceding subsections. To wit,
the reader is encouraged to confirm that the closed loop voltage gain, say Avs, is of the form
+
Zs
Vs
−
1 I1
+
V1
−
I2
Linear Model
Of Electronic
Network
2
+
1 I1
Zs
+
V1
−
Vs
−
Zin
Zs
3
+
V2
−
Zl
4
h11
I2 3
+
h12 V2
h21 I1 1/h22
−
2
+
V2
−
4
(a).
1 I1
+
V1
−
h11
Zl
Yout
I2 3
−
h12 Vtest
+
2
h21 I1 1/h22
+
V2
−
Zl
4
(b).
Figure (1.36). (a). The h-parameter equivalent circuit for a linear model of an electronic network designed to provide voltage gain signal processing. The applied input signal is represented
as an independent voltage source because of the Thévenin nature of the h-parameter input
port model. (b). Equivalent circuit used to compute the h-parameter return ratio, Th(Zs,
Yl), as the voltage ratio, V2/Vtest.
Avo
Avo
V2
=
=
,
(1-86)
Vs
1 + h12 A fo
1 + Th ( Z s ,Yl )
where Avo, the open loop voltage gain, is
h21
(1-87)
Avo = Avs h =0 = −
,
12
( h11 + Z s )( h22 + Yl )
and the loop gain, Th(Zs, Yl), in terms of hybrid h-parameters is
h12h21
(1-88)
Th ( Z s , Yl ) = h12 Avo = −
.
( h11 + Z s )( h22 + Yl )
It is worthwhile pointing out that admittance is used herewith to designate the load impedance
terminating the output port because of the Norton topological nature of the output port in the hparameter model. Thus, the load admittance, Yl, merely sums with the open circuit output admittance, h22, as (1-86) and (1-87) imply.
Avs =
Like y-parameter representations of the electrical properties of feedback networks, the
output voltage, V2, drives the feedback subcircuit in an h-parameter model of a network.
Accordingly, a test voltage signal, −Vtest, is applied to the feedback unit. With the signal drive,
Vs, set to zero, the resultant model pertinent to a circuit level examination of the h-parameter
loop gain is the structure appearing in Figure (1.36b). A worthwhile exercise for the reader is to
confirm that the loop gain defined by (1-87) is simply the ratio, V2/Vtest, in the latter model.
Ming Hsieh Department of Electrical Engineering
- 149 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
The determination of the driving point input impedance and driving point output admittance mimics the impedance and admittance analyses undertaken in conjunction with the
transimpedance and transadmittance amplifiers. In the present voltage amplifier case, h11 represents the open loop input impedance, while h22 is the open loop output admittance. The closed
loop input impedance, Zin, and closed loop output admittance, Yout, results are
Zin = h11 ⎡⎣1 + Tz ( 0, Yl ) ⎤⎦ ,
(1-89)
and
Yout = h22 ⎡⎣1 + Tz ( Z s , 0 ) ⎤⎦ .
(1-90)
We note that in a voltage amplifier, feedback enhances the driving point input impedance and
diminishes the driving point output impedance. The potentially large input impedance allows a
voltage signal to be coupled efficiently to the amplifier input port, while low output impedance
enables an expedient delivery of the output port voltage response to the load termination.
EXAMPLE #1.7:
Figure (1.37) diagrams a two-stage amplifier utilizing two identical active devices that
are biased at the same quiescent operating points. The parameters, ri and gm, in the circuit are model elements associated with the active devices, which are biased for nominally linear operation. Feedback in the form of the R1-R2 divider is connected around
the amplifier as shown. In the interest of clarity, the input and output port currents, I1b
and I2b, respectively, are delineated for the feedback subcircuit, as are the net input and
output port currents, I1 and I2, for the entire feedback amplifier. Derive expressions for
the feedback factor, open loop voltage gain, closed loop voltage gain, and closed loop
driving point input and output resistances. Numerically evaluate these performance
metrics for Rs = 300 Ω, ri = 2.5 KΩ, gm = 60 mS, Ra = 10 KΩ, R1 = 120 Ω, R2 = 1 KΩ,
and Rl = 5 KΩ.
V1
I1
I2
+
Rs
+
Va
Rin
V2
+
ri
gmVa
Ra
−
ri
Vb
gmVb
Rl
−
Vs
Rout
I1b
−
I2b
R2
+
V1b
−
R1
Feedback Subcircuit
Figure (1.37). Schematic diagram of the two stage feedback amplifier studied in Example #1.7.
SOLUTION #1.7:
(1).
The output ports of both the base amplifier and the feedback subcircuit are connected in
parallel with one another in that these ports sustain the same voltage, V2, which is seen to be
the net output voltage of the entire interconnection. On the other hand, the input port volt-
Ming Hsieh Department of Electrical Engineering
- 150 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
age, V1b, of the feedback unit algebraically adds with the voltage, Va, which happens to be
the input port voltage of the base amplifier, to establish the input port voltage, V1 for the entire feedback configuration. Accordingly, the feedback subcircuit can be viewed as interconnected in series-shunt with the base amplifier, thereby suggesting the propriety of using hparameters to model its terminal volt-ampere characteristics. From Figure (1.37),
V
= R1 R2 ,
h11b = 1b
(E7-1)
I1b V =0
2
h21b =
I 2b
R1
= −
,
I1b V =0
R1 + R2
2
(E7-2)
h12b =
V1b
R1
=
,
V2b I =0
R1 + R2
1b
(E7-3)
and
I 2b
1
=
.
V2b I =0
R1 + R2
1b
Recalling the characteristic h-parameter equations, the foregoing results infer
⎛ R1 ⎞
V1b = ( R1 R2 ) I1b + ⎜
⎟V2
⎝ R1 + R2 ⎠
,
⎛ R1 ⎞
⎛ V2 ⎞
I 2b = − ⎜
⎟ I 1b + ⎜
⎟
⎝ R1 + R2 ⎠
⎝ R1 + R2 ⎠
h22b =
(E7-4)
(E7-5)
which in turn suggests that an equivalent electrical depiction of the circuit in Figure (1.37) is
the structure offered in Figure (1.38a). In the latter diagram, the symbol, kf, denotes
R1
(E7-6)
kf .
R1 + R2
(2).
At this juncture, the hybrid h-parameters of the base amplifier can be discerned in accordance with Figure (1.38a), whereupon the matrix of these parameters can be suitably combined with the matrix of the h-parameters for the feedback subcircuit to produce the effective
hybrid h-parameters for the complete network. However, the relative simplicity of the
circuit at hand renders this computational step unnecessary (although certainly valid). Instead, set the kfV2 feedback generator in Figure (1.38a) to zero to arrive at the open loop version of the circuit drawn in Figure (1.38b). In the latter diagram, the current, I1b, flowing
into the input port of the feedback subcircuit is
V
V
(E7-7)
I1b = g mVa + a = a (1 + g m ri ) .
ri
ri
It follows that the feedforward current, kfI1b, produced by the feedback structure is
k f Va
V ⎛ R1 ⎞
(E7-8)
k f I1b =
(1 + gm ri ) = a ⎜
⎟ (1 + g m ri ) .
ri
ri ⎝ R1 + R2 ⎠
It should also be noted that the conduction of current I1b by the parallel combination of resistances R1 and R2 produces a voltage across this shunt resistance connection that is equivalent
to the voltage established by the flow of the input port current, Va/ri, through an effective
resistance of value, (1 + gmri)(R1||R2).
On the other hand, the interstage potential, Vb, is seen to be
(E7-9)
Vb = − g m ( Ra ri )Va ,
Ming Hsieh Department of Electrical Engineering
- 151 -
USC Viterbi School of Engineering
Lecture Supplement #2
V1
Two-Port & Basic Amplifier Networks
I1
I2
+
Rs
Va
Rin
+
J. Choma
+
ri
gmVa
Ra
−
Vb
ri
V2
I2b
gmVb
Rl
−
Rout
I1b
Vs
−
+
V1b
−
R1||R2
kfI1b
R1+R2
+
kfV2
−
(a).
V1
I1
I2
+
Rs
Va
Rino
+
+
ri
gmVa
Ra
−
Vb
ri
gmVb
I2b
Rl
−
I1b
Vs
−
Routo
R1+R2
R1||R2
V2
kfI1b
(b).
V1
I1
I2
+
Rs
+
Vs
−
Va
Rino
−
ri
gm2(Ra||ri )Va
kf(1+gmri )Va
ri
R1+R2
V2
Rl
Routo
Va /ri
(1+gmri )(R1||R2)
(c).
Figure (1.38). (a). The circuit model of Figure (1.37) with the feedback subcircuit supplanted by its h-parameter equivalent circuit. (b). The circuit model of (a) under open loop operating conditions. By
comparison with the network in (a), note that only the controlled feedback subcircuit source,
kfV2, is set to zero. The resultant open loop input resistance is symbolized as Rino, while its
counterpart output resistance is Routo. (c). Simplified version of the model in (b).
whence a feedforward base amplifier current of
gmVb = − gm2 ( Ra ri )Va .
(E7-10)
The design goal of achieving an amplifier feedforward current that is much larger than the
feedforward current evidenced by the feedback subcircuit requires that the magnitude of the
current in (E7-10) be significantly larger than the current defined by (E7-8). Since gmri in
Ming Hsieh Department of Electrical Engineering
- 152 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
this example is 150 and therefore much larger than one, this design objective translates into
the requirement,
⎛
r ⎞
gm ri >> ⎜ 1 + i ⎟ k f .
(E7-11)
Ra ⎠
⎝
The foregoing observations, and specifically (E7-7), (E7-8), and (E7-10), allow recasting the
model in Figure (1.38b) into the topological structure shown in Figure (1.38c). It is to be
understood that this revised topology remains applicable only for open loop operation of the
original amplifier modeled in Figure (1.38a).
(3).
Figure (1.38c) renders immediately clear the facts that the open loop input resistance, Rino, is
(E7-12)
Rino = ri + (1 + gm ri ) ( R1 R2 ) = 18.68 KΩ ,
while the open loop output resistance, Routo, is
Routo = R1 + R2 = 1.12 KΩ .
The figure at hand also confirms an open loop voltage gain, Avo, of
Avo =
(E7-13)
V V
V2
= a× 2
Vs k V =0
Vs Va k V =0
f 2
f 2
(E7-14)
⎡
⎤
ri
= ⎢
⎥ Geff ⎡⎣( R1 + R2 ) Rl ⎤⎦ ,
⎣⎢ Rs + ri + (1 + gm ri ) ( R1 R2 ) ⎥⎦
where Geff, which represents an effective forward transconductance of the open loop
configuration, is
k f (1 + g m ri )
(E7-15)
= 7.21 S .
Geff = gm2 ( Ra ri ) +
ri
This result and (E7-14) give an open loop voltage gain of Avo = 868.63 volts/volt. Moreover,
the loop gain computes as
Th ( Rs , Gl ) = k f Avo = 93.07 .
(E7-16)
{
}
where Gl is the conductance corresponding to the stipulated load resistance, Rl. With Rs = 0,
Th(0, Gl) = 94.56, while for the case of infinitely large load resistance, Th(Rs, 0) = 113.91.
These last two loop gain special cases are, of course, germane to the computation of the driving point input and output resistances.
(4). Recalling (1-86), the closed loop voltage gain, Avs, is
Avo
V
Avs = 2 =
= 9.23 volts/volt .
Vs
1 + Th ( Rs , Gl )
(E7-17)
In view of the fact that the loop gain computed in (E7-16) is very large, this gain closely
approximates the inverse of the feedback factor, kf. From (E7-6),
1
R
Avs ≈
= 1 + 2 = 9.33 volts/volt ,
(E7-18)
kf
R1
which exceeds the true voltage gain predicted in (E7-17) by only 1.07%.
(5). From (1-88), the driving point input resistance, Rin, is
Rin = Rino ⎡⎣1 + Th (0, Gl ) ⎤⎦ = 1.78 Meg Ω ,
while (1-89) provides a driving point output resistance, Rout, of
Routo
Rout =
= 9.75 Ω .
1 + Th ( Rs , 0 )
Ming Hsieh Department of Electrical Engineering
- 153 -
(E7-19)
(E7-20)
USC Viterbi School of Engineering
Lecture Supplement #2
COMMENTS:
Two-Port & Basic Amplifier Networks
J. Choma
The amplifier tackled in this example is an excellent voltage amplifier
for at least three reasons. First, its very large loop gain robustly desensitizes its I/O gain characteristics with respect to source resistance, load
resistance, and model parameters. Indeed and as is suggested by (E718), its forward gain is fundamentally set by the resistance ratio, R2/R1.
This resistance ratio conclusion is a circuit attribute, for while individual
resistances synthesized in integrated circuits are subject to tolerances of
at last ±20%, ratios of appropriate resistances can generally be controlled
to tolerances of less than ±5%. Second, the driving point input resistance
is exceedingly large, thereby allowing a wide range of source resistances
to be utilized without significantly affecting the voltage gain. For example, the source resistance in the considered amplifier can be increased to
as much as 90 KΩ without incurring a gain degradation of larger than
5%. Finally, the very low driving point output resistance allows for the
incorporation of a wide range of load terminations. To wit, the load
resistance, Rl, can be decreased to as little as 175 Ω without altering the
voltage gain by more than 5%.
A valuable lesson learned herewith, albeit subliminally, is that two port
parameters are a powerful tool underlying the insightful analysis of feedback circuits. In this example, the two port parameters for the feedback
circuit are computed and thence exploited from a circuits perspective to
allow for a straightforward circuit analysis without leaning on the two
port parameters of the entire configuration. In particular, the open loop
gain is obtained almost by mere inspection, as are the corresponding loop
gain and closed loop gain metrics.
1.3.4. ANALYSIS VIA g-PARAMETERS
In contrast to the voltage amplifier addressed in the preceding subsection, a current
amplifier requires low input impedance and high output impedance in order to deliver a current
gain that is nominally independent of source and load terminations. The g-parameters, which extol Norton input port and Thévenin output port topologies, are best suited for the current amplifier, as we suggest in Figure (1.39a).
As in the case of all previous two port network analyses, an analytical study premised
on g-parameters is a case of déjà vu all over again. Thus, without explicit derivation, the closed
loop current gain, say Ais, is expressible as
Aio
Aio
I
Ais = 2 =
=
,
(1-91)
Is
1 + g12 Aio
1 + Tg (Ys , Z l )
where the open loop current gain, Aio, is given by
g 21
(1-92)
Aio = Ais g =0 = −
,
12
( g11 + Ys )( g 22 + Z l )
and the loop gain, Tg(Ys, Zl), is
g12 g 21
(1-93)
Tg (Ys , Z l ) = g12 Aio = −
.
( g11 + Ys )( g 22 + Zl )
This loop gain computes as the current ratio, I2/Itest, in the model of Figure (1.39b). Finally, the
closed loop input admittance, Yin, can be shown to satisfy
Yin = g11 ⎡⎣1 + Tg (0, Z l ) ⎤⎦ ,
(1-94)
Ming Hsieh Department of Electrical Engineering
- 154 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
while the closed loop output impedance, Zout, is
Zout = g 22 ⎡⎣1 + Tg (Ys , 0 ) ⎤⎦ .
(1-95)
1 I1
Zs
Is
+
V1
−
I2
Linear Model
Of Electronic
Network
+
V2
−
2
Is
Zs
Yin
+
1/g11
g12 I2
g22
I2
3
+
V2
−
g21 V1
−
2
4
(a).
1 I1
Zs
Zl
4
1 I1
+
V1
−
3
+
V1
−
+
1/g11
g12 Itest
g21 V1
−
2
g22
I2
Zl
Zout
3
+
V2
−
Zl
4
(b).
Figure (1.39). (a). The g-parameter equivalent circuit for a linear model of an electronic network designed to provide current gain signal processing. The applied input signal is represented
as an independent current source because of the Norton nature of the g-parameter input
port model. (b). Equivalent circuit used to evaluate the g-parameter return ratio, Tg(Ys,
Zl), as the current ratio, I2/Itest.
EXAMPLE #1.8:
The linear amplifier studied in Example #1.7 is reconfigured for current gain signal
processing in accord with the equivalent circuit of the feedback amplifier drawn in Figure (1.40). The device model parameters, ri and gm, have the values stipulated in the
preceding example; namely, ri = 2.5 KΩ and gm = 60 mS. Feedback in the form of the
R1-R2 divider is connected in shunt with the amplifier input port and in series with the
amplifier output port. In the interest of clarity, the input and output port currents, I1b
and I2b, respectively, are delineated for the feedback subcircuit, as are the net input and
output port currents, I1 and I2, for the entire feedback amplifier. Derive expressions for
the feedback factor, loop gain, open loop current gain, closed loop current gain, and
closed loop driving point input and output resistances. Numerically evaluate these
performance indices for Rs = 20 KΩ, Ra = 500 Ω, R1 = 120 Ω, R2 = 1 KΩ, and Rl = 300
Ω.
Ming Hsieh Department of Electrical Engineering
- 155 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
V1
I1
I2
+
Is
J. Choma
Rs
Va
+
ri
gmVa
Ra
−
Rin
V2
Vb
ri
gmVb
−
Rl
Rout
I1b
I2b
R2
+
V2b
Feedback Subcircuit
R1
−
Figure (1.40). The current amplifier addressed in Example #1.8. The input signal is the current, Is,
whose Thévenin resistance is Rs, and the output response is taken as the current, I2, conducted by the terminating load impedance, Zl.
SOLUTION #1.8:
(1).
As noted in the problem statement, the feedback subcircuit delineated in Figure (1.40) is
connected in shunt with the input port of the amplifier and in series with its output port. This
shunt-series topology encourages modeling the feedback unit with a g-parameter equivalent
circuit, which implicitly advances a Norton (shunt) input port and Thévenin (series) output
port architecture. To this end,
I
(E8-1)
g11b = 1b
= R1 + R2 ,
V1 I = 0
2b
g 21b =
V2b
R1
=
,
V1 I = 0
R1 + R2
2b
(E8-2)
g12b =
I1b
R1
= −
,
I 2b V =0
R1 + R2
1
(E8-3)
and
V2b
= R1 R2 .
I 2b V =0
1
From (1-35) and the foregoing disclosures, it follows that
V1
− k g I 2b
I1b =
R1 + R2
,
g 22b =
(E8-4)
(E8-5)
V2b = k gV1 + ( R1 R2 ) I 2b
where
R1
(E8-6)
kg = 0.107
R1 + R2
represents the magnitude of the reverse current gain established by the feedback subcircuit.
(2).
Equation (E8-5) forges the alternative circuit model offered in Figure (1.41a). In this
embodiment, observe that the feedback generator, kgI2b, is, in accordance with g-parameter
modeling, a dependent current generator controlled by the current, I2b, flowing into the out-
Ming Hsieh Department of Electrical Engineering
- 156 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
put port of the feedback subcircuit. The polarity of this controlled source accounts for the
fact that the feedback transconductance, g12b in (E8-3), is a negative number. From the
perspective of loop gain computation, it is desirable to cast this feedback current as a function that is linearly dependent on the output current response, I2, which is, of course, an
independent variable in the g-parameter model formulation. To this end, Figure (1.41a)
confirms
⎛ 1 + gm ri ⎞
V
V
I 2b = gmVb + b = b (1 + gm ri ) = I 2 ⎜
(E8-7)
⎟,
ri
ri
⎝ gm ri ⎠
whence
⎛ 1 + gm ri ⎞
k g I 2b = k g ⎜
(E8-8)
⎟ I2 k f I2 ,
⎝ gm ri ⎠
where
⎛ 1 + gm ri ⎞
⎛ R1 ⎞ ⎛ 1 + gm ri ⎞
k f = kg ⎜
(E8-9)
⎟ = ⎜
⎟ = 0.108
⎟⎜
⎝ R1 + R2 ⎠ ⎝ gm ri ⎠
⎝ gm ri ⎠
represents the feedback factor of the entire amplifier in that it quantifies, as a direct
proportionality to the output response, the amount of current fed back to the input port of the
base amplifier. The circuit implications of the foregoing disclosures are incorporated into
the modified equivalent circuit of Figure (1.41b).
V1
I1
I2
+
Is
I1b Va
Rs
+
ri
gmVa
Ra
Vb
−
Rin
V2
ri
−
gmVb
V2b
I2b
Rl
Rout
g
kV
R1||R2
1
+
−
kgI2b
R1+R2
(a).
V1
I1
I2
+
Is
I1b Va
Rs
Rin
V2
+
ri
gmVa
Ra
Vb
−
ri
−
gmVb
V2b
I2b
Rl
Rout
g
kV
R1||R2
1
+
kf I 2
−
R1+R2
(b).
Figure (1.41). (a). The current amplifier in Figure (1.40) with the feedback subcircuit replaced by its
g-parameter equivalent circuit. (b). An alternative form of the model in (a), wherein the
Ming Hsieh Department of Electrical Engineering
- 157 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
feedback current source is cast as an explicit function of the output current response, I2.
The feedback factor, kf, is defined in (E8-9).
(3). The most straightforward way to compute the loop gain of the amplifier at hand is to exploit
(1-93). Unfortunately, this solution tack requires an identification of the g-parameters for
the entire feedback amplifier, which in turn requires an evaluation of the g-parameters for
the base amplifier. The latter requirement entails analytical tedium owing to the reasonably
cumbersome nature of the base amplifier topology. A computationally more efficient
determination of the loop gain, Tg(Gs, Rl), derives from injecting a test current, −Itest, into the
output port of the feedback subcircuit (which is driven by the amplifier output port) and then
computing the resultant current transfer ratio, I2/Itest, under the condition of zero input signal
current, Is = 0. The pertinent circuit model appears in Figure (1.42), which renders clear the
fact that
Va
(E8-10)
= − k f ⎡⎣ Rs ( R1 + R2 ) ri ⎤⎦ .
I test
Moreover,
⎛
⎛V ⎞
V ⎞
Ra ⎜ gmVa + b ⎟ + Vb + ( R1 R2 ) ⎜ b ⎟ ( 1 + gm ri ) + k gVa = 0 ,
(E8-11)
ri ⎠
⎝
⎝ ri ⎠
where we exploit the fact that the input port voltage, V1, is identical to the indicated control
voltage, Va. After enduring a trifle of algebraic grief, the last relationship provides
⎡
⎤
Vb
ri
= − gm Ra + k g ⎢
(E8-12)
⎥ .
Va
⎢⎣ Ra + (1 + gm ri ) ( R1 R2 ) ⎥⎦
(
)
V1
I2
+
Rs
R1+R2
kf Itest Va
V2
+
ri
gmVa
Ra
Vb
−
ri
gmVb
Rl
−
g
kV
Vb
gmVa + r
i
1
+
−
R1||R2 Vb
(1 + gmr i )
ri
Figure (1.42). Circuit model used to evaluate the loop gain of the network in Figure (1.41b). Observe that the input current signal is set to null value, while the direction of the original
feedback current generator, kfI2, is reversed and set to kfItest to reflect the injection of
the test current, −Itest, into the output port of the feedback subcircuit.
Recognizing that the output port current, I2, is little more than gmVb, (E8-12) and (E8-10)
produce a network loop gain of
I
I
I V
Tg ( Gs , Rl ) = 2 = 2 × b × a
I est
Vb Va I test
⎤
⎥ ⎡⎣ Rs ( R1 + R2 ) ri ⎤⎦
⎢⎣ a + (1 + gm ri ) ( R1 R2 ) ⎦⎥
= 21.75 amps/amp ,
=
(4).
⎡
( gm Ra + k g ) ⎢ R
k f gm ri
(E8-13)
The open loop current gain, Aio = I2/Is, can be evaluated by undertaking an analysis of the
circuit in Figure (1.41b) under the condition of zero feedback; that is, kfI2 = 0. But this
analytical procedure can be obviated in favor of observing that the resultant open loop circuit
Ming Hsieh Department of Electrical Engineering
- 158 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
is topologically identical to the structure in Figure (1.42), which precipitates the loop gain
expression in the preceding step of this solution process. In effect, the latter circuit collapses
to the former if the current source, kfItest, in the latter diagram is supplanted by −Is. Consequently,
⎛I ⎞
I 2 = I test Tg ( Gs , Rl ) = − ⎜ s ⎟ Tg ( Gs , Rl ) ,
(E8-14)
⎜kf ⎟
⎝
⎠
whence an open loop current gain (without further circuit analysis) of
Tg ( Gs , Rl )
I
Aio = 2
= −
= − 201.64 amps/amp .
(E8-15)
I s k I =0
kf
f 2
The corresponding closed loop current gain, Ais, is
Aio
I
Ais = 2 =
= − 8.86 amps/amp .
Is
1 + Tg ( Gs , Rl )
(5).
(E8-15)
Under open loop circumstances, the input resistance, say Rino, established at the amplifier input port is obviously
Rino = ( R1 + R2 ) ri = 773.48 Ω .
(E8-16)
With the source conductance, Gs, set to zero, which is equivalent to remanding the source
resistance, Rs, to an infinitely large value, (E8-13) yields
⎡
⎤
k f g m ri
Tg ( 0, Rl ) = g m Ra + k g ⎢
⎥ ⎡⎣( R1 + R2 ) ri ⎤⎦
(E8-17)
⎣⎢ Ra + (1 + gm ri ) ( R1 R2 ) ⎦⎥
(
)
= 22.59 amps/amp .
Accordingly, the closed loop driving point input resistance, Rin, follows from (1-94) as
Rino
Rin =
= 32.79 Ω .
(E8-18)
1 + Tg ( 0, Rl )
(6).
The open loop output resistance, Routo, is calculated by setting kfI2 = 0 and the independent
signal source, Is, to zero. The immediate ramification of this due diligence is Va = 0 and Vb
= 0, whence gmVb at the amplifier output port is zero. But gmVb = 0 is tantamount to an open
circuited output port, whence an infinitely large open loop, and therefore closed loop,
driving point output resistance.
COMMENTS:
Because of the reasonably large loop gain computed in (E8-13), the
amplifier studied in this example delivers a current gain that is essentially invariant with model parameter perturbations and source impedance fluctuations. In particular, the closed loop current gain is very
nearly, −1/kf = −9.27, whose magnitude differs from that of the actual
current gain by only 4.60%. This approximation entails neglecting unity
in the [1 + Tg(Gs, Rl)] denominator of the closed loop gain expression in
(E8-15).
Such neglect is tantamount to a percentage error of
100%/Tg(Gs, Rl), which is shockingly 4.60%.
Although two port network theory is the theoretic basis of all computations required of this problem, it is interesting that two port parameter
methods requiring the evaluation of the g-parameters for the overall network, are forsaken. Instead, the circuit analyses undertaken take advantage of the insights and pragmatic implications spawned by classic two
port theory to advance a computationally efficient and an arguably
illuminating evaluation of amplifier performance. For example, it is
Ming Hsieh Department of Electrical Engineering
- 159 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
interesting that the loop gain and open loop gain derive from effectively
one set of circuit equations. In the process, an initial assessment of the
relative quality of the amplifier is almost immediate in that the magnitude of the open loop gain becomes transparent from the circuit
manipulations undertaken to arrive at the loop gain of the network.
1.4.0. REFERENCES
[1].
J. Choma and W-K Chen, Feedback Networks: Theory and Circuit Applications. Singapore:
World Scientific Press, Inc., 2007, chap. 3.
Ming Hsieh Department of Electrical Engineering
- 160 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
EXERCISES
Problem #1.1
Derive general expressions for the short circuit admittance parameters of the passive network depicted in Figure (P1.1). As usual, the input port voltage and current variables are
delineated as V1 and I1 respectively, while V2 and I2 denote the corresponding variables at
the output port. Evaluate these parameters for the special case of R1R2 = R3R4, and comment on the engineering significance of this resistive constraint.
+
R1
R4
− V2 +
V1
R3
−
R2
Figure (P1.1)
Problem #1.2
The circuit in Figure (P1.2) is a simplified, linearized model of a voltage buffer realized in
MOSFET technology. If terminal (1) and ground comprise the input port of the buffer and
terminal (2) and ground form the output port, derive expressions for the short circuit admittance parameters and alternative π-model parameters for the subject circuit.
V1
(1)
I1
V
+
−
C1
gmV
ro
I2
C2
R
V2
(2)
Figure (P1.2)
Problem #1.3
The circuit in Figure (P1.3) is a simplified, linearized model of a voltage amplifier realized
in bipolar technology. If terminal (1) and ground comprise the input port of the amplifier
and terminal (2) and ground form its output port, derive expressions for the short circuit
admittance parameters and alternative π-model parameters for the subject circuit.
Ming Hsieh Department of Electrical Engineering
- 161 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
(1)
V1
I1
rπ
I
C1
ro
βI
C2
J. Choma
I2
(2)
V2
R
Figure (P1.3)
Problem #1.4
The twin tee structure shown in Figure (P1.4) is commonly used as a notch filter; that is, it
ideally affords zero transmission between its input and output ports at a single frequency,
say ωn, which is known as the notch frequency.
Vi
2R
2R
C
C
2C
Vo
R
Figure (P1.4)
Without evaluating the actual voltage transfer function, Vo/Vi, from the network input port
to the network output port, use y-parameter concepts to determine an expression for the
notch frequency, ωn, in terms of resistance R and capacitance C.
Problem #1.5
The circuit given in Figure (P1.5) is capable of realizing a negative resistance between
terminals (1) and (2). Derive an expression for this negative resistance, assuming ideal
transconductors.
(1)
Gm
(2)
+
−
+
G
− m
Figure (P1.5)
Problem #1.6
The terminal volt-ampere characteristics of the linear network depicted in Figure (P1.6a)
subscribe to the matric,
Ming Hsieh Department of Electrical Engineering
- 162 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
È I1 ˘
È 1 -1 -2 ˘ ÈV1 ˘
Í I ˙ = Í -1 1 -2 ˙ ÍV ˙ ,
Í 2˙
Í
˙Í 2˙
3 ˚˙ ÎÍV3 ˚˙
ÎÍ -3 0
ÎÍ I 3 ˚˙
2Ω
V1
1 I1
2
I2
Linear
Network
I3
4
3
V2
V3
V1
V4
1 I1
I4
I2
Linear
Network
4
2
I3
3
(a).
V3
(b).
Figure (P1.6)
where all elements in the 3x3 coefficient matrix are in units of siemens, and terminal voltages V1, V2, and V3 are measured with respect to network terminal #4. Find the short circuit
admittance matrix, Y, of the modified architecture offered in Figure (P1.6b), such that
È I1 ˘
ÈV1 ˘
Í I ˙ = Y ÍV ˙ ,
Í 3˙
Í 3˙
ÍÎ I 4 ˙˚
ÍÎV4 ˙˚
with the understanding that terminal voltages V1, V3, and V4 are measured with respect to
network terminal #2.
Problem #1.7
A three terminal, two port, bilateral circuit is terminated at its output port in a resistance, RL.
The circuit is known to have short circuit admittance parameters, yij and is symmetrical in
the sense that y11 = y22. Show that if the driving point input resistance of the circuit is to
identical to RL, resistance RL must be given by
1
RL =
.
2
2
y11 − y12
Problem #1.8
I2
gmVc
ro
+ Va −
+
Vb
−
gmV b
ro
+
Vc
−
gmV a
ro
V2
I1
V1
Figure (P1.8)
Figure (P1.8) depicts the linear model of a MOSFET amplifier formed of nominally identical transistors biased at roughly identical quiescent operating points. The input port is
associated with voltage V1 and current I1, while the output port is associated with voltage V2
Ming Hsieh Department of Electrical Engineering
- 163 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
and current I2. Determine the short circuit admittance parameters of this amplifier, and
draw the corresponding y-parameter equivalent circuit for the case of gmro >> 1.
Problem #1.9
Derive expressions for the open circuit impedance parameters of the network given in Problem #1.1.
Problem #1.10
Derive expressions for the open circuit impedance parameters of the network given in Problem #1.2.
Problem #1.11
Derive expressions for the open circuit impedance parameters of the network given in Problem #1.8.
Problem #1.12
Derive relationships for the hybrid h-parameters in terms of the open circuit admittance, or
z- parameters.
Problem #1.13
Derive expressions for the hybrid h-parameters of the network given in Problem #1.1.
Problem #1.14
Derive expressions for the hybrid h-parameters of the network given in Problem #1.3.
Problem #1.15
Derive expressions for the hybrid h-parameters of the linear equivalent circuit appearing in
Figure (P1.15). Discuss the engineering ramifications of a very large resistance, ro.
+ V −
gmV
V1
ro
I2
V2
R2
I1
R1
Figure (P1.15)
Problem #1.16
Derive expressions for the hybrid g-parameters in terms of the short circuit admittance
parameters of a linear two port network.
Problem #1.17
Figure (P1.17) is a low frequency, small signal equivalent circuit of a bipolar junction
transistor amplifier that utilizes an emitter degeneration resistance, Re, to achieve a forward
gain that is nominally independent of the transistor current gain parameter, β. Let the
amplifier input resistance, ri, be 2.7 KΩ, the transistor output resistance, ro, be 40 KΩ, β =
100, and Re = 120 Ω. Derive general expressions for, and numerically evaluate, the four gparameters, gij, of the emitter degenerated configuration.
Ming Hsieh Department of Electrical Engineering
- 164 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
V1
I1
I2
ri
βI1
J. Choma
V2
ro
Re
Figure (P1.17)
Problem #1.18
I1
Cgd
Cgs
I2
gmV1
ro
2 (Drain)
V1
1 (Gate)
Figure (P1.18) is an approximate small signal model of a metal-oxide-semiconductor fieldeffect transistor (MOSFET) configured to operate ultimately as a common source amplifier.
Terminal 1 represents the gate of the transistor, terminal 2 is the transistor drain terminal,
and terminal 3 is the source terminal of the device. In this model, Cgs represents the gate to
source capacitance of the transistor, Cgd is the gate to drain capacitance, Cbd is the bulk to
drain substrate capacitance, ro designates the source-drain channel resistance, and finally, gm
is the forward transconductance of the device.
V2
Cbd
3 (Source)
Figure (P1.18)
(a). Find general expressions for each of the four common source y-parameters, yij. Use
these y-parameters to give general expressions for the h-parameters of the equivalent
circuit.
(b). Use the appropriate hybrid h-parameter to give a general expression for the short circuit (meaning the drain terminal is short circuited to the source terminal) current gain,
I2/I1.
(c). Use the preceding result to evaluate the frequency at which the magnitude of the short
circuit current gain degrades to unity. If gm = 10 mS, ro = 10 KΩ, Cgs = 20 fF, Cgd = 4
fF, and Cbd = 15 fF, numerically evaluate this unity gain frequency, which is commonly symbolized as fT.
Problem #1.19
The circuit in Figure (1.31) is modified through the incorporation of resistive degeneration,
R, as depicted in Figure (P1.19). Resistance R is 20 Ω, and all other circuit parameters remain as stipulated in Example #1.6; namely, Rs = 300 Ω, ri = 4 KΩ, Rf = 2.7 KΩ, ro = 40
KΩ, Rl = 5 KΩ, and β = 150.
Ming Hsieh Department of Electrical Engineering
- 165 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
Rin
V1
J. Choma
Rout
Rf
I1
V2
I2
I
Rs
ri
+
βI
ro
Rl
Vs
−
R
Figure (P1.19)
(a). Derive expressions for and numerically compute the open loop voltage gain, Avo, the
loop gain, Ty(Gs, Gl), and the closed loop voltage gain, Av.
(b). Derive expressions for and numerically compute the open loop and closed loop driving
point input impedances, Rino and Rin, respectively, as well as the open loop and closed
loop driving point output resistances, Routo and Rout, respectively.
(c). Compare the results of parts (a) and (b) with those generated in Example #1.6. Comment on any differences observed, particularly with regard to the suitability of the present amplifier as either a voltage amplifier or a transimpedance processor.
Problem #1.20
The circuit in Figure (1.31) is modified through the incorporation of a capacitance, Cf, in
shunt with the feedback resistance, Rf, as depicted in Figure (P1.20). While Rf retains its
original 2.7 KΩ value, the other circuit and model parameters have been suitably modified
to ensure that the loading by resistance Rf on both the input and output ports of the base
amplifier are negligible, as is the effect of Rf on the forward transconductance of the base
unit.
Cf
V1
Rs
+
Rf
I1
I2
V2
I
ri
βI
ro
Rl
Vs
−
Figure (P1.20)
(a). Use the feedback theory and methods exploited in Example #1.6 to deduce a general
expression, in terms of the open loop transimpedance, for the time constant, say τf,
associated with Cf. Be aware that the numerical value of the open loop transimpedance
in this exercise differs from that computed in Example #1.6 because of the aforementioned parametric modifications.
(b). Assuming a revised value, Zfo, of the open loop transimpedance of 20 KΩ, what value
of capacitance Cf delivers a voltage gain 3-dB bandwidth of at least 500 MHz?
Ming Hsieh Department of Electrical Engineering
- 166 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
Problem #1.21
The passive two port network in Figure (P1.21) is to be modeled by open circuit impedance
parameters, zij. Observe that the input and output ports are electrically connected together
so that the entire two port network functions as an impedance established between the indicated terminals, 1 and 2. In terms of the z-parameters of the network, derive a general
expression for this two-terminal impedance.
1
I1
+
V1
−
I2
Passive
Linear
Network
+
V2
−
2
Figure (P1.21)
Problem #1.22
Confirm the expressions given in Section (1.3.4) for the closed loop current gain, the open
loop current gain, the loop gain, the driving point input admittance, and the driving point
output impedance of a current amplifier.
Problem #1.23
Show that the loop gain, Th(Zs, Yl), computed in terms of the hybrid h-parameters of a linear
two port network, is related to the loop gain, Ty(Ys, Yl), computed as a function of the short
circuit admittance parameters, by the relationship,
YsTy (Ys , Yl )
Th (Ys , Z l ) = −
,
Yin
where Ys is the admittance of the signal source applied to the network, Zl = 1/Yl is the load
impedance terminating the output port of the network, and Yin is the driving point input
admittance of the linear network.
Problem #1.24
The loop gain, computed in terms of the open circuit impedance parameters of a linear two
port network, is Tz(Zs, Zl), while the loop gain, computed as a function of the short circuit
admittance parameters, is Ty(Ys, Yl). If the impedance, Zs, of the signal source that drives
the network is identical to the inverse of the network driving point input admittance and if
the load impedance, Zl, which terminates the network output port is equal to the inverse of
the network driving point output admittance, show that these two loop gains are identical.
Problem #1.25
In the amplifier studied in Example #1.8, a capacitance, Ca, is added in shunt with resistance Ra as depicted in Figure (P1.25). Assume that the parameters in this circuit satisfy the
inequalities,
Ming Hsieh Department of Electrical Engineering
- 167 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
gm Ra >>
R1
R1 + R2
.
Ra
1 + gm ri >>
R1 R2
V1
I1
I2
+
Is
J. Choma
Rs
Va
V2
+
ri
gmV a
Ra
−
Ca Vb
ri
gmVb
Rl
−
R2
R1
Figure (P1.25)
(a). Derive an expression for the closed loop time constant, say τa, associated with capacitance Ca and use this time constant relationship to deduce the closed loop 3-dB bandwidth. Express this bandwidth in terms of the low frequency loop gain, Tg(Gs, Rl).
(b). Give engineering arguments as to design strategies commensurate with increasing the
closed loop bandwidth.
(c). What major disadvantage accrues if attempts are made to set the closed loop 3-dB
bandwidth by connecting capacitance Ca directly across the input port of the amplifier,
as opposed to the indicated shunt incidence with resistance Ra?
(d). As is verified in Example #1.8, the driving point closed loop output resistance of the
feedback amplifier is infinitely large. This attribute allows the amplifier to deliver a
proscribed closed loop current gain for broad ranges of load resistance. In light of this
observation, is there an engineering disadvantage to setting the bandwidth by placing
capacitance Ca in shunt with the load termination, Rl?
Problem #1.26
A three-stage transadmittance amplifier projects the linear equivalent circuit of Figure
(P1.26). The response to the applied voltage signal, Vs, is the indicated current, I2.
(a). Identify the feedback network and indicate the type of feedback (series-series, seriesshunt, etc.) applied to the three-stage base amplifier.
(b). In light of the topological feedback form deduced in Part (a), determine the appropriate
set of two port parameters for the feedback subcircuit.
(c). Use the results of Part (b) to provide an alternate linear equivalent circuit that explicitly
identifies the feedback factor, as well as the amount of feedforward.
(d). Exploit the results of Part (c) to determine expressions for the loop gain, open loop
transadmittance, closed loop transadmittance, and closed loop driving point input and
output resistances, Rin, and Rout, respectively.
(e). What conditions must be satisfied if a high loop gain is to be achieved?
(f). If the loop gain is indeed very large, what is the approximate closed loop transadmittance?
Ming Hsieh Department of Electrical Engineering
- 168 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
I2
+
Va
Rs
+
Rin
+
gmVa
Ra
−
+
Vb
gmVb
−
Rb Vc
gmVc
−
Rc
Rout
Vs
−
R
R1
R1
R2
Figure (P1.26)
Problem #1.27
The feedback subcircuit in the three-stage transadmittance amplifier studied in Problem
#1.26 is modified in accordance with the schematic diagram in Figure (P1.27). In terms of
resistances R1 and R2 in the preceding problem, what relationships must be satisfied by
resistances Rx and Ry if the two networks are to deliver identical closed loop performance?
I2
+
Va
Rs
+
Rin
+
gmVa
−
Ra
+
Vb
gmVb
−
Rb Vc
gmVc
−
Vs
Rc
Rout
R
−
Rx
Ry
Rx
Figure (P1.27)
Problem #1.28
The two port network in Figure (P1.28) is fundamentally a voltage amplifier that utilizes a
feedback capacitance, Cf, to establish a low frequency network pole.
(a). Determine the short circuit admittance parameters and corresponding y-parameter
equivalent circuit of the feedback subcircuit. Use this y-parameter model to construct
an alternative amplifier equivalent circuit that clearly identifies the feedback and
feedforward factors associated with the closed loop voltage gain, V2/V1.
(b). Use the alternative model developed in Part (a) to derive an expression for the loop
gain of the overall network.
(c). Give an expression for the open loop voltage gain, V2/V1.
Ming Hsieh Department of Electrical Engineering
- 169 -
USC Viterbi School of Engineering
Lecture Supplement #2
Two-Port & Basic Amplifier Networks
J. Choma
(d). Give an expression for the closed loop voltage gain, V2/V1.
(e). Derive expressions for the frequencies of the closed loop pole and closed loop zero
established by the feedback capacitance, Cf.
Cf
ra
ro
V1
+
rb
V
V2
−
Rl
AoV
−
+
Figure (P1.28)
Problem #1.29
Figure (P1.29) depicts the schematic diagram of a model for a current amplifier commonly
used in MOS technology architectures. Find the hybrid g-parameters of the model and draw
the corresponding g-parameter equivalent circuit.
I2
gmVc
+
ro Vb
−
gmV b
ro
+
Vc
−
gmV a
ro
+ Va −
V2
I1
V1
Figure (P1.29)
Problem #1.30
For the two RC networks appearing in Figure (P1.30), use the appropriate two port parameters to evaluate the frequencies associated with the pole and zero of the forward transadmittance function.
V1
I1
R
C
I2
V2
V1
I1
R
R
I2
V2
C
(a).
(b).
Figure (P1.30)
Ming Hsieh Department of Electrical Engineering
- 170 -
USC Viterbi School of Engineering