MCOR Hardware Design Notes
Version 2.0
March 24, 2016
Jeff Olsen
Table of Contents
Revision History ................................................................................................................................... 4
Document .......................................................................................................................................... 4
FPGA ................................................................................................................................................ 4
BAR 0 Memory Map – MCOR Registers............................................................................................. 6
BAR 2 Memory Map – EVR Registers ................................................................................................ 6
Configuration/Status Set/Reset Registers ............................................................................................ 7
Configuration/Status Register ........................................................................................................... 7
Set Register ....................................................................................................................................... 7
Reset Register ................................................................................................................................... 7
MCOR Channel Registers..................................................................................................................... 8
Channel Registers ............................................................................................................................. 8
Channel Configuration/Status Register......................................................................................... 9
Configuration Set/Reset Register .................................................................................................. 9
Ramp Rate..................................................................................................................................... 9
Full Scale Current ............................................................................................................................. 9
Full Scale SetPoint Current ......................................................................................................... 10
Full Scale ReadBack Current ...................................................................................................... 10
Samples/Average ........................................................................................................................ 10
Bulk Supply ........................................................................................................................................ 10
Bulk Supply Registers .................................................................................................................... 10
Bulk Supply Status/Configuration Register ................................................................................ 11
Bulk Supply Set/Reset Configuration Register........................................................................... 11
MCOR ADC Control .......................................................................................................................... 12
ADC Control Registers ................................................................................................................... 12
Control Register .......................................................................................................................... 12
Control Set/Reset Register .......................................................................................................... 12
Oversampling Control ................................................................................................................. 13
MCOR Faults ...................................................................................................................................... 14
Fault Registers ................................................................................................................................ 14
Fault Status.................................................................................................................................. 14
Latched Fault Status .................................................................................................................... 14
Reset Latched Fault Status .......................................................................................................... 14
Control Register .......................................................................................................................... 14
Control Set/Reset Register .......................................................................................................... 15
WaveForm Capture ............................................................................................................................. 15
WaveForm Capture Registers ......................................................................................................... 15
Rate ............................................................................................................................................. 15
Trigger Delay .............................................................................................................................. 15
Channel Mask ............................................................................................................................. 15
Control ........................................................................................................................................ 15
Trigger......................................................................................................................................... 16
Memory Size ............................................................................................................................... 16
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Wave Form Memory ....................................................................................................................... 16
Interlocks............................................................................................................................................. 17
Interlock Registers .......................................................................................................................... 17
Set/Reset Output ......................................................................................................................... 17
Output Status............................................................................................................................... 17
Input Status ................................................................................................................................. 17
MCOR Voltage Monitor Interface ...................................................................................................... 18
Voltage Monitor Registers .............................................................................................................. 18
Xilinx System Monitor ....................................................................................................................... 19
Read Xilinx Monitor ....................................................................................................................... 19
System Information ............................................................................................................................. 20
Beam Synchronous Acquisition (BSA) – NOT Implemented ............................................................ 20
Interrupts ............................................................................................................................................. 21
Interrupt Registers........................................................................................................................... 21
Interrupt Source .......................................................................................................................... 21
Interrupt Source Enable Set/Reset .............................................................................................. 21
EVR Control Registers ....................................................................................................................... 22
Trigger Output Select...................................................................................................................... 22
Selection Control word ............................................................................................................... 22
Fiber Optic Transceiver data ............................................................................................................... 23
EEPROM Serial ID Memory Contents – ........................................................................................ 24
Serial ID data fields – Address 0xA0 (from SFF-8472 MSA). .................................................. 24
Enhanced Feature Set Memory (Address A2h) .......................................................................... 25
EVR Interface ..................................................................................................................................... 27
Timing Registers ............................................................................................................................. 27
Data Buffer Memory ....................................................................................................................... 28
Control and Status Register [0x000] ........................................................................................... 28
Map Address Register [0x002] ................................................................................................... 29
Map Data Register [0x004] ......................................................................................................... 29
Output Pulse Enable Register [0x006] ........................................................................................ 29
Level Enable Register [0x008].................................................................................................... 29
Trigger Enable Register [0x00A] ................................................................................................ 29
Timestamp Event Counter Register [0x00C] .............................................................................. 29
Timestamp Latch Register [0x010]............................................................................................. 29
Event FIFO Register [0x014] ...................................................................................................... 29
PDP Enable Register [0x018] ..................................................................................................... 30
Indirect Address Register [0x01A] ............................................................................................. 30
CPU Interrupt Vector [0x020] .................................................................................................... 30
IRQ Enable
[0x022]................................................................................................................... 30
Distributed Bus Enable [0x024] .................................................................................................. 31
Multiplexed PreScaler Data [0x028]........................................................................................... 32
Event PreScaler Data [0x02A] .................................................................................................... 32
Firmware Version [0x02E] ......................................................................................................... 32
Seconds Shift Register [0x054]................................................................................................... 32
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Timestamp Latched Seconds [0x058] ......................................................................................... 32
Event FIFO Seconds [0x060] ...................................................................................................... 32
Event FIFO Event Counter [0x064] ............................................................................................ 32
Output Polarity [0x068] ............................................................................................................. 33
Extended 32bit Multiplexed Delay [0x06C] .............................................................................. 33
Extended 32bit Multiplexed Width [0x070] .............................................................................. 33
Data Buffer Control and Status [0x07A] ................................................................................... 33
MCOR Voltage and Current Monitoring ADC .................................................................................. 34
Address “000” ................................................................................................................................. 34
Register 1 .................................................................................................................................... 34
Register 6 .................................................................................................................................... 34
Register 7 .................................................................................................................................... 35
Register 8 .................................................................................................................................... 35
Address “001” ................................................................................................................................. 35
Register 1 – Channel Enable ....................................................................................................... 36
Register 6 – V1-V4 Control ........................................................................................................ 36
Register 7 – V5-V7 Control ........................................................................................................ 36
Register 8 – Temperature Control............................................................................................... 36
Address “010” ................................................................................................................................. 37
Register 1 .................................................................................................................................... 37
Register 6 .................................................................................................................................... 37
Register 7 .................................................................................................................................... 38
Register 8 .................................................................................................................................... 38
Revision History
Document
Version
1.0
2.0
Date
7/20/2012
7/20/2012
7/31/2012
USB Waveform, no interrupts
Added Interrupt section
Updated Wave Form Acquisition section
Added EVR Control Registers
FPGA
Date
FPGA
2.00
7/12/2012
7/31/2012
USB Waveform, no interrupts
Increased PCIe Address space to accommodate Wave Form Memory
Added EVR Control Registers
Added EVR Functionality
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BAR 0 Memory Map – MCOR Registers
BAR 0 Address
0x003C0 – 0x00000
0x0043C – 0x00400
0x0047C – 0x00440
0x004BC – 0x00480
0x004FC – 0x004C0
0x0053C – 0x00500
0x0057C – 0x00540
0x005BC – 0x00580
0x005FC – 0x005C0
0x0067C – 0x00600
0x006BC – 0x00680
0x006FC – 0x006C0
0x017FE – 0x01000
0x01FFF – 0x01800
0x7FFFC – 0x40000
Channel Control Registers
Bulk Supply Registers
MCOR ADC Control Registers
Fault Registers
Waveform Capture Registers
Interlocks (Future Use)
MCOR Voltage Monitor
Xilinx System Monitor
MCOR System Information
512 Bytes Transceiver data
Interrupt Registers
MCOR EVR Control Registers
EVR Register Interface from USB (No BAR)
EVR Data Buffer Memory from USB (No BAR)
Waveform Memory
BAR 2 Memory Map – EVR Registers
0xFFFF – 0x0000
ERV Interface Base
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Configuration/Status Set/Reset Registers
Many of the MCOR functions are controlled by three registers within the block of registers:
Configuration/Status Register
This Register will contain the current value of the settings for the particular bits.
Set Register
Writing a ‘1’ to a bit in this register will SET the corresponding bit in the Configuration/Status register
without affecting any other bits.
Reset Register
Writing a ‘1’ to a bit in the register will CLEAR the corresponding bit in the Configuration/Status register
without affecting any other bits.
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MCOR Channel Registers
Each channel has a set of Configuration and Data Registers.
Channel Base
0x0000
0x0040
0x0080
0x00C0
0x0100
0x0140
0x0180
0x01C0
0x0200
0x0240
0x0280
0x02C0
0x0300
0x0340
0x0380
0x03C0
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Channel 9
Channel 10
Channel 11
Channel 12
Channel 13
Channel 14
Channel 15
Channel Registers
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
Reg
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Set Point Requested
Current Set Point
Monitor ADC Reading
Monitor Average ADC Reading
Monitor Ripple Measurement
FeedBack ADC Reading
FeedBack Average ADC Reading
FeedBack Ripple Measurement
Fullscale SetPoint Current
Fullscale ReadBack Current
Ramp Rate
Samples per Average
Configuration/Status Register
Set Configuration Register
Reset Configuration Register
Int32 in uA
Int32 uA/sec
UInt32
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Channel Configuration/Status Register
Bit
6
Fault Status
5
Ramping
4
Standardized
Direction
Ramp Mode
3
2
1
0
‘1’  MCOR Power Module Faulted
‘0’  MCOR Power Module OK
‘1’  Ramping in progress
‘0’  Ramping done
‘1’  Falling
‘0’  Rising
‘1’  Immediate, no ramping
‘0’  Normal Ramp Mode Selected
‘1’  Closed Loop
‘0’  Open Loop
‘1’  Channel being used for Fast Feedback
‘0’  Normal MCOR functionality
Cleared by power on, set to indicate the
channel has been configured.
Closed Loop
(Auto Trim)
Fast
FeedBack
Configured
Not implemented
Not implemented
Not implemented
Configuration Set/Reset Register
Bit
4
3
2
1
0
Standardized Direction
Ramp/Immediate
Closed Loop
Fast FeedBack
Configured
Ramp Rate
Bit
[31:00]
Ramp Rate
Int32 in ua/sec
Full Scale Current
The Fullscale value for the SetPoint DAC and the ReadBack ADC can be different depending on the type of
MCOR installed. MCOR 6, 9 and 12 have a ReadBack of 10V is 12A. MCOR 1, 1.5 and 2 have a ReadBack of
10V is 2A.
MCOR
30
20
12
9
6
2
1.5
1
Set Point Conversion
DAC
Current
10V
30A
10V
20A
10V
12A
10V
9A
10V
6A
10V
2A
10V
1.5A
10V
1A
Read Back Conversion
ADC
Current
10V
30A
10V
20A
10V
12A
7.5V
9A
5V
6A
10V
2A
7.5V
1.5A
5V
1A
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Full Scale SetPoint Current
Bit
[31:00]
Full Scale Current
Int32 in ua
Full Scale ReadBack Current
Bit
[31:00]
Full Scale Current
Int32 in ua
Samples/Average
Applies to both the Monitor and the FeedBack Channel
Bit
[31:03]
[02:00]
unused
Number of samples
to average over
0x5  32
0x4  16
0x3  8
0x2  4
0x1  2
0x0  1
Bulk Supply
Bulk Supply Registers
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
Reg
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Base 0x0400
Bulk Voltage Request
Bulk Supply Voltage
Bulk Supply Current
Ground Fault Current
Bulk Current Limit Request
Bulk Supply DAC Full Scale Voltage
Bulk Supply DAC Full Scale Current
Bulk Supply ADC Full Scale Voltage
Bulk Supply ADC Full Scale Current
Bulk Supply ADC Full Scale Ground Current
Ground Fault Current Threshold
Ramp Rate
Configuration/Status Register
Set Configuration Register
Reset Configuration Register
Int32 in uV
Int32 in uV
Int32 in uA
Int32 in uA
Int32 in uA
Int32 in uV
Int32 in uA
Int32 in uV
Int32 in uA
Int32 in uA
Int32 in uV
Int32 in uV/Sec
UInt32
UInt32
UInt32
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Bulk Supply Status/Configuration Register
Bit
7
Configured
6
Ground Fault
5
Fault
4
Ramping
3
Bulk On Status
(Bulk PS_OK)
Control Type
2
1
0
PS Reset
(Bulk SO)
PS On/Off Request
(Bulk ENA_In/Out)
‘1’  Bulk Supply Configured
‘0’  Bulk Supply not Configured
‘1’  Bulk Supply Ground Fault
‘0’  No Bulk Supply Ground Fault
‘1’  Bulk Supply Fault
‘0’  No Bulk Supply Fault
‘1’  Ramping in progress
‘0’  Ramping done
‘1’  Bulk Supply is ON
‘0’  Bulk Supply is OFF
‘1’  Slave
‘0’  Master
‘1’  Reset Asserted
‘0’  Reset Not Asserted
‘1’  Bulk Supply ON
‘0’  Bulk Supply OFF
Bulk Supply Set/Reset Configuration Register
Bit
4
Control Type
1
PS Reset
0
PS On/Off
Request
‘1’ Slave
‘0’  Master
‘1’  Assert Reset
‘0’  De-assert Reset
‘1’  Turn Bulk Supply ON
‘0’  Turn Bulk Supply OFF
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MCOR ADC Control
The ADC’s used for reading the MCOR has the option of running with oversampling. The following registers
control the functionality of the ADC’s.
ADC Control Registers
Offset
0x00
0x04
0x08
0x0C
0x0A
0x3C
Base = 0x0440
Control
Set Control
Reset Control
MCOR ADC OverSampling
Uint32
Control Register
Bit
[1]
Bulk ADC Reset
[0]
MCOR ADC’s Reset
‘1’  Bulk ADC Reset Asserted
‘0’  Bulk ADC Reset Not Asserted
‘1’  MCOR ADC Reset Asserted
‘0’  MCOR ADC Reset Not Asserted
Control Set/Reset Register
Bit
[1]
[0]
Bulk ADC Reset
MCOR ADC’s Reset
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Oversampling Control
Bit
[14-12]
[11-09]
[08-06]
[05-03]
[02-00]
Bulk Supply
MCOR ADC Channels 15 – 12
MCOR ADC Channels 11 – 8
MCOR ADC Channels 7 – 4
MCOR ADC Channels 3 – 0
See Analog Devices AD7609 for
more details
Increasing the oversampling rate will slow down the conversion rate of the ADC, this will affect the 100Khz
normal operation of the ADC.
From Analog Devices AD7609 datasheet
OS [2:0]
OS Ratio
000
001
010
011
100
101
110
111
No OS
2
4
8
16
32
64
Invalid
SNR ±5V
Range (dB)
90.8
93.3
95.5
98
100.6
101.8
102.7
SNR ±10V
Range (dB)
91.5
93.9
96.4
98.9
101
102
102.9
−3 dB BW 5V
Range (kHz)
22
22
18.5
11.9
6
3
1.5
−3 dB BW 10V
Range (kHz)
33
28.9
21.5
12
6
3
1.5
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MCOR Faults
Fault Registers
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x29
0x28
0x2C
0x30
0x34
0x38
0x3C
Base = 0x0480
MCOR Power Module Fault Status
MCOR Power Module Latched Fault Status
Reset Latched Fault Status
Control
Set Control
Reset Control
Fault ByPass
Set Fault Bypass
Reset Fault Bypass
Magnet Fault Status
Magnet Latched Fault Status
Reset Magnet
Latched Fault Status
External Interlock Status
Set External Interlock
Reset External Interlock
Uint32
The MCOR Faults and the Magnet Faults are conditioned with a 2.55us filter.
Fault Status
Bit
[15:00]
MCOR Power Module Fault Status
Latched Fault Status
Bit
[15:00]
MCOR Power Module Latched Fault Status
Reset Latched Fault Status
Bit
[15:00]
Reset MCOR Power Module Latched Fault Status
Control Register
Bit
[1]
MCOR Inhibit
[0]
MCOR Reset
‘1’  MCOR Inhibit Asserted
‘0’  MCOR Inhibit Not Asserted
‘1’  MCOR Reset Asserted
‘0’  MCOR Reset Not Asserted
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Control Set/Reset Register
Bit
[1]
[0]
MCOR Inhibit
MCOR Reset
WaveForm Capture
WaveForm Capture Registers
The Xilinx XC5VLX30T has 1296Kb of internal RAM, 162Kbytes, 64Kwords. The rate and timing of the capture
is controlled by the following registers:
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
Base = 0x04C0
Rate
Channel Mask
Trigger Delay
Control
Trigger
Memory Size
20Khz/N+1; N=0-1023
Select which Channels are stored.
Delay in 20Khz ticks, N=0-1023
Rate
Controls the rate at which the samples are stored into memory. It does not affect the normal 20Khz
operation of the ADC’s (Oversampling control will still effect the 20Khz operation).
Trigger Delay
This value delays the start of the Waveform acquisition by N ticks from either the ramp or EVR trigger. It has
no effect in the immediate mode.
Channel Mask
The channel mask selects which of the 32 ADC channels are stored into the Waveform memory.
Control
Bit
[31-02]
[01-00]
Trigger Mode
“11”  EVR
“10”  Ramp End
“01”  Ramp Start
“00”  Immediate
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Trigger
[31-08]
[07-02]
[01]
[00]
unused
Channel Count
Stop Acq
Trigger
Count of channels enabled from 0 to 32
‘1’  Terminate current Waveform Acquisition
‘1’  Enable
‘0’  Done
Setting this Bit 0 enables the Waveform acquisition. In the immediate mode, the acquisition will start when
bit 0 is set. In the Ramp Start mode, the acquisition will start when the next new setpoint is written. In the
Ramp End mode, the acquisition will start when all of the channels have finished Ramping. In the EVR mode,
the acquisition will start when the selected EVR trigger occurs. Bit 0 is reset when the Waveform acquisition
is done.
Memory Size
[31-24]
[23-00]
Memory Size
Channel Block
Size
Waveform Memory size in 1K words
Number of Samples for each of the enabled
channels
Wave Form Memory
The Waveform Memory contains up to 64K samples of ADC Data, depending on the Xilinx internal memory
size. The content of the Waveform Memory depends on which channels are selected in the Channel Mask. If
channels A, B and C are enabled, then the memory would look like this:
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
Base 0x40000
Channel A-0
Channel B-0
Channel C-0
Channel A-1
Channel B-1
Channel C-1
Int32 in ADC Counts
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Interlocks
For future use, 4 outputs and 8 inputs are provided.
Interlock Registers
Offset
0x00
0x04
0x08
0x0C
0x10
0x0E
Base = 0x0500
Set Output
Reset Output
Output Status
Input Status
UInt32
Set/Reset Output
Bit
[31:4]
[03:00]
Unused
Output
Output Status
Bit
[31:4]
[03:00]
Unused
Output
Input Status
Bit
[31:08]
[07:00]
Inputs
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MCOR Voltage Monitor Interface
Several Board voltages are monitored. They can be read back in the following registers.
Voltage Monitor Registers
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
Base = 0x0540
+15.0V(In)
+12.0V(In)
+5.0V(In)
+3.3V
+3.3VCC IO
-15.0V(In)
+15.0V(In) Current
+12.0V(In) Current
+5.0V(In) Current
+3.3V Current
+3.3VCCIO Current
+2.5V Current
+1.0V Current
-15.0V(In) Current
Board Temperature
Int32
𝑉 = 𝑁 ∗ 6.0 ∗ 305.18𝐸 −6
𝑉 = 𝑁 ∗ 4.83 ∗ 305.18𝐸 −6
𝑉 = 𝑁 ∗ 2.0 ∗ 305.18𝐸 −6
𝑉 = 𝑁 ∗ 305.18𝐸 −6
𝑉 = 𝑁 ∗ 305.18𝐸 −6
𝑉 = 𝑁 ∗ −16.0 ∗ 305.18𝐸 −6
𝐼 = 𝑁 ∗ 19.0735𝐸 −6 /60𝐸 −3
𝐼 = 𝑁 ∗ 19.0735𝐸 −6 /150𝐸 −3
𝐼 = 𝑁 ∗ 19.0735𝐸 −6 /30𝐸 −3
𝐼 = 𝑁 ∗ 19.0735𝐸 −6 /150𝐸 −3
𝐼 = 𝑁 ∗ 19.0735𝐸 −6 /150𝐸 −3
𝐼 = 𝑁 ∗ 19.0735𝐸 −6 /150𝐸 −3
𝐼 = 𝑁 ∗ 19.0735𝐸 −6 /150𝐸 −3
𝐼 = 𝑁 ∗ 19.0735𝐸 −6 /60𝐸 −3
N* 0.0625
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Xilinx System Monitor
Base Address for the Xilinx System Monitor is 0x00000580
The Xilinx contains an on chip monitor that, among other things, allows access to the chip temperature and
V(Int) and V(Aux). The current value as well as the Min and Max are stored in the Xilinx and can be readout
via the System Monitor Interface.
Read Xilinx Monitor
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x3C
Base = 0x0580
Current Temp
Current V(Int)
Current V(Aux)
Max Temp
Max V(Int)
Max V(Aux)
Min Temp
Min V(Int)
Min V(Aux)
Int32 in ADC Counts
𝐶𝑜𝑢𝑛𝑡𝑠
𝑇𝑒𝑚𝑝𝑒𝑟𝑎𝑡𝑢𝑟𝑒 (°C) = (
∗ 503.975/1024) − 273.15
64
Volts =
𝑐𝑜𝑢𝑛𝑡𝑠
/ 1024 ∗ 3
64
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System Information
Offset
0x00
0x08
0x0C
0x16
0x1F
Base = 0x05C0
Firmware Version
System ID
Sub Type
Firmware Date
8 Bytes, ASCII = ” 00000001”
4 Bytes, ASCII = “MCOR”
10 Bytes, ASCII = “
“
10 Bytes, ASCII = ” dd/mm/yyyy”
Beam Synchronous Acquisition (BSA) – NOT Implemented
Address
Time Stamp
⁞
Time Stamp
MCOR 0 Monitor Average ADC
⁞
MCOR 15 Monitor Average ADC
MCOR 0 FeedBack Average ADC
⁞
MCOR 15 FeedBack Average ADC
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Interrupts
The MCOR Controller could generate several interrupts.
1.
2.
3.
4.
Fault Detected
Waveform Acquisition complete
BSA Message available
EVR Interrupts
Interrupt Registers
Offset
0x00
0x08
0x0C
0x16
Base = 0x0680
Interrupt Source
Interrupt Source Enables
Interrupt Source Set Enable
Interrupt Source Reset Enable
Interrupt Source
Bit
[31:06]
[05]
[04]
[03]
[02]
[01]
[00]
Unused
COMx GPI
BSA Message Available
EVR Interrupt
OR of the Magnet Faults
OR of the MCOR Channel
Faults
Waveform Acquisition
complete
From COMx GPIO
Not Implemented
Not Implemented
External Interlocks
Writing a ‘1’ to a bit in the Interrupt Source will reset the corresponding bit if the cause of the interrupt has
been cleared. If the cause of the interrupt has not been cleared, the corresponding bit will not be reset and
another interrupt will be generated.
Interrupt Source Enable Set/Reset
Bit
[31:01]
[00]
Unused
End of Waveform Capture
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EVR Control Registers
Offset
0x00
0x04
Base = 0x06C0
Trigger Select for EVR OUT 1 (P5)
Trigger Select for EVR OUT 2 (P6)
Trigger Output Select
Bit
[31:05]
[04:00]
Trigger Select for EVR
Selection Control word
Value
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
EVR Trigger
PDP(3)
PDP(2)
PDP(1)
PDP(0)
TEV(6)
TEV(5)
TEV(4)
TEV(3)
TEV(2)
TEV(1)
TEV(0)
OTP(13)
OTP(12)
OTP(11)
OTP(10)
OTP(9)
Value
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EVR Trigger
OTP(8)
OTP(7)
OTP(6)
OTP(5)
OTP(4)
OTP(3)
OTP(2)
OTP(1)
OTP(0)
LVL(6)
LVL(5)
LVL(4)
LVL(3)
LVL(2)
LVL(1)
LVL(0)
PDP – Programmable Delayed Pulse
TEV – Trigger Event
OTP – Output Pulse
LVL – Output Level
See EVR Documentation for more information
SLAC NATIONAL ACCELERATOR LABORATORY
Page 22 of 38
Fiber Optic Transceiver data
The Transceivers have diagnostics built in to facilitate component monitoring, fault isolation and predictive
failure (See AVAGO app note 5016). All 512 bytes of diagnostic data is available in the Xilinx memory starting
at location 0x1000. The byte data from the transceiver is read as 32 bit word.
Offset
SFP 0xA0
0x00
0x04
0x40
0x44
SFP 0XA2
Extended Data
Base = 0x0600
MSB
Byte 3
Byte 2
Byte 7
Byte 6
Byte 1
Byte 5
LSB
Byte 0
Byte 4
Byte 3
Byte 7
Byte 1
Byte 5
Byte 0
Byte 4
Byte 2
Byte 6
SLAC NATIONAL ACCELERATOR LABORATORY
Page 23 of 38
EEPROM Serial ID Memory Contents –
The following tables are from the AVAGO datasheet. For detailed information see AVAGO Datasheet.
Serial ID data fields – Address 0xA0 (from SFF-8472 MSA).
Byte #
0
1
2
3-10
11
12
13
14
15
16
17
18
19
20-35
36
37-39
40-55
58-59
60-61
62
63
Size
1
1
1
8
1
1
1
1
1
1
1
1
1
16
1
3
16
4
2
1
1
64-65
66
67
68-83
84-91
92
2
1
1
16
8
1
93
1
94
95
1
1
96-127
128-255
32
128
Name Field
Identifier
Ext. Identifier
Connector
Transceiver
Encoding
BR, Nominal
Reserved
Length (9μm) km
Length (9μm)
Length (50μm)
Length (62.5μm)
Length (Copper)
Reserved
Vendor name
Reserved
Vendor OUI
Vendor PN
Vendor rev
Wavelength
Reserved
CC_BASE
BASE ID FIELDS
Description Field
Type of serial transceiver
Extended identifier of type of serial transceiver
Code for connector type
Code for electronic compatibility or optical compatibility
Code for serial encoding algorithm
Nominal bit rate, units of 100 Mbits/sec.
Link length supported for 9/125 Ïm fiber, units of km
Link length supported for 9/125 Ïm fiber, units of 100m
Link length supported for 50/125 Ïm fiber, units of 10m
Link length supported for 62.5/125 Ïm fiber, units of 10m
Link length supported for copper, units of meters
SFP vendor name (ASCII)
SRP vendor IEEE company ID
Part number provided by SFP vendor (ASCII)
Revision level for part number provided by vendor (ASCII)
Laser wavelength
Check code for Base ID Fields (addresses 0 to 62)
EXTENDED ID FIELDS
Options
Indicates which optional transceiver signals are implemented
BR, max
Upper bit rate margin, units of %
BR, min
Lower bit rate margin, units of %
Vendor SN
Serial number provided by vendor (ASCII)
Date Code
Vendor’s manufacturing date code
Diagnostic Monitoring Type Indicates which type of diagnostic monitoring is implemented (if any) in
the transceiver
Enhanced Options
Indicates which optional enhanced features are implemented (if any) in
the transceiver
SFF-8472 Compliance
Indicates which revision of SFF8472 the transceiver complies with
CC_EXT
Check code for the Extended ID Fields addresses 64 to94
VENDOR SPECIFIC ID FIELDS
Vendor Specific
Vendor Specific EEPROM
Reserved
Reserved for future use
SLAC NATIONAL ACCELERATOR LABORATORY
Page 24 of 38
Enhanced Feature Set Memory (Address A2h)
Byte #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Temp H Alarm LSB[1]
Temp L Alarm MSB[1]
Temp L Alarm LSB[1]
Temp H Warning MSB[1]
Temp H Warning LSB[1]
Temp L Warning MSB[1]
Temp L Warning LSB[1]
Vcc H Alarm MSB[2]
Vcc H Alarm LSB[2]
Vcc L Alarm MSB[2]
Vcc L Alarm LSB[2]
Vcc H Warning MSB[2]
Vcc H Warning LSB[2]
Vcc L Warning MSB[2]
Vcc L Warning LSB[2]
Tx Bias H Alarm MSB[3]
Tx Bias H Alarm LSB[3]
Tx Bias L Alarm MSB[3]
Tx Bias L Alarm LSB[3]
Tx Bias H Warning MSB[3]
Tx Bias H Warning LSB[3]
Tx Bias L Warning MSB[3]
Tx Bias L Warning LSB[3]
Tx Pwr H Alarm MSB[4]
Tx Pwr H Alarm LSB[4]
Tx Pwr L Alarm MSB[4]
Tx Pwr L Alarm LSB[4]
Tx Pwr H Warning MSB[4]
Tx Pwr H Warning LSB[4]
Tx Pwr L Warning MSB[4]
Tx Pwr L Warning LSB[4]
Rx Pwr H Alarm MSB[5]
Rx Pwr H Alarm LSB[5]
Byte #
34
35
36
37
38
39
40-55
56-94
95
96
97
98
99
100
101
102
103
104
105
106
107
110
111
112
113
114
115
116
117
118-127
128-247
248-255
Rx Pwr L Alarm MSB[5]
Rx Pwr L Alarm LSB[5]
Rx Pwr H Warning MSB[5]
Rx Pwr H Warning LSB[5]
Rx Pwr L Warning MSB[5]
Rx Pwr L Warning LSB[5]
Reserved
External Calibration Constants[6]
Checksum for Bytes 0-94[7]
Real Time Temperature MSB[1]
Real Time Temperature LSB[1]
Real Time Vcc MSB[2]
Real Time Vcc LSB[2]
Real Time Tx Bias MSB[3]
Real Time Tx Bias LSB[3]
Real Time Tx Power MSB[4]
Real Time Tx Power LSB[4]
Real Time Rx average MSB[5]
Real Time Rx average LSB[5]
Reserved
Reserved
Status/Control
Reserved
Flag Bits
Flag Bits
Reserved
Reserved
Flag Bits
Flag Bits
Reserved
Customer Writeable
Vendor Specific
SLAC NATIONAL ACCELERATOR LABORATORY
Page 25 of 38
Notes:
1. Temperature (Temp) is decoded as a 16 bit signed two’s compliment integer in increments of 1/256°C.
2. Supply Voltage (Vcc) is decoded as a 16 bit unsigned integer in increments of 100 μV.
3. Laser bias current (Tx Bias) is decoded as a 16 bit unsigned integer in increments of 2 μA.
4. Transmitted average optical power (Tx Pwr) is decoded as a 16 bit unsigned integer in increments of 0.1
μW.
5. Received average optical power (Rx Pwr) is decoded as a 16 bit unsigned integer in increments of 0.1 μW.
6. Bytes 55-94 are not intended for use with AFCT-57R5APZ, but have been set to default values per SFF8472.
7. Byte 95 is a checksum calculated (per SFF-8472) and stored prior to product shipment.
SLAC NATIONAL ACCELERATOR LABORATORY
Page 26 of 38
EVR Interface
Timing Registers
Register
61
60-58
56
54
52
50
48
46
44
42
41
40
39
38-37
36-32
31-24
23
22
21
20
19
18
17
16
15
14
13
12
10
8
6
5
4
3
2
1
0
Address
0x07A
0x78-0x074
0x070
0x06C
0x068
0x064
0x060
0x05C
0x058
0x054
0x052
0x050
0x04E
0x04C-0x04A
0x048-0x040
0x03C-0x030
0x02E
0x02C
0x02A
0x028
0x026
0x024
0x022
0x020
0x01E
0x01C
0x01A
0x018
0x014
0x010
0x00C
0x00A
0x008
0x006
0x004
0x002
0x000
Width
16
16
32
32
32
32
32
32
32
32
16
16
16
16
16
32
16
Name
Data Buffer Control and Status
16
16
16
16
16
16
16
16
16
16
32
32
32
16
16
16
16
16
16
Event Prescaler
Prescaler Data
Distributed Bus Data
Distributed Bus Enable
IRQ Enable
IRQ Vector
unused
Multiplexed Width
Multiplexed Delay
Output Polarity
Event FIFO Counter
Event FIFO Seconds
unused
Timestamp Seconds Latch
Seconds Shift Register
Event Clock Control
External Event Code
sec Divider
LVPECL Output Map
TTL Output Map
unused
not implemented
not implemented
not implemented
not implemented
unused
Version
unused
not implemented
unused
unused
Register Select
Delayed Pulse Enable
Event FIFO
Timestamp Latch
Timestamp Event Counter
Trigger Output Enable
Level Output Enable
Output Pulse Enable
Mapping Ram Data
Mapping Ram Address
Control
Data Buffer Memory
The Data Buffer Memory is at 0xFFF – 0x800
Control and Status Register
[0x000]
Bit
[15]
Name
EVREN
Use
Master Enable
[14]
IRQEN
[13]
[12]
RSTS
HRTBT
[11]
IRQFL
[10]
[09]
LTS
MAPEN
Interrupt Request Enable
Individual interrupts sources are
controlled by IRQEnable
Reset Timestamp and Event Counters
Heart Beat Lost Flag
Set if no HeartBeat event is received in
last 1.6s
Event FIFO interrupt Flag
Set by FIFO Not Empty
Latch Timestamp Counter
Event Mapping Enable
[08]
MAPRS
Event Decoder Mapping Ram Select
[07]
NFRAM
[06]
VMERS
Null Fill Mapping RAM selected by
VMERS. Returns 0 when done
CPU R/W Mapping RAM Select
[05]
AUTOI
[04]
DIRQ
RSADR
RSFIFO
FF
[03]
[02]
[01]
[00]
Auto Increment Mapping RAM
Address
Delayed Interrupt Request Flag
Reset Mapping RAM address
Reset Event FIFO
FIFO Full Flag
FNE
RSDIRQ
RXVIO
‘1’ => Receiver Enabled
‘0’ => Receiver Disabled
‘1’ => Enable Interrupts
‘0’ => Disable all interrupts
‘1’ => Reset
‘1’ => Clear Flag
‘1’ => Clear Flag
‘1’ => Latch
‘1’ => Enabled
‘0’ => Disabled
‘1’ => RAM1
‘0’ => RAM0
‘1’ => Null Fill RAM
‘0’ <= Operation Done
‘1’ => RAM1
‘0’ => RAM0
‘1’ => Auto Increment
‘1’ => Reset Address
‘1’ => Reset FIFO
‘1’ => Clear FF Flag
Event FIFO Not Empty
Receiver Fault
Not Locked, invalid 8B/10B Character
or Disparity error on Link. Disables
Receiver for 50ms.
‘1’ => Clear DIRQ Flag
‘1’ => Clear RXVIO Flag
SLAC NATIONAL ACCELERATOR LABORATORY
Page 28 of 38
Map Address Register
Bit
[15:08]
[07:00]
Use
Unused
MAP RAM address for RAM selected
by VMERS
MAPAddr
Map Data Register
Bit
[15:00]
[0x002]
Name
Incremented by 1 when data is
written to MAPData register if
AUTOI is set.
[0x004]
Name
MAPData
Use
Writes Data to MAP Ram selected by
VMERS at address in MAPAddr
register
Increments MAPAddr by 1
when if AUTOI is set
Output Pulse Enable Register [0x006]
Bit
[15:14]
[13:00]
Name
OTP[13:00]
Level Enable Register
Bit
[15:07]
[06:00]
Use
unused
Enable or Disable the OTP Pulse
Does not affect OTP[7:0] when they are
configured for the Distributed Data bus
outputs in the DBEN register
[0x008]
Name
Use
unused
Enable or Disable the LVL outputs
LVL[06:00]
Trigger Enable Register
Bit
[15:07]
[06:00]
‘1’ => Enabled
‘0’ => Disabled
‘1’ => Enabled
‘0’ => Disabled
[0x00A]
Name
Use
unused
Enable or Disable the LVL outputs
TEV[06:00]
‘1’ => Enabled
‘0’ => Disabled
Timestamp Event Counter Register [0x00C]
Bit
[32:00]
Name
EventCounter
Use
Timestamp Event Counter
Timestamp Latch Register
Bit
[32:00]
Name
EventLatch
Event FIFO Register
Bit
[32:08]
[07:00]
[0x010]
Use
Timestamp Latch
[0x014]
Name
Timestamp
Counter
Event Code
Use
Timestamp Latch
SLAC NATIONAL ACCELERATOR LABORATORY
Page 29 of 38
PDP Enable Register
Bit
[15:04]
[03:00]
[0x018]
Name
Use
unused
Enable or Disable the PDP outputs
PDP[3:0]
Indirect Address Register
Bit
[15:05]
[04:00]
Name
DSEL[4:0]
‘1’ => Enabled
‘0’ => Disabled
[0x01A]
Use
unused
Select which register will be written for
the Multiplexed write operations
“11101” => OTP13
“11100” => OTP12
“11011” => OTP11
“11010” => OTP10
“11001” => OTP9
“11000” => OTP8
“10111” => OTP7
“10110” => OTP6
“10101” => OTP5
“10100” => OTP4
“10011” => OTP3
“10010” => OTP2
“10001” => OTP1
“10000” => OTP0
“00100” => Delayed IRQ
“00011” => PDP3
“00010” => PDP2
“00001” => PDP1
“00000” => PDP0
CPU Interrupt Vector
Bit
[15:08]
[07:00]
Name
IRQVect
[0x020]
Use
unused
Not implemented
IRQ Enable [0x022]
Bit
[15:06]
[05]
Name
IEDBUF
Use
unused
Data Buffer Interrupt Enable
[04]
IEDIRQ
Delayed Interrupt Enable
[03]
IEEVT
Event Interrupt Enable
Interrupt is set when a new
message is available in the Data
Buffer, DBRDY
Interrupt is cleared by DBENA,
DBDIS or if DBENable = ‘0’
Interrupt is set by Delayed
Interrupt MAP13
Interrupt is cleared by RSDIRQ
Interrupt is set by Event FIFO
SLAC NATIONAL ACCELERATOR LABORATORY
Page 30 of 38
[02]
IEHRT
HeartBeat lost Interrupt Enable
[01]
IEFF
Event FIFO Full Interrupt Enable
[00]
IEVIO
Receiver violation Interrupt Enable
Not Empty
Interrupt is clear by reading the
Event FIFO until it is empty.
Interrupt is set if no HeartBeat
event is received in the last 1.6s
Interrupt is cleared by HRTBT
Interrupt is set if the Event
FIFO goes full.
Interrupt is cleared by FF
Interrupt is set if the Receiver
losses lock, an invalid 8B/10B
code is received, or there is a
receiver disparity error.
Distributed Bus Enable [0x024]
Bit
[15:13]
[12]
[11:08]
[07:00]
Name
DBVEC
DBEN
Use
unused
Event counter clock source when Event
Prescaler is 0
Unused
OTP(x) output select
‘1’ => use counter clock event
‘0’ => use DisBus(4)
‘1’ => OTPx
‘0’ => DisBus(x)
SLAC NATIONAL ACCELERATOR LABORATORY
Page 31 of 38
Multiplexed PreScaler Data
Bit
[15:00]
Name
PRESCALE
Event PreScaler Data
Bit
[15:00]
Bit
[15:00]
Use
Prescale value written to Prescale
register pointed to by the indirect
address register (0x18)
[0x02A]
Name
PRESCALE
Firmware Version
[0x028]
Use
Event Prescaler
[0x02E]
Name
Version
Use
Firmware Version
0x0001 => SLAC
Seconds Shift Register [0x054]
Bit
[31:00]
Name
SecondsSr
Use
Seconds Shift register
Timestamp Latched Seconds [0x058]
Bit
[31:00]
Name
TSSec
Use
Timestamp Seconds latch
Event FIFO Seconds
Bit
[31:00]
[0x060]
Name
EvFIFOSec
Event FIFO Event Counter
Bit
[31:00]
Name
EvFIFOCntr
Use
Event FIFO Seconds
[0x064]
Use
Event FIFO Event Counter
SLAC NATIONAL ACCELERATOR LABORATORY
Page 32 of 38
Output Polarity
Bit
[31:25]
[24:11]
[10:04]
[03:00]
[0x068]
Name
POL[24:11]
Use
Unused
OTP[13:0] Polarity
POL[3:0]
Unused
PDP[3:0] Polarity
Extended 32bit Multiplexed Delay
Bit
[31:00]
Name
ExtDelay
‘1’ => Normal Active Hi
‘0’ => Inverted Active Lo
‘1’ => Normal Active Hi
‘0’ => Inverted Active Lo
[0x06C]
Use
Value written to Delay register pointed
to by the indirect address register
(0x18)
Extended 32bit Multiplexed Width [0x070]
Bit
[31:00]
Name
ExtWidth
Use
Value written to Width register pointed
to by the indirect address register
(0x18)
Data Buffer Control and Status
Bit
[15]
[0x07A]
[13]
Name
DBENA
DBRX
DBDIS
DBRDY
DBCS
Use
Enable single event
Data Buffer busy
Disable Data Buffer
Data Buffer Available
CheckSum Error
[12]
DBEN
Data Buffer Mode
[14]
Cleared by DBRX, DBRDY or
DBDIS
‘1’ => Shared Distributed Bus
and Data
‘0’ => Distributed Bus only
SLAC NATIONAL ACCELERATOR LABORATORY
Page 33 of 38
MCOR Voltage and Current Monitoring ADC
Three Linear Technology LTC2991, Octal I2C Voltage, Current and Temperature Monitor chips are used
to read the MCOR Monitor voltage and Currents. They are configured as follows:
Address “000”
Register
0x00
0x01
0x06
0x07
0x08
0x0D-0x0C
0x11-0x10
0x15-0x14
0x19-0x18
Value
Status Low
Channel Enable/Trigger
V1-4 Control
V5-8 Control
Acquisition Mode
V1-V2
V3-V4
V5-V6
V7-V8
0xF8
0xAA
0xAA
0x18
+3.3V Current
+2.5V Current
+1.0V Current
+5.0V(In) Current
Register 1
Bit
7
6
5
4
3
2
1
0
Enable V7/V8
Enable V5/V6
Enable V3/V4
Enable V1/V2
Enable Temp and VCC
Busy
Tempature(Internal) Valid
VCC Valid
+5.0V(In) Current
+1.0V Current
+2.5V Current
+3.3V Current
Read Only
Read Only
Read Only
Value
1
1
1
1
1
0
0
0
0xF8
Register 6
Bit
7
6
5
4
3
2
1
0
Enable Filter
Kelvin/Celsius
Temperature/Volts
V3-V4
Enable Filter
Kelvin/Celsius
Temperature/Volts
V1-V2
+2.5V Current
+3.3V Current
Value
1
0
0
1
1
0
0
1
0x99
SLAC NATIONAL ACCELERATOR LABORATORY
Page 34 of 38
Register 7
Bit
7
6
5
4
3
2
1
0
Enable Filter
Kelvin/Celsius
Temperature/Volts
V7-V8
Enable Filter
Kelvin/Celsius
Temperature/Volts
V5-V6
+5.0V(In) Current
+1.0V Current
Value
1
0
0
1
1
0
0
1
0x99
Register 8
Bit
7
6
5
4
3
2
1
0
PWM[0]
PWM Invert
PWM Enable
Repeated Acquisition Mode
Temperature(Internal) Filter
Kelvin/Celsius
Reserved
Reserved
Value
0
0
0
1
1
0
0
0
0x18
Address “001”
Register
0x00
0x01
0x06
0x07
0x08
0x0D-0xC
0x11-0x10
0x15-0x14
0x19-0x18
Value
Status Low
Channel Enable/Trigger
V1-4 Control
V5-8 Control
Acquisition Mode
V1-V2
V3-V4
V5-V6
V7-V8
0xF8
0xAA
0xAA
0x18
+15.0V(In) Current
-15.0V(In) Current
+3.3VCCIO Current
+12.0V(In) Current
SLAC NATIONAL ACCELERATOR LABORATORY
Page 35 of 38
Register 1 – Channel Enable
Bit
7
6
5
4
3
2
1
0
Enable V7/V8
Enable V5/V6
Enable V3/V4
Enable V1/V2
Enable Temp and VCC
Busy
Temperature(Internal) Valid
VCC Valid
+12.0V(In) Current
+3.3VCCIO Current
-15.0V(In) Current
+15.0V(In) Current
Read Only
Read Only
Read Only
Value
1
1
1
1
1
0
0
0
0xF8
Register 6 – V1-V4 Control
Bit
7
6
5
4
3
2
1
0
Enable Filter
Kelvin/Celsius
Temperature/Volts
V3-V4
Enable Filter
Kelvin/Celsius
Temperature/Volts
V1-V2
-15.0V(In) Current
+15.0V(In) Current
Value
1
0
0
1
1
0
0
1
0xAA
Register 7 – V5-V7 Control
Bit
7
6
5
4
3
2
1
0
Enable Filter
Kelvin/Celsius
Temperature/Volts
V7-V8
Enable Filter
Kelvin/Celsius
Temperature/Volts
V5-V6
+12.0V(In) Current
+3.3VCCIO Current
Value
1
0
0
1
1
0
0
1
0xAA
Register 8 – Temperature Control
Bit
7
6
5
4
3
2
1
0
PWM[0]
PWM Invert
PWM Enable
Repeated Acquisition Mode
Temperature(Internal) Filter
Kelvin/Celsius
Reserved
Reserved
Value
0
0
0
1
1
0
0
0
0x18
SLAC NATIONAL ACCELERATOR LABORATORY
Page 36 of 38
Address “010”
Register
0x00
0x01
0x06
0x07
0x08
0x0B-0x0A
0x0D-0x0C
0x0F-0x0E
0x11-0x10
0x13-0x12
0x15-0x14
Value
Status Low
Channel Enable/Trigger
V1-4 Control
V5-8 Control
Acquisition Mode
V1
V2
V3
V4
V5
V6
0x78
0x88
0x08
0x18
+3.3V
+3.3VCCIO
+5.0V(In)
+15.0V(In)
-15.0V(In)
+12.0V(In)
Register 1
Bit
7
6
5
4
3
2
1
0
Enable V7/V8
Enable V5/V6
Enable V3/V4
Enable V1/V2
Enable Temp and VCC
Busy
Temperature(Internal) Valid
VCC Valid
Unused
-15.0V(In) , +12.0V(In)
+5.0V(In) , +15.0V(In)
+3.3V, +3.3VCCIO
Read Only
Read Only
Read Only
Value
0
1
1
1
1
0
0
0
0x78
Register 6
Bit
7
6
5
4
3
2
1
0
Enable Filter
Kelvin/Celsius
Temperature/Volts
V3 and V4
Enable Filter
Kelvin/Celsius
Temperature/Volts
V1 and V2
+5.0V(In) , +15.0V(In)
+3.3V, +3.3VCCIO
Value
1
0
0
0
1
0
0
0
0x88
SLAC NATIONAL ACCELERATOR LABORATORY
Page 37 of 38
Register 7
Bit
7
6
5
4
3
2
1
0
Enable Filter
Kelvin/Celsius
Temperature/Volts
V7 and V8
Enable Filter
Kelvin/Celsius
Temperature/Volts
V5 and V6
Unused
-15.0V(In) , +12.0V(In)
Value
0
0
0
0
1
0
0
0
0x08
Register 8
Bit
7
6
5
4
3
2
1
0
PWM[0]
PWM Invert
PWM Enable
Repeated Acquisition Mode
Temperature(Internal) Filter
Kelvin/Celsius
Reserved
Reserved
Value
0
0
0
1
1
0
0
0
0x18
SLAC NATIONAL ACCELERATOR LABORATORY
Page 38 of 38