SEU Mitigation for FPGA-based
Systems
Roy Lee
Advisor: Lei He
royjylee@ucla.edu
http://eda.ee.ucla.edu
October 26, 2011
1
Outline
•
Introduction
•
In-Place Decomposition (IPD)
•
In-Place LUT Polarity Inversion (IPV)
•
Experimental Results
•
Conclusions & Future Works
Robustness in FPGAs
•
FPGAs are extensively used not only for prototyping but
also in a wide range of applications such as internet
networking and communication equipment, and
robustness is among the most important design objectives
•
An effective approach for reducing the impact of Single
Event Upset can lead to higher mean-time-tofailure(MTTF), increased quality of service, and reduced
maintenance cost
Single Event Upset (SEU)
•
Single Event Upsets (SEUs) : one of the main causes of
reliability reduction caused by charge particle strikes due
to cosmic radiation which create soft errors
•
Major effect on circuits : change the logic state of a static
memory element
•
Trend : SEU vulnerability is increasing with technology
shrinking
SEU in FPGAs
Thousands
•
Most of the commercial FPGAs employ SRAM as their
configuration memory elements for higher logic density
and programming flexibility
Three of the major memory elements in FPGAs : user
flip-flop, block RAM, and configuration RAM
Quantity
•
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
User Flip-Flop
Block RAM
xc5vlx220t
Configuration
RAM
Single Event Upset in FPGA
•
The circuit effect of SEUs in a FPGA is permanent until
the FPGA is re-programmed
 Interconnect :
 Logic :
LUT
I1
0
0
0
1
I2
I1
0
Configuration
Bits
MUX
I2
1
0
0
1
1
0
Configuration
Bits
SEU on Configuration RAM is much more critical!
Demand for In-Place Reliability Optimizations
•
Triple Modular Redundancy (TMR) is the most popular
fault tolerant technique, but it requires more than 3X
overhead on power, area, and cost
•
For non-mission critical applications, such as
communication systems, robustness improvement with
little or no overhead is highly demanded
•
In-place optimization techniques provide reliability
improvement while preserving circuit placement and
routing, and therefore the overhead is minimal
In-Place Resyntheses Flow
•
Mitigation after placement and routing without change of
placement and routing (and no change on design closure)
Design Entry
Logic Synthesis
In-Place Resyntheses
Map
In-Place Decomposition
(IPD)
Placement and Routing
Bitstream
In-Place LUT Polarity
Inversion (IPV)
Outline
•
Introduction
•
In-Place Decomposition (IPD)
•
In-Place LUT Polarity Inversion (IPV)
•
Experimental Results
•
Conclusions & Future Works
Fault Metrics
•
Soft Error Rate(SER) of a configuration SRAM bit:
1
SERb  n | {x | C ( x)  Cb ( x)} |
2
•
Mean-Time-To-Failure (MTTF)
•
System level measurement of reliability
•
For single fault model, MTTF  1/average(SERb)
In-Place LUT Decomposition
•
Leveraging the dual-output feature of LUT architecture
and the built-in carry chains
Dual-output 6LUT
Xilinx Virtex-5 6-input LUT architecture
LUT Decomposition
•
Decomposition : F = C( F1, F2, ……, Fn )
(C is the converging logic function)
Decomposition
Original LUT
Decomposed LUT
Example 1 : In-Place Duplication
Input
Output
SER
00000
0
S0
00001
0
S1
00010
0
S2
•
……
5-input AND function
……
……
5-input
11110
0
S30
11111
1
S31
The average SER of the LUT is : (S0+……+ S31)/32
Example 1 : In-Place Duplication
0 -> 1
Input
Output
SER
00000
0
S0
00001
0
S1
00010
0
S2
……
……
……
…...
Orig
11110
0
S30
11111
1
S31
Input
Output
SER
00000
0
S0
00001
0
S1
00010
0
S2
Covered
F
…...
Dup
0
……
……
……
•
11110
0
S30
11111
1
S31
Covered
The average SER of the LUT is reduced to (2*S31)/32
Example 2 : In-Place Decomposition
000
0
AS0
001
0
AS1
……
•
SER
……
F
•
Output
……
3LUT
2LUT
Input
110
0
AS6
111
1
AS7
Input
Output
SER
00
0
BS0
01
0
BS1
10
0
BS2
11
1
BS3
The number of SRAM bits used is reduced from 32 to 12,
and the SERs of unused bits are 0
The average SER is also reduced due to logic masking of
the converging logic
Outline
•
Introduction
•
In-Place Decomposition (IPD)
•
In-Place LUT Polarity Inversion (IPV)
•
Experimental Results
•
Conclusions & Future Works
Fault Masking for MUX
• Fault is masked when logic(i) = logic(j)
SEU on a routing MUX
b
…
…
b1
bm
MUX m
logic(i)
pin i
…
…
logic(j)
pin j
Example of Fault Masking
b1
MUX m
v(i)
v(j)
0 1 0 1 0 1 1 0 0 1 (+)
……
1 1 1 0 1 0 0 1 1 1 (+)
bm
MUX m
0 1 0 1 0 1 1 0 0 1 (+)
……
0 0 0 1 0 1 1 0 0 0 (–)
observ(m) 1 0 1 0 1 0 1 0 1 0
1010101010
soft error
0000000000
1010101010
bk
…
bm
…
bk
…
…
b1
SER(bk)=( v(i)  v(j) ) · observ(m)
observ(m) is the fault observability at MUX m : the
probability of the fault that can be propagated to
the primary outputs
LUT Polarity Inversion
a,+
b,+
a,+
b,+
c,+
(000) = 0
(001) = 1
(010) = 0
(011) = 1
(100) = 0
(101) = 1
(110) = 1
(111) = 0
c,+
(000) = 1
(001) = 0
(010) = 1
(011) = 0
(100) = 1
(101) = 0
(110) = 0
(111) = 1
o,-
(000) = 1
(001) = 0
(010) = 0
(011) = 1
(100) = 1
(101) = 0
(110) = 1
(111) = 0
o,+
LUT inversion
o,+
a,b,+
c,-
Fanout adjustment
Polarity can be determined independently
for each input and the output of an LUT
Inversion to Reduce SER
b1
MUX m
1 (90%)
0 (10%)
1 (20%)
0 (80%)
pin i, +
…
…
pin j, +
SER: 1-0.9*0.20.1*0.8=0.74
b
…
bm
…
b
…
…
b1
bm
MUX m
1 (90%)
0 (10%)
0 (20%)
1 (80%)
pin i, +
…
…
pin j, -
SER: 1-0.9*0.80.1*0.2=0.26
Outline
•
Introduction
•
In-Place Decomposition (IPD)
•
In-Place LUT Polarity Inversion (IPV)
•
Experimental Results
•
Conclusions & Future Works
Improvement by IPD
SER reduction for MCNC benchmarks mapped to 6-input LUTs
LUT-Level
ABC
Chip-level
IPD
ABC
IPD
alu4
0.34%
0.11%
0.45%
3.23%
apex2
0.29%
0.04%
0.33%
2.67%
apex4
1.16%
0.25%
1.41%
10.63%
des
1.42%
1.01%
2.43%
13.95%
ex1010
1.24%
0.29%
1.53%
11.60%
exp5p
0.73%
0.24%
0.97%
7.06%
misex3
0.55%
0.10%
0.65%
5.08%
pdc
0.91%
0.11%
1.02%
8.51%
seq
0.63%
0.11%
0.74%
5.78%
spla
1.14%
0.16%
1.30%
10.67%
SER Ratio
1.00
0.22
1.00
0.94
MTTF Imp.
1.00
4.52
1.00
1.07
IPV increase LUT-level MTTF by 4.52x, and
chip-level MTTF by 1.07x (due to
dominance of interconnects)
Improvement by IPV
SER for MCNC benchmarks mapped to 6-input LUTs
Interconnect
ABC
Chip-level
IPV
ABC
IPV
alu4
3.06%
1.54%
3.40%
0.88%
apex2
2.61%
0.70%
2.90%
1.04%
apex4
10.44%
2.13%
11.60%
6.37%
des
12.78%
11.71%
14.20%
13.03%
ex1010
11.16%
1.50%
12.40%
4.40%
exp5p
6.57%
3.46%
7.30%
4.10%
misex3
4.95%
1.66%
5.50%
2.20%
pdc
8.19%
0.65%
9.10%
1.24%
seq
5.67%
1.67%
6.30%
1.28%
spla
10.26%
0.73%
11.40%
1.47%
SER Ratio
1.00
0.25
1.00
0.33
MTTF Imp.
1.00
3.99
1.00
3.07
IPV on average increases chip-level MTTF
by 3.07X
Less than 50% LUTs need to be inverted
Improvement by Combined Algorithms
Averaged SER reduction for MCNC benchmarks mapped to 6-input LUTs
Combined
Algorithms
LUT Level
Chip Level
IPF + IPD
66.53%
19.63%
IPF + IPV
14.76%
65.30%
IPD + IPV
76.06%
67.48%
IPF + IPD + IPV
66.53%
70.53%
IPF+IPD+IPV reduces chip-level SER by 70.53%  3.39x chip-level MTTF increase
Zhe Feng, Naifeng Jing and Lei He, “IPF: In-Place X-Filling to Migrate Soft Errors in SRAM-Based FPGAS,” FPL 2011
Conclusions & Future Works
•
Proposed two robust resynthesis techniques, In-Place
Decomposition(IPD) for logic and In-Place LUT Polarity
Inversion(IPV) for interconnect, to improve circuit
robustness without global overhead
•
We show on average 3.39X MTTF improvement on the
MCNC benchmark circuits when combining IPD, IPV,
and IPF
•
In the future, we will develop more in-place resynthesis
techniques and investigate the interaction among different
techniques
Thank you!