FPGA: Field Programmable Gate Array Yann-Hang Lee CSE 422 page 1 The Next Step of PAL So far, have only talked about PALs (see 22V10 figure next page). What is the next step in the evolution of PLDs? More gates! How do we get more gates? We could put several PALs on one chip and put an interconnection matrix between them!! This is called a Complex PLD (CPLD). CSE 422 page 2 Example: 22V10 PLD CSE 422 page 3 Programmable interconnect matrix. Cypress CPLD Each logic block is similar to a 22V10. CSE 422 page 4 Any other approaches? Another approach to building a “better” PLD is place a lot of primitive gates on a die, and then place programmable interconnect between them: CSE 422 page 5 Field Programmable Gate Arrays The FPGA approach to arrange primitive logic elements (logic cells) arrange in rows/columns with programmable routing between them. What constitutes a primitive logic element? Lots of different choices can be made! Primitive element must be classified as a “complete logic family”. A primitive gate like a NAND gate A 2/1 mux (this happens to be a complete logic family) A Lookup table (I.e, 16x1 lookup table can implement any 4 input logic function). Often combine one of the above with a D-FF to form the primitive logic element. CSE 422 page 6 Altera Flex 10K FPGA Family CSE 422 page 7 Dedicated memory CSE 422 page 8 What is FPGA Field Programmable Gate Arrays Array of logic cells connected via routing channels Special I/O cells logic cells are mainly LUT with associated registers interconnection on SRAM basis or antifuse elements Architecting a FPGA Performance Density and capacity Ease of use In-system programmability and in-circuit reprogrammability CSE 422 page 9 Technology and Architecture Tradeoffs Antifuse elements high density non volatile not reprogrammable CSE 422 page 10 Technology and Architecture Tradeoffs SRAM cells uses more space reconfigurable volatile, requires PROM CSE 422 page 11 Other FPGA features Besides primitive logic elements and programmable routing, some FPGA families add other features Embedded memory Many hardware applications need memory for data storage. Many FPGAs include blocks of RAM for this purpose Dedicated logic for carry generation, or other arithmetic functions Phase locked loops for clock synchronization, division, multiplication. CSE 422 page 12 Programmable Logic Device Families Source: Dataquest Logic Standard Logic Programmable Logic Devices (PLDs) SPLDs (PALs) ASIC Gate Arrays Cell-Based ICs CPLDs Full Custom ICs FPGAs Acronyms SPLD = Simple Prog. Logic Device PAL = Prog. Array of Logic CPLD = Complex PLD FPGA = Field Prog. Gate Array CSE 422 Common Resources Configurable Logic Blocks (CLB) Memory Look-Up Table AND-OR planes Simple gates Input / Output Blocks (IOB) Bidirectional, latches, inverters, pullup/pulldowns Interconnect or Routing Local, internal feedback, and global page 13 CPLDs and FPGAs Complex Programmable Logic Device Field-Programmable Gate Array Architecture PAL/22V10-like More Combinational Gate array-like More Registers + RAM Density Low-to-medium 0.5-10K logic gates Medium-to-high 1K to 500K system gates Performance Predictable timing Up to 200 MHz today Application dependent Up to 135MHz today Interconnect “Crossbar” Incremental Not shown: Simple PLD (SPLD) Architecture CSE 422 page 14 XC9500 CPLDs 3 JTAG Controller JTAG Port In-System Programming Controller Functio n Block 1 I/O I/O I/O I/O Blocks I/O Global Clocks Global Set/Rese t Global TriStates Function Block 2 FastCONNEC T Switch Matrix 3 1 CSE 422 • • • • Function Block 3 Function Block 4 2 or 4 • • 5 volt in-system programmable (ISP) CPLDs 5 ns pin-to-pin 36 to 288 macrocells (6400 gates) Industry’s best pinlocking architecture 10,000 program/erase cycles Complete IEEE 1149.1 JTAG capability page 15 XC4000 Architecture CLB Slew Rate Control CLB Switch Matrix D CLB Q Passive Pull-Up, Pull-Down Vcc Output Buffer Input Buffer CLB Q Programmable Interconnect D Delay I/O Blocks (IOBs) C1 C2 C3 C4 H1 DIN S/R EC S/R Control G4 G3 G2 G1 DIN G Func. Gen. SD F' H' EC RD 1 F4 F3 F2 F1 H Func. Gen. F Func. Gen. Y G' H' S/R Control DIN SD F' D G' Q H' 1 H' K Q D G' F' EC RD X Configurable Logic Blocks (CLBs) CSE 422 page 16 Pad Exponential Growth in Density Logic Cells Logic Gates 1,000,000 12M 2 Million logic gates 100,000 1.2M 10,000 120K 1,000 1994 • • • Year 1996 1998 2000 2002 Nov. 1997- shipping world’s largest FPGA, XC40125XV (10,982 logic cells, 250K System Gates) 1 Logic cell = 4-input LUT + FF 175,000 Logic cells = 2.0 M logic gates in 2001 CSE 422 12K LUT D Q FF page 17 XC4000E/X Configurable Logic Blocks C1 C2 C3 C4 2 Four-input function generators (Look Up Tables) - 16x1 RAM or Logic function 2 Registers - Each can be configured as Flip Flop or Latch - Independent clock polarity - Synchronous and asynchronous Set/Reset H1 DIN S/R EC S/R Control G4 G3 G2 G1 DIN F' G' G Func. Gen. SD D H Func .Gen. F Func. Gen. G' H' Y S/R Control DIN F' G' SD D Q EC RD H' CSE 422 XQ H' 1 K YQ EC RD 1 F4 F3 F2 F1 Q H' X F' page 18 Look Up Tables Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB Look Up Table Combinatorial Logic Example: 4-bit address A B C D Capacity is limited by number of inputs, not complexity Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM A B C D Z WE G4 G3 G2 G1 CSE 422 0 0 0 0 0 0 G Func. Gen. 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Z 0 0 0 1 1 1 . . . 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 1 page 19 XC4000X I/O Block Diagram Shaded areas are not included in XC4000E family. CSE 422 page 20 Xilinx FPGA Routing 1) Fast Direct Interconnect - CLB to CLB 2) General Purpose Interconnect - Uses switch matrix 3) Long Lines Segmented across chip Global clocks, lowest skew 2 Tri-states per CLB for busses Other routing types in CPLDs and XC6200 CLB Switch Matrix CSE 422 CLB Switch Matrix CLB CLB page 21 Other FPGA Resources Tri-state buffers for busses (BUFT’s) Global clock & high speed buffers (BUFG’s) Wide Decoders (DECODEx) Internal Oscillator (OSC4) Global Reset to all Flip-Flops, Latches (STARTUP) CLB special resources Fast Carry logic built into CLBs Synchronous Dual Port RAM Boundary Scan CSE 422 page 22 What’s Really In that Chip? Programmable Interconnect Points, PIPs (White) Switch Matrix Routed Wires (Blue) Direct Interconnect (Green) CLB (Red) Long Lines (Purple) CSE 422 page 23 Design Flow 1 Design Entry in schematic, ABEL, VHDL, and/or Verilog. Vendors include Synopsys, Aldec (Xilinx Foundation), Mentor, Cadence, Viewlogic, and 35 others. Implementation includes Placement & and bitstream generation using 2 Routing Xilinx’s M1 Technology. Also, analyze timing, view layout, and more. M1 Technology Download directly to the Xilinx hardware device(s) with unlimited reconfigurations* !! 3 XC4000 XC4000 XC4000 *XC9500 has 10,000 write/erase cycles CSE 422 page 24 Foundation Series Delivers Value & Ease of Use Complete, ready-to-use software solution Simple, easy-to-use design environment Easy-to-learn schematic, statediagram, ABEL, VHDL, & Verilog design Synopsys FPGA Express Integration* CSE 422 page 25 Xilinx Spartan/XL Series FPGAs Similar to 4000’s, except --- Synchronous RAM only No RAM16X1, RAM32X1 (asynchronous) Only RAM16(32)X1S, RAM16X1D No Edge Decoders (wide AND of I/Os) No DECODEx BUFTs for Muxes only No WANDx or WOR2AND Serial configuration modes only No master parallel or peripheral Mode pins for configuration only Not usable as I/O No MD0, MD1, MD2 CSE 422 page 26 Spartan/XL Family Benefits Standard 5V and 3V supplies 3V Spartan-XL devices are 5V tolerant Lowest power Xilinx FPGA family Spartan-XL K factor is 11 Spartan-XL family adds power down pin 50 uA typical CSE 422 page 27 Spartan-XL Family Advanced 0.35m Process Transistor gates 0.35 All other features 0.25 Small size Low capacitance Performance Low power Allows 3.3 V supply Combines 3.3 V operation with 0.25 benefits Chip CSE 422 page 28 Spartan-XL Family Voltage Compatibility 5V 3.3V Any 5V device 5V 3.3V Spartan-XL FPGA Advanced 0.35 3.3V Core 3.3V I/O Meets TTL Levels Spartan-XL inputs accept 5V signals Spartan-XL outputs drive standard TTL 100% compatible in 5 volt environment CSE 422 page 29 Spartan/XL Top-Level Architecture • Based on XC4000 Architecture • Logic is implemented in CLBs • IOBs provide the interface between internal signals and package pins • Routing channels provide paths to interconnect the inputs and outputs of CLBs and IOBs CSE 422 page 30 Spartan CLB Two 4-input LUTs and one 3-input LUT Two edgetriggered FFs CSE 422 page 31 Spartan IOB CSE 422 page 32 Single-Port RAM Synchronous write, asynchronous read 16 x 2 or 32 x 1 max per CLB CSE 422 page 33 Dual-Port RAM One common synchronous write port Two asynchronous read ports 16 x 1 max per CLB CSE 422 page 34 New Features in Spartan-XL Family Higher speed (-4/-5) 8 flexible global low-skew buffers (BUFGLS) CLB latches Input Fast Capture Latch Output multiplexer or lookup table 3.3V supply for low power with 5V tolerance Programmable 3V input clamp for 3V PCI Programmable 24 mA output drive for 5V PCI Power-down pin Improved boundary scan Express parallel configuration mode CSE 422 page 35 Xilinx FPGA Family Summaries Virtex Family SRAM Based Largest device has 1M gates Configurable Logic Blocks (CLBs) have two 4-input LUTS, 2 DFFs Four onboard Delay Locked Loops (DLLs) for clock synchronization Dedicated RAM blocks (LUTs can also function as RAM). Fast Carry Logic XC4000 and Spartan Families Previous version of Virtex No DLLs, No dedicated RAM blocks CSE 422 page 36 Issues in FPGA Technologies Complexity of Logic Element How many inputs/outputs for the logic element? Does the basic logic element contain a FF? What type? Interconnect How fast is it? Does it offer ‘high speed’ paths that cross the chip? How many of these? Can I have on-chip tri-state busses? How routable is the design? If 95% of the logic elements are used, can I route the design? More routing means more routability, but less room for logic elements CSE 422 page 37 Issues in FPGA Technologies (cont) Macro elements Are there SRAM blocks? Is the SRAM dual ported? Is there fast adder support (i.e. fast carry chains?) Is there fast logic support (i.e. cascade chains) What other types of macro blocks are available (fast decoders? register files? ) Clock support How many global clocks can I have? Are there any on-chip Phase Logic Loops (PLLs) or Delay Locked Loops (DLLs) for clock synchronization, clock multiplication? CSE 422 page 38 Issues in FPGA Technologies (cont) What type of IO support do I have? TTL, CMOS are a given Support for mixed 5V, 3.3v IOs? 3.3 v internal, but 5V tolerant inputs? Support for new low voltage signaling standards? GTL+, GTL (Gunning Tranceiver Logic) - used on Pentium II HSTL - High Speed Transceiver Logic SSTL - Stub Series-Terminate Logic USB - IO used for Universal Serial Bus (differential signaling) AGP - IO used for Advanced Graphics Port Maximum number of IO? Package types? Ball Grid Array (BGA) for high density IO CSE 422 page 39