Parallel Data Acquisition Systems
for a Compton Camera
By:
Kıvanç Nurdan, T. Çonka-Nurdan CAESAR / Uni-Siegen
H.J. Besch, B. Freisleben, N.A. Pavel, A.H. Walenta
Uni-Siegen
INTRODUCTION
• Physical Facts
- System Considerations
- Coincidence timing
- Proposed System Parameters
• Proposed DAQ System
- Architecture
- Implementation
 Channel Processor Subsystem
 Backplane
 Event Builder Subsystem
• Current Status
• Extendibility of the System
• Discussion
Compton Camera Principle
Monolithic array of 19 hexagonal SDD’s of 5mm² of each
arranged in a honeycomb configuration designed and
produced by MPI Semiconductor Laboratory.
Integrated on-chip JFET => low noise, excellent energy
resolution
Reference: C. Fiorini et al., IEEE NSS 2001 and to be
published at Nucl. and Medical Imaging Science, June 2002
Anger Camera:
• NaI(Tl) crystal of
10” diameter and of
3/8” thickness
• Read out via
37 x 3” hexagonal PMTs
• Integrated analog readout
electronics
System Considerations
•
Time coincidence
-
•
Any valid Compton event should be detected in
both detectors, within 1 ns time difference.
It can be assumed that they appear at the same
time quanta
Expected Timing Properties
-
Trigger signal occurs 10-15 ns after an event in
Gamma Camera
Trigger signal occurs after 0-150 ns in Silicon
Drift Detector
PROPOSED SYSTEM PARAMETERS
66 Ms/sec 12bit resolution per channel
19 channels from SDD
4 channels from Gamma Detector.
19 triggers from SDD , 1 Trigger from Gamma
Detector. ( self triggering)
12 bit data and 5 bit address bus for interfacing
channels to coincidence unit
Architecture:
Event Reconstruction Mechanism
1. Each channel tracks its input continuously and
creates trigger with digitally programmable
threshold for any reasonable ripple in the signal,
finds the peak and integral of the signal in the
given time window.
2. Coincidence logic waits for a trigger from Gamma
detector then for a trigger from SDD for at most
total drift time of the SDD.
3. If and only if one SDD channel creates trigger
within this time, this is taken as a true coincidence
CHANNEL PROCESSOR
SUBSYSTEM
•
Conceptional design
-
Internal digital delay
Internal trigger generation and external trigger
Pre trigger delay
Peak detection
Integration
Time stamping
Raw data for direct inspection
event output buffer
System bus interface
256 sample Prog. D. Delay
Analog
Stage
ADC
Event Size
Controller
Trigger
Unit
32 sample Prog.
Pre_trg delay
Peak
Master
Controller
Integral
Time
256 sample output buffer
Buffer1
Ch 1 Master Cnt.
Backplane
Semaphore 1
Buffer N
Ch N Master Cnt.
Semaphore N
Bus interface
Implemented PCB
Selected Hardware:
• 65 Msamples/s 12bit ADCs from Analog Devices.
AD9235
• Xilinx FPGAs : SpartanIIE
• Differential line receivers from Analog Devices.
AD8138
• Voltage regulators from National Instruments
• Configuration eeprom: ATMEL 17002
Channel 1
Line receiver
ADC 1
FPGA
Conf.
Memory
Results:
RAW
DATA
PEAK
INTEGRAL
TIME STAMP
Event 1
1722
1720
1719
1719
1719
3431
2346
1735
1724
1698
1698
1714
1725
1720
1699
1690
3431
7
1107
1831
516
3431
29779
29779
540
8.181
Event 2
1721
1718
1717
1717
1716
2911
3442
1748
1729
1708
1694
1708
1721
1724
1710
1693
3442
7
1705
1831
1056
30377
30377
541
8.19615
Event 3
1735
1731
1730
1739
1743
3445
2916
1748
1744
1712
1715
1731
1741
1737
1720
1708
3445
7
1923
1831
1597
30595
30595
540
8.181
Event 4
1679
1707
1740
1720
1713
2667
3442
1743
1732
1715
1698
1704
1713
1717
1709
1695
3442
7
1286
1831
2137
2MHz Sine Wave
4500
4000
3500
3000
2500
2000
1500
1000
500
497
466
435
404
373
342
311
280
249
218
187
156
125
94
63
32
1
0
BUS (backplane)
• Clock Distribution
- Central-synchronous system clock
• Supports
- 44 ( +2) parallel I/O
- 3 Serial I/O
- 2 Clock lines ( may configured for
differential clocking)
To simulate INPUT for xilinx i/o pin
input
: tied to Vcc
Enable
: tied to GND or Vee
output
: connected as signal input
To simulate
input
Enable
output
OUTPUT for xilinx i/o pin
: tied to pulse generator
: tied to Vcc
: connected as signal output
Vt
Vt
Rt2
LOSSY
2
CC1
LOSSY
T x1
X1
OUT PUT
E nabl e
V cc
E nabl e
V cc
90 8.0mV
V ee
90 8.4mV
E nabl e
V cc
90 7.3mV
90 7.5mV
OUT PUT
3.30 0V
E nabl e
V cc
90 6.5mV
90 6.7mV
E nabl e
V cc
90 5.7mV
V ee
IOp in
0V
T x6
E nabl e
V cc
90 4.0mV
INP UT
RX6
OUT PUT
RX7
ou t7
23
V cc
3.30 0V
90 6.0mV
E nabl e
V cc
90 5.0mV
V ee
90 6.0mV
90 5.0mV
V ee
IOp in
0V
T x7
90 5.0mV
23
V cc
60 0.0mV
IOp in
0V
90 5.0mV
CC7
0.02
CR7
90 5.0mV
ou t6
V cc
V ee
IOp in
0V
2p F
X7
INP UT
OUT PUT
25
LOSSY
90 5.0mV
RX5
23
V cc
V ee
IOp in
0V
OUT PUT
2
0.02
CR6
90 5.0mV
T x5
ou t5
LOSSY
50
T t2
Connector Model
CL7
6n H
CC6
X6
INP UT
RX4
ou t4
23
V cc
V ee
IOp in
V 1 = .6
V2 = 3V
T D = 5ns
T R = .0 1ns
T F = .01 ns
P W = 1 0ns
P ER = 2 0ns
OUT PUT
2
90 4.7mV
X5
INP UT
RX3
1
T 6_7
CL6
6n H
90 5.0mV
2p F
LOSSY
0.02
90 5.0mV
CR5 Connector Model
T x4
90 5.7mV
ou t3
27
V cc
2
CL5
6n H
90 5.0mV
2p F
CC5
X4
INP UT
LOSSY
0.02
CR4
90 5.7mV
T x3
1
Connector Model
T 5_6
CC4
X3
RX2
23
V cc
2
90 6.5mV
ou t2
1
T 4_5
CL4
6n H
90 5.7mV
2p F
LOSSY
0.02
90 6.5mV
CR3
T x2
X2
INP UT
1
Connector Model
T 3_4
CL3
6n H
90 6.5mV
2p F
CC3
90 7.3mV
RX1
ou t1
OUT PUT
2
0.02
90 7.3mV
CR2 Connector Model
90 8.0mV
INP UT
LOSSY
CC2
0.02
90 8.0mV
CR1
LOSSY
CL2
6n H
90 7.3mV
2p F
LOSSY
2
90 9.2mV
1
Connector Model
T 2_3
20
LOSSY
LOSSY
1
T 1_2
CL1
6n H
90 8.0mV
2p F
LOSSY
30
LOSSY
1
Connector Model
T t1
LOSSY
Rt1
50
1.50 0V
IOp in
0V
0V
V3
60 0.0mV
90 5.0mV
1
Connector Model
T 7_8
1
Connector Model
T 8_9
CL8
6n H
LOSSY
2
CL9
6n H
LOSSY
2p F
2
CC8
CC9
0.02
CR8
90 5.0mV
90 5.0mV
0.02
CR9
90 5.0mV
T x8
LOSSY
LOSSY
2p F
90 5.0mV
T x9
90 5.0mV
X8
X9
INP UT
OUT PUT
INP UT
RX8
ou t8
OUT PUT
RX9
ou t9
23
V cc
E nabl e
V cc
V cc
23
V cc
E nabl e
V cc
90 5.0mV
V ee
Vt
V cc
3.3V
90 6.0mV
3.30 0V
90 6.0mV
V ee
Vt
1.5V
IOp in
IOp in
0V
0V
T itl e
bu s data tran smis si on
S ize
A3
0V
Date:
Docume nt Numbe r
1.0
Fri day, A pri l 26, 200 2
Rev
1.9
S heet
1
of
1
Event Builder
• Conceptional Design
- An event consists of;
 X
 Y
Gamma Detector
 E1
 E2
Silicon Detector
 SDD pixel
- Each element has a time stamp, an integral and a peak
value.
- ~8M detector events per second bus data transfer
throughput.
- .7M Compton events ( depending on integration time)
may be reconstructed.
- 10K compton events are expected for the prototype
system
Coincidence Algorithm
1.
2.
a)
b)
3.
a)
b)
4.
Wait for a trigger from Gamma Detector
Trigger received from Gamma Detector,
If one and only one channel from Silicon detector triggers
within a max drift time, this coincidence is considered as an
event candidate. GOTO 3
Else GOTO 1.
If within total integration and accumulation time;
no other triggers received, accept this coincidence as an event,
and push its data to output buffers
Else purge data
GOTO 1
DATA
BUS
BUS
MASTER
SRAM
ABS_REG
Slave
controllers
Time
Stamps
SCAT_REGS
SRAM
Controller
Coincidence
Logic
Programmable
System
Controller
PC
Interface
Parallel port
interface
FPGA
18x1 Mbit
133MHz
SSRAM
PC interface
• Simple parallel port interface (implemented)
8 Mbits/sec
• Ethernet interface ?
100 Mbits/sec
• IEEE 1394 interface ?
400 Mbits/sec
• USB 2.0 interface ?
480 Mbits/sec
Support DAQ Software
Current Status
A concept has been developed for the whole Data Acquisition System
of the Compton Camera.
Analog Interface and digital electronics developed and tested for the
Channel Processor module.
Electrical characteristics for bus architecture has been finalized and
Backplane Module has been fabricated .
Event builder module has been electrically characterized. Bus
implementation in VHDL code is ongoing.
Initial PC interface over parallel port for a single Channel Processor
module has been built and DAQ software has been written to transfer
data to PC.
A Possible Parallel DAQ System
for a Future Compton Camera
COMPTON CAMERA TRIGGERING DAQ SYSTEM
Scatter detector module
Trigger Flow
Absorption Detector Module
Fast
Fast
L0 Trigger
L0 Trigger
Detector
Detector
L0 Buffer
Slow
L0 Depth
Manager
Fast
Readout
Unit
Time Coincidence
L1 Buffer
L0 Trigger
Manager
L1 Buffer
L1 Trigger
Buffer
Manager
Buffer
Manager
Data Bus
Command Bus
Data Bus
Event Builder
Derandomized Event Buffer
Command Bus
L0 Buffer
Further Discussion
• Deadtime of such a system ?
• How fast we can go ?
• Extensible ? How far ?
• Support Software ? Balance between
programmable firmware and computer software ?
References & Acknowledgements
Dipl. Ing. M. Adamek (SiemensVDO A.G) (general design)
Dipl. Ing. Alan Rudge (CERN) (low noise electronics)
High-Speed Digital Design, H. W. Johnson, M. Graham, 1993
An Innovative Distributed Termination Scheme for GTL Backplane Bus
Designs, High-Performance System Design Conference 1998
Application Report SCEA022 Texas Instruments- April 2001
Application Report SLLA067 Texas Instruments- March 2000
EIA/JESD8-8, Stub Series Terminated Logic for 3.3 V (SSTL_3)
EIA/JESD8-9, Stub Series Terminated Logic for 2.5 V (SSTL_2)