Regular Expression Manipulation
FSM Model
Sequential Machine Theory
Prof. K. J. Hintz
Department of Electrical and Computer
Engineering
Lecture 6
Modifications by Marek
Perkowski
Null Machine
3 Methods for Proving That a Machine
Accepts No Words
– By inspection
• Any path from the start state to a final state means
that at least one word is accepted by the machine
– By state diagram manipulation
• If a final state is relabeled as a start state, then the
machine must accept at least one word
Null Machine
– By converting the regular expression into a
deterministic FA
• If possible, FA must accept at least one word
• Conversion to FA may not be possible
– Machine may have no final states.
– There is no path from the initial state to any final state.
State Diagram Manipulation
A procedure to determine if a machine accepts no
strings
1. Remove all edges (arrows) to the start state.
2. From the start state, identify all single-step “next
states.”
3. Relabel these “next states” as start states and
eliminate the edges used to get there.
4. go to (b)
5. If a final state is relabeled as a start state, then the
machine must accept at least one word.
State Diagram Manipulation
State Diagram Manipulation
State Diagram Manipulation
Does Not Accept Any
Word Since
There Is No
Path From
- To +.
The Complement Machine
• A Complement Machine Accepts All
Expressions Other Than Those Accepted by
the Original Machine
• Method
– Change all non-final states into final states
– Change all final states into non-final states
– Leave start state unchanged
Language Decidability
Methods for Determining If Two Regular
Expressions Define the Same Language
– Language Enumeration with 1:1
correspondence between the 2 languages.
– The regular languages can be accepted by
identical FAs.
– Generate
?
L overlap   L 1  L 2    L 2  L 1   
Language Overlap
• If the Overlap Language Is NOT the Null
Set, Then There Is Some Word in L1 Which
Is Not Accepted by L2 and Vice Versa.
• If the Overlap Language Accepts the Null
String, Then the Languages Are Not Equal.
L1
L1
L2
L2
DeMorgan’s Theorem
Applies Equally Well to Sets As Well As
Boolean Algebra
A  B  A B
and
A B  A  B
Regular Expression Equivalence
Methodology
– Construct the complement machines
– Apply DeMorgan’s theorem since it is difficult
to form the intersect machine
L overlap   L 1  L 2    L 2  L 1
  L 1  L 2    L 2  L 1

Regular Expression Equivalence
Take the Unions of the Complemented and
Non-complemented Several Times to
Determine Whether Loverlap Is the Null Set
or Not
RE Equivalence Example*
Two REs are represented by their equivalent
FAs (FA1 does = FA2)
*Cohen, Prob. 2, page 233.
RE Equivalence Example
Form the Complement Machines
RE Equivalence Example
Make the Product Machine of FA2 and the
Complement of FA1.
RE Equivalence Example
• States of Product Machine, FA1-bar & FA2
• Only One Start State / Multiple Final States
Start/Final New State
State
-/+
Vector
-/+
1
( p1, y1 )
+
2
( p1, y2 )
+
3
( p1, y3 )
RE Equivalence Example
Start/Final New State
-/+
4
+
State
Vector
( p2, y1 )
5
( p2, y2 )
6
( p2, y3 )
Product Machine State Table
Start/Final
-/+
-/+
+
+
+
Present State
a
b
1
2
3
4
5
6
5
5
5
5
5
5
3
3
3
3
3
3
State Diagram of Product
FA1-Bar, FA2
Reduced State Diagram
Non-Reachable
States Removed
RE Equivalence Example
•
Take the Complement Of the
Union by changing final states
to non-final and vice-versa
L L 
1
•
2
No Final States, So
Complement FA Accepts No
Words
RE Equivalence Example
Do the Same for the Right Term of Loverlap
RE Equivalence Example
• Application of Same Procedure to
Preceding Machine Also Results in No
Recognizable Words.
• Since Both Terms of Loverlap are Null, Then
REs Are Equivalent Since Their Union Is
Null.
Moore & Mealy Machines
• The Behavior of Sequential Machines
Depends on Previous Inputs.
– Moore Machine
• Output only depends on present state
– Mealy Machine
• Output depends on both the present state and the
present input
Moore & Mealy Machines
Equivalent Descriptive Methods
–
–
–
–
Transition (state) table
Transition (state) diagram
Operational descriptions using set theory
(Language recognized by the machine)
Moore Machine
Input
Comb
Ckt
Present
State
Comb
Ckt
Output
Memory
Output Is Only a Function
of Present State
Primitive State Diagram, Moore
input
on
state/
output
off
A/0
B/1
off
Legend
C/0
D/0
etc.
Moore Machine State Diagram
x1x0
10
s1s0/z
00
00/1
01/0
01
Legend
10/1
11/1
etc.
Mealy Machine
Input
Comb
Ckt
Present
State
Comb
Ckt
Output
Memory
Output Is Function of
Present State AND Present
Input
Primitive State Diagram, Mealy
input/output
on/0
state
off/1
A
B
off /0
Legend
C
D
etc.
Mealy Machine State Diagram
x1x0 /z
10 /0
s1 s0
00 /1
00
01
01 /1
Legend
10
11
etc.
Transition Table
Present
Input
Next
Output
State
Variables
State
Variables
Variables
Variables
si
xj
sk
zm
FSM Design Approaches
• “One-Hot”
– One flip-flop is used to represent each state
– Costly in terms of discrete hardware, but trivial to
design
– Efficient in FPGAs because FF part of each CLB
• Binary Coded State
– n flip-flops used to store 2n states
– Most efficient
– Need to account for unused states
FSM and Clocks
• Synchronous FSMs may change state only
when a unique input, the clock, occurs
• Asynchronous FSMs may change state
when input changes
• Next state depends on present input and
present state for both Moore and Mealy
Synchronous versus Asynchronous
Machines in Design
• Synchronous FSMs
– Easier to design, turn the crank
– Slower operation
• Asynchronous
– Harder to design because of potential for races,
iterative solutions
– Faster operation
Mealy “0101” Detector
S:
I:
O:
d:
b:
M = ( S, I, O, d, b )
{ A, B, C, D }
{ ‘0’, ‘1’ }
{ 0, 1 } = { not detected, detected}
next slide
next slide
Mealy Transition/Output Table
Next State/Output
Present
State
A
B
C
D
Present Input
‘0’
‘1’
B/0
A/0
B/0
C/0
D/0
A/0
B/0
C/1
“0101“ State Diagram
‘1’/0
‘0’/0
A
B
‘0’/0
‘1’/0
‘1’/0
C
‘0’/0
‘1’/1
‘0’/0
D
Moore “0101” Detector
S:
I:
O:
d:
l:
M = ( S, I, O, d, l )
{ A, B, C, D, E }
{ ‘0’, ‘1’ }
{ 0, 1 } = { not detected, detected}
next slide
next slide
Moore Transition/Output Table
Present
State
A
B
C
D
E
Present Input
‘0’
‘1’
B
A
B
C
D
A
B
E
D
A
Output(l)
Next State
0
0
0
0
1
Moore “0101“ State Diagram
‘0’
‘1’
‘0’
A/0
B/0 ‘0’ detected
‘0’
‘1’
‘1’
‘0’
D/0
C/0
“01” det
‘1’
‘0’
E/1
‘1’
“010” det
“0101” det
Asynchronous FSM
Fundamental Mode Assumption
– Only one input can change at a time
• Analysis too complicated if multiple inputs are
allowed to change simultaneously
– Circuit must be allowed to settle to its final
value before an input is allowed to change
• Behavior is unpredictable (nondeterministic) if
circuit not allowed to settle
Asynch. Design Difficulties
Delay in Feedback Path
– Not reproducible from implementation to
implementation
– Variable
• may be temperature or electrical parameter
dependent within the same device
– Analog
• not known exactly
Stable State
• PS = present state
• NS = next state
• PS = NS = Stability
– Machine may pass through none or more intermediate
states on the way to a stable state
– Desired behavior since only time delay separates PS
from NS
• Oscillation
– Machine never stabilizes in a single state
Races
• A Race Occurs in a Transition From One
State to the Next When More Than One
Next State Variables Changes in Response
to a Change in an Input
• Slight Environment Differences Can Cause
Different State Transitions to Occur
– Supply voltage
– Temperature, etc.
Races
01
if Y1
changes
first
11
10
desired NS
PS
00 if Y2
changes
first
Types of Races
• Non-Critical
– Machine stabilizes in desired state, but may
transition through other states on the way
• Critical
– Machine does not stabilize in the desired state
Races
01
if Y1
changes
first
PS
if Y2
changes
00 first
11
10
desired NS
non- critical race
00
critical race
Asynchronous FSM Benefits
• Fastest FSM
• Economical
– No need for clock generator
• Output Changes When Signals Change, Not When
Clock Occurs
• Data Can Be Passed Between Two Circuits Which
Are Not Synchronized
• In some technologies, like quantum, clock is just
not possible to exist
Asynchronous FSM Example
input
next
present
state
y1
y2
state
Next State Variables
   x y y  x  y
Y1  x, y1 , y2   x y1
1
2
 x y1  x y1 y2  x y2
Y2  x, y1 , y2   y2 x y
 y2  x y1
2
Sequential Machines Problems
Three Problems of Sequential Machines
– State minimization problem
• Determine all equivalent states of a sequential
machine, and,
• Eliminate redundant states
– Machine Decomposition
• Separate large machines into an interconnected set
of smaller machines
• Easier to design and analyze small machines
Sequential Machine Problems
– State assignment problem
• There is no guidance on which binary number to
assign to which state in a primitive state table
• Complexity of implementation is dependent on
mapping of states to binary numbers
• Unsolved problem
– Design all machines and compare
– Benefit of decomposition of large machine into smaller
machines.
Set Theoretic Description
Moore Machine is an ordered quintuple
M oore=  S, I, O, d, l

where
S Finite set of states  ,  s1 , s 2 , , s n
I
O

Finite set of inputs  ,  i1 , i 2 , , i m 
Finite set of outputs  ,  o1 , o 2 , , o l 
d Next state function which maps
l Output function which maps
SI  S
SO
Set Theoretic Description
Mealy Machine is an ordered quintuple
Mealy =  S, I, O, d , b 
where
S  Finite set of states  ,  s1 , s2 ,, s n 
I  Finite set of inputs  ,  i1 , i 2 ,, i m 
O  Finite set of outputs  ,  o1 , o2 ,, ol 
d  Next state function which maps S  I  S
b  Output function which maps
SIO
Recursive Definitions of Delta
State Transition for Moore & Mealy
–
–
–
–
Single-valued, else not deterministic.
At least a partial function
Not necessarily injective or surjective
Shield’s nomenclature
d: S  I  S
d:
   sk 1, ik , sk ,    S  I   S
Recursive Definitions of Delta
d * is none or more occurrances of the definition
of a particular mapping from S  I  S
Let
s S
a I
x  I * i. e., a string
then define
d *  s, e   s, i. e., the response to a null string
is no state change
Recursive Definitions of Beta
• Causal, No Output for No Input.
• For a Given Input Sequence, There Will Be
a Deterministic Output Sequence of the
Same Length As the Input.
b :SI  O
b :    sk 1 , ik , ok ,   S  I  O
Recursive Definitions of Lambda
Same Caveats As Beta
l: S  O
l :  sk 1, ok ,    S  O
l *  sk ,    
l *  sk , a . x   l  d  sk 1, a   . l *  d  sk 2 , x , x 
sk
sk-1