1 - Electrical and Computer Engineering

CprE 281:

Digital Logic

Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/

Simple Processor

CprE 281: Digital Logic

Iowa State University, Ames, IA

Copyright © Alexander Stoytchev

Administrative Stuff

• Final Project (7% of your grade)

• Posted on the class web page (Labs section)

• This is due this week (during your lab)

Administrative Stuff

• The FINAL exam is scheduled for

• Thursday May 8 @ 2:15-4:15 PM

• It will be in this room.

Final Exam Format

• The exam will cover: Chapter 1 to Chapter 6, and

Sections 7.1-7.2

• Emphasis will be on Chapter 6 and Chapter 5

• The exam will be open book and open notes (you can bring up to 5 pages of handwritten notes) plus your textbook.

Final Exam Format

• The exam will be out of 130 points

• You need 95 points to get an A

• It will be great if you can score more than 100 points.

▪ but you can ’t roll over your extra points 

Topics for the Final Exam

• K-maps for 2, 3, and 4 variables

• Multiplexers (circuits and function)

• Synthesis of logic functions using multiplexers

• Shannon ’s Expansion Theorem

• 1 ’s complement and 2’s complement representation

• Addition and subtraction of binary numbers

• Circuits for adding and subtracting

• Serial adder

• Latches (circuits, behavior, timing diagrams)

• Flip-Flops (circuits, behavior, timing diagrams)

• Counters

• Registers

Topics for the Final Exam

• Synchronous Sequential Circuits

• FSMs

• Moore Machine

• Mealy Machines

• State diagrams, state tables, state-assigned tables

• State minimization

• Designing a counter

• Arbiter Circuits

• Reverse engineering a circuit

• ASM Charts

• Register Machines

• Bus structure and Simple Processors

• Something from Star Wars

How to Study for the Final Exam

• Form a study group

• Go over the slides for this class

• Go over the problems at the end of Ch 5 & 6

• Exercise

• Get some sleep

Digital System

• Datapath circuit

▪ To store data

▪ To manipulate data

▪ To transfer data from one part of the system to another

▪ Comprise building blocks such as registers, shift registers, counters, multipliers, decoders, encoders, adders, etc.

• Control circuit

▪ Controls the operation of the datapath circuit

▪ Designed as a FSM

A Simple Processor

[ Figure 7.9 from the textbook ]

What are the components?


Register R0


All Registers


IN

1

0

1

2-Bit Register

OUT

1

IN

0

0

1

OUT

0

4-Bit parallel-access shift register

(this one is not used in this example)


Tri-State Driver


All Tri-State Drivers


Tri-state driver

(see Appendix B for more details)


Bus Structure

• A way to transfer data from any register (device) to any other register (device)

• A set of n wires to transfer an n-bit data n Bus

• What if two registers write to the bus at the same time?

Tri-State Driver

• Also called tri-state buffer Z: High impedance state

Figure 7.1. Tri-state driver.

device3 device2 device1

• Then several devices can be connected to a single wire

• Note that at any time, at most e3 one of e0, e1, e2, and e3 can e2 e1 be set to 1 device0 e0

An n-bit Tri-State Driver

• An n-bit tri-state buffer can be constructed using n

1-bit tri-state buffers.

Input e

Output e e e e

A digital system with k registers


How to connect registers to a bus

(using tri-state drivers)

This shows only two 2-bit registers, but this design scales to more and larger registers.


An alternative approach uses multiplexers to implement a bus


An alternative approach uses multiplexers to implement a bus

(eight 5-to-1 multiplexers)

This requires one multiplexer per bit.

Assuming 8-bit registers, we need eight 5-to-1 multiplexers.


Adder/Subtractor


c n x n – 1

Adder/subtractor unit y n – 1 y

1 y

0

Add



Sub control x

1 x

0 c

0 n -bit adder s

– 1 s

1 s

0


The first two stages of a carry-lookahead adder x

1 y

1 x

0 y

0 x

0 y

0 g

1 p

1 g

0 p

0 c

0 c

2 c

1


A hierarchical carry-lookahead adder x y x y x y

Block

3

G

3

P

3 s c

24

Block

1

G

1

P

1 s

Block

0

G

0

P

0 s c

0 c

32

Second-level lookahead c

16 c

8


Control Circuit


Designing The Control Circuit

The function register and decoders

I

0

I

1

I

2

I

3

X

0

X

1

X

2

X

3

Y

0

Y

1

Y

2

Y

3 y

0 y

1 y

2 y

3

2-to-4 decoder w

1 w

0

En y

0 y

1 y

2 y

3

2-to-4 decoder w

1 w

0

En y

0 y

1 y

2 y

3

2-to-4 decoder w

1 w

0

En

1 1 1

Clock

FR in

Function Register f

1 f

0

Rx

1

Rx

0

Ry

1

Ry

0

Function


Operations performed by this processor

Operation Function Performed

Load Rx, Data Rx  Data

Move

Add

Sub

Rx, Ry

Rx, Ry

Rx, Ry

Rx  [Ry]

Rx  [Rx] + [Ry]

Rx  [Rx] - [Ry]

[ Table 7.1 from the textbook ]

Operations performed by this processor

Operation Function Performed

Load Rx, Data Rx  Data

Move

Add

Sub

Rx, Ry

Rx, Ry

Rx, Ry

Rx  [Ry]

Rx  [Rx] + [Ry]

Rx  [Rx] - [Ry]

Where Rx and Ry can be one of four possible options: R0, R1, R2, and R3


Operations performed by this processor f

1 f

0

Function

0 0 Load

0 1 Move

1 0 Add

1 1 Sub

Rx

1

0

0

1

1

Rx

0

Register

0 R0

1 R1

0 R2

1 R3

Ry

1

0

0

1

1

Ry

0

Register

0 R0

1 R1

0 R2

1 R3


1 f

0

Function

0 0 Load

0 1 Move

1 0 Add

1 1 Sub

0 1 1 1 0 0  Move R3, R0

Rx

1

0

0

1

1

Rx

0

Register

0 R0

1 R1

0 R2

1 R3

Ry

1

0

0

1

1

Ry

0

Register

0 R0

1 R1

0 R2

1 R3


1 f

0

Function

0 0 Load

0 1 Move

1 0 Add

1 1 Sub

1 0 0 1 1 1  Add R1, R3

Rx

1

0

0

1

1

Rx

0

Register

0 R0

1 R1

0 R2

1 R3

Ry

1

0

0

1

1

Ry

0

Register

0 R0

1 R1

0 R2

1 R3


1 f

0

Function

0 0 Load

0 1 Move

1 0 Add

1 1 Sub

1 1 0 0 1 0  Sub R0, R2

Rx

1

0

0

1

1

Rx

0

Register

0 R0

1 R1

0 R2

1 R3

Ry

1

0

0

1

1

Ry

0

Register

0 R0

1 R1

0 R2

1 R3


1 f

0

Function

0 0 Load

0 1 Move

1 0 Add

1 1 Sub

0 0 1 0 x x  Load R2, Data

Rx

1

0

0

1

1

Rx

0

Register

0 R0

1 R1

0 R2

1 R3

Ry

1

0

0

1

1

Ry

0

Register

0 R0

1 R1

0 R2

1 R3

Similar Encoding is Used by Modern Chips

[http://en.wikipedia.org/wiki/Instruction_set]

Sample Assembly Language Program

For This Processor

Move R3, R0

Add R1, R3

Sub R0, R2

Load R2, Data

Machine Language vs Assembly Language

Machine Language

011100

100111

110010

001000

Assembly Language

Move R3, R0

Add R1, R3

Sub R0, R2

Load R2, Data

Meaning / Interpretation

R3  [R0]

R1  [R1] + [R3]

R0  [R0] – [R2]

R2  Data



01 11 00

10 01 11

11 00 10

00 10 00


Move R3 , R0

Add R1 , R3

Sub R0 , R2

Load R2 , Data


R3  [R0]

R1  [R1] + [R3]

R0  [R0] – [R2]

R2  Data



011100

100111

110010

001000


Move R3, R0

Add R1, R3

Sub R0, R2

Load R2, Data


R3  [R0]

R1  [R1] + [R3]

R0  [R0] – [R2]

R2  Data

For short, each line can be expresses as a hexadecimal number



1C

27

32

08


Move R3, R0

Add R1, R3

Sub R0, R2

Load R2, Data


R3  [R0]

R1  [R1] + [R3]

R0  [R0] – [R2]

R2  Data

Intel 8086

[http://en.wikipedia.org/wiki/Intel_8086]

Intel 8086

Memory Address


Intel 8086

Machine

Language


Intel 8086

Assembly

Language


Intel 8086

Comments


Control signals asserted in each time step

(Load): I

0

(Move): I

(Add): I

(Sub): I

1

2

3

T

1

Extern

R in

= X

Done

R in

R out

= X

= Y

Done

R out

A in

= X

R out

A in

= X

T

2

R out

G in

= Y

AddSub = 0

R out

G in

= Y

AddSub = 1

T

3

G out

R in

= X

Done

G out

R in

= X

Done



(Load): I

0

(Move): I

(Add): I

(Sub): I

1

2

3

T

1

Extern

R in

= X

Done

R in

R out

= X

= Y

Done

R out

A in

= X

R out

A in

= X

T

2

R out

G in

= Y

AddSub = 0

R out

G in

= Y

AddSub = 1

T

3

1 clock cycle

1 clock cycle

G out

R in

= X

Done

G out

R in

= X

Done

3 clock cycles

3 clock cycles


A part of the control circuit for the processor

Clock

Clear

T

0

T

1

T

2

T

3 y

0 y

1 y

2 y

3

2-to-4 decoder w

1 w

0

En

1

Q

1

Q

0

Up-counter

Reset


What are the components?

Clock

Clear

T

0

T

1

T

2

T

3 y

0 y

1 y

2 y

3

2-to-4 decoder w

1 w

0

En

1

Q

1

Q

0

Up-counter

Reset


Clock

Clear

2-Bit Up-Counter

T

0

T

1

T

2

T

3 y

0 y

1 y

2 y

3

2-to-4 decoder w

1 w

0

En

1

Q

1

Q

0

Up-counter

Reset


2-bit Synchronous Up-Counter

1

Clock

T Q

Q

Clear_n

T Q

Q

2-bit Synchronous Up-Counter with Enable

Enable

Clock

T Q

Q

Clear_n

T Q

Q

2-to-4 Decoder with Enable Input

Clock

Clear

T

0

T

1

T

2

T

3 y

0 y

1 y

2 y

3

2-to-4 decoder w

1 w

0

En

1

Q

1

Q

0

Up-counter

Reset


2-to-4 Decoder with an Enable Input

En

[ Figure 4.13c from the textbook ]

2-to-4 Decoder with an Enable Input

1

(always enabled in this example)

[ Figure 4.13c from the textbook ]

In Chapter 6 we looked at the following

Register Swap Example

Register Swap Controller


Register Swap Controller

Design a Moore machine control circuit for swapping the contents of registers R1 and R2 by using R3 as a temporary.


State Diagram w = 0

A: No Transfer w = 0 w = 1 w = 1

B : R 2 out

= 1 , R 3 in

= 1 w = 0 w = 1

C : R 1 out

= 1 , R 2 in

= 1 w = 0 w = 1

D : R 3 out

= 1 , R 1 in

= 1 , Done = 1

Reset

If an output is not given, then assume that it is 0.


Animated Register Swap


0xFF

0x42

0xC9

These are the original values of the 8-bit registers

1


0xFF

0x42

0xC9

For clarity, only inputs that are equal to 1 will be shown.

1


1

0xFF

0x42

1 0xC9

1


1

0xFF

0x42

0x42

1 0xC9

1


1

0xFF

0x42

1 0x42

1


1

0xFF

1 0x42

0x42

1


1

0xFF

1 0x42

0x42

0xFF

1


1

0xFF

1 0xFF

0x42

1


1

0xFF

1

0xFF

0x42

1


1

0xFF

1

0xFF

0x42

0x42

1


1

0x42

1

0xFF

0x42

1


0x42

0xFF

0x42

State Diagram w = 0

A: No Transfer w = 0 w = 1 w = 1

B : R 2 out

= 1 , R 3 in

= 1 w = 0 w = 1

C : R 1 out

= 1 , R 2 in

= 1 w = 0 w = 1

D : R 3 out

= 1 , R 1 in

= 1 , Done = 1

Reset

If an output is not given, then assume that it is 0.


Encoding #1:

A=00, B=01, C=10, D=11

(Uses Two Flip-Flops)

y

1 y

2 y

1 y

2 y

1 y

2

Present state y

2 y

1

A 00

B 01

C 10

D 11

Next state w = 0 w = 1

Y

2

Y

1

00

10

11

00

Y

2

Y

1

0 1

1 0

1 1

0 0

R1 out

0

0

1

0

R1 in

0

0

0

1

Outputs

R2 out

0

1

0

0

R2 in

0

0

1

0

R3 out

0

0

0

1

R3 in

0

1

0

0

Done

0

0

0

1

Encoding #3:

A=0001, B=0010, C=0100, D=1000

(One-Hot Encoding – Uses Four Flip-Flops)

Let's Complete the Circuit Diagram

R1 out

= R2 in

= y

3

R1 in

= R3 out

= Done = y

4

R2 out

= R3 in

= y

2

D Q

Q y

4

Y

3

D Q y

3

Q

D Q y

2

Q

Y

1

= w y

1

+ y

4

Y

2

= w y

1

Y

3

= y

2

Y

4

= y

3 w

Clock

D Q y

1

Q

Implementing the States with a Counter


(Load): I

0

(Move): I

(Add): I

(Sub): I

1

2

3

T

1

Extern

R in

= X

Done

R in

R out

= X

= Y

Done

R out

A in

= X

R out

A in

= X

T

2

R out

G in

= Y

AddSub = 0

R out

G in

= Y

AddSub = 1

T

3

G out

R in

= X

Done

G out

R in

= X

Done


Derivation of the Control Inputs

• See pages 434- and 435 in the textbook

Arithmetic Logic Unit (ALU)

Arithmetic Logic Unit (ALU)

• Arithmetic Logic Unit (ALU) computes arithmetic or logic functions

• Example: A four-function ALU has two selection bits S1 S0

(also called OpCode) to specify the function

– 00 (ADD), 01 (SUB), 10 (AND), 11 (OR)

• Then the following set up will work

S1 S0 Function

0 0 ADD

0 1

1 0

1 1

SUB

AND

OR

A

B

ADD 00

A

A

B

A

B

A

B

SUB

AND

OR

01

MUX

10

11

S1 S0

Result

B

A

L

U

Result

S1 S0

(OpCode)

Symbol

An Alternative Design of Four-Function ALU

A

B

A

B

A

B

• The previous design is not very efficient as it uses an adder and a subtractor circuit

• We can design an add/subtract unit as discussed earlier

• Then we can design a logical unit (AND and OR) separately

• Then select appropriate output as result

• What are the control signals, Add/Sub, Select0, and Select1?

Add/Sub

ADD/SUB

AND

OR

0

MUX

1

0

MUX

1

Result

S1 S0 Function

0 0 ADD

0 1

1 0

1 1

SUB

AND

OR

Select0 Select1

A Digital System that Implements a Simple Processor

For this ALU,

A+B if AddSub=1

A-B if AddSub=0


Examples of Some Famous

Microprocessors

Intel's 4004 Chip


Technical specifications

• Maximum clock speed was 740 kHz

• Instruction cycle time: 10.8 µs

(8 clock cycles / instruction cycle)

• Instruction execution time 1 or 2 instruction cycles

(10.8 or 21.6 µs), 46300 to 92600 instructions per second

• Built using 2,300 transistors


Technical specifications

• Separate program and data storage.

• The 4004, with its need to keep pin count down, used a single multiplexed 4-bit bus for transferring:

▪ 12-bit addresses

▪ 8-bit instructions

▪ 4-bit data words

• Instruction set contained 46 instructions (of which

41 were 8 bits wide and 5 were 16 bits wide)

• Register set contained 16 registers of 4 bits each

• Internal subroutine stack, 3 levels deep.




Intel's 8086 Chip




Simplified block diagram of

Intel 8088 (a variant of 8086);

1=main registers;

2=segment registers and IP;

3=address adder;

4=internal address bus;

5=instruction queue;

6=control unit (very simplified!);

7=bus interface;

8=internal databus;

9=ALU;

10/11/12=external address/ data/control bus.

Questions?

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Simple Processor

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