State Machine Signaling
 Timing Behavior
 Glitches/hazards and how to avoid them
 FSM Partitioning
 What to do when the state machine doesn’t fit!
 State Machine Signaling
 Introducing Idle States (synchronous model)
 Four Cycle Signaling (asynchronous model)
 Dealing with Asynchronous Inputs
 Metastability and synchronization
CS 150 - Spring 2008 – Lec #22 – Signaling - 1
Momentary Changes in Outputs
 Can be useful—pulse shaping circuits
 Can be a problem—incorrect circuit
operation (glitches/hazards)
 Example: pulse shaping circuit
A
B
C
D
A' • A = 0
delays matter
in function
D remains high for
three gate delays after
A changes from low to high
CS 150 - Spring 2008 – Lec #22 – Signaling - 2
F is not always 0
pulse 3 gate-delays wide
F
Oscillatory Behavior
 Another pulse shaping circuit
+
resistor
A
open
switch
close switch
initially
undefined
open switch
CS 150 - Spring 2008 – Lec #22 – Signaling - 3
B
C
D
Hazards/Glitches
 Hazards/glitches: unwanted switching at the outputs
Occur when different paths through circuit have different
propagation delays
As in pulse shaping circuits we just analyzed
Dangerous if logic causes an action while output is unstable
May need to guarantee absence of glitches
 Usual solutions
1) Wait until signals are stable (by using a clock): preferable
(easiest to design when there is a clock – synchronous design)
2) Design hazard-free circuits: sometimes necessary (clock not
used – asynchronous design)
CS 150 - Spring 2008 – Lec #22 – Signaling - 4
Types of Hazards
 Static 1-hazard
1
Input change causes output to go from 1 to 0 to 1
0
 Static 0-hazard
Input change causes output to go from 0 to 1 to 0
Input change causes a double change
from 0 to 1 to 0 to 1 OR from 1 to 0 to 1 to 0
0
1
CS 150 - Spring 2008 – Lec #22 – Signaling - 5
1
0
 Dynamic hazards
1
1
0
0
0
1
1
0
Static Hazards
 Due to a literal and its complement momentarily taking
on the same value
Thru different paths with different delays and reconverging
 May cause an output that should have stayed at the
same value to momentarily take on the wrong value
 Example:
A
A
S
F
B
S
S'
B
F
S'
static-0 hazard
static-1 hazard
CS 150 - Spring 2008 – Lec #22 – Signaling - 6
hazard
Dynamic Hazards
 Due to the same versions of a literal taking on
opposite values
Thru different paths with different delays and reconverging
 May cause an output that was to change value to
change 3 times instead of once
A
 Example:
C
A
3
B
F
2
B1
B2
1
B3
C
F
dynamic hazards
CS 150 - Spring 2008 – Lec #22 – Signaling - 7
hazard
Eliminating Static Hazards
 Following 2-level logic function has a hazard, e.g.,
when inputs change from ABCD = 0101 to 1101
AB
00
CD
00 0
01
A
01
11
0
1
1
1
10
1
1
1
A
\C
1
0
\A
D
1
C
11
1
1
0
0
10
0
0
0
0
G3
\A
D
1
G1
1
0
1
ABCD = 1101
G1
1
0
1
G3
1
F
G2
0
10
ABCD = 1101
ABCD = 1100
This is the fix
Glitch in this case
G3
0
\A
D
1
No Glitch in this case
A
\C
1
G2
F
0
B
A
\C
1
G2
0
D
A
\C
1
G1
1
F
\A
D
0
G1
1
0
1
0
G3
0
A
\C
F
G2
0
ABCD = 0101 (A is still 0)
CS 150 - Spring 2008 – Lec #22 – Signaling - 8
\A
D
0
G1
1
1
1
0
G3
G2
1
ABCD = 0101 (A is 1)
1
F
Eliminating Dynamic Hazards
 Very difficult!
\A 1
B
01
\B 1 0
\C
1
G1
01
Slow
G2
 A circuit that is static
hazard free can still
have dynamic hazards
 Best approach:
G3
1 01
10
A 0
\B
10
G5
G4
V ery slow
10
1 01 0
F
 Design critical
circuits to be two
level and eliminate all
static hazards
 OR, use good clocked
synchronous design
style
CS 150 - Spring 2008 – Lec #22 – Signaling - 9
Hazard-Free Circuit Families
 NORA, Domino, DCVS
Use “evaluate” signal
Every gate guaranteed to transition at most once
 Very similar, we’ll consider Domino
CS 150 - Spring 2008 – Lec #22 – Signaling - 10
Domino
 Basic Domino Gate
 When Evaluation is LOW,
Output is low
 When Evaluation turns high,
connection to power is off
 If gate inputs are high,
connection to ground is made
and output (inverted) goes
low to high
Power
Evaluation
Output
Gate
Logic
 So:
 Gate output transitions at
MOST once, low to high
 Gate cannot glitch
CS 150 - Spring 2008 – Lec #22 – Signaling - 11
Ground
Domino: Plusses and Minusses
 Plus
 Minus
 Cannot glitch
 Timing analysis (false path
analysis) very simple
 Safe to connect Domino
gates together
 Non-inverting logic only
 Not functionally complete
 Use inverters on the circuit
outputs and inputs to
complete
 Glitches on inputs cause gate
to fail
Ensure circuit inputs are
stable when evaluation is
high
 Charge leaks away if
Evaluation stays on too long
How to do the Evaluation signal?
CS 150 - Spring 2008 – Lec #22 – Signaling - 12
DOMINO AND Gate
Power
Evaluation
Evaluation
A
F
Output
B
A
F
Output
B
Ground
CS 150 - Spring 2008 – Lec #22 – Signaling - 13
DOMINO AND Gate
Power
Evaluation
Evaluation
A
F
Output
B
A
F
Output
B
Ground
CS 150 - Spring 2008 – Lec #22 – Signaling - 14
DOMINO AND Gate
Power
Evaluation
Evaluation
A
F
Output
B
A
F
Output
B
Ground
CS 150 - Spring 2008 – Lec #22 – Signaling - 15
DOMINO AND Gate
Power
Evaluation
Evaluation
A
F
Output
B
A
F
Output
B
Ground
CS 150 - Spring 2008 – Lec #22 – Signaling - 16
Using Domino in a Larger Circuit safely
Domino Circuit
Clocked by
Evaluation
Latch bank stable
when Evaluation = 1
Latch bank active
when Evaluation = 1
CS 150 - Spring 2008 – Lec #22 – Signaling - 17
Key to Safe Operation
 Inputs glitch/hazard free
Guaranteed by latch discipline
 Foreach gate:
Inputs hazard-free => outputs hazard-free
 By induction:
Every node in circuit is hazard-free
CS 150 - Spring 2008 – Lec #22 – Signaling - 18
Differential Cascode Voltage Switch
 Two Domino Gates back-toback
Power
Evaluation’
notA = notC or notD
 One realizes A, the other A’
 Achieve by dualizing pulldown
trees
 Note A, A’ therefore
available for every DCVS
output
 Clever tricks can let one
combine the pulldowns
Use BDDs!
notD
notC
Ground
Power
Evaluation’
A = C and D
C
D
Ground
CS 150 - Spring 2008 – Lec #22 – Signaling - 19
Nice properties of DCVS
 Exactly one of A, notA will transition to high during
evaluation
 At most twice the size of DOMINO, static circuit
(often less)
 A XOR notA = 1 for every circuit output A is
completion signal
Can use this to clock latches
 Nice building block for unclocked circuits
 Still has charge leakage problem
 All other positive properties of Domino remain
CS 150 - Spring 2008 – Lec #22 – Signaling - 20
Domino In Static Logic
 Key elements of Domino
Noninverting logic only
All nodes evaluate to 0 when eval = 0 (or 1)
Inputs change at most once, low to high
 Problem
Leakage due to finite capacitance
Need access to transistor-level design
 Question: Can we build DOMINO (also DCVS) using
only static logic?
CS 150 - Spring 2008 – Lec #22 – Signaling - 21
Yes!
 Key element of Domino: evaluate only once
 All elements have one of two state changes
Low->high
Low->low (no change)
 State change high->low forbidden
 Let’s achieve that in full-static
CS 150 - Spring 2008 – Lec #22 – Signaling - 22
Static Domino AND Gate
 To form A & B
 A NAND B
 NOR the result with a new
signal, Evaluation’
A
B
 Evaluation is high when
circuit is evaluated
 Evaluation is low => evaluation’
is high output is 0
 Evaluation is high, Evaluation’
is low, NOR gate becomes an
inverter
Evaluation’
A
B
 Output is A & B
CS 150 - Spring 2008 – Lec #22 – Signaling - 23
Static DOMINO AND Gate
Evaluation’
Evaluation
A
B
A
B
F
Output
CS 150 - Spring 2008 – Lec #22 – Signaling - 24
DOMINO AND Gate (Example)
Evaluation
Evaluation’
A
B
A
B
F
Output
CS 150 - Spring 2008 – Lec #22 – Signaling - 25
DOMINO AND Gate
Evaluation
A
Evaluation’
B
F
A
B
Output
CS 150 - Spring 2008 – Lec #22 – Signaling - 26
Domino and Static Domino
 Domino
 Static Domino
 Glitch-free when inputs and
evaluation glitch-free
 Non-inverting logic only
 Requires transistor-level
design
 Incorrect when inputs glitch
 Fast since pull-ups inactive
during evaluation
 Glitch-free when inputs and
evaluation glitch-free
 Non-inverting logic only
 Use with any design style
 Correct when inputs glitch
(but not glitch-free)
 Slow since double gate-delay
 Key: Evaluation line must be glitch-free
CS 150 - Spring 2008 – Lec #22 – Signaling - 27
FSM Partitioning
 Why Partition?
 What if programmable logic is limited in number of inputs and
outputs that can be used in a particular device?
 For PLAs, the number of product terms are limited, thus limiting the
complexity of the next state and output functions
CS 150 - Spring 2008 – Lec #22 – Signaling - 28
Partitioning the State Machine
 Suppose that FSM is
partitioned so that states at
the right are in one partition
and states at the left are in
the other
 How do you support
intersignaling between the
state machine partitions?
 It is usually a good idea to
partition the machine so there
are as few cross links as
possible (min cut set in graph
theoretic terms)
CS 150 - Spring 2008 – Lec #22 – Signaling - 29
Partitioning the State Machine
 Solution: introduce idle states SA and SB
 Machine at left enters SA allowing machine at right to exit SB
 When machine at right returns to SB, machine at left exits SA
CS 150 - Spring 2008 – Lec #22 – Signaling - 30
Rules for Introducing Idle States
CS 150 - Spring 2008 – Lec #22 – Signaling - 31
Example: Partitioning the Up/Down
Counter
CS 150 - Spring 2008 – Lec #22 – Signaling - 32
Example Partitioning: Traffic Light
Controller
 Main Controller vs. Counter/Timer
 ST triggers transfer of control
 TS or TL triggers return of
control
Reset
(TL•C)'
TL•C / ST
TS'
HG
TS / ST
HY
FY
TS / ST
T19
[TL]
T00
ST
T01
T09
T10
T18
T02
T08
T11
T17
T03
T07
T12
T16
T04
[TS]
T06
T13
T15
TS'
TL+C' / ST
FG
(TL+C')'
(a) Main controller
T05
(b) Counter/timer
CS 150 - Spring 2008 – Lec #22 – Signaling - 33
T14
Partitioned FSM Block Diagram
reset
C
HR
HY
HG
FR
FY
FG
traffic light
controller
ST
TS
TL
 Interface between the
two partitions are the
signals ST, TS, TL
 NOTE: Main Controller
and Timer use the same
clock and are operating
in a synchronous mode
timer
CS 150 - Spring 2008 – Lec #22 – Signaling - 34
Generalized Inter-FSM Signaling
 Interlocked Synchronized Signaling
CS 150 - Spring 2008 – Lec #22 – Signaling - 35
Asynchronous Signaling
 Also known as “speed-independent” signaling
Requester/client/master vs. Provider/Server/Slave
Clocked
Subsys tem
Communications
Signals
Clocked
Subsys tem
Reques t
S2
S1
requester
client
mas ter
Data Flow
Acknow ledgement
provider
server
slav e
CS 150 - Spring 2008 – Lec #22 – Signaling - 36
Asynchronous Signaling
 First consider the common clock case (synchronous)
Req
Data
Ac k
Clk
 Master asserts Request
 Slave recognizes request, processes request, indicates
completion by asserting Acknowledgement
 Master accepts results, removes Request
 Slave see Request removed, removes Acknowledge
CS 150 - Spring 2008 – Lec #22 – Signaling - 37
Asynchronous Signaling
 What if Slave can’t respond in single cycle? Solution: Wait
signaling
Req
Data
Wait
Clk
 Slave inhibits master by asserting wait
 When slave unasserts wait, master knows request has been
processed, and can latch results
CS 150 - Spring 2008 – Lec #22 – Signaling - 38
True Asynchronous Signaling
 Now remove the assumption of a single common clock
 How do we make sure that receiver has seen the sender’s signal?
Solution: Interlocked signaling
 Four cycle signaling: assert Req, process request, assert ack,
latch result, remove Req, remove Ack and start again
 Sometimes called “Return to Zero” signaling
Req
1
3
Data
Ack
2
4
CS 150 - Spring 2008 – Lec #22 – Signaling - 39
True Asynchronous Signaling
 Alternative scheme: Two-Cycle Signaling
Non-return-to-zero signaling
Transaction start by Req lo-to-hi, finishes Ack lo-to-hi
Next transaction starts by Req hi-to-lo, finishes Ack hi-to-lo
Requires EXTRA state to keep track of the current sense of
the transitions—faster than 4 cycle case, but usually involves
more hardware
Req
1
1
Data
Ack
2
CS 150 - Spring 2008 – Lec #22 – Signaling - 40
2
True Asynchronous Timing
 Self-Timed Circuits
 Uses Req/Ack signaling as described
 Components can be constructed with
NO internal clocks
 Determines on its own when the
request has been processed
 Concept of the delay line simply
slows down the pass through of the
Req to the Ack—usually matched to
the worst case delay path
 Becoming MORE important for large
scale VLSI chips were global clock
distribution is a challenge
Input
Combinational
logic
Req
CS 150 - Spring 2008 – Lec #22 – Signaling - 41
Output
Ack
Delay
Metastability and Asynchronous inputs
 Clocked synchronous circuits
 Inputs, state, and outputs sampled or changed in relation to a
common reference signal (called the clock)
 E.g., master/slave, edge-triggered
 Asynchronous circuits
 Inputs, state, and outputs sampled or changed independently of a
common reference signal (glitches/hazards a major concern)
 E.g., R-S latch
 Asynchronous inputs to synchronous circuits
 Inputs can change at any time, will not meet setup/hold times
 Dangerous, synchronous inputs are greatly preferred
 Cannot be avoided (e.g., reset signal, memory wait, user input)
CS 150 - Spring 2008 – Lec #22 – Signaling - 42
Synchronization Failure
 Occurs when FF input changes close to clock edge
FF may enter a metastable state – neither a logic 0 nor 1 –
May stay in this state an indefinite amount of time
Is not likely in practice but has some probability
logic 1
logic 0
logic 1
small, but non-zero probability
that the FF output will get stuck
in an in-between state
logic 0
oscilloscope traces demonstrating
synchronizer failure and eventual
decay to steady state
CS 150 - Spring 2008 – Lec #22 – Signaling - 43
Dealing with Synchronization Failure
 Probability of failure can never be reduced to 0, but
it can be reduced
(1) slow down the system clock: this gives the synchronizer
more time to decay into a steady state; synchronizer failure
becomes a big problem for very high speed systems
(2) use fastest possible logic technology in the synchronizer:
this makes for a very sharp "peak" upon which to balance
(3) cascade two synchronizers: this effectively synchronizes
twice (both would have to fail)
asynchronous
input
D
Q
D
synchronized
input
Q
Clk
CS 150 - Spring 2008 – Lec #22 – Signaling - 44
synchronous system
Handling Asynchronous Inputs
 Never allow asynchronous inputs to fan-out to more
than one flip-flop
Synchronize as soon as possible and then treat as
synchronous signal
Clocked
Synchronous
System
Async
Input
D Q
Synchronizer
Q0
Async
Input
D Q
D Q
Clock
Clock
D Q
Q1
Clock
CS 150 - Spring 2008 – Lec #22 – Signaling - 45
Q0
D Q
Q1
Clock
Handling Asynchronous Inputs (cont’d)
 What can go wrong?
Input changes too close to clock edge (violating setup time
constraint)
In
Q0
Q1
In is asynchronous and
fans out to D0 and D1
one FF catches the
signal, one does not
inconsistent state may
be reached!
CLK
CS 150 - Spring 2008 – Lec #22 – Signaling - 46
Signaling Summary
 Glitches/Hazards
Introduce redundant logic terms to avoid them OR use synchronous
design!
 FSM Partitioning
Replacing monolithic State Machine with simpler communicating
state machine
Technique of introducing idle states
 Machine-to-machine Signaling
Synchronous vs. asynchronous
Four vs. Two Cycle Signaling
 Asynchronous inputs and their dangers
Synchronizer failure: what it is and how to minimize its impact
CS 150 - Spring 2008 – Lec #22 – Signaling - 47