Reliability Analysis of
Flexible Electronics:
Case Study of
Hydrogenated Amorphous Silicon
(a-Si:H) TFT Scan Driver
Tsung-Ching (Jim) Huang
Tim Cheng
Feb. 10th 2007
Outline
 Introduction
 Motivation: Why a-Si:H TFT scan driver
 Reliability of a-Si:H TFT circuits
 Electrical degradation and self-recovery
 Reliability Analysis for Flexible Electronics
 Device degradation model
 Reliability simulation
 Conclusion
2
Why A-Si:H TFT Scan Driver
• Type
Samsung
Gen VII
display line will produce
of TFT
Single-Crystal
Poly- Si
an area of active electronics equal to ~ 10%
Proc. Temp.
1000 ºC
450 ºC
of total worldwide IC area per year
Mobility
cm2/Vs
250 cm2/Vs
• 60,000
1870 mm270
X 2200
mm panel/month
Cost/Area
High
• Scan
driver is used toHigh
generate scanning
signal
to drive TFTs High
Maturity
Medium
A-Si:H
Organic
200 ºC
< 100 ºC
1 cm2/Vs
0.5 cm2/Vs
Medium
Low
High
Low
Flex. Sub.
Transfer
Transfer
Direct
Direct
Degrade.
N/A
Electrical
Electrical
Elec./Chem.
Ref: Samsung; T.N. Jackson, Penn State Univ.
3
Reliability Concern of
A-Si:H TFT
• Prolonged bias-stress to a-Si:H TFTs will
induce electrical degradation which causes
threshold voltage (VTH) shift
• Electrical degradation is attributed to biasinduced dangling bonds
Drain
a-Si:H
(Semiconductor)
Source
SiNx
n+ a-Si:H
SiNx (Insulator)
Gate
Substrate
• Charge trapping in the SiNx layer and point
defect creation in the a-Si:H layer are the
major mechanisms
Ref: C.-S. Chiang et al, Jap. J. Applied
Physics, 1998; AUO Taiwan
4
Outline
 Introduction
 Motivation: Why a-Si:H TFT scan driver
 Reliability of a-Si:H TFT circuits
 Electrical degradation and self-recovery
 Reliability Analysis for Flexible Electronics
 Device degradation model
 Reliability simulation
 Conclusion
5
Electrical Degradation Model
 VTH degradation
 Pulsed-bias VGS
 DC-bias VGS
 Pulsed-bias VGS + pulsed-biased VDS
 VTH recovery
 Reverse pulsed-bias VGS
6
Methodology for
Reliability Simulation
 SPICE-level circuit simulation
 High accuracy
 Compatible with RPI TFT- model
 Compatible with Verilog-a behavioral
model
 Comprehensive model parameters
Input
Pattern
Device
Characterization
Input Segment
Slicer
Fitting
Parameters
Device Analyzer
Analytical Model
Selection
 Simulation time reduction
Prediction
&
Optimization
Optimizer
Analyze
 Iterative reliability simulation
 Incrementally change model parameters
to mimic physical degradation process
 High-accuracy with measured device
degradation model parameters under
various conditions
Circuit
Netlist
HSPICE
Simulator/Interface
Transient Output
Extractor
Model Parameter
Adjustment
Degraded Netlist
Generator
Ready For Simulation
Control Console
 Auto-regressive invariant moving average (ARIMA) model
7
Case Study: A-Si:H TFT
Scan Driver
 A-Si:H TFT scan driver integrated with the
LCD pixel circuits on the glass substrate
 Save the cost of wire bonding and
packaging
 Eliminate the need for driver ICs
 Compatible with low-temperature process
for plastic substrates
 Device degradation depends on its bias-stress
 Degradation profile for each TFT can be
obtained by analyzing its bias-stress
 Reliability simulation can predict circuit
lifetime based on bias-stress analysis
8
Comparison of Simulation and
Measurement Results
Simulation
Measured
Fig. 1. Before Degradation
Simulation
Measured
Fig. 2 After Degradation (33,000s, 85 ºC)
 Reliability simulation tool provides a fast and yet accurate way of estimating circuit
reliability with a-Si:H TFTs
 No physical layout information is required
 SPICE-compatible
 Device degradation model and input pattern are needed
9
Conclusion
 Flexible electronics are emerging
 Future trend in consumer electronics
 Potential applications includes:
 E-paper, flexible display
 RFID tags, Implantable IDtags
 Ubiquitous sensor arrays & rollable solar cells
 Reliability analysis is essential
 Electrical degradation is severe vs. CMOS
 Robust circuit design and architecture is critical
 Our reliability simulation tool shows:
 Predicting circuit reliability is possible with high accuracy
within reasonable simulation time
10
Q&A
Thank you for your attention !!
11