CS 152 Computer Architecture and Engineering
Lecture 9 - Virtual Memory
Krste Asanovic
Electrical Engineering and Computer Sciences
University of California at Berkeley
http://www.eecs.berkeley.edu/~krste
http://inst.eecs.berkeley.edu/~cs152
2/21/2013
CS152, Spring 2013
Last time in Lecture 9
 Protection and translation required for multiprogramming
– Base and bounds was early simple scheme
 Page-based translation and protection avoids need for
memory compaction, easy allocation by OS
– But need to indirect in large page table on every access
 Address spaces accessed sparsely
– Can use multi-level page table to hold translation/protection
information, but implies multiple memory accesses per reference
 Address space access with locality
– Can use “translation lookaside buffer” (TLB) to cache address
translations (sometimes known as address translation cache)
– Still have to walk page tables on TLB miss, can be hardware or software
talk
 Virtual memory uses DRAM as a “cache” of disk memory,
allows very cheap main memory
2/21/2013
CS152, Spring 2013
2
Memory Management
 Can separate into orthogonal functions:
– Translation (mapping of virtual address to physical address)
– Protection (permission to access word in memory)
– Virtual memory (transparent extension of memory space using slower
disk or flash storage)
 But most modern systems provide support for all the
above functions with a single page-based system
2/21/2013
CS152, Spring 2013
3
Modern Virtual Memory Systems
Illusion of a large, private, uniform store
OS
Protection & Privacy
several users, each with their private address
space and one or more shared address spaces
page table name space
useri
Demand Paging
Provides the ability to run programs larger
than the primary memory
Primary
Memory
Secondary
Storage
Hides differences in machine configurations
The price is address translation on
each memory reference
VA
2/21/2013
CS152, Spring 2013
mapping
TLB
PA
4
Hierarchical Page Table
Virtual Address
22 21
p1
12 11
p2
0
offset
10-bit 10-bit
L1 index L2 index
offset
p2
p1
Root of Current
Page Table
(Processor Register)
Level 1
Page Table
page in primary memory
page in secondary memory
PTE of a nonexistent page
2/21/2013
CS152, Spring 2013
Physical Memory
31
Level 2
Page Tables
Data Pages
5
Page-Based Virtual-Memory Machine
(Hardware Page-Table Walk)
Page Fault?
Page Fault?
Protection violation?
Virtual
Physical
Address
Address
Inst.
TLB
PC
Inst.
Cache
Miss?
D
Decode
E
Page-Table Base
Register
Physical
Address
Protection violation?
Virtual
Physical
Address
Address
Data
Data
M
+
TLB
Cache
W
Miss?
Hardware Page
Table Walker
Memory Controller
Physical
Address
Physical Address
Main Memory (DRAM)
 Assumes page tables held in untranslated physical memory
2/21/2013
CS152, Spring 2013
6
Address Translation:
putting it all together
Virtual Address
hardware
hardware or software
software
TLB
Lookup
miss
hit
Protection
Check
Page Table
Walk
 memory
the page is
Page Fault
(OS loads page)
Where?
2/21/2013
 memory
denied
Protection
Fault
Update TLB
permitted
Physical
Address
(to cache)
SEGFAULT
CS152, Spring 2013
7
Page Fault Handler
 When the referenced page is not in DRAM:
– The missing page is located (or created)
– It is brought in from disk, and page table is updated
• Another job may be run on the CPU while the first job waits
for the requested page to be read from disk
– If no free pages are left, a page is swapped out
• Pseudo-LRU replacement policy, implemented in software
 Since it takes a long time to transfer a page
(msecs), page faults are handled completely in
software by the OS
– Untranslated addressing mode is essential to allow kernel to
access page tables
2/21/2013
CS152, Spring 2013
8
Handling VM-related exceptions
PC
Inst
TLB
Inst.
Cache D
Decode
E
+ M Data
TLB
Data
Cache W
TLB miss? Page Fault?
TLB miss? Page Fault?
Protection violation?
Protection violation?
 Handling a TLB miss needs a hardware or software mechanism
to refill TLB
 Handling a page fault (e.g., page is on disk) needs a restartable
exception so software handler can resume after retrieving page
– Precise exceptions are easy to restart
– Can be imprecise but restartable, but this complicates OS software
 Handling protection violation may abort process
– But often handled the same as a page fault
2/21/2013
CS152, Spring 2013
9
Address Translation in CPU Pipeline
PC
Inst
TLB
Inst.
Cache D
Decode
E
TLB miss? Page Fault?
Protection violation?
+ M Data
TLB
Data
Cache W
TLB miss? Page Fault?
Protection violation?
 Need to cope with additional latency of TLB:
–
–
–
–
2/21/2013
slow down the clock?
pipeline the TLB and cache access?
virtual address caches
parallel TLB/cache access
CS152, Spring 2013
10
Virtual-Address Caches
CPU
VA
TLB
PA Physical
Cache
PA Primary
Memory
Alternative: place the cache before the TLB
CPU
VA
Virtual
Cache
VA
TLB
PA
Primary
Memory (StrongARM)
 one-step process in case of a hit (+)
 cache needs to be flushed on a context switch unless address space
identifiers (ASIDs) included in tags (-)
 aliasing problems due to the sharing of pages (-)
 maintaining cache coherence (-) (see later in course)
2/21/2013
CS152, Spring 2013
11
Virtually Addressed Cache
(Virtual Index/Virtual Tag)
Virtual
Address
Virtual
Address
PC
Inst.
Cache
D
Decode
E
+
M
Data
Cache
Miss?
Inst.
TLB
Miss?
Page-Table Base
Register
Physical
Address
Instruction data
W
Hardware Page
Table Walker
Memory Controller
Data
TLB
Physical
Address
Physical Address
Main Memory (DRAM)
Translate on miss
2/21/2013
CS152, Spring 2013
12
Aliasing in Virtual-Address Caches
VA1
Page Table
Data Pages
PA
Tag
Data
VA1
1st Copy of Data at PA
VA2
2nd Copy of Data at PA
VA2
Virtual cache can have two copies of
Two virtual pages share
same physical data. Writes to one
one physical page
copy not visible to reads of other!
General Solution: Prevent aliases coexisting in cache
Software (i.e., OS) solution for direct-mapped cache
VAs of shared pages must agree in cache index bits; this ensures
all VAs accessing same PA will conflict in direct-mapped cache
(early SPARCs)
2/21/2013
CS152, Spring 2013
13
Concurrent Access to TLB & Cache
(Virtual Index/Physical Tag)
VA
VPN
L
TLB
PA
PPN
b
k
Page Offset
Tag
Virtual
Index
=
Direct-map Cache
2L blocks
2b-byte block
Physical Tag Data
hit?
Index L is available without consulting the TLB
cache and TLB accesses can begin simultaneously!
Tag comparison is made after both accesses are completed
Cases: L + b = k, L + b < k, L + b > k
2/21/2013
CS152, Spring 2013
14
Virtual-Index Physical-Tag Caches:
Associative Organization
VA
VPN
a
L = k-b
TLB
PA
PPN
b
k
2
Virtual
Index
a
Direct-map
2L blocks
Direct-map
2L blocks
Phy.
Tag
Page Offset
=
Tag
hit?
=
2a
Data
After the PPN is known, 2a physical tags are compared
How does this scheme scale to larger caches?
2/21/2013
CS152, Spring 2013
15
Concurrent Access to TLB & Large L1
The problem with L1 > Page size
Virtual Index
VA
VPN
a
Page Offset
b
TLB
PA
PPN
Page Offset
L1 PA cache
Direct-map
VA1 PPNa
Data
VA2 PPNa
Data
b
=
Tag
hit?
Can VA1 and VA2 both map to PA ?
2/21/2013
CS152, Spring 2013
16
CS152 Administrivia
 PS 2 and Lab 2 out
 Short time frame – only one week left till due so start soon
 Quiz 2, Tuesday March 5
– Lectures 6-9, PS 2, Lab 2, readings
2/21/2013
CS152, Spring 2013
17
A solution via Second Level Cache
CPU
RF
L1
Instruction
Cache
L1 Data
Cache
Unified L2
Cache
Memory
Memory
Memory
Memory
Usually a common L2 cache backs up both Instruction
and Data L1 caches
L2 is “inclusive” of both Instruction and Data caches
• Inclusive means L2 has copy of any line in either L1
2/21/2013
CS152, Spring 2013
18
Anti-Aliasing Using L2 [MIPS R10000,1996]
Virtual Index
VA
VPN
TLB
PA
PPN
a Page Offset
b
into L2 tag
Page Offset
VA1 PPNa
Data
VA2 PPNa
Data
b
PPN
Tag
 Suppose VA1 and VA2 both map to PA and
VA1 is already in L1, L2 (VA1  VA2)
 After VA2 is resolved to PA, a collision will be
detected in L2.
 VA1 will be purged from L1 and L2, and VA2
will be loaded  no aliasing !
2/21/2013
L1 PA cache
Direct-map
CS152, Spring 2013
=
hit?
PA a1
Data
Direct-Mapped L2
19
Anti-Aliasing using L2 for a Virtually
Addressed L1
VA
VPN
Page Offset
b
VA1 Data
TLB
PA
PPN
Tag
VA2 Data
Page Offset
b
Physical
Index & Tag
Physically-addressed L2 can also be
used to avoid aliases in virtuallyaddressed L1
2/21/2013
Virtual
Index & Tag
CS152, Spring 2013
L1 VA Cache
“Virtual Tag”
PA VA1
Data
L2 PA Cache
L2 “contains” L1
20
Atlas Revisited
 One PAR for each physical page
PAR’s
 PAR’s contain the VPN’s of the pages
resident in primary memory
 Advantage: The size is proportional to the
size of the primary memory
PPN
VPN
 What is the disadvantage ?
2/21/2013
CS152, Spring 2013
21
Hashed Page Table:
Approximating Associative Addressing
VPN
Virtual Address
d
Page Table
PID
hash
Offset
+
Base of Table
PA of PTE
VPN PID PPN
 Hashed Page Table is typically 2 to 3 times larger
VPN PID DPN
than the number of PPN’s to reduce collision
VPN PID
probability
 It can also contain DPN’s for some non-resident
pages (not common)
Primary
 If a translation cannot be resolved in this table then
Memory
the software consults a data structure that has an
entry for every existing page (e.g., full page table)
2/21/2013
CS152, Spring 2013
22
Power PC: Hashed Page Table
VPN
hash
d
Offset
80-bit VA
+
PA of Slot
Page Table
VPN
VPN
PPN
Base of Table
 Each hash table slot has 8 PTE's <VPN,PPN> that
are searched sequentially
 If the first hash slot fails, an alternate hash
function is used to look in another slot
All these steps are done in hardware!
 Hashed Table is typically 2 to 3 times larger than
the number of physical pages
 The full backup Page Table is managed in software
2/21/2013
CS152, Spring 2013
Primary
Memory
23
VM features track historical uses:
 Bare machine, only physical addresses
– One program owned entire machine
 Batch-style multiprogramming
– Several programs sharing CPU while waiting for I/O
– Base & bound: translation and protection between programs (supports
swapping entire programs but not demand-paged virtual memory)
– Problem with external fragmentation (holes in memory), needed occasional
memory defragmentation as new jobs arrived
 Time sharing
– More interactive programs, waiting for user. Also, more jobs/second.
– Motivated move to fixed-size page translation and protection, no external
fragmentation (but now internal fragmentation, wasted bytes in page)
– Motivated adoption of virtual memory to allow more jobs to share limited
physical memory resources while holding working set in memory
 Virtual Machine Monitors
– Run multiple operating systems on one machine
– Idea from 1970s IBM mainframes, now common on laptops
• e.g., run Windows on top of Mac OS X
– Hardware support for two levels of translation/protection
• Guest OS virtual -> Guest OS physical -> Host machine physical
2/21/2013
CS152, Spring 2013
24
Virtual Memory Use Today - 1
 Servers/desktops/laptops/smartphones have full demandpaged virtual memory
–
–
–
–
Portability between machines with different memory sizes
Protection between multiple users or multiple tasks
Share small physical memory among active tasks
Simplifies implementation of some OS features
 Vector supercomputers have translation and protection but
rarely complete demand-paging
 (Older Crays: base&bound, Japanese & Cray X1/X2: pages)
– Don’t waste expensive CPU time thrashing to disk (make jobs fit in memory)
– Mostly run in batch mode (run set of jobs that fits in memory)
– Difficult to implement restartable vector instructions
2/21/2013
CS152, Spring 2013
25
Virtual Memory Use Today - 2
 Most embedded processors and DSPs provide physical
addressing only
–
–
–
–
2/21/2013
Can’t afford area/speed/power budget for virtual memory support
Often there is no secondary storage to swap to!
Programs custom written for particular memory configuration in product
Difficult to implement restartable instructions for exposed architectures
CS152, Spring 2013
26
Acknowledgements
 These slides contain material developed and copyright by:
–
–
–
–
–
–
Arvind (MIT)
Krste Asanovic (MIT/UCB)
Joel Emer (Intel/MIT)
James Hoe (CMU)
John Kubiatowicz (UCB)
David Patterson (UCB)
 MIT material derived from course 6.823
 UCB material derived from course CS252
2/21/2013
CS152, Spring 2013
27