CS 152 Computer Architecture and
Engineering
Lecture 11 - Virtual Memory and Caches
Krste Asanovic
Electrical Engineering and Computer Sciences
University of California at Berkeley
http://www.eecs.berkeley.edu/~krste
http://inst.eecs.berkeley.edu/~cs152
February 25, 2010
CS152, Spring 2010
Today is a review of last two lectures
• Translation/Protection/Virtual Memory
• This is complex material - often takes several passes
before the concepts sink in
• Try to take a different path through concepts today
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VM features track historical uses:
• Bare machine, only physical addresses
– One program owned entire machine
• Batch-style multiprogramming
– Several programs sharing CPU while waiting for I/O
– Base & bound: translation and protection between programs (not virtual
memory)
– Problem with external fragmentation (holes in memory), needed occasional
memory defragmentation as new jobs arrived
• Time sharing
– More interactive programs, waiting for user. Also, more jobs/second.
– Motivated move to fixed-size page translation and protection, no external
fragmentation (but now internal fragmentation, wasted bytes in page)
– Motivated adoption of virtual memory to allow more jobs to share limited
physical memory resources while holding working set in memory
• Virtual Machine Monitors
– Run multiple operating systems on one machine
– Idea from 1970s IBM mainframes, now common on laptops
» e.g., run Windows on top of Mac OS X
– Hardware support for two levels of translation/protection
» Guest OS virtual -> Guest OS physical -> Host machine physical
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Bare Machine
PC
Physical
Address
Inst.
Cache
Physical
Address
D
Decode
E
+
M
Physical
Address
Data
Cache
Memory Controller
W
Physical
Address
Physical Address
Main Memory (DRAM)
• In a bare machine, the only kind of address is a
physical address
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Data Bound
Register
Mem. Address Logical
Register
Address
Load X
Program
Address
Space

Bounds
Violation?
Data Base
Register
+
Physical
Address
Program Bound
Register

Bounds
Violation?
Program
Counter
Program Base
Register
Logical
Address
+
data
segment
program
segment
Physical
Address
Logical address is what user software sees. Translated to
physical address by adding base register.
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Main Memory
Base and Bound Scheme
Base and Bound Machine
Prog. Bound
Register
Logical
Address
PC
Bounds
Violation?

+
Data Bound
Register
Inst.
Cache
D

Logical
Address
Decode
E
+
M
+
Physical
Address
Program Base
Register
Bounds
Violation?
Data
Cache
W
Physical
Address
Physical
Address
Data Base
Register
Memory Controller
Physical
Address
Physical Address
Main Memory (DRAM)
[ Can fold addition of base register into (base+offset) calculation
using a carry-save adder (sum three numbers with only a few
gate delays more than adding two numbers) ]
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Memory Fragmentation
OS
Space
Users 4 & 5
arrive
OS
Space
Users 2 & 5
leave
free
OS
Space
user 1
16K
user 1
16K
user 2
24K
user 2
24K
user 4
16K
8K
user 4
32K
user 3
32K
16K
8K
user 3
32K
24K
user 5
24K
24K
user 3
user 1
16K
24K
24K
As users come and go, the storage is “fragmented”.
Therefore, at some stage programs have to be moved
around to compact the storage.
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Paged Memory Systems
• Processor generated address can be interpreted as a pair
<page number, offset>
page number
offset
• A page table contains the physical address of the base of
each page
0
1
2
3
Address Space
of User-1
1
0
0
1
2
3
3
Page Table
of User-1
2
Page tables make it possible to store the
pages of a program non-contiguously.
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User 1
VA1
Page Table
User 2
Physical
Memory
Private Address Space per User
OS
pages
VA1
Page Table
User 3
VA1
Page Table
free
• Each user has a page table
• Page table contains an entry for each user page
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Linear Page Table
• Page Table Entry (PTE)
contains:
Data Pages
Page Table
– A bit to indicate if a page exists
– PPN (physical page number) for
a memory-resident page
– DPN (disk page number) for a
page on the disk
– Status bits for protection and
usage
• OS sets the Page Table
Base Register whenever
active user process
changes
PPN
PPN
DPN
PPN
Data word
Offset
DPN
PPN
PPN
DPN
DPN
VPN
DPN
PPN
PPN
PT Base Register
VPN
Offset
Virtual address
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Page Tables in Physical Memory
PT User 1
VA1
PT User 2
User 1
VA1
User 2
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Size of Linear Page Table
With 32-bit addresses, 4-KB pages & 4-byte PTEs:
 220 PTEs, i.e, 4 MB page table per user
 4 GB of swap needed to back up full virtual address
space
Larger pages?
• Internal fragmentation (Not all memory in a page is used)
• Larger page fault penalty (more time to read from disk)
What about 64-bit virtual address space???
• Even 1MB pages would require 244 8-byte PTEs (35 TB!)
What is the “saving grace” ?
sparsity of virtual address usage
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Hierarchical (Two-Level) Page Table
Virtual Address
31
22 21
p1
0
12 11
p2
offset
10-bit 10-bit
L1 index L2 index
offset
Root of the Current
Page Table
p2
p1
(Processor
Register)
Level 1
Page Table
page in primary memory
page in secondary memory
Level 2
Page Tables
PTE of a nonexistent page
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Data Pages
13
Two-Level Page Tables in Physical
Memory
Physical
Virtual
Address
Spaces
Memory
Level 1 PT
User 1
VA1
Level 1 PT
User 2
User 1
User2/VA1
User1/VA1
VA1
User 2
Level 2 PT
User 2
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Address Translation & Protection
Virtual Address
Virtual Page No. (VPN)
offset
Kernel/User Mode
Read/Write
Protection
Check
Address
Translation
Exception?
Physical Address
Physical Page No. (PPN)
offset
• Every instruction and data access needs address
translation and protection checks
A good VM design needs to be fast (~ one cycle) and
space efficient
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Translation Lookaside Buffers
Address translation is very expensive!
In a two-level page table, each reference
becomes several memory accesses
Solution: Cache translations in TLB
TLB hit
TLB miss
 Single Cycle Translation
 Page Table Walk to refill
virtual address
VRWD
tag
PPN
VPN
offset
(VPN = virtual page number)
(PPN = physical page number)
hit?
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physical address
CS152, Spring 2010
PPN
offset
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Handling a TLB Miss
Software (MIPS, Alpha)
TLB miss causes an exception and the operating system
walks the page tables and reloads TLB. A privileged
“untranslated” addressing mode used for walk
Hardware (SPARC v8, x86, PowerPC)
A memory management unit (MMU) walks the page
tables and reloads the TLB
If a missing (data or PT) page is encountered during the
TLB reloading, MMU gives up and signals an exception
for the original instruction
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Page-Based Virtual Memory Machine
(Hardware Page Table Walk)
Page Fault?
Protection violation?
Virtual
Address
PC
Page Fault?
Protection violation?
Virtual
Address
Physical
Address
Inst.
TLB
Inst.
Cache
Miss?
Physical
Address
D
Decode
E
Page Table Base
Register
+
Physical
Address
Data
TLB
M
Data
Cache
W
Miss?
Hardware Page
Table Walker
Memory Controller
Physical
Address
Physical Address
Main Memory (DRAM)
• Assumes page tables held in untranslated physical memory
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CS152 Administrivia
• Tuesday Mar 9, Quiz 2
– Cache and virtual memory lectures, L6-L11, PS 2, Lab 2
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Virtual Memory
•
•
•
•
More than just translation and protection
Use disk to extend apparent size of main memory
Treat DRAM as cache of disk contents
Only need to hold active working set of processes in
DRAM, rest of memory image can be swapped to disk
• Inactive processes can be completely swapped to disk
(except usually the root of the page table)
• Combination of hardware and software used to
implement this feature
• (ATLAS was first implementation of this idea)
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Page Fault Handler
• When the referenced page is not in DRAM:
– The missing page is located (or created)
– It is brought in from disk, and page table is updated
Another job may be run on the CPU while the first job waits
for the requested page to be read from disk
– If no free pages are left, a page is swapped out
Pseudo-LRU replacement policy
• Since it takes a long time to transfer a page
(msecs), page faults are handled completely in
software by the OS
– Untranslated addressing mode is essential to allow kernel
to access page tables
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Caching vs. Demand Paging
secondary
memory
CPU
cache
primary
memory
CPU
primary
memory
Caching
Demand paging
cache entry
page frame
cache block (~32 bytes)
page (~4K bytes)
cache miss rate (1% to 20%) page miss rate (<0.001%)
cache hit (~1 cycle)
page hit (~100 cycles)
cache miss (~100 cycles)
page miss (~5M cycles)
a miss is handled
a miss is handled
in hardware
mostly in software
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Address Translation:
putting it all together
Virtual Address
Restart instruction
TLB
Lookup
miss
hit
Protection
Check
Page Table
Walk
 memory
the page is
Page Fault
(OS loads page)
hardware
hardware or software
software
 memory
Update TLB
denied
Protection
Fault
permitted
Physical
Address
(to cache)
SEGFAULT
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Address Translation in CPU Pipeline
PC
Inst
TLB
Inst.
Cache
TLB miss? Page Fault?
Protection violation?
D
Decode
E
+
M
Data
TLB
Data
Cache
W
TLB miss? Page Fault?
Protection violation?
• Software handlers need restartable exception on TLB fault
• Handling a TLB miss needs a hardware or software mechanism to refill TLB
• Need mechanisms to cope with the additional latency of a TLB:
– slow down the clock
– pipeline the TLB and cache access
– virtual address caches
– parallel TLB/cache access
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Virtual Address Caches
CPU
VA
PA
TLB
Physical
Cache
Primary
Memory
Alternative: place the cache before the TLB
VA
CPU
Virtual
Cache
TLB
PA
Primary
Memory (StrongARM)
• one-step process in case of a hit (+)
• cache needs to be flushed on a context switch unless address
space identifiers (ASIDs) included in tags (-)
• aliasing problems due to the sharing of pages (-)
• maintaining cache coherence (-) (see later in course)
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Aliasing in Virtual-Address Caches
VA1
Page Table
Data Pages
PA
VA2
Two virtual pages share
one physical page
Tag
Data
VA1
1st Copy of Data at PA
VA2
2nd Copy of Data at PA
Virtual cache can have two
copies of same physical data.
Writes to one copy not visible
to reads of other!
General Solution: Disallow aliases to coexist in cache
Software (i.e., OS) solution for direct-mapped cache
VAs of shared pages must agree in cache index bits; this
ensures all VAs accessing same PA will conflict in directmapped cache (early SPARCs)
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Concurrent Access to TLB & Cache
VA
VPN
L
TLB
PA
PPN
b
k
Page Offset
Tag
Virtual
Index
=
hit?
Direct-map Cache
2L blocks
2b-byte block
Physical Tag
Data
Index L is available without consulting the TLB
cache and TLB accesses can begin simultaneously
Tag comparison is made after both accesses are completed
Cases: L + b = k
February 25, 2010
L+b<k
L+b>k
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Virtual-Index Physical-Tag Caches:
Associative Organization
VA
VPN
a
L = k-b
TLB
PA
k
PPN
Virtual
Index
2a
b
Direct-map
2L blocks
Direct-map
2L blocks
Phy.
Tag
Page Offset
=
Tag
hit?
a
After the PPN is known, 2 physical tags are compared
=
2a
Data
Is this scheme realistic?
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Concurrent Access to TLB & Large L1
The problem with L1 > Page size
Virtual Index
VA
VPN
a
Page Offset
b
TLB
PPN
PA
Page Offset
L1 PA cache
Direct-map
VA1 PPNa
Data
VA2 PPNa
Data
b
=
Tag
hit?
Can VA1 and VA2 both map to PA ?
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A solution via
Second Level Cache
CPU
RF
L1
Instruction
Cache
Memory
Unified L2
Cache
L1 Data
Cache
Memory
Memory
Memory
Often, a common L2 cache backs up both
Instruction and Data L1 caches
L2 is “inclusive” of both Instruction and Data caches
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Anti-Aliasing Using L2: MIPS R10000
Virtual Index
VA
VPN
TLB
PPN
PA
a
Page Offset
b
into L2 tag
Page Offset
VA1 PPNa
Data
VA2 PPNa
Data
b
PPN
Tag
•
•
•
Suppose VA1 and VA2 both map to PA and VA1 is
already in L1, L2 (VA1  VA2)
After VA2 is resolved to PA, a collision will be
detected in L2.
VA1 will be purged from L1 and L2, and VA2 will be
loaded  no aliasing !
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L1 PA cache
Direct-map
CS152, Spring 2010
PA
=
a1
hit?
Data
Direct-Mapped L2
31
Virtually-Addressed L1:
Anti-Aliasing using L2
VA
VPN
Page Offset
Virtual
Index & Tag
b
TLB
PA
PPN
Tag
Page Offset
February 25, 2010
VA2
Data
“Virtual
Tag”
Physical
Index & Tag
CS152, Spring 2010
Data
L1 VA Cache
b
Physically-addressed L2 can also be
used to avoid aliases in virtuallyaddressed L1
VA1
PA
VA1
Data
L2 PA Cache
L2 “contains” L1
32
Atlas Revisited
• One PAR for each physical page
PAR’s
• PAR’s contain the VPN’s of the pages
resident in primary memory
PPN
• Advantage: The size is proportional to
the size of the primary memory
VPN
• What is the disadvantage ?
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Hashed Page Table:
Approximating Associative Addressing
VPN
d
Virtual Address
Page Table
PID
hash
Offset
+
PA of PTE
Base of Table
•
•
•
VPN PID PPN
Hashed Page Table is typically 2 to 3 times larger
than the number of PPN’s to reduce collision
probability
It can also contain DPN’s for some non-resident
pages (not common)
If a translation cannot be resolved in this table then
the software consults a data structure that has an
entry for every existing page
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VPN PID DPN
VPN PID
Primary
Memory
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Acknowledgements
• These slides contain material developed and
copyright by:
–
–
–
–
–
–
Arvind (MIT)
Krste Asanovic (MIT/UCB)
Joel Emer (Intel/MIT)
James Hoe (CMU)
John Kubiatowicz (UCB)
David Patterson (UCB)
• MIT material derived from course 6.823
• UCB material derived from course CS252
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