ECE397A Operating Systems – FINAL EXAM, 2002 - SOLUTIONS
Instructions:
 Put your name and student number on the exam books!
 The exam is closed book and closed notes.
 You have 1.5 hours to complete the exam.
 First read the entire exam and then budget your time accordingly. Don't waste your time giving details
that the question does not request.
 Max score is 100.
 Good luck!
A. (20 pts) Short Answers (be short!)
1. List the content of PCB.
See textbook
2. What is the advantage of using threads compared to processes?
Sharing the address space of the process and lighter switching between threads
3. What is the difference between binary and counting semaphores?
Counting semaphores are used to synchronize multiple resources at the time
4. List three of the four necessary conditions for deadlock to occur.
See textbook
5. What is the difference between deadlock prevention and deadlock avoidance?
See textbook
6. What happens during swapping and when it is used?
One process’s memory is moved out to disk to free memory for a new process
7. What happens during a page fault?
See textbook
8. What happens during trashing (in the memory system) and why it happens?
The required number of frames inside a loop for example are more than available memory
9. What is Belady’s anomaly?
In some cases increasing the number of frames does not reduce pagefaults
10. What is a symbolic link in a file system and what is the problem with supporting links?
Removing a file that has a link associated
B. (20 pts) Performance of Paged Systems. This question asks you to compute the effective memory
access time (ema) in symbolic terms for different hardware implementations of paging. Let ma be the time
to read or write a value in memory. Define other terms (e.g., TLB hit rate, page faults, cache hit rate) as you
need them.
In all questions ignore the instruction memory related cache, TLB, and paging aspects. Before showing the
equations show a table containing all your notations (e.g., in left column have variables, in right column
what it means) and other assumptions you may have.
1.
First assume the process and its page table fit and stay in memory while the program executes, and
there is no TLB or cache. What is the ema for this system?
ema=2ma
2.
Now assume there is a TLB. What is the ema for this system? Include l, the time for the TLB lookup
in your equation.
ema=tlbhitrate*(l +m) + (1-tlbhitrate)(l+2m)
1
3.
Now consider a virtual memory system with a TLB where the process can grow larger than the
memory, and the page may not be in memory (note that page fault can occur now). What is the ema
now? Assume that the page table is always in memory.
Ema= tlbhitrate*(l +m) + (1-tlbhitrate)[(1-pagefault)(l+2m) + pagefault(l+2m + pagefaultcost)]
4.
Now what is the ema for the same system except that the page table entry itself may not be in
memory?
add a rate for page misses in the page fault case and change above one instance of ‘m’ with a new m’ that
depends on the rate
5.
Now assume that there is a first level cache for data accesses. Let ca be the time to access the cache.
Assume that the TLB access must be completed first before the cache can be accessed. This, because
the physical address is used to index and tag the cache. What is the ema now?
Replace all m with m’ like this m’=cachehitrate*ca + (1-cachehitrate) m
C. (20) Replacement policy. Assume that you have 3 frames and you get the following sequence of page
requests: A,B,C,D,E,D,A,A,B,C,C,B,A,E,D,A
1. Show the replacement for FIFO and LRU, and calculate the number of page faults.
Follow replacement rule
D. (20pts) Segmentation with Paging. Design a virtual memory management scheme that uses
segmentation with paging. Use 32 bit addresses and 1Kbyte page sizes.
1. Specify and justify the number of segments.
>> e.g., text, stack, heap, etc. it is based on user’s view of the program
2. Calculate the total size of ALL page tables (i.e., the sum of page table sizes including all
segments). Assume inverted page table is used for all segments, and 128Kbyte SRAM is
available as total physical memory. Assume that frames are assigned in proportion to
segment size. Show the content of a page table entry (PTE).
>> page table size in an inverted is equal with # of frames and multiplied with size of each
entry that is typically a logical page number and some other protection/valid bits
3. Specify hardware support to make address translation fast. Explain how it works.
>> TLB
4. Draw a picture including ALL components of your system. In your figure show the page
table for one segment only (similar as we have shown for the MULTICS scheme in
lecture notes). It should be clear how a logical address is translated into a physical one.
>> see lecture notes
5. Draw a picture assuming there is a first level cache.
>> add a cache before the TLB in the figure
See also lecture notes for segmentation with paging
E. (20pts) Synchronization and Deadlocks. The dining-philosophers problem.
Access to food is the critical section, each Philosopher needs 2 chopsticks to eat.
The philosophers are either eating or thinking.
1. Check the solution below and identify how deadlock can occur. Use a
2
Resource –allocation graph. Show your work.
>>It occurs between accessing the chopstics (i.e., resource) and philosophers
>> (consumers)
1.
Modify the code to avoid deadlock.
>>Make it an asymmetric solution. Many approaches available.
>> Next, I add a counting semaphore grab that I initialize to 2. Only two philosophers can pick up
chopsticks (left and right) at the same time.
// Shared data
semaphore chopstick[5]; // Initially all values are 1
>> semaphore grab // initially set to 2
// Pseudo code for Philosopher i:
do {
>>
wait (grab){
wait(chopstick[i]) // grab left chopstick
wait(chopstick[(i+1) % 5]) // right one
>>
} signal(grab)
…
eat
…
signal(chopstick[i]); // put left on table
signal(chopstick[(i+1) % 5]); // put back right
…
think
…
} while (1);
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