Dr. Andrei Grebennikov
(grandrei@ieee.org)
M/A-COM Eurotec Operations
Loughmahon Technology Park, Skehard Road, Blackrock
Cork, Ireland
RF AND MICROWAVE
POWER AMPLIFIER DESIGN
A. Grebennikov, RF and Microwave Power Amplifier Design,
New York: McGraw-Hill, 2004
1
LECTURE 1. NONLINEAR ACTIVE DEVICE MODELING
1.1. Power MOSFETs
- small-signal equivalent circuit and determination of its elements
- nonlinear I-V models
- nonlinear C-V models and charge conservation
1.2. GaAs MESFETs and HEMTs
- small-signal equivalent circuit and determination of its elements
- nonlinear I-V and C-V models
1.3. BJTs and HBTs
- small-signal equivalent circuit and determination
of its elements
- equivalence of  -circuit and T-circuit topologies
- nonlinear I-V and C-Vmodels
2
1.1. Power MOSFETs
Simplified structure of n-channel metal-oxide-silicon (MOS) transistor
Oxide
Gate
Source
n+
Channel
Drain
n+
p substrate
Body
- transistor is formed on p-type silicon body (substrate)
- low-resistivity gate is formed on oxide top
- two heavily doped n regions with low resistivity: source and drain
- region between source and drain is channel characterized by
its length L and width W
3
1.1. Power MOSFETs
n+
Channel
p substrate
Body
•
Operation principle:
Oxide
Gate
Source
Drain
n+
•
if gate potential is made
sufficiently positive with respect
to other part of the structure,
electrons can be attracted
directly below insulator
these electrons can come through n+ regions where they exist in
abundance and can fill channel between them
• number
of electrons in channel can be varied through gate potential
two n+ regions are biased at different potentials, lower-potential
n+ region acts as source for electrons, which then flow through
channel and are drained by higher-potential n+ region
• if
4
1.1. Power MOSFETs
Simplified structure of complimentary CMOS transistor
(local oxidation of silicon)
n+
n+
Oxide
p+
p+
n well
p substrate
- p substrate is common to all nMOS devices and serves as isolation
region between them
- pMOS devices are contained within n-type well regions
- thick oxide is needed to eliminate accident creation of parasitic
channel underneath of it
- sufficient distance between various regions must be maintained to
prevent latchup: elimination bipolar transistor action
5
1.1. Power MOSFETs
Simplified structure of CMOS transistor
(shallow-trench isolation)
Oxide
p+
p+
n+
n+
Oxide
Oxide
- devices are closer to
each other
n well
p substrate
Simplified structure of CMOS transistor
(silicon on insulator)
n+
p
p+
n+
n
p+
Oxide
- complete device isolation
substrate
6
1.1. Power MOSFETs
N-channel MOS transistor under bias in inversion region
+ Vg
Vs = 0 V
+ Vd
Gate
Source
Drain
n+
n+
p substrate
Vb = 0 V
- positive charges applied to gate repel holes from surface 
depletion region with negatively charged acceptors: inversion
- drain potential is positive: larger number of negatively
charged acceptors around drain than source
- fewer electrons are needed in channel near drain to balance
positive gate charge: largest electron concentration near source
7
1.1. Power MOSFETs
N-channel MOS transistor under bias in inversion region
Gate potential is raised  three inversion region:
weak inversion, moderate inversion and strong inversion
Id
Saturation
Nonsaturation
Vth
Vds
• for small Vds, effect of drain potential on drain current is large:
nonsaturation region
• for large Vds, drain current gradually tends to saturate draining all
electrons that can be supplied by channel for given gate potential:
saturation region
8
1.1. Power MOSFETs
Physical structure of lateral diffusion MOS transistor
(LDMOSFET)
Gate
S
n+
Cg
Rch
p+
sinker
p+ threshold adjust
p epitaxial layer
D
n
n+
- heavily doped p+ sinker
for low resistivity
between source and p+
substrate (source
grounding) to provide
high current flow between
drain and source
p+ substrate
- low substrate resistivity and sufficient distance between
regions to prevent latchup (forward-biased p-n diodes): lightly
doped p- epitaxial layer and heavily doped p+ substrate
- lightly doped n- drain layer for drain-source breakdown protection
9
1.1. Power MOSFETs
Gate channel model: bias-dependent RC distributed
transmission line
cosh  L Z 0 sinh  L
ABCD    sinh  L cosh  L 


Z
0


where

  Rch / L
Rch
Z gs  Rch
 Cg
j Rch
- propagation
constant,
- gate charging resistance
per unit length
coth  L Rch

 L
 L
A
coth  L
Z gs   Rch
C
L
 /  - characteristic
Z o  Rch
impedance
Cg  Cg / L - gate capacitance
per unit length
 1
R
 L
1

  ch 

3 
3
j C g
 L
- intrinsic impedance between gate and source
10
1.1. Power MOSFETs
Equivalent circuit of lateral diffusion MOS transistor (LDMOSFET)
Rg
Cgd
d
g
Cgs
Cds
Rds
gm,
Rgs
- intrinsic device model including
nonlinear current source and device
resistances and capacitances
s
Lg
Rge
Rgi
Cgd
intrinsic MOSFET
Rd
Ld
g
d
Rds
Cgs
Rgs
gm,
- complete small-signal
MOSFET equivalent
circuit describing device
electrical behavior over
entire frequency range
up to maximum
frequency
Cds
Cdp
Cgp
Rs
Ls
s
s
11
1.1. Power MOSFETs
Determination of equivalent circuit parameters
To determine intrinsic circuit
parameters, it is best to use Yparameters for intrinsic device:
where
j Cgs



j

C

j

C
gd
gd


1

j

g

Y 
 g m exp  j 




j

C
G

j

C

C
gd
ds
ds
gd 
 1  j 
g


 g  RgsCgs - gate constant ,  - effective channel carrier transit time
For known (measured or analytically estimated) extrinsic parameters, procedure
of determination of intrinsic Y-parameters from experimental data is:
• measurement of S-parameters of extrinsic device
• transformation of S-parameters to Y-parameters with subtraction of
parallel elements: capacitances
• transformation of Y-parameters to Z-parameters with subtraction of
series elements: inductances
• transformation of Z-parameters to Y-parameters of intrinsic device
two-port network
12
1.1. Power MOSFETs
Determination of equivalent circuit parameters
Lg
Rg
Intrinsic
device
g
Rd
Ld
d
Rs
Cgp
- transformation of S-parameters to Yparameters with subtraction of parallel
elements: capacitances
S11 S12 


S21 S22 
Cdp
Ls
Lg
g
Rg
Intrinsic
device
Rd
Intrinsic
device
g
s
s
Ld
s
d
s

Z11  Rg  Rs  j Lg  Ls

Z 21  Rs  j Ls

Rs
Ls
Y12
Y11  j Cgp



Y21
Y22  j Cdp 


Z12  Rs  j Ls


Z 22  Rd  Rs  j Ld  Ls 
- transformation of Z-parameters to Ys
s
d
parameters of intrinsic device two-port
network
- transformation of Y-parameters to Z-parameters with subtraction
of series elements: inductances
13
1.1. Power MOSFETs
Nonlinear I-V models
Ids
Isat
ln Ids
• drain current in weakinversion region is
dominated by diffusion
component - exponential
dependencies
Ipk
ln Ith
Vth
Vgs
To achieve continuous behavior
from weak-inversion region to
strong-inversion region 
To describe drain current in
saturation region 
Entire I-V model 
Vgs
Vpk
• drain current in stronginversion region is
proportional to square of
Vgs - Vth


I ds Vgs   A  ln 1  exp BVgs  Vth 
where
I ds V
gs Vth
I ds
Vgs
 I th
2
 S th
Vg s Vth
I max Vds   I sat 1   Vds  tanh  Vds 
  I
I ds Vgs ,Vds   I o / 1   o
  I max



n



1
n
14
1.1. Power MOSFETs
Nonlinear I-V models
Low voltage MOSFET
(w = 2 mm)
High voltage LDMOSFET
(l = 1.1 um, w = 4 cm)
Ids, A
Ids, mA
modeled
12 V
measured
5.0
10 V
180
modeled
measured
Vgs = 3.6 V
160
140
4.0
8V
120
3.0
6V
2.0
3.1 V
100
2.6 V
80
2.1 V
60
1.6 V
40
1.0
Vgs = 4 V
0
2
4
6
8
10
12
14
16
Mean-square error - 0.5%
18
Vds , V
20
0
1.1 V
1.0
2.0
3.0
Vds, V
4.0
Mean-square error - 0.42%
15
1.1. Power MOSFETs
Nonlinear I-V models: high voltage LDMOSFET
Ids vs Vgs
gm vs Vgs
Ids, A
gm, A/V
Vds = 7 V
Vds = 7 V
5
1.0
4
0.8
3
0.6
empirical model
experiment
two-dimensional model
2
empirical
model
experiment
two-dimensional
model
0.4
0.2
1
0
0
3
5
7
9
11
13
15
5
3
Vgs, V
7
9
11
13
15
Vgs, V
I ds , %
Normalized linear deviation of
Ids vs Vgs
• maximum deviation of
8% in inversion region
8
6
4
2
0
-2
-4
-6
-8
10
4
6
8
12
14
Vgs, V
16
1.1. Power MOSFETs
Nonlinear C-V models
Cgs/Cox
Gate-source capacitance Cgs
• constant in accumulation region equal
1.0
to total intrinsic oxide capacitance
0.8
• reduces in depletion and weak0.6
inversion regions and increases in
moderate inversion region
0.4
• constant in saturation region
0.2
Vs1
0
accumulation
depletion
equal to 2/3 of oxide capacitance
Vs2
weak moderate strong
inversion inversion inversion
Vgs

S

Cgs  Cgsmin  Cs 1  tanh  Vgs  Vs  
 Cs


where
S1 
Cgs
Vgs
Vgs  Vs1
S2 
- hyperbolic function to describe
each part of Cgs (Vgs)
Cgs
Vgs
Vgs  Vs2

S
 
S

Cgs  Cgsmax  Cgso 1  tanh  1 Vgs  Vs1  1  tanh  2 Vgs  Vs2  
 Cs
 
 Cs


- resulting
approximation
17
1.1. Power MOSFETs
Nonlinear C-V models
Gate-drain capacitance Cgd
Drain-source capacitance Cds
Cgd, pF
Cds, pF
8
40
measured
modeled
7
6
measured
35
5
modeled
30
4
25
3
20
2
1
15
0
0
5
10
15
20
25
   Vdso 

C gd(ds)  C gdo(dso)
   Vds 
For LDMOSFETs 
Capacitance
Cgd
Cds
10
0
Vds, V
5
10
15
20
25
Vds, V
m
- junction approximation
where m depends on doping concentration
Cgd(ds)o , pF
7.88
39.42
m
0.8
0.33
, V
2.94
1.0
Mean-square error
- 4.3%
18
1.1. Power MOSFETs
Charge conservation
Ig 
 I   j
 d
 I s 
 Cgg  Cgd  Cgs  Vg 

  

C
C

C
dd
ds   Vd 
 dg
  Csg  Csd Css  Vs 


To transform three-terminal into twoport network with common source
terminal 
Cgg  Cgd  Cgs  Cdg  Csg ,
Cdd  Cdg  Cds  Cgd  Csd ,
Css  Csg  Csd  Cgs  Cds ,
- relationships between capacitances
in three-terminal devices
- matrix equation for small-signal
charging circuit in frequency
domain: three-terminal MOSFET
Ig = Igs, Id = Ids, Is = -(Igs + Ids)
Vg - Vs = Vgs, Vd - Vs = Vds
 j Cgd
 j Cgs  Cgd 

Yc  






j

C

C
j

C

C

C
gd
m
ds
m
gd 

- admittance matrix for capacitive
two-port network
where Cm = Cdg - Cgd is
transcapacitance

  Cm 


1   C m 


where
1
exp  j tan
  g m exp  j c 
 C 



C

 T gs 
 T gs 
 c  Cm /  TCgs
2
g m  j C m  g m
19
1.2. GaAs MESFETs and HEMTs
Simplified structure of GaAs metal-semiconductor
field-effect transistor (MESFET)
Source
Drain
Gate
n
+
n
-
+
- transistor is formed on semiinsulating GaAs substrate
n - epilayer
Semi-insulating GaAs buffer
Semi-insulating GaAs substrate
- n-doped epilayer is necessary to
realize channel and is made
thicker to minimize source and
drain resistances
- two heavily doped n regions with low resistivity between metal
source and drain
- semi-insulating buffer for high resistivity and to prevent impurities
in substrate from diffusing into epilayer
20
1.2. GaAs MESFETs and HEMTs
Operation principle:
Source
Drain
Gate
n+
n+
n- - epilayer
Semi-insulating GaAs buffer
two n+ regions are biased at
different potentials, lower-potential
n+ region acts as source for
electrons, which then flow through
channel and are drained by higherpotential n+ region
• if
Semi-insulating GaAs substrate
• depletion
region under Schottkybarrier gate is formed containing only
positively charged donors
• thickness
of depletion region can be varied through gate
potential resulting in changing of channel conductivity
•
channel current is due to electrons and device operation speed is
defined by only velocity of charge variation under gate
21
1.2. GaAs MESFETs and HEMTs
GaAs MESFET operation
 Vg
Vs = 0 V
n+
+Vd
n+
Id
linear
region
n- - epilayer
Vds
- when Vgs = 0 V and Vds is raised from zero to some low value, depletion
region under gate is relatively narrow with longitudinal electric field and
current in channel where current is proportional to Vds
- when Vgs < 0 V and Vds = const, depletion region widens reducing current
and at some pinch-off voltage channel becomes fully depleted with zero
drain current
22
1.2. GaAs MESFETs and HEMTs
GaAs MESFET operation
 Vg
Vs = 0 V
n+
+Vd
Id
n+
n- - epilayer
Vds
- when Vgs = 0 V and Vds is raised further, channel current
increases; however, depletion region becomes wider at
drain end with narrower conductive channel resulting in
region of electron accumulation near gate end
- for higher Vds, electron cannot move faster as electron
velocity cannot exceed their saturated drift velocity
23
1.2. GaAs MESFETs and HEMTs
GaAs MESFET operation
 Vg
Vs = 0 V
n+
+Vd
n+
Id
saturation
region
n- - epilayer
Vds
- as Vds is increased further, depleted region widens towards
drain and more of voltage increase is dropped across depletion
region (charge domain) whereas less is dropped across
unsaturated region
- saturation occurs when electrons move at saturated drift velocity
over large part of channel length; no longer increase in charge in
depletion region, so gate-drain capacitance reduces to stray
capacitance between metalizations whereas gate-source capacitance
rises to approximately twice compared with value in linear operation
24
1.2. GaAs MESFETs and HEMTs
High mobility electron transistor (HEMT)
Source
Drain
Gate
n+ - GaAs
n+ - AlGaAs
n+ - GaAs
n+ - AlGaAs
- transistor is formed
on semi-insulating
GaAs substrate
n- – InGaAs - epilayer
n+ - AlGaAs
n+ - AlGaAs
Semi-insulating GaAs buffer
Semi-insulating GaAs substrate
- two heavily n-doped
GaAs regions with low
resistivity between
metal source and
drain
- two heavily n-doped AlGaAs layers with high energetic
barrier for holes to maximize high electron mobility in channel
- undoped InGaAs n-epilayer as channel
25
1.2. GaAs MESFETs and HEMTs
HEMT: operation principle
Source
Drain
Gate
n+ - GaAs
n+ - AlGaAs
n+ - GaAs
n+ - AlGaAs
n- – InGaAs - epilayer
n+ - AlGaAs
n+ - AlGaAs
two n+ regions are biased at
different potentials, lowerpotential n+ region acts as source
for electrons, which then flow
through channel and are drained
by higher-potential n+ region
• if
Semi-insulating GaAs buffer
• depletion
Semi-insulating GaAs substrate
region under Schottkybarrier gate is formed containing
only positively charged donors
• two
heavily n-doped AlGaAs layers with high energetic barriers for holes
and low energetic barrier for electrons protect channel from hole injection
resulting in high mobility of electrons in channel (in 3 times higher than
electron saturation velocity in GaAs epilayer)
•
spacing between AlGaAs layer and InGaAs channel is optimized to
achieve high breakdown voltage
26
1.2. GaAs MESFETs and HEMTs
Small-signal equivalent circuit of MESFET and HEMT
Lg
intrinsic
device
Cgd
Rg
Rd
Ld
g
d
Cgs
Rgs
Cdsd
gm, 
Rds
Cgd 
Cds
Rdsd
Cgp
Cdp
Rs
Cgs 
Ls
s
 Qg  Qd 
Vgd
 Qg  Qd 
Vgs
s
- gate-source capacitance Cgs and gate-drain capacitance Cgd represent
charging effect in depletion region; drain-source capacitance Cds is small
and its influence is insignificant
- capacitance Cdsd and resistance Rdsd represent model dispersion of I-V
characteristic due to trapping effects in channel resulting in discrepancy
between DC measurement and S-parameter measurements at high frequencies
27
1.2. GaAs MESFETs and HEMTs
Determination of equivalent circuit parameters
To determine intrinsic circuit
parameters, it is best to use Yparameters for intrinsic device:
where
j Cgs

 j Cgd

1  j g
Y  
 g m exp  j 
 j Cgd
 1  j 
g




1

 j Cds  Cgd 
Rds

 j Cgd
 g  RgsCgs - gate constant ,  - effective channel carrier transit time
From real and imaginary parts of intrinsic Y-parameters:
Cgd  
Rgs 
Im Y12

Cgs
2



Im Y11   Cgd 
Re
Y
11
 
1  
 



Im
Y


C

11
gd  



Re Y11
Im Y11   Cgd 2  Re Y11 2
Rds 
1
Re Y22
gm 

Re Y21 2  Im Y21
Cds 
Im Y22   Cgd

  Cgd   1   Cgs Rgs 
2
1 1    Cgd  Im Y21   Cgs Rgs Re Y21 

sin 

gm


2
28
1.2. GaAs MESFETs and HEMTs
Determination of equivalent circuit parameters
Lg
Rg
Intrinsic
device
g
Ld
Rd
d
Rs
S11 S12 


S21 S22 
Cdp
Cgp
- measurements of
S-parameters of full
equivalent circuit
Ls
s
s
Rg
g
Intrinsic
device
Rd
d
Z12 
Z11  j Lg


Z22  j Ld 
 Z21
Rs
Cdp
Cgp
Ls
s
- transformation of
S-parameters to Zparameters with
subtraction of
series inductances
s
29
1.2. GaAs MESFETs and HEMTs
Determination of equivalent circuit parameters
Rg
g
Rd
Intrinsic
device
d
Y12
Y11  j Cgp



Y21
Y22  j Cdp 

Rs
Ls
s
- transformation of
Z-parameters to Yparameters with
subtraction of
parallel
capacitances
s
g
s
Intrinsic
device
d
s
Z12  Rs  j Ls 
Z11  Rg  Rs  j Ls


 Z21  Rs  j Ls Z22  Rd  Rs  j Ls 
- transformation of Yparameters to Zparameters with
subtraction of series
resistances and
inductance
- transformation of Z-parameters to intrinsic two-port Y-parameters
30
1.2. GaAs MESFETs and HEMTs
Cgd
Nonlinear I-V and C-V models
g
d
Curtice quadratic model
Cgs  Cgs0

Vgs 


/ 1

Vgsi 

Igs
0.5
Ids
Cgs
- abrupt junction
approximation
s
I ds   Vgs  Vp  1   Vds  tanh  Vds 
2
Ids
Id
Saturation
Linear
region
Vp
Vgs
where  - slope in saturation region
Vth
Vds
Vp - pinch-off voltage
 - transconductance parameter defined from experimental data
31
1.2. GaAs MESFETs and HEMTs
Nonlinear I-V and C-V models
Curtice cubic model
Igd
Cgd
g
Igs
Vgs
d
Cgs
Ids
• additional gate-source resistor Rgs
• additional diode between drain
Rgs
and gate
s


I ds  A0  A1Vgs  A2Vgs2  A3Vgs3 tanh  Vds 
Cgs  Cgs0

Vgs 


/ 1

Vgsi 

0.5
- abrupt junction approximation
32
1.2. GaAs MESFETs and HEMTs
Nonlinear I-V and C-V models
2
Materka model
I ds
Igd
Cgd
g
Igs
Vgs
d
Cgs

  Vds 
Vgs 



 I dss 1 
tanh 

V  V 
Vp 
p 

 gs

exp 
I gd  I gdsr
Ids

I gs  I gss exp  s Vgs   1
Rgs
Cgs  Cgs0
s
sr

Vgd   1

Vgs 

/ 1 

Vgsi 

0.5
TriQuint model
I ds 
I ds0
I ds0
,
1   Vds I ds0
3




V
3


Q
ds
  Vgs  VT  1  1 
  , 0  Vds 

3  


 

3
Q




V

V
,
V

gs
T
ds


• better approximation at
near pinch-off region
• decrease of drain current Ids
at higher values which is
result of self-heating effect
33
1.2. GaAs MESFETs and HEMTs
Nonlinear I-V and C-V models
I ds  I pk 1  tanh  1   Vds  tanh  Vds 
Angelov model
Igd
where Ipk - drain current at maximum transconductance
Cgd
g
Vgs
Igs
d
Cgs
Ids
Rgs
  P1 Vgs  Vpk   P2 Vgs  Vpk 2  P3 Vgs  Vpk 3  ...
where Pi can be obtained from experimental data
Ids
Isat
s
Accurate description
of Ids-Vgs dependence
in pinch-off and
Ipk
saturation regions
Cgs/Cgs0
2.0
Cgd/Cgd0
Cgs/Cgs0
1.5
1.0
Cgd/Cgd0
0
-1
0
1
2

1 
3
Vds, V
Cgd  Cgd0
tanh P1gdg Vgs
Vpk
1  tanh P1gsd Vds


1  tanh P
Cgs  Cgs0 1  tanh P1gsg Vgs 
0.5
where P1gsg, P1gsd, P1gdg, P1gdd are fitting parameters
1gdd
Vgs


Vds  P1ccVgsVgd 
34
1.3. BJTs and HBTs
Simplified structures of n-p-n bipolar-junction transistor (BJT)
BJT for integrated circuit made by planar process
Emitter
Base
n+
Collector
n+
p
nn+ buried layer
p- substrate
- heavily doped n-region is
diffused into p-region to
produce emitter-base junction
- lightly doped p-type layer
is used for substrate
- lightly n-doped collector region allows collector-base junction to
sustain relatively high voltages without breaking down
- heavily n-doped buried layer added to reduce series resistance
between junction and metallic collector contact
- base doping level and its width is quite small to minimize base
transit time and maximize electron injection efficiency from emitter
35
1.3. BJTs and HBTs
Simplified structures of n-p-n bipolar-junction transistor (BJT)
Base
BJT for power
application
p
Base
Emitter
p+
n+
p+
n- collector
n+ collector
Collector
isolating BeO heatsink
- for constant base-emitter bias, increase in collector-base voltage widens
collector-base space-charge layer, thus reducing base width resulting in
collector current increase when collector voltage is increased ( Early effect)
- for constant collector voltage, effect of high injection results in widening
of charge-neutral base region when entire space-charge region is pushed
toward heavily doped collector region decreasing transistor current gain
and degrades device frequency response ( Kirk effect)
36
1.3. BJTs and HBTs
Simplified structures of n-p-n heterojunction bipolar transistor (HBT)
AlGaAs HBT for integrated circuit made by planar process
Base
Collector
Emitter
n -AlGaAs
Base
p+-GaAs
n- - GaAs
n+ - GaAs
Semi-insulating GaAs substrate
substrate
- forward-bias emitter injection
efficiency is very high since wider
bandgap AlGaAs emitter injects
electrons into GaAs p-base at lower
energy level, but holes are
prevented from flowing into emitter
by high energy barrier, thus
resulting in possibility to decrease
base length, base-width modulation
and increase frequency response
- heavily p-doped base to reduce base resistance
- lightly n-doped emitter to minimize emitter capacitance
- lightly n-doped collector region allows collector-base junction to
sustain relatively high voltages without breaking down
37
1.3. BJTs and HBTs
Simplified structures of n-p-n heterojunction bipolar transistor (HBT)
Single-chip
AlGaAs/GaAs HBT
Base
Emitter
Base
p+
n - AlGaAs
p+
p - GaAs
n- - GaAs
n+ - GaAs
Collector
- lower 1/f noise since surface states of GaAs no longer contribute
significant noise to emitter current
- using wide bandgap InGaP layer instead of AlGaAs results in
improvement of device performance over temperature
38
1.3. BJTs and HBTs
Small-signal equivalent -circuit of bipolar transistor
Cpbc
Lb
Rb
Cco
Rc
rb
Lc
c
b
+
V
Cci
r
rce
C

gmV
Cpbe
Intrinsic device
Cpce
Re
Le
e
e
- intrinsic dynamic resistance r and charging capacitance C represent baseemitter diode p-n junction
- feedback capacitance Cco is extrinsic and capacitance Cci is intrinsic representing
base-collector junction capacitance having significant effect on device performance
- intrinsic collector-emitter resistance rce models Early effect
39
1.3. BJTs and HBTs
Determination of equivalent circuit parameters
To determine intrinsic
circuit parameters, it is best
to use Y-parameters for
intrinsic device:
Y11 
1
 j C  Cci 
r
Y12   j Cci
Y21  g mexp -j    j Cci
Y22 
1
 j Cci
rce
where  - effective transit time
From real and imaginary parts of intrinsic Y-parameters:
C 
Im Y11  Y12 

 
gm 
Re Y21 
2
1

cos 1
r 
1
Re Y11
Cci  
Im Y12

Re Y21  Re Y12
Re Y21 2
 Im Y21  Im Y12 
2
 Im Y21  ImY12 
2
rce 
1
Re Y22
40
1.3. BJTs and HBTs
Small-signal equivalent T-circuit of bipolar transistor
Cpbc
Cco
rbc
Lb
Rb
Cci
rb
b
Rc
Lc
c
 Ie
Ce
re
Intrinsic device
Cpbe
Cpce
Re
Ie
Le
e
e
- intrinsic dynamic resistance re and charging capacitance Ce represent
base-emitter diode p-n junction
-  is collector-to-emitter current gain
- intrinsic collector-emitter resistance rbc models Early effect
41
1.3. BJTs and HBTs
Equivalence of intrinsic  - and T-circuit topologies
c
b
+
V
r
c
b
+

C
Vbe

Ce

e
e
 exp(-jtee)Ie
Ie
gm exp(-j)V
Ye 
re
e
Ie
1
1

 j C e 
 j C  g m exp  j   - equal admittances
Vbe
re
r
 exp  j tee  I e  g m exp  j  V - equal collector currents where    0 /1  j 
Relationships between circuit intrinsic parameters:
g m   0 1 / re    Ce  / 1    
2
    tee 

tan

1
2
1
 Ce re  
2

tan 1   
1
1

 g m cos  
r
re
sin   
C  Ce  g m

42
1.3. BJTs and HBTs
Ebers-Moll model
Nonlinear I-V and C-V models
I ce
I be 
VT 

I sat   Vbc 


exp

1


 R   VT 

- base-collector diode current
where R - reverse current gain
Ic
Ibc
Rc
Cbc
c
Rb +

Ice
C
V
Cs
Ibe

I sat   V 


exp

1

 - base-emitter diode current
 F   VT 

Cbe

Vbc
b
kT
- thermal voltage
q
where F - forward current gain
I bc 
Ib
 V 
 V 
 I sat exp     exp  bc 
 VT 
  VT 
where
+
Re
Ie
e

dI
V 
  F be  C jeo 1   
dV
e 

 me
- base-emitter diode
capacitance
 mc

dI
V 
Cbc   R bc  C jco 1  bc  - base-collector diode
capacitance
dVbc
c 

where F - forward transit time, R - reverse
transit time, me and mc - grading factors
43
1.3. BJTs and HBTs
Cco
Gummel-Poon model
+
Nonlinear I-V model
Ib
Ic
rb
I ce
I
 ss
qb
  V 
 Vbc 




exp

exp
 

 nR VT 
  nF VT 

Vbc
Cci
b
c
Rb
where nF - forward current emission coefficient,
nR - reverse current emission coefficient, qb variable model parameter (Early and Kirk effects)
Rc
+
V
Ice
C
Cs

Re
Ie
e
I be

  V 

I sat 0   V 





 1  C2 I sat 0exp 
 1
exp 


 FM 0   nF VT 

  nELVT 

- base-emitter
diode current
I bc
  Vbc 


I sat 0   Vbc 





 1  C4 I sat 0exp 
exp
  1
 RM 0   nR VT 
n
V

  CL T 

- base-collector
diode current
where C2, C4,nEL, nCL - model parameters responsible for low-current effects
44
1.3. BJTs and HBTs
Gummel-Poon model
Base resistance model
rb  rbm  3rb0
tan z  z
 rbm 
z tan 2 z
where z - current-dependent
model parameter
Model advantages:
- base-width modulation (Early effect)
- variation of forward current gain F
with collector current (Kirk effect)
- better approximation of distributed
structure of base-collector junction (base
resistance between two capacitances)
- variation of base resistance with
base current
Nonlinear C-V models

I cc 
V 
d 




C 
 FF   C jeo 1 

dV 
qb 
e 

 me
- base-emitter diode capacitance, FF
- current-dependent transit time
Cci   R
dI bc
dVbc

Vbc 

 kcC jco 1 
c 

 mc
- base-collector diode capacitance

V 
Cco  C jco 1  kc  1  bco 
c 

 mc
- junction capacitance, kc - fraction
of base-collector capacitance
connected to base resistance
45