Supplemental Material for
Hysteretic Response of Chemical Vapor Deposition Graphene Field Effect
Transistors on SiC Substrates
Edward Cazalas,1,a) Isaac Childres,2,3 Amanda Majcher,1 Ting-Fung
Chung,2 Yong P. Chen,2,3,4 and Igor Jovanovic1
1
Department of Mechanical and Nuclear Engineering, The Pennsylvania State University,
University Park, PA 16802, USA
2
Department of Physics, Purdue University, West Lafayette, IN 47907, USA
3
Birck Nanotechnology Center, Purdue University, West Lafayette, IN 47907, USA
4
School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907,
USA
The graphene was grown on a Cu foil through the decomposition of CH4 in a
furnace at 1000 ˚C, leading to carbon deposition and graphene formation. A PMMA film
was spun-coat on graphene/Cu substrate to protect the graphene on one side. The reverse
side (without PMMA) of Cu was removed by plasma etching followed by overnight
etching with ~0.1 g/ml iron (III) chloride aqueous solution. The transparent PMMAgraphene membrane was scooped out from the surface of etchant solution and was rinsed
in de-ionized water several times and diluted hydrochloric acid (<5% in de-ionized water)
to reduce the residual etchant. Finally, the membrane was cleaned in de-ionized water
again before being placed on a SiC substrate. Graphene field-effect devices were
fabricated using electron-beam lithography. The electrical contacts (5 nm-thick
a)
Electronic mail: ejc149@psu.edu
chromium and 35 nm-thick gold) were fabricated by electron-beam evaporation. A figure
of the graphene’s dimension is given in Figure S1.
S
1 µm
4 µm
D
FIG. S1. (color online) SiC GFET as viewed from top. Shown is the contact array
composed of gold electrodes with source (S) and drain (D) indicated. The graphene
region used during experiment is enclosed by the dotted box, representing a graphene
area of 4 μm2.
Graphene measurements have been conducted at room temperature in ambient air
by 2-point resistance measurement. 4-point measurements of graphene reveal that contact
resistance was small compared to the resistance of graphene samples. An Ametek Model
7270 lock-in amplifier was used to apply the source-drain voltage and measure the
source-drain current passing through graphene. The current is then converted to resistance
for analysis. A Keithley Model 2400 source meter was used to apply voltage between the
gold backgate and graphene and measures the leakage current. The data acquisition
system was controlled by a customized LabView code, which also controls
instrumentation. A cross section of a GFET device along with the electrical setup is given
in Figure S2.
Vsd
Isd
Graphene
Semiconductor – SiC
Backgate – Au
1 atom
300 µm
Vbg
40 nm
FIG. S2. (color online) Cross section of our GFET design is shown with graphene on a
semiconductor (SiC) substrate with ohmic electrodes and backgate. Graphene current, Isd,
is monitored in response to a change in backgate voltage, Vbg, with a voltage, Vsd, applied
across graphene.