Final Presentation
Winter 2009/2010
High Speed Digital Systems Lab
Spring 2008
Students:
Jenia Kuksin
Alexander Milys
Instructor:
Yossi Hipsh
Content


Project Objectives
Project Description
 Block
Diagram
 Elecrical Scheme

PCB Design
 Stackup
 Simulation

PCB Assembly
 Bugs


and fixing
Measurements
Design Proposals
Project Objectives
Designing High Speed Transmission Line
Board which will provide an ideal vehicle for
learning about Signal Integrity issues like:
• Reflections in Transmission Lines
• Cross Talk in Transmission Lines
• Jitter
• Skew
Project Description
The purpose of the board is to provide the ideal vehicle for High Speed
Phenomena Experiment in High Speed Digital Labaratory.
It uses the high speed generarator to expose students to a wide range
of SI phenomena as Reflections and Cross Talk in Transmission Lines,
Jitter and Skew .
Experiment Environment
Controller
Instructor
Switching System
Transmission
Lines Array
Student
Block Diagram
Controller
S0
0narrow pulse
1wide pulse
S1
Will be OE
for splitters
Pulser
1
Signal
Splitter
S2
Connects
One channel from 36
To scope
Analog
Switches
Z(Source)
36
36
Analog
Switches
Transmission
Lines
36 lines
36
S5
Control for MCP195
(jitter)
S3
Connects
One channel from 36
To scope
Termination
Z(Load)
Description of Main Blocks



Pulser - creates short (0.5-1 nsec) and long (10-13
nsec) pulse signal with very low rise/fall time (200ps)
.
Signal Splitter – launching a signal into a
transmission line and converts differential signal to
single ended while only one line can be alive at the
same time
Analog Switches – transmit the measured voltage
signal on input/output of selected transmission line to
oscilloscope.

Transmission Lines – will contain 36 microstrip,
single ended transmission lines with different
terminations.

Controller – Based on Altera DE2 Board, controls
all of the operation of the High Speed Transmission
Line Board.
PCB Design







8 layers, 25x30cm board dimensions.
High speed data lines, microstrip and stripline formats.
Rise time of signals range from 150ps to 300ps.
Pre and post layout simulations are required.
Multiple onboard power supplies – many local power
planes.
Many identical hierarchical blocks on a schematics
require efficient layout reuse.
Design is completed in OrCAD PCB Editor
Layout Stackup
Total Thickness 101.8 mil
Top Layer
Microstrip Lines
Second Layer
GND Plane
•Support for microstrip lines from
top layer.
•Support for Striplines from third
layer
Third Layer
Striplines and power plane
Forth Layer
GND Plane and Power Planes
Support for Striplines from third
layer
Fifth Layer
GND plane
Support for Striplines from six layer
Six Layer
Striplines
Seven Layer
GND Plane and Power Planes
Bottom Layer
Microstrip Lines
Design File: 1.ffs
HyperLynx LineSim V7.7
Pre Layout Simulation
Circuit In HyperLynx
Vt1
1.3V
R12
Simulation of Microstrip Lines
without Amplifier
Driver: MC100LVEP111
IBIS Model for MC100LVEP111FA
3.3V was downloaded from ON
Semiconductor site
23.0 ohms
R13
C4
32.0 ohms
2.9 nF
R21
17.0 ohms
R9
292.0 ohms
TL6
R24
49.3 ohms
502.710 ps
8.500 cm
Coupled Stackup
292.0 ohms
TL8
32.0 ohms
U5
1
2
MC100LVEP111FA...
Q0
48.7 ohms
499.974 ps
8.500 cm
Coupled Stackup
C2
R16
TL9
10.0 nF
75.0 ohms
Load: 250 Ω
For the sake of observing
reflections.
R23
R20
150.0 ohms
48.6 ohms
499.968 ps
8.500 cm
Coupled Stackup
TL10
Vt1
1.3V
48.6 ohms
500.399 ps
8.500 cm
Coupled Stackup
TL13
48.6 ohms
499.968 ps
8.500 cm
Coupled Stackup
TL14
48.7 ohms
499.974 ps
8.500 cm
Coupled Stackup
TL15
49.3 ohms
502.710 ps
8.500 cm
Coupled Stackup
R22
250.0 ohms
Pre Layout Simulation
results In HyperLynx
For getting clean output signal
without interference necessary to
get over crosstalk between
microstrip line folds.
In order to determine the optimal
spacing between microstrip line
folds the simulation accomplished
with several values 203um, 600um,
800um and 1000um.
Desired Signal Without coupling effect
203um spacing
600um spacing
OSCILLOSCOPE
OSCILLOSCOPE
Design file: 1.FFS
Design file: 1.FFS
Designer: High Speed Digital S
HyperLynx V7.7
V
V
V
V
200.00
Designer: High Speed Digital S
HyperLynx V7.7
V
V
V
V
[U5.2 (at pin)]
[U5.1 (at pin)]
[R22.1 (at pin)]
[R24.1 (at pin)]
[U5.2 (at pin)]
[U5.1 (at pin)]
[R22.1 (at pin)]
[R24.1 (at pin)]
150.00
150.00
100.00
100.00
50.00
50.00
0.00
V ol t ag e -mV -
V ol t ag e -mV -
0.00
-50.00
-50.00
-100.00
-100.00
-150.00
-150.00
-200.00
-200.00
-250.00
-300.00
-250.00
870.000
1710.00
1720.00
1730.00
1740.00
1750.00
1760.00
Time (ns)
1770.00
1780.00
1790.00
875.000
885.000
890.000
895.000
Time (ns)
900.000
905.000
910.000
915.000
Date: Tuesday Jun. 30, 2009 Time: 13:36:45
Show Latest Waveform = YES, Show Previous Waveform = YES
800um spacing
1000um spacing
Date: Tuesday Jun. 30, 2009 Time: 13:30:34
Show Latest Waveform = YES, Show Previous Waveform = YES
OSCILLOSCOPE
Design file: 1.FFS
880.000
1800.00
OSCILLOSCOPE
Designer: High Speed Digital S
HyperLynx V7.7
Design file: 1.FFS
V
V
V
V
150.00
Designer: High Speed Digital S
HyperLynx V7.7
[U5.2 (at pin)]
[U5.1 (at pin)]
[R22.1 (at pin)]
[R24.1 (at pin)]
V
V
V
V
150.00
100.00
100.00
50.00
50.00
0.00
0.00
V ol t ag e -mV -
V ol t ag e -mV -
-50.00
-100.00
-50.00
-100.00
-150.00
-150.00
-200.00
-200.00
-250.00
-250.00
-300.00
910.000
915.000
920.000
925.000
930.000
935.000
Time (ns)
940.000
945.000
Date: Tuesday Jun. 30, 2009 Time: 13:40:38
Show Latest Waveform = YES, Show Previous Waveform = YES
950.000
955.000
-300.00
850.000
855.000
860.000
865.000
870.000
Time (ns)
875.000
880.000
Date: Tuesday Jun. 30, 2009 Time: 13:58:24
Show Latest Waveform = YES, Show Previous Waveform = YES
885.000
890.000
[U5.2 (at pin)]
[U5.1 (at pin)]
[R22.1 (at pin)]
[R24.1 (at pin)]
From simulation results it is clear that optimal spacing between
microstrip line folds is 800 um since no noticeable
improvements were seen when increasing to 1000um.
OrCAD SigXplorer Simulation
Unmatched source termination
 Rsource =15Ω Rload =20Ω
 Rsource =15Ω Rload =50Ω
 Rsource =15Ω Rload =250Ω
Matched source termination
 Rsource =50Ω Rload =20Ω
 Rsource =50Ω Rload =50Ω
 Rsource =50Ω Rload =250Ω
Unmatched source termination
 Rsource =100Ω Rload =20Ω
 Rsource =100Ω Rload =50Ω
 Rsource =100Ω Rload =250Ω

Crasstalk
10mil space
Unmatched source termination
Rsource =15Ω
Unmatched source termination
Rsource =100Ω
Matched source termination
Rsource =50Ω
Rsource =15Ω Rload =20Ω
Manufactured PCB
Top and Bottom
Top
Bottom
PCB Assembly
Working hard
Component soldering
Bugs and repairs



Voltage regulator U40 (TPS76650) is replaced with two
diodes 1N0007 in parallel after the short circuit current
appeared and voltage dropped below 5V. Apparently
because of excessive turn on current need by SP6T
switches.
LE Input (pin 1) of U36 and U37 (4 to 16 line decoder
74HCT4515) was connected to 5V because when LE is
high the selected output is determined by the data on An.
The termination resistors are added to U22
(MC100EP195) in pin 4 and 5 as described in datasheet.
Termination Voltage Vt bug

Voltage regulator for 1.3V was detected as not
properly working due to high output currents
from PECL outputs that incoming to voltage
regulator output and caused it to stop working.
The solution was to remove the voltage
regulator from the board and connect to the VT
current source or power resistor which constrain
voltage of 1.3V.
Problem description
Vt is the biasing voltage for output stage of PECL circuit.
As can be seen, for Biasing condition of output drivers , it will be necessary to
source current out of the PECL circuit.
This will set a constrain on the power supply that can be connected to the Vtt
pin.
Why simple (Linear) Voltage Regulator
Cannot be used as Vtt supply.
Voltage Regulator (Linear)
I
Linear (non switching) regulator is always sourcing current  it will not be
able to provide appropriate current direction for PECL output stage biasing.
In order to provide Vtt we need to use regulator with Push-Pull stage,
Negative configuration of linear regulator or dynamic current source with
constant voltage drop.
In order to check the Vtt generation we will use the last option.
Solution for Vt
OP1 : LM741 may be used (or any other)
Bias LM741 with +/-10v.
Latter we will use better opamp with
higher output swing and single supply
operation.
Q1 must be with IDmax>2A
If mosfet is not available. BJT might be used ,
but because of limited output current sourcing
of the opamp and a power BJT low current gain.
We will need to connect two BJTs in darlington
configuration , for achieving higher total current
amplification.
Vdd
R1
OP1
The feedback has to be connected to positive input
because of the additional 180deg phase shift caused
by the Q1.
Q1
+
R2
R1/R2 = (Vdd/1.3)-1
R1+R2 >1K
Calculate it according resistor availability
Final board measurements
Measurements were accomplished with 1156A Active Probe, 1.5 GHz
Signal creation chain
OSC
One
Shot
CMOS to
ECL
And
Output
Differentiator
CM
DM
Rise/fall times = 200ps
Rise/fall times = 200ps
DM
CM
One Shot : T=20.11ns, Ton=9.11ns
50 to 50 measurement Narrow
Probe A
50ohm
Zo = 50 ohm
Start X
50ohm
Amp
6dB
Att.
Probe B
End X
Test= 3.844-(8.28-7.422)=2.9ns
Rise and fall time from 20% to 80%.
Tfall (SX) = 266ps
Trise (SX) = 400ps
Tfall (EX) = 300ps
Trise (EX) = 496ps
7.422ns
8.28ns
3.844ns
2v
2.94ns
End X
Probe B
Probe A
Start X
Tfall (PA) = 208ps
Trise (PA) = 232ps
Tfall (PB) = 312ps
Trise (PB) = 328ps
50 to 0 measurement Narrow
Probe A
50ohm
Zo = 50 ohm
Start X
1 ohm
Amp
6dB
Att.
Probe B
End X
Scale factor of StartX and EndX is ~10
Scale factor of StartX and ProbeA is ~10
Tfall (SX) = 232ps
Trise (SX) = 322ps
Tfall (SXsecond) = 433ps
Trise (SXsecond) = 496ps
7.55ns
Tfall (PA) = 229ps
Trise (PA) = 275ps
Tfall (PAsecond) = 322ps
Trise (PAsecond) = 455ps
7.68ns
7.24ns
7.63ns
Probe B
End X
Start X
Probe A
50 to 0 measurement Wide
Start X
Probe A
7.55ns
End X
Probe B
403mv
7.533ns 3.76ns
1.08mv
22.4mv
8.8mv
15 to 1 measurements
281mv
103mv
2.3mv
6.2mv
Scale factor of StartX and EndX is ~10
Scale factor of StartX and ProbeA is ~10
Probe B
3.766ns
3.711ns
Tfall = 222ps
Trise = 366ps
End X
Probe A
972mv
18.9mv
Start X
50 to 100nH measurements Narrow
Tfall (SX) = 244ps
Tfall (EX) = 333ps
Tfall (PA) = 222ps
Trise (PA) = 244ps

3.82ns
Probe A
Start X
3.83ns
Probe B
3.42ns
End X
t (t2  t1 )
1.31n

 1.89
 V2 
 1.1 
ln 
ln  

 0.55 
 V1 
L  R  1.89*50  94nH
50 to 100nH measurements Wide
Probe A
Probe B
End X
Start X
50 to 100pF measurements Narrow
Tfall (SX) = 222ps
Tfall (SX) = 244ps
Tfall (PA) = 246ps
Trise (PA) = 265ps
7.511ns  3.75ns
3.644ns

t (t2  t1 )
2.0667 ns

 5.31ns
 V2 
 143mv 
ln 
ln  

 211mv 
 V1 
C   / R  5.31/ 50  106 pF
50 to 100pF measurements Wide
Probe A
50ohm
Zo = 50 ohm
Start X

t (t2  t1 )
1.67 ns

 6.35ns
 V2 
 123mv 
ln 
ln  

 173mv 
 V1 
C   / R  6.35 / 50  127 pF
100pF
Amp
PECL
6dB
Att.
Probe B
End X
Design Proposals






Change to switching power supply
Add push-pull stage on Vt voltage
Change to balanced transformer to converting signals to
single ended.
Add microcontroller on board with RS232/USB interface
to PC and control everything this way.
Put sensing to crosstalk input Aggressor line.
Several lines can be driven from one source (one AMP)
using analog mux to direct the power.
New available module for Differential to Single ended conversion
New high frequency transformers allow to convert signal from differential
to single ended in a single stage without use of amplifier.
VCC_CIRCLE
VCC_CIRCLE
R3
1k
R2
1k
Q1
Q2
Q3
QbreakN
QbreakN
QbreakN
Q4
QbreakN
TX1
Vtt
Q5
QbreakN
R6
1k
PECL
0
At the design stage, transformers with proper BW
was not available.

We want to thank everyone for helping in
our project.
 Yossi
Hipsh
 Eli Shoshan
 Mony Orbach
 Ela Gluzman
 Ina Rivkin
The End