Design
Methodologies
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
The Design Problem
Source: sematech97
A growing gap between design complexity and design productivity
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Design Methodology
• Design process traverses iteratively between three abstractions:
behavior, structure, and geometry
• More and more automation for each of these steps
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Design Analysis and Verification



Accounts for largest fraction of design time
More efficient when done at higher levels of
abstraction - selection of correct analysis
level can account for multiple orders of
magnitude in verification time
Two major approaches:
» Simulation
» Verification
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Digital Data treated as Analog Signal
VD D
Sp
Vin
Vou t
5.0
Gn ,p
In
D n,p
Out
Vo ut (V)
Bp
3.0
tpHL
1.0
Bn
Sn
–1.0
0
0.5
1
1.5
2
t (nsec)
Circuit Simulation
Both Time and Data treated as Analog Quantities
Also complicated by presence of non-linear elements
(relaxed in timing simulation)
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Representing Data as Discrete Entity
V
0
1
VDD
0
VM
Rp
t1
t
t2
CL
Discretizing the data using
switching threshold
Rn
The linear switch model
of the inverter
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Circuit versus Switch-Level Simulation
5.0
CIN
OUT[2]
Circuit
3.0
OUT[3]
1.0
–1.0
0
5
10
15
20
Switch
time (nsec)
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Structural Description of Accumulator
entity accumulator is
port ( -- definition of input and output terminals
DI: in bit_vector(15 downto 0) -- a vector of 16 bit wide
DO: inout bit_vector(15 downto 0);
CLK: in bit
);
end accumulator;
architecture structure of accumulator is
component reg -- definition of register ports
port (
DI : in bit_vector(15 downto 0);
DO : out bit_vector(15 downto 0);
CLK : in bit
);
end component;
component add -- definition of adder ports
port (
IN0 : in bit_vector(15 downto 0);
IN1 : in bit_vector(15 downto 0);
OUT0 : out bit_vector(15 downto 0)
);
end component;
-- definition of accumulator structure
signal X : bit_vector(15 downto 0);
begin
add1 : add
port map (DI, DO, X); -- defines port connectivity
reg1 : reg
port map (X, DO, CLK);
end structure;
Digital Integrated Circuits
Design defined as composition of
register and full-adder cells (“netlist”)
Data represented as {0,1,Z}
Time discretized and progresses with
unit steps
Description language: VHDL
Other options: schematics, Verilog
Design Methodologies
© Prentice Hall 1995
Behavioral Description of Accumulator
entity accumulator is
port (
DI : in integer;
DO : inout integer := 0;
CLK : in bit
);
end accumulator;
architecture behavior of accumulator is
begin
process(CLK)
variable X : integer := 0; -- intermediate variable
begin
if CLK = '1' then
X < = DO + D1;
DO <= X;
end if;
end process;
end behavior;
Digital Integrated Circuits
Design described as set of input-output
relations, regardless of chosen
implementation
Data described at higher abstraction
level (“integer”)
Design Methodologies
© Prentice Hall 1995
Behavioral simulation of accumulator
Discrete time
Integer data
(Synopsys Waves display tool)
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Timing Verification
Critical path
Enumerates and rank
orders critical timing paths
No simulation needed!
(Synopsys-Epic Pathmill)
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Issues in Timing Verification
In
4-bit adder
MUX
Out
False Timing Paths
Digital Integrated Circuits
Design Methodologies
bypass
© Prentice Hall 1995
Implementation Methodologies
Digital Circuit Implementation Approaches
Semi-custom
Custom
Cell-Based
Standard Cells
Compiled Cells
Digital Integrated Circuits
Macro Cells
Design Methodologies
Array-Based
Pre-diffused
(Gate Arrays)
Pre-wired
(FPGA)
© Prentice Hall 1995
Custom Design –
Layout Editor
Magic Layout Editor
(UC Berkeley)
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Symbolic Layout
VDD
3
Out
In
1
• Dimensionless layout entities
• Only topology is important
• Final layout generated by
“compaction” program
GND
Stick diagram of inverter
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Cell-based Design (or standard cells)
Rows of Cells
Feedthrough Cell
Digital Integrated Circuits
Logic Cell
Routing
Channel
Functional
Module
(RAM,
multiplier, )
Design Methodologies
Routing channel
requirements are
reduced by presence
of more interconnect
layers
© Prentice Hall 1995
Standard Cell — Example
[Brodersen92]
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Standard Cell - Example
3-input NAND cell
(from Mississippi State Library)
characterized for fanout of 4 and
for three different technologies
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Automatic Cell Generation
Random-logic layout
generated by CLEO
cell compiler (Digital)
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Module Generators —
Compiled Datapath
buffer
adder
reg1
reg0
bus2
mux
bus0
bus1
routing area
feed-through
bit-slice
Advantages: One-dimensional placement/routing problem
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Macrocell Design Methodology
Macrocell
Interconnect Bus
Floorplan:
Defines overall
topology of design,
relative placement of
modules, and global
routes of busses,
supplies, and clocks
Digital Integrated Circuits
Routing Channel
Design Methodologies
© Prentice Hall 1995
Macrocell-Based Design
Example
SRAM
SRAM
Data paths
Standard cells
Video-encoder chip
[Brodersen92]
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Gate Array — Sea-of-gates
polysilicon
VD D
rows of
uncommitted
cells
metal
possible
contact
GND
In1 In 2
Uncommited
Cell
In3 In4
routing
channel
Committed
Cell
(4-input NOR)
Out
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Sea-of-gate Primitive Cells
Oxide-isolation
PMOS
PMOS
NMOS
NMOS
NMOS
Using oxide-isolation
Digital Integrated Circuits
Using gate-isolation
Design Methodologies
© Prentice Hall 1995
Sea-of-gates
Random Logic
Memory
Subsystem
LSI Logic LEA300K
(0.6 mm CMOS)
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Prewired Arrays
Categories of prewired arrays (or fieldprogrammable devices):
 Fuse-based (program-once)
 Non-volatile EPROM based
 RAM based
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Programmable Logic Devices
PLA
Digital Integrated Circuits
PROM
Design Methodologies
PAL
© Prentice Hall 1995
EPLD Block Diagram
Macrocell
Primary inputs
Courtesy Altera Corp.
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Field-Programmable Gate Arrays
Fuse-based
I/O Buffers
Program/Test/Diagnostics
Vertical routes
I/O Buffers
I/O Buffers
Standard-cell like
floorplan
Rows of logic modules
Routing channels
I/O Buffers
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Interconnect
Programmed interconnection
Input/output pin
Cell
Antifuse
Horizontal
tracks
Vertical tracks
Digital Integrated Circuits
Programming interconnect using anti-fuses
Design Methodologies
© Prentice Hall 1995
Field-Programmable Gate Arrays
RAM-based
CLB
CLB
switching matrix
Horizontal
routing
channel
Interconnect point
CLB
CLB
Vertical routing channel
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
RAM-based FPGA
Basic Cell (CLB)
Combinational logic
Storage elements
R
A
B/Q1/Q2
Any function of up to
4 variables
C/Q1/Q2
Din
R
F
F
G
CE
D
A
B/Q1/Q2
D Q1
Any function of up to
4 variables
R
G
C/Q1/Q2
F
D
G
E
F
D Q2
CE
G
Clock
CE
Courtesy of Xilinx
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
RAM-based FPGA
Xilinx XC4025
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Taxonomy of Synthesis Tasks
Structural View
Behavioral View
Architectural Level
Logic Level
Circuit Level
state
a
b
0
(i: 1..16) ::
sum = sum*z–1 +
coeff[i]*In*z–1
2
1
3
Logic
Synthesis
Architecture
Synthesis
4
fsm
c
*
Digital Integrated Circuits
Circuit
Synthesis
a
b
mem
x
c
tp
x
D
Design Methodologies
a
2
b
2
1
c
© Prentice Hall 1995
Design
for Test
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Validation and Test of
Manufactured Circuits
Goals of Design-for-Test (DFT)
Make testing of manufactured part swift and
comprehensive
DFT Mantra
Provide controllability and observability
Components of DFT strategy
• Provide circuitry to enable test
• Provide test patterns that guarantee reasonable
coverage
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Test Classification

Diagnostic test
» used in chip/board debugging
» defect localization

“go/no go” or production test
» Used in chip production

Parametric test
» x e [v,i] versus x e [0,1]
» check parameters such as NM, Vt, tp, T
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Design for Testability
N inputs
N inputs
Combinational
K outputs
Combinational
K outputs
Logic
Logic
Module
Module
M state regs
(a) Combinational function
(b) Sequential engine
2N patterns
2N+M patterns
Exhaustive test is impossible or unpractical
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Problem:
Controllability/Observability

Combinational Circuits:
controllable and observable - relatively easy to
determine test patterns

Sequential Circuits: State!
Turn into combinational circuits or use self-test

Memory: requires complex patterns
Use self-test
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Test Approaches
Ad-hoc testing
 Scan-based Test
 Self-Test
Problem is getting harder

» increasing complexity and heterogeneous
combination of modules in system-on-a-chip.
» Advanced packaging and assembly techniques
extend problem to the board level
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Generating and Validating
Test-Vectors

Automatic test-pattern generation (ATPG)
» for given fault, determine excitation vector (called test vector)
that will propagate error to primary (observable) output
» majority of available tools: combinational networks only
» sequential ATPG available from academic research

Fault simulation
» determines test coverage of proposed test-vector set
» simulates correct network in parallel with faulty networks

Both require adequate models of faults in
CMOS integrated circuits
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Fault Models
Most Popular - “Stuck - at” model
sa0
(output)
0
1
sa1
(input)
Covers almost all (other)
occurring faults, such as
opens and shorts.
Z
x1


x2
Digital Integrated Circuits

Design Methodologies
x3
,  : x1 sa1
 : x1 sa0 or
x2 sa0
 : Z sa1
© Prentice Hall 1995
Problem with stuck-at model:
CMOS open fault
x1
x2
Z
x1
x2
Sequential effect
Needs two vectors to ensure detection!
Other options: use stuck-open or stuck-short models
This requires fault-simulation and analysis at the switch or
transistor level - Very expensive!
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Problem with stuck-at model:
CMOS short fault
‘0’
‘0’
C
D
A
B
‘0’
A
C
‘1’
B
D
Digital Integrated Circuits
Causes short circuit between
Vdd and GND for A=C=0, B=1
Possible approach:
Supply Current Measurement (IDDQ)
but: not applicable for gigascale
integration
Design Methodologies
© Prentice Hall 1995
Path Sensitization
Goals: Determine input pattern that makes a fault
controllable (triggers the fault, and makes its impact
visible at the output nodes)
Fault enabling
1
1
1
1
Fault propagation
0
sa0
1
Out
1
0
Techniques Used: D-algorithm, Podem
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Ad-hoc Test
data
address
data
test
address
Memory
Memory
select
Processor
Processor
I/O bus
I/O bus
Inserting multiplexer improves testability
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Scan-based Test
ScanIn
Digital Integrated Circuits
Combinational
Logic
A
Register
Register
In
ScanOut
Design Methodologies
Combinational
Out
Logic
B
© Prentice Hall 1995
Polarity-Hold SRL
(Shift-Register Latch)
System Data
System Clock
Scan Data
Shift A Clock
D
C
SI
A
Q
L1
Q
SO
Shift B Clock
B
L2
SO
Introduced at IBM and set as company policy
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Scan-Path Register
OUT
SCAN
PHI2
PHI1
SCANIN
SCANOUT
IN
LOAD
Digital Integrated Circuits
KEEP
Design Methodologies
© Prentice Hall 1995
Scan-based Test —Operation
In 0
Test
In1
Test
ScanIn
Test
In2
Test
Test
In 3
Test
Test
Test
ScanOut
Latch
Latch
Latch
Latch
Out0
Out1
Out2
Out3
Test
1
2
N cycles
scan-in
Digital Integrated Circuits
1 cycle
evaluation
Design Methodologies
N cycles
scan-out
© Prentice Hall 1995
Scan-Path Testing
A
B
REG[1]
REG[0]
REG[2]
REG[3]
SCANIN
+
REG[4]
COMPIN
COMP
REG[5]
SCANOUT
OUT
Partial-Scan can be more effective for pipelined datapaths
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Boundary Scan (JTAG)
Printed-circuit board
Logic
Scan-out
si
so
scan path
normal interconnect
Scan-in
Packaged IC
Bonding Pad
Board testing becomes as problematic as chip testing
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Self-test
(Sub)-Circuit
Stimulus Generator
Under
Response Analyzer
Test
Test Controller
Rapidly becoming more important with increasing
chip-complexity and larger modules
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Linear-Feedback Shift Register (LFSR)
R
R
R
S0
S1
S2
1
0
1
1
1
0
0
1
0
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
Pseudo-Random Pattern Generator
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Signature Analysis
In
Counter
R
Counts transitions on single-bit stream
 Compression in time
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
BILBO
D0
B0
D1
D2
B1
ScanOut
mux
ScanIn
R
R
S0
Digital Integrated Circuits
R
S1
B0 B1
Operation mode
1
1
Normal
0
0
1
0
0
1
Scan
Pattern generation or
Signature analysis
Reset
Design Methodologies
S2
© Prentice Hall 1995
BILBO Application
Digital Integrated Circuits
Combinational
Logic
BILBO-B
In
ScanOut
BILBO-A
ScanIn
Design Methodologies
Combinational
Out
Logic
© Prentice Hall 1995
Memory Self-Test
data -in
Memory
data-out
Signature
FSM
Under Test
Analysis
address &
R/W control
Patterns: Writing/Reading 0s, 1s,
Walking 0s, 1s
Galloping 0s, 1s
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995