Controlling the
System
© 2003 Xilinx, Inc. All Rights Reserved
Objectives
After completing this module, you will be able to:
• Describe the control mechanism available in System Generator
• State the available blocks in System Generator to control data
movement
• Describe how to design state machines
• Distinguish between valid and invalid data
Controlling the System - 6 - 3
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
• Control Mechanisms
– Clock Enables and Reset
– Valid and Invalid Data
• Control Blocks
–
–
–
–
–
MicroBlaze (FSL)
M-Code Block
Expression Block
PicoBlaze
PowerPC/MicroBlaze (App Note)
• Simulink Tips and Tricks
–
–
–
–
Controlling the System - 6 - 4
Masked Subsystems
Icon Editor
Parameter Initialization
Documentation Editor
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Control Mechanisms
Enable and Reset Ports
• Many blocks have optional Enable ports
– Gated by the CE signal going to the block
– When the CE signal is de-asserted the block holds its current state until
the enable signal is asserted again or the reset signal is asserted
– The enable signal has to run at a multiple of the block's sample rate
– The signal driving the enable port must be Boolean
• Some blocks have an optional Reset port
–
–
–
–
–
Gated by the CE signal going to the block
Reset port has precedence over Enable port when both are present
When the reset signal is asserted the block goes back to its initial state
The reset signal has to run at a multiple of the block's sample rate
The signal driving the reset port must be Boolean
Controlling the System - 6 - 5
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Control Mechanisms
Clock Enable Port
• SysGen infers the clock from the design sample times, and abstracts
away the Clock Enables
• In multi-rate systems further Clock Enables are inferred due to the more
complex hardware elaboration scheme. This is covered in next module
• This clock enables are ANDed with optional enable ports, which users
can turned-ON from the block parameters
Controlling the System - 6 - 6
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Clock Enable Behavior
• CE is modeled to reflect the hardware behavior
– Output changes one clock cycle after CE is asserted
System Clock
DIN
0
7
2
1
4
7
8
11
3
0
6
3
1
2
CE
DOUT
Controlling the System - 6 - 7
5
0
1
8
© 2003 Xilinx, Inc. All Rights Reserved
0
1
For Academic Use Only
Control Pin Cheat Sheet
Basic Elements
Enable Pin
Reset Pin
Control Logic
Addressable Shift Register
Y
N
None
Black Box
??
??
??
Concat
N
N
Constant
N
Convert
Enable Pin
Reset Pin
Control Logic
Accumulator
Y
Y
None
AddSub (Latency > 0)
Y
N
None
None
CMult (Latency > 0)
Y
N
None
N
None
Expression (Latency > 0)
Y
N
None
N
N
None
Logical (Latency > 0)
Y
N
None
Counter
Y
Y
Load
MCode
N
N
None
Delay
Y
N
None
Mult (Latency > 0)
Y
N
None
Down Sample
Y
N
None
Negate (Latency > 0)
Y
N
None
Enable
Y
N
None
Scale
N
N
None
Inverter
Y
N
None
Shift (Latency > 0)
Y
N
None
LFSR
Y
N
None
SineCosine
Y
N
None
Logical
Y
N
None
Threshold (Latency > 0)
Y
N
None
Mux (Latency > 0)
Y
N
None
Parallel to Serial
Y
N
None
Relational
Y
N
None
Memory
Enable Pin
Reset Pin
Control Logic
Register
Y
Y
None
Dual Port RAM
N
N
Reinterpret
N
N
None
We_A, we_B,
Vout
Serial to Parallel
Y
N
None
FIFO
Y
Y
we, re
Slice
N
N
None
ROM
Y
N
None
Sync
N
N
None
Single Port RAM
Y
N
we
Up Sample
N
N
None
Controlling the System - 6 - 8
Math
?? – Depending on application corresponding pin(s) may exist
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Control Pin Cheat Sheet
Communication
Enable Pin
Reset Pin
Control Logic
Convolution Encoder
Y
Y
Vin, Vout
Depuncture
N
N
None
Interleaver/Deinterlever
Y
Y
Vin, Vout
Puncture
N
N
None
RS Decoder
N
Y
Start, Erase,
Vin, Vout
RS Encoder
N
Y
Start, Bypass,
Vin, Vout
Viterbi Decoder
Y
Y
Vin, Vout
DSP
Controlling the System - 6 - 9
Enable Pin
Reset Pin
Control Logic
CIC
N
N
Vin, Vout
DDS
Y
Y
None
FDATool
N
N
None
FFT
N
Y
Inverse, Vin, Vout
FIR
N
N
Vin, Vout
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Control Mechanism
Valid and Invalid Ports
•
Issue: How to model ‘invalid data’ in the confines of a System Level environment.
Required for data burst applications, one-shot FFTs, and latency output from high
level cores
•
Solution: Certain blocks have a ‘valid bit’ input (vin) that is a control signal to the
data input. It is also accompanied by a valid out (vout) signal that signals whether
the output data is valid
•
Most high level blocks have ‘valid’ input and output ports
Controlling the System - 6 - 10
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Valid Bits
•
There are several conditions that result in a Xilinx block producing indeterminate
data, which is represented as ‘not a number’ or NaN in Simulink
– One case is with the Dual-Port Memory block, when there is a write-write collision
on a particular address. Consequently, in Simulink simulation, the corresponding
data is marked as indeterminate
– A block having vin and vout ports may produce indeterminate values, for example to
model pipeline flushing at the beginning of a simulation, but will have accompanying
vout set to 0
– Special attention should be paid if you encounter indeterminate data in a model,
because it indicates unobservable behavior in the ultimate hardware
– System Generator will catch some instances of indeterminate data as simulation
errors in Simulink, when this represents a semantic problem with your model
– Be aware that although these design errors will be caught in Simulink simulation,
such cases will not be detected in hardware
Controlling the System - 6 - 11
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Valid Bits
• Blocks that have Valid bit modeling:
–
–
–
–
–
–
–
FIR (optional)
FFT
Reed Solomon Encoder/Decoder
Viterbi Decoder
Convolutional Encoder
Interleaver/DeInterleaver
CIC
Controlling the System - 6 - 12
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Valid Bits Question
• Cost in hardware
– The SysGen block typically has a ‘valid bit’ pipe parallel to the data path. The
length of the pipe is equal to the latency of the block
– An AND gate controls the data path input
What would be the most efficient way of implementing
the valid pipe?
Controlling the System - 6 - 13
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
• Control Mechanisms
– Clock Enables and Reset
– Valid and Invalid Data
• Control Blocks
–
–
–
–
–
MicroBlaze (FSL)
M-Code Block
Expression Block
PicoBlaze
PowerPC/MicroBlaze (App Note)
• Simulink Tips and Tricks
–
–
–
–
Controlling the System - 6 - 14
Masked Subsystems
Icon Editor
Parameter Initialization
Documentation Editor
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Modeling Control Circuits
• System Generator provides many ways to model Control
Circuits
– Develop DSP peripherals for MicroBlaze (via FSL)
– M-Code block for subset of MATLAB m-code compilation
• Gives designer more design language choice
– Expression block for bit-wise logical operations
• Provides simple level control using Logical and Boolean expressions
– Xilinx PicoBlaze 8-bit soft microprocessor block
• Allows designers to model more complex control functions
– Develop DSP Peripherals for 32-bit PowerPC/MicroBlaze (app note)
Controlling the System - 6 - 15
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Xilinx Processor Family
Embedded Processor
Inst
µP Core
Bus
Coding
Environment
C&
Assembly
Embedded
Development
Kit - EDK
Assembly
& µCode
Assembler
Target Families
PLB
32-bit
Hard IP
OPB
8-bit
Soft IP
Controlling the System - 6 - 16
Reference
Design in VHDL
(Custom Bus)
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
SysGen-EDK Connection
Controlling the System - 6 - 17
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
New MicroBlaze Block
•
•
•
•
Found in Index and Control Logic Library
Exposes FSL interfaces to System Generator blocks in Simulink
A maximum of 8 input FSLs and 8 output FSLs
Reset port to allow processor
controlled reset
• Simple hardware design idiom:
FSLs look like FIFOs
• No simulation model
Controlling the System - 6 - 18
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
EDK Export Tool
•
•
•
•
EDK compilation target
Exports a System Generator design with a
MicroBlaze Block
Creates necessary EDK files: mpd, pao, bbd
Marshals required files into a directory
structure understood by the EDK
Controlling the System - 6 - 19
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Accessing FSLs in software
•
Blocking and non-blocking reads and writes
(8 macros) e.g.
– Blocking data and control reads
microblaze_bread_datafsl(val,id);
microblaze_bread_cntlfsl(val,id);
– Non-Blocking data and control writes
microblaze_nbwrite_datafsl(val,id);
microblaze_nbwrite_cntlfsl(val,id);
•
Error conditions visible in the MicroBlaze status register, MSR register
– MSR[27] = FSL error (mismatch in data/value pair)
– MSR[29] = data invalid (0 if read or write succeeds)
Controlling the System - 6 - 20
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Expression Block
•
•
Performs a bitwise logical expression
The expression is specified with operators
–
–
–
–
–
•
And - & -- highest precedence
Or - |
Not - ~
Xor - ^ -- lowest precedence
Precedence can be changed using parenthesis
The number of input ports is inferred from the expression
– Maximum of 16 possible input ports
•
The input port labels are identified from the expression, and the block is
subsequently labeled accordingly
– Block Parameters
• Expression : Bitwise logical expression
• Align Binary Point : specifies that the block must align binary points automatically. If
not selected, all inputs must have the same binary point position
Controlling the System - 6 - 22
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Expression Block
•
Entering following expression in the block parameters Expression field will
generate the resulting symbol
– ~((A1 | A2) & (B1 ^ B2))
Controlling the System - 6 - 23
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
8-bit PicoBlaze Controller
within Simulink
•
•
PicoBlaze provides
8-bit microprocessor
type control
Xilinx’s Home-Grown
8-bit processor
–
–
–
–
–
Very compact (85 slices)
49 instructions
Assembly language
2 clocks/instruction
10,000+ users
For more information on the Picoblaze microprocessor, visit:
http://www.xilinx.com/ipcenter/processor_central/picoblaze/index.htm
Controlling the System - 6 - 24
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Use System Generator to
Develop DSP Peripherals for OPB
Application Note XAPP264
• XAPP264 shows designers
how to use Simulink &
System Generator to create
DSP peripherals that can
connect to the OPB
Using SysGen to Create
CoreConnectTM Peripherals
– PowerPC
– MicroBlaze
UART Lite
• This enables 32-bit control for
XtremeDSP using:
PowerPC/
MicroBla
ze
– VirtexTM-II, Virtex-II ProTM
– Spartan-3
OPB
Reloadable
DA FIR
Peripheral
• Still need EDK to program the
processor
Controlling the System - 6 - 25
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Host PC
(post-processing
and filter design in
Matlab)
Quick System Resource
Estimation from Simulink
• Designers can now
estimate how many
FPGA resources
will be used directly
from Simulink
– Can be invoked at
any level in the
system hierarchy
• No need for:
– System Generation
– Synthesis
– Implementation
Controlling the System - 6 - 26
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
• Control Mechanisms
– Clock Enables and Reset
– Valid and Invalid Data
• Control Blocks
–
–
–
–
–
MicroBlaze (FSL)
M-Code Block
Expression Block
PicoBlaze
PowerPC/MicroBlaze (App Note)
• Simulink Tips and Tricks
–
–
–
–
Controlling the System - 6 - 27
Masked Subsystems
Icon Editor
Parameter Initialization
Documentation Editor
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Masked Subsystems
• Simulink provides the power to “personalize” a subsystem. This is
called masking
• This enables you to:
–
–
–
–
–
Generate custom macro blocks with a custom icon
Create a parameter dialog box for the block
Create your help for the block
Shield complexity of the internals of the block
Protect the contents of a block from ‘dirty hands’
Controlling the System - 6 - 28
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Masking a Subsystem
• Right click on a subsystem and
select “Mask Subsystem”
(Ctrl+M)
• The Mask editor contains the:
–
–
–
–
Icon editor
Parameters editor
Initialization editor
Documentation editor
• To disable a mask simply click
unmask on the mask editor
Controlling the System - 6 - 29
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Icon Editor
• The Icon tab controls the appearance
of the icon
• The drawing commands edit box
allows the use of MATLAB syntax
plotting and image commands to
define your icon. Try:
• plot(peaks)
• disp(‘my Icon’)
• image(imread(‘xilinx.jpg’))
• Play with the other properties to
view their effects
Controlling the System - 6 - 30
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Parameters Editor
• The Parameters tab enables you to
define and describe mask dialog box
parameter prompts and name the
variables associated with the
parameters
• Users must:
– Add a parameter
– Give a prompt name
– Assign a variable name to pass the
value to
– Select the type of variable
– Select if enabled or not
– Select if tunable or not
Controlling the System - 6 - 31
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Initialization Editor
• Initialization tab allows you to specify
initialization command
• After this, MATLAB workspace
variables are no longer visible
• Simulink executes the initialization
commands when it
–
–
–
–
–
Loads the model
Starts the simulation
Updates the block diagram
Rotates the masked block
Redraws the block's icon (if the mask's
icon creation code depends on
variables defined in the initialization
code)
Controlling the System - 6 - 32
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Documentation Editor
•
There are three fields:
– Mask type
– Mask description
– Mask Help (can be written in html). Click Help in the block mask to access the block help
Type ‘maskedsubsytem’
to view the example
Controlling the System - 6 - 33
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Lab 7:
Controlling the System
•
In this lab, you are to create an address generator to control the storage of
samples and coefficients for a 92 tap MAC-based FIR filter, using
– Xilinx Blockset’s predefined blocks
– Xilinx Blockset’s MCode block
•
Below is a block diagram of the MAC-based FIR filter
Sample Memory
• Cyclic RAM buffer
Full Multiplier
Accumulator
Capture of final result
Samplein
Sample
Address
8
Samples
92 × 8
20
+
27
DQ
CE
DQ
+
12
Coefficient
Address
Controlling the System - 6 - 34
Coefficients
92 × 12
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
27
Lab 7:
Controlling the System
• One way to implement this filter is to store the filter coefficients and samples
in a dual port block RAM used as a cyclic RAM buffer
– The dual port RAM will be used in a mixed mode configuration with the data
written and read from port A (RAM mode) and the coefficients read from port B
(ROM mode)
Your task is to generate the logic that will drive each address
port of the Dual Port Block Memory
y(0) = h(0) x(0)
y(1) = h(1) x(0) + h(0) x(1)
y(2) = h(2) x(0) + h(1) x(1) + h(0) x(2)
y(3) = h(3) x(0) + h(2) x(1) + h(1) x(2) + h(0) x(3)
etc.
Controlling the System - 6 - 35
© 2003 Xilinx, Inc. All Rights Reserved
N-1
yn = S xn-i hi
i=0
For Academic Use Only
Lab 7:
Controlling the System
The idea is as follows:
Read address
Data buffer
start
Fast rate
x(0) x(91) x(90) ...
...
x(3) x(2) x(1)
Write address
Slow rate
Stall one clock cycle
at this address
Read Address sequence: 92 93 94 95 … 183
Read address
Coefficient
array
Controlling the System - 6 - 36
start
Fast rate
h(0) h(1) h(2)
...
... h(89) h(90) h(91)
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
0
DIN_A
A
CE
WE_B
ADDR_A
CYCLIC
COUNTER
N-1
0 – N-1
N
LOGIC
DIN_B
ROM
B
WE_B
CYCLIC
COUNTER
ADDR_B
N – 2N-1
2N-1
RAM MUST BE:
READ AFTER WRITE
WE
WE
WE
DIN
D1 X X
X
…X
D2 X X X
X
… X D3 X X X X
X
ADDR_ A
0 1 2
3
…91 91 0 1 2
3
…90 90 91 0 1
3
2
ADDR_B 92 93 94 95 … 183 92 93 94 95 96 …183 92 93 94 95 96 97
Controlling the System - 6 - 37
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only