CHAPTER 14 CMOS DIGITAL LOGIC CIRCUITS
Chapter Outline
14.1 Digital Logic Inverters
14.2 The CMOS Inverter
14.3 Dynamic Operation of the CMOS Inverter
14.4 CMOS Logic-Gate Circuits
14.5 Implications of Technology Scaling: Issues in Deep-Submicron Design
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14.1 DIGITAL LOGIC INVERTERS
The Voltage-Transfer Characteristic (VTC)
 The function of the inverter is to invert the logic value of its input signal
 The voltage-transfer characteristic is used to evaluate the quality of inverter operation
 VTC parameters
 VOH: output high level
 VOL: output low level
 VIH: the minimum value of input interpreted by the inverter as a logic 1
 VIL: the maximum value of input interpreted by the inverter as a logic 0
 Transition region: input level between VIL and VIH
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Noise Margins
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The VTC is generally non-linear
VIH and VIL are defined as the points at which the slope of the VTC is 1
Robustness (noise margin at a high level): NMH = VOH  VIH
Robustness (noise margin at a low level): NML = VIL  VOL
Static inverter characteristics for ideal VTC:
 VOH = VDD
 VOL = 0
 VIH = VIL = VDD/2
 NMH = NML = VDD/2
Ideal VTC
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Power Dissipation
 Static power dissipation: power dissipated when the inverter stays in logic 0 or logic 1
 Dynamic power dissipation: power dissipated as the output is switching
2
PD  f CVDD
Propagation Delay





tPHL : high-to-low propagation delay
tPLH : low-to-high propagation delay
tP (propagation delay) = ( tPLH + tPHL )/2
Maximum switching frequency fmax = 1/2tP
The output transient of the inverter can be characterized by a RC charge/discharge model
vO (t )  V  (V  V0 )e t / RC
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Power-Delay Product and Energy-Delay Product
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Power and delay are often in conflict for inverter operation
Power-delay product is a figure-of-merit for comparing logic-circuit technologies or families
2
Power-delay product is defined as PDP  PD t P  CVDD
/2
2
Energy-delay product is defined as EDP  CVDD
tP / 2
Silicon Area
 Area reduction through advances in processing technology
 Area reduction through advances in circuit design techniques
 Area reduction through careful chip layout
Fan-In and Fan-Out
 Fan-in of a gate is the number of its inputs
 Fan-out is the maximum number of similar gates that a gate can drive
Logic-Circuit Families
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Inverter Implementation
 Simplest implementation of the inverter with a MOSFET and a load
 Inverter implementation with complementary switches
 Inverter implementation with a double-throw switch
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14.2 THE CMOS INVERTER
Circuit Operation
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A CMOS inverter consists of an n-channel and a p-channel MOSFET
The n-channel device turns on and the p-channel device turns off as the input level goes high
The p-channel device turns on and the n-channel device turns off as the input level goes low
1
1
The turn-on device is modeled by a resistance: rDSN  kn' W / L n (VDD  Vtn ) and rDSP  k p' W / L  p (VDD  | Vtp |)
VOH = VDD and VOL = 0 for any CMOS inverter
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The Voltage-Transfer Characteristic
 The transistors go through five different operation regions as the input goes from 0 to VDD
 The operating point is obtained by making iDN = iDP
 Region I: (QN off; QP tri.)
iDN ( 0)  iDP
 Region II: (QN sat.; QP tri.)
iDN 
 Region III: (QN sat; QP sat)
iDN
 Region IV: (QN tri.; QP sat.)
iDN
 Region V: (QN tri.;
tri ; QP off)
iDN
1
1


k n (vI  Vtn ) 2  iDP  k p (VDD  vI  | Vtp |)(VDD  vO )  (VDD  vO ) 2 
2
2


1
1
 k n (vI  Vtn ) 2  iDP  k p (VDD  vI  | Vtp |) 2
2
2
1 2
1

 k n (vI  Vtn )vO  vO   iDP  k p (VDD  vI  | Vtp |) 2
2 
2

 iDP ( 0)
iD
iD
Region I
iD
vO
Region II
iD
Region III
vO
vO
iD
Region IV
vO
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Region V
vO
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Static Characteristics of the CMOS Inverter
 Ratioless logic: VOH and VOL are independent of ratio of the transistors
 VOH = VDD
 VOL = 0
 Static power dissipation is zero for both states
 Noise margins can be determined by the VTC
 The switching voltage (when vI = vO) is defined by
VM 
r (VDD  | Vtp )  Vtn
r 1
where r 
kp
kn

 p (W / L) p
 n (W / L) n
 VM increases (VTC shifts) with r
 NML increases and NMH decreases as r increases
 NML decreases and NMH increases as r decreases
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The Matched Inverter
 A matched inverter has equivalent pull-up and pull-down device with kn = kp and Vtn = |Vtp| = Vt
 The VTC is symmetric
 Determine VIL from the VTC in Region II:
1
1


(vI  Vt ) 2  (VDD  vI  Vt )(VDD  vO )  (VDD  vO ) 2 
2
2


vI  Vt  (VDD  vO )  (VDD  vI  Vt )
dvO
dv
 (VDD  vO ) O
dvI
dvI
1
VIL  (3VDD  2Vt )
8
 Determine VIH from the VTC in Region IV:
1
1
(vI  Vt )vo  vO2  (VDD  vI  Vt ) 2
2
2
dv
dv
vO  (vI  Vt ) O  vO O  (VDD  vI  Vt )
dvI
dvI
1
VIH  (5VDD  2Vt )
8
 Noise margins: NMH = NML = (3VDD + 2Vt)/8
 Switching voltage: VM = VDD/2
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14.3 DYNAMIC OPERATION OF THE CMOS INVERTER
Determining the Propagation Delay
 Evaluated by charging/discharge the output capacitor C through QP and QN
 Average current method:
 tPHL:
1
iDN ( E )  iDN (M )
2
1
iDN ( E )  k n (VDD  Vtn ) 2
2
2

 VDD  1  VDD  
iDN ( M )  k n (VDD  Vtn )
 
 
2
 2  2  


CVDD
C
t PHL 
 n
k nVDD
2 I av
I av 
 7 3Vtn Vtn2 
 2 
4
V
VDD 
DD

where  n  2 /  
 tPLH:
t PLH 
 pC
CVDD

k pVDD
2 I av
 7 3 | Vtp | Vtp2 
 2 
where n  2 /  
VDD 
 4 VDD
 Propagation delay: tP = (tPHL+tPLH)/2
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 An alternative approach:
 Modeling the turn-on device as a resistance
 Use RC charge/discharge behavior to evaluate the propagation delay
 The empirical values of the resistors are given by
RN 
12.5
(k)
(W / L) n
and
RP 
30
(k)
(W / L) p
 tPHL= 0.69RNC
 tPLH= 0.69RPC
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Determining the Equivalent Load Capacitance
 Components accountable for the equivalent load capacitance
 Transistor parasitic capacitances
 Wiring capacitance or interconnect capacitance
 Input capacitance of the following stages
C  2C gd 1  2C gd 2  Cdb1  Cdb 2  C g 3  C g 4  Cw
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Inverter Sizing
 Minimum length permitted by the technology is usually used as the length for all channels
 Device aspect ratio (W/L)n is usually selected in the range 1 to 1.5
 The selection of (W/L)n is relative to (W/L)n
 Matched inverter by (W/L)p : (W/L)n = n: p
 (W/L)p = (W/L)n: minimum area, small propagation delay
 (W/L)p = 2(W/L)n: a frequently used compromise
 Transistor sizing (aspect ratios are increased by a factor of S) versus propagation delay
 Load capacitance: C  Cint  Cext  SCint 0  Cext
 Equivalent resistance: Req  1 ( RN  RP ) 
2 S
S
Req 0
S
 Req 0 
1


( SCint 0  Cext )  0.69 Req 0Cint 0  Req 0Cext 
S


 S 
 Propagation delay: t P  0.69
Dynamic Power Dissipation
2
 Dynamic power dissipation: PD  fCVDD
 Peak current: I peak  1 kn  VDD  Vtn 
2
 2
2

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14.4 CMOS LOGIC-GATE CIRCUITS
CMOS Logic-Gate Structure
Implementation of PDN
Implementation of PUN
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The PDN can be most directly synthesized by expressing Y .
The PUN can be most directly synthesized by expressing Y .
The PDN can be obtained from the PUN (and vice versa) using duality property.
However, duality of the PDN and PUN is not a necessary condition.
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Transistor Sizing
 The (W/L) ratios are chosen for a worst-case gate delay equal to
that of the basic inverter
 The derivation of equivalent (W/L) ratio is based on the equivalent
resistance of the transistors
rDS  (W / L) 1
 1

1

 ...
Series Connection  (W / L) eq  
 (W / L)1 (W / L) 2

1
Parallel Connection  (W / L) eq  (W / L)1  (W / L) 2  ...
Effects of Fan-In and Fan-Out
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Each additional input to a CMOS gate requires two additional transistors
Increases the chip area and the propagation delay due to excess capacitive loading
The number of NAND gate is typically limited to 4
Redesign the logic design may be required for a higher number of inputs
Advantages of using CMOS logic: static power dissipation, ratioless design, noise margin
Disadvantage of using CMOS logic: area, complexity, capacitive loading, propagation delay
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Examples for CMOS Logic Gates
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14.5 IMPLICATIONS OF TECHNOLOGY SCALING
Moore’s Law
 A new technology is developed for every 2~3 years due to cost and speed requirement
 The trend was predicted more than 40 years ago by Gordon Moore
 For every new technology generation:
 The minimum length is reduced by a factor of 1.414 and the area is reduced by a factor of 2
 The cost is reduced by half or the circuit complexity is doubled
 Device scaling generally decreases the parasitics and enhances the operating speed
 The operating power is reduced
 The current technology node advances into deep-submicron
 Issues in deep
deep-submicron
submicron technologies have to be taken into account for circuit designs
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Scaling Implications
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Velocity Saturation
 Long-channel devices:
 Drift velocity: vn = nE
 Electric field in the channel: E = vDS/L
 Short-channel devices:
 Velocity saturates at a critical field Ecr with vsat  107 cm/s
 The vDS at which velocity saturates is denoted by VDSsat
 VDSsat = EcrL = vsatL/n
 VDSsat is a device parameter
The II-V
V Characteristics
 Long-channel devices
1
W
 Saturation current: iD   nCox (VGS  Vt ) 2
2
L
 Short-channel devices
 For VGS-Vt < VDSsat: same as long-channel devices
 For VGS-Vt > VDSsat:
1 2 
W
(VGS  Vt )VDSsat  VDSsat


2
L
1


 WCox vsat VGS  Vt  VDSsat 
2


I Dsat   nCox
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Current Equation for Velocity Saturation
 For vGS-Vt  VDSsat and vDS  VDSsat, the drain current is given by
iD   n Cox
W
1


VDSsat  vGS  Vt  VDSsat (1  VDS )
L
2


 The current is reduced from the predication of a long-channel device
 The dependence on vGS is more linear rather than quadratic
 Four regions of operation: cutoff, triode, saturation and velocity saturation
 Short-channel PMOS transistors undergo velocity saturation at the same value of vsat
 The effects on PMOS are less pronounced due to lower mobility and higher VDSsat
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Subthreshold Conduction
 The device is not complete off in deep-submicron devices as vGS < Vt
 The subthreshold current is exponentially proportional to vGS: iD = Isexp(vGS/nVT)
 It is a problem in digital IC design for two reasons:
 Such current leads to nonzero static power dissipation for CMOS logics
 May cause undesirable discharge of capacitors in dynamic CMOS logics
The Interconnect
 The width of the interconnect scales down with the CMOS technology
 The metal wire is no longer an ideal short
 Series parasitic resistance may cause undesirable voltage drop and excess delay
 Parasitic capacitance to ground may lead to speed degradation and additional dynamic power
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