FPGA DESIGN FLOW
Course Description
Module 2
This course provides participants with an introduction to designing with
Xilinx FPGAs using ISE® Foundation™ software.
Course Outline
Course Part Number –FPGA-FLOW-01
Who Should Attend?
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Professors who are new to FPGAs or Xilinx technology and
wish to use Xilinx FPGAs in digital design.
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Junior Engineer / Graduates
Duration: 2 days
Prerequisites
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Digital design experience
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Basic HDL knowledge (VHDL or Verilog)
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Understanding of 8-bit microcontrollers
After completing this comprehensive training, you will have the
necessary skills and knowledge to:
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Describe the general FPGA architectures and the design flow
Configure FPGA architecture features, such as the Digital Clock
Manager (DCM), using the Architecture Wizard
Communicate design timing objectives through the use of global
timing constraints
Pinpoint design bottlenecks using the reports
Utilize synthesis options to improve performance
Understand the various implementation options
Create and integrate IP cores into your design flow using CORE
Generator™ software
Use ChipScope™ Pro tool to perform on-chip verification
Use the 8-bit PicoBlaze™ microcontroller to interface to various
board components
Topics/Labs:
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FPGA Design Techniques
Synchronous Design Techniques
Synthesis Techniques
Lab 4: Synthesis Techniques with Xilinx Synthesis
Technology (XST)
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Implementation Options
Core Generator System
Lab 5: CORE Generator Software
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Set various synthesis options to improve results
for a simple PicoBlaze design. Download the
design and test in hardware using hyperterminal.
Generate the instruction ROM for a PicoBlaze
design using CORE Generator, initialized with
instructions generated from the PicoBlaze
assembler. Download and test in hardware.
ChipScope-Pro Tool
Lab 6: ChipScope-Pro Tool
o Use the ChipScope-Pro tool to debug a simple
PicoBlaze design using an Integrated Logic
Analyzer (ILA) core.
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Module 1
Topics/Labs:
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Basic FPGA Architecture
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Xilinx Tool Flow
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Lab 1: Xilinx Tool Flow
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An introduction to FPGA design flow. Open a
project containing the PicoBlaze 8-bit
microcontroller and simulate the design using the
ISim HDL simulator provided with the ISE
Foundation software.
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Architecture Wizard and Pins Assignment
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Lab 2: Architecture Wizard and Pins Assignment
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Use the Architecture Wizard to configure and
instantiate a DCM into a PicoBlaze design. Assign
pin locations with PACE. Implement design to
generate a bitstream file. Download and test in
hardware using hyperterminal.
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Reading Reports
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Global Timing Reports
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Lab 3: Global Timing Constraints
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Enter and analyze the effects of global timing
constraints on a simple PicoBlaze design.
Download and test the design in hardware using
hyperterminal.
FPGA DESIGN FLOW
Course Specification
“The Only ARM Accreditation Training Partner in Malaysia”
Malaysia
Elvira Systems Sdn Bhd (976024-T)
6th Floor Suite 16, IOI Business Park
Persiaran Puchong Jaya Selatan
Bandar Puchong Jaya
47100 Selangor
Malaysia.
Tel: +603 8064 4190
Fax: +603 8064 2190
E-mail : info@elvirasys.com
Web: http://www.elvirasys.com
www.elvirasys.com
+603-8064 4190